From: Michael McMaster Date: Sat, 6 Feb 2021 07:58:56 +0000 (+1000) Subject: STMCUBEMX to 1.8 update X-Git-Tag: v6.4.0~6^2~14 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=fa09595d5ccdac631e816c17ecfc9b2b2f5798ec;p=SCSI2SD-V6.git STMCUBEMX to 1.8 update --- diff --git a/Makefile.2020c b/Makefile.2020c index 8c7057c4..33a3f4fd 100644 --- a/Makefile.2020c +++ b/Makefile.2020c @@ -39,7 +39,6 @@ build/2020c/stm32cubemx/stm32f2xx_it.o: STM32CubeMX/2020c/Src/stm32f2xx_it.c build/2020c/stm32cubemx/tim.o: STM32CubeMX/2020c/Src/tim.c build/2020c/stm32cubemx/usart.o: STM32CubeMX/2020c/Src/usart.c build/2020c/stm32cubemx/usbd_conf.o: STM32CubeMX/2020c/Src/usbd_conf.c -build/2020c/stm32cubemx/usb_otg_fs.o: STM32CubeMX/2020c/Src/usb_otg_fs.c build/2020c/stm32cubemx/stm32f2xx_hal.o: STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c build/2020c/stm32cubemx/stm32f2xx_hal_cortex.o: STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c build/2020c/stm32cubemx/stm32f2xx_hal_dma.o: STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c @@ -77,7 +76,6 @@ STM32OBJS = \ build/2020c/stm32cubemx/tim.o \ build/2020c/stm32cubemx/usart.o \ build/2020c/stm32cubemx/usbd_conf.o \ - build/2020c/stm32cubemx/usb_otg_fs.o \ build/2020c/stm32cubemx/stm32f2xx_hal.o \ build/2020c/stm32cubemx/stm32f2xx_hal_cortex.o \ build/2020c/stm32cubemx/stm32f2xx_hal_dma.o \ diff --git a/Makefile.2021 b/Makefile.2021 index 7483ef61..5894e973 100644 --- a/Makefile.2021 +++ b/Makefile.2021 @@ -28,6 +28,7 @@ STM32CubeMX_INCUDE = \ all: build/firmware.V6.2021.dfu +build/2021/stm32cubemx/dma.o: STM32CubeMX/2021/Src/dma.c build/2021/stm32cubemx/fmc.o: STM32CubeMX/2021/Src/fmc.c build/2021/stm32cubemx/gpio.o: STM32CubeMX/2021/Src/gpio.c build/2021/stm32cubemx/main.o: STM32CubeMX/2021/Src/main.c @@ -46,13 +47,16 @@ build/2021/stm32cubemx/stm32f4xx_hal_gpio.o: STM32CubeMX/2021/Drivers/STM32F4xx_ build/2021/stm32cubemx/stm32f4xx_hal_hcd.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c build/2021/stm32cubemx/stm32f4xx_hal_pcd.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c build/2021/stm32cubemx/stm32f4xx_hal_pcd_ex.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +build/2021/stm32cubemx/stm32f4xx_hal_pwr_ex.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c build/2021/stm32cubemx/stm32f4xx_hal_rcc.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +build/2021/stm32cubemx/stm32f4xx_hal_rcc_ex.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c build/2021/stm32cubemx/stm32f4xx_hal_sd.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c build/2021/stm32cubemx/stm32f4xx_hal_spi.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c build/2021/stm32cubemx/stm32f4xx_hal_sram.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c build/2021/stm32cubemx/stm32f4xx_hal_tim.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c build/2021/stm32cubemx/stm32f4xx_hal_tim_ex.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c build/2021/stm32cubemx/stm32f4xx_hal_uart.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +build/2021/stm32cubemx/stm32f4xx_ll_fmc.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c build/2021/stm32cubemx/stm32f4xx_ll_fsmc.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c build/2021/stm32cubemx/stm32f4xx_ll_sdmmc.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c build/2021/stm32cubemx/stm32f4xx_ll_usb.o: STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -63,6 +67,7 @@ build/2021/stm32cubemx/system_stm32f4xx.o: STM32CubeMX/2021/Drivers/CMSIS/Device build/2021/stm32cubemx/startup_stm32f446xx.o: STM32CubeMX/2021/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s STM32OBJS = \ + build/2021/stm32cubemx/dma.o \ build/2021/stm32cubemx/fmc.o \ build/2021/stm32cubemx/gpio.o \ build/2021/stm32cubemx/main.o \ @@ -81,13 +86,16 @@ STM32OBJS = \ build/2021/stm32cubemx/stm32f4xx_hal_hcd.o \ build/2021/stm32cubemx/stm32f4xx_hal_pcd.o \ build/2021/stm32cubemx/stm32f4xx_hal_pcd_ex.o \ + build/2021/stm32cubemx/stm32f4xx_hal_pwr_ex.o \ build/2021/stm32cubemx/stm32f4xx_hal_rcc.o \ + build/2021/stm32cubemx/stm32f4xx_hal_rcc_ex.o \ build/2021/stm32cubemx/stm32f4xx_hal_sd.o \ build/2021/stm32cubemx/stm32f4xx_hal_spi.o \ build/2021/stm32cubemx/stm32f4xx_hal_sram.o \ build/2021/stm32cubemx/stm32f4xx_hal_tim.o \ build/2021/stm32cubemx/stm32f4xx_hal_tim_ex.o \ build/2021/stm32cubemx/stm32f4xx_hal_uart.o \ + build/2021/stm32cubemx/stm32f4xx_ll_fmc.o \ build/2021/stm32cubemx/stm32f4xx_ll_fsmc.o \ build/2021/stm32cubemx/stm32f4xx_ll_sdmmc.o \ build/2021/stm32cubemx/stm32f4xx_ll_usb.o \ diff --git a/STM32CubeMX/2020c/.mxproject b/STM32CubeMX/2020c/.mxproject index 77d89994..b6a40d7c 100644 --- a/STM32CubeMX/2020c/.mxproject +++ b/STM32CubeMX/2020c/.mxproject @@ -5,10 +5,10 @@ SourceFiles=gpio.h;dma.h;ffconf.h;bsp_driver_sd.h;fatfs.h;fsmc.h;sdio.h;spi.h;ti HeaderFiles=gpio.h;dma.h;ffconf.h;bsp_driver_sd.h;fatfs.h;fsmc.h;sdio.h;spi.h;tim.h;usart.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_storage_if.h;usb_host.h;usbh_conf.h;stm32f2xx_it.h;stm32f2xx_hal_conf.h;;sys.h;usb_otg_hs.h;usb_otg_fs.h;main.h; [PreviousLibFiles] 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CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__));USE_HAL_DRIVER;STM32F205xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c deleted file mode 100644 index 66b10df4..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c +++ /dev/null @@ -1,165 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_abs_f32.c -* -* Description: Vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" -#include - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicAbs Vector Absolute Value - * - * Computes the absolute value of a vector on an element-by-element basis. - * - * 
        
- *     pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.        
- *
- * - * The functions support in-place computation allowing the source and - * destination pointers to reference the same memory buffer. - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute and then store the results in the destination buffer. */ - /* read sample from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - - /* find absolute value */ - in1 = fabsf(in1); - - /* read sample from source */ - in4 = *(pSrc + 3); - - /* find absolute value */ - in2 = fabsf(in2); - - /* read sample from source */ - *pDst = in1; - - /* find absolute value */ - in3 = fabsf(in3); - - /* find absolute value */ - in4 = fabsf(in4); - - /* store result to destination */ - *(pDst + 1) = in2; - - /* store result to destination */ - *(pDst + 2) = in3; - - /* store result to destination */ - *(pDst + 3) = in4; - - - /* Update source pointer to process next sampels */ - pSrc += 4u; - - /* Update destination pointer to process next sampels */ - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute and then store the results in the destination buffer. */ - *pDst++ = fabsf(*pSrc++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAbs group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c deleted file mode 100644 index f0af0911..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c +++ /dev/null @@ -1,179 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q15.c -* -* Description: Q15 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. - */ - -void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *simd; - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q15_t in1; /* Input value1 */ - q15_t in2; /* Input value2 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - simd = __SIMD32_CONST(pDst); - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read two inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - - - /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ -#ifndef ARM_MATH_BIG_ENDIAN - *simd++ = - __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), - ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16); - -#else - - - *simd++ = - __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), - ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - - -#ifndef ARM_MATH_BIG_ENDIAN - - *simd++ = - __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), - ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16); - -#else - - - *simd++ = - __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), - ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - pDst = (q15_t *)simd; - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in1 = *pSrc++; - - /* Calculate absolute value of input and then store the result in the destination buffer. */ - *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - q15_t in; /* Temporary input variable */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in = *pSrc++; - - /* Calculate absolute value of input and then store the result in the destination buffer. */ - *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of BasicAbs group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c deleted file mode 100644 index 294ba75a..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q31.c -* -* Description: Q31 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - - -/** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. - */ - -void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q31_t in; /* Input value */ - -#ifndef ARM_MATH_CM0_FAMILY - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1); - *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2); - *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3); - *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); - - /* Decrement the loop counter */ - blkCnt--; - } - -} - -/** - * @} end of BasicAbs group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c deleted file mode 100644 index 5056290c..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c +++ /dev/null @@ -1,157 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q7.c -* -* Description: Q7 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. - */ - -void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q7_t in; /* Input value1 */ - -#ifndef ARM_MATH_CM0_FAMILY - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read inputs */ - in1 = (q31_t) * pSrc; - in2 = (q31_t) * (pSrc + 1); - in3 = (q31_t) * (pSrc + 2); - - /* find absolute value */ - out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1); - - /* read input */ - in4 = (q31_t) * (pSrc + 3); - - /* find absolute value */ - out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2); - - /* store result to destination */ - *pDst = (q7_t) out1; - - /* find absolute value */ - out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3); - - /* find absolute value */ - out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4); - - /* store result to destination */ - *(pDst + 1) = (q7_t) out2; - - /* store result to destination */ - *(pDst + 2) = (q7_t) out3; - - /* store result to destination */ - *(pDst + 3) = (q7_t) out4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; -#else - - /* Run the below code for Cortex-M0 */ - blkCnt = blockSize; - -#endif // #define ARM_MATH_CM0_FAMILY - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in = *pSrc++; - - /* Store the Absolute result in the destination buffer */ - *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAbs group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c deleted file mode 100644 index 3430e83e..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c +++ /dev/null @@ -1,150 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_add_f32.c -* -* Description: Floating-point vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicAdd Vector Addition - * - * Element-by-element addition of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ - float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - - /* read four inputs from sourceA and four inputs from sourceB */ - inA1 = *pSrcA; - inB1 = *pSrcB; - inA2 = *(pSrcA + 1); - inB2 = *(pSrcB + 1); - inA3 = *(pSrcA + 2); - inB3 = *(pSrcB + 2); - inA4 = *(pSrcA + 3); - inB4 = *(pSrcB + 3); - - /* C = A + B */ - /* add and store result to destination */ - *pDst = inA1 + inB1; - *(pDst + 1) = inA2 + inB2; - *(pDst + 2) = inA3 + inB3; - *(pDst + 3) = inA4 + inB4; - - /* update pointers to process next samples */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (*pSrcA++) + (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAdd group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c deleted file mode 100644 index 570aa4c8..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c +++ /dev/null @@ -1,140 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_add_q15.c -* -* Description: Q15 vector addition -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inB1, inB2; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - inA1 = *__SIMD32(pSrcA)++; - inA2 = *__SIMD32(pSrcA)++; - inB1 = *__SIMD32(pSrcB)++; - inB2 = *__SIMD32(pSrcB)++; - - *__SIMD32(pDst)++ = __QADD16(inA1, inB1); - *__SIMD32(pDst)++ = __QADD16(inA2, inB2); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - -} - -/** - * @} end of BasicAdd group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c deleted file mode 100644 index 63d83a8e..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c +++ /dev/null @@ -1,148 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_add_q31.c -* -* Description: Q31 vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - - -/** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - *pDst++ = __QADD(inA1, inB1); - *pDst++ = __QADD(inA2, inB2); - *pDst++ = __QADD(inA3, inB3); - *pDst++ = __QADD(inA4, inB4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = __QADD(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of BasicAdd group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c deleted file mode 100644 index 66e1e23c..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c +++ /dev/null @@ -1,134 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_add_q7.c -* -* Description: Q7 vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - -} - -/** - * @} end of BasicAdd group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c deleted file mode 100644 index d7f7bdcb..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_f32.c -* -* Description: Floating-point dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup dot_prod Vector Dot Product - * - * Computes the dot product of two vectors. - * The vectors are multiplied element-by-element and then summed. - * - * 
- *     sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - -void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result) -{ - float32_t sum = 0.0f; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer */ - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum += (*pSrcA++) * (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - /* Store the result back in the destination buffer */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c deleted file mode 100644 index 6f04ed1b..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c +++ /dev/null @@ -1,140 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q15.c -* -* Description: Q15 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these - * results are added to a 64-bit accumulator in 34.30 format. - * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator - * there is no risk of overflow. - * The return result is in 34.30 format. - */ - -void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result) -{ - q63_t sum = 0; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); - sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the results in a temporary buffer. */ - sum = __SMLALD(*pSrcA++, *pSrcB++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the results in a temporary buffer. */ - sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - /* Store the result in the destination buffer in 34.30 format */ - *result = sum; - -} - -/** - * @} end of dot_prod group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c deleted file mode 100644 index b199f8b8..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q31.c -* -* Description: Q31 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these - * are truncated to 2.48 format by discarding the lower 14 bits. - * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. - * There are 15 guard bits in the accumulator and there is no risk of overflow as long as - * the length of the vectors is less than 2^16 elements. - * The return result is in 16.48 format. - */ - -void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result) -{ - q63_t sum = 0; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - sum += ((q63_t) inA1 * inB1) >> 14u; - sum += ((q63_t) inA2 * inB2) >> 14u; - sum += ((q63_t) inA3 * inB3) >> 14u; - sum += ((q63_t) inA4 * inB4) >> 14u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* Store the result in the destination buffer in 16.48 format */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c deleted file mode 100644 index 0ad6ae47..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c +++ /dev/null @@ -1,159 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q7.c -* -* Description: Q7 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these - * results are added to an accumulator in 18.14 format. - * Nonsaturating additions are used and there is no danger of wrap around as long as - * the vectors are less than 2^18 elements long. - * The return result is in 18.14 format. - */ - -void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result) -{ - uint32_t blkCnt; /* loop counter */ - - q31_t sum = 0; /* Temporary variables to store output */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t input1, input2; /* Temporary variables to store input */ - q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */ - - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read 4 samples at a time from sourceA */ - input1 = *__SIMD32(pSrcA)++; - /* read 4 samples at a time from sourceB */ - input2 = *__SIMD32(pSrcB)++; - - /* extract two q7_t samples to q15_t samples */ - inA1 = __SXTB16(__ROR(input1, 8)); - /* extract reminaing two samples */ - inA2 = __SXTB16(input1); - /* extract two q7_t samples to q15_t samples */ - inB1 = __SXTB16(__ROR(input2, 8)); - /* extract reminaing two samples */ - inB2 = __SXTB16(input2); - - /* multiply and accumulate two samples at a time */ - sum = __SMLAD(inA1, inB1, sum); - sum = __SMLAD(inA2, inB2, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Dot product and then store the results in a temporary buffer. */ - sum = __SMLAD(*pSrcA++, *pSrcB++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Dot product and then store the results in a temporary buffer. */ - sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - /* Store the result in the destination buffer in 18.14 format */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c deleted file mode 100644 index 27eca680..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c +++ /dev/null @@ -1,174 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_mult_f32.c -* -* Description: Floating-point vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicMult Vector Multiplication - * - * Element-by-element multiplication of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ -#ifndef ARM_MATH_CM0_FAMILY - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary input variables */ - float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ - float32_t out1, out2, out3, out4; /* temporary output variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in output buffer */ - /* read sample from sourceA */ - inA1 = *pSrcA; - /* read sample from sourceB */ - inB1 = *pSrcB; - /* read sample from sourceA */ - inA2 = *(pSrcA + 1); - /* read sample from sourceB */ - inB2 = *(pSrcB + 1); - - /* out = sourceA * sourceB */ - out1 = inA1 * inB1; - - /* read sample from sourceA */ - inA3 = *(pSrcA + 2); - /* read sample from sourceB */ - inB3 = *(pSrcB + 2); - - /* out = sourceA * sourceB */ - out2 = inA2 * inB2; - - /* read sample from sourceA */ - inA4 = *(pSrcA + 3); - - /* store result to destination buffer */ - *pDst = out1; - - /* read sample from sourceB */ - inB4 = *(pSrcB + 3); - - /* out = sourceA * sourceB */ - out3 = inA3 * inB3; - - /* store result to destination buffer */ - *(pDst + 1) = out2; - - /* out = sourceA * sourceB */ - out4 = inA4 * inB4; - /* store result to destination buffer */ - *(pDst + 2) = out3; - /* store result to destination buffer */ - *(pDst + 3) = out4; - - - /* update pointers to process next samples */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in output buffer */ - *pDst++ = (*pSrcA++) * (*pSrcB++); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c deleted file mode 100644 index d546f8af..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c +++ /dev/null @@ -1,154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q15.c -* -* Description: Q15 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - - -/** - * @brief Q15 vector multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ - q15_t out1, out2, out3, out4; /* temporary output variables */ - q31_t mul1, mul2, mul3, mul4; /* temporary variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read two samples at a time from sourceA */ - inA1 = *__SIMD32(pSrcA)++; - /* read two samples at a time from sourceB */ - inB1 = *__SIMD32(pSrcB)++; - /* read two samples at a time from sourceA */ - inA2 = *__SIMD32(pSrcA)++; - /* read two samples at a time from sourceB */ - inB2 = *__SIMD32(pSrcB)++; - - /* multiply mul = sourceA * sourceB */ - mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); - mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); - mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); - mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); - - /* saturate result to 16 bit */ - out1 = (q15_t) __SSAT(mul1 >> 15, 16); - out2 = (q15_t) __SSAT(mul2 >> 15, 16); - out3 = (q15_t) __SSAT(mul3 >> 15, 16); - out4 = (q15_t) __SSAT(mul4 >> 15, 16); - - /* store the result */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); - *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); - *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); - -#endif // #ifndef ARM_MATH_BIG_ENDIAN - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the result in the destination buffer */ - *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c deleted file mode 100644 index ca8b07b9..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c +++ /dev/null @@ -1,160 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q31.c -* -* Description: Q31 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; /* temporary input variables */ - q31_t inB1, inB2, inB3, inB4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - out1 = ((q63_t) inA1 * inB1) >> 32; - out2 = ((q63_t) inA2 * inB2) >> 32; - out3 = ((q63_t) inA3 * inB3) >> 32; - out4 = ((q63_t) inA4 * inB4) >> 32; - - out1 = __SSAT(out1, 31); - out2 = __SSAT(out2, 31); - out3 = __SSAT(out3, 31); - out4 = __SSAT(out4, 31); - - *pDst++ = out1 << 1u; - *pDst++ = out2 << 1u; - *pDst++ = out3 << 1u; - *pDst++ = out4 << 1u; - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inB1 = *pSrcB++; - out1 = ((q63_t) inA1 * inB1) >> 32; - out1 = __SSAT(out1, 31); - *pDst++ = out1 << 1u; - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and then store the results in the destination buffer. */ - *pDst++ = - (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ -} - -/** - * @} end of BasicMult group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c deleted file mode 100644 index c2b50b67..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c +++ /dev/null @@ -1,127 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q7.c -* -* Description: Q7 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Q7 vector multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in temporary variables */ - out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - - /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ - *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the result in the destination buffer */ - *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c deleted file mode 100644 index 4a260b05..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c +++ /dev/null @@ -1,146 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_negate_f32.c -* -* Description: Negates floating-point vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup negate Vector Negate - * - * Negates the elements of a vector. - * - * 
        
- *     pDst[n] = -pSrc[n],   0 <= n < blockSize.        
- *
- * - * The functions support in-place computation allowing the source and - * destination pointers to reference the same memory buffer. - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - -void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* negate the input */ - in1 = -in1; - in2 = -in2; - in3 = -in3; - in4 = -in4; - - /* store the result to destination */ - *pDst = in1; - *(pDst + 1) = in2; - *(pDst + 2) = in3; - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ - *pDst++ = -*pSrc++; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c deleted file mode 100644 index b130e7b5..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c +++ /dev/null @@ -1,142 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q15.c -* -* Description: Negates Q15 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. - */ - -void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q15_t in; - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t in1, in2; /* Temporary variables */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Read two inputs at a time */ - in1 = _SIMD32_OFFSET(pSrc); - in2 = _SIMD32_OFFSET(pSrc + 2); - - /* negate two samples at a time */ - in1 = __QSUB16(0, in1); - - /* negate two samples at a time */ - in2 = __QSUB16(0, in2); - - /* store the result to destination 2 samples at a time */ - _SIMD32_OFFSET(pDst) = in1; - /* store the result to destination 2 samples at a time */ - _SIMD32_OFFSET(pDst + 2) = in2; - - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the result in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c deleted file mode 100644 index 470e151c..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c +++ /dev/null @@ -1,129 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q31.c -* -* Description: Negates Q31 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. - */ - -void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize) -{ - q31_t in; /* Temporary variable */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = __QSUB(0, in1); - *pDst++ = __QSUB(0, in2); - *pDst++ = __QSUB(0, in3); - *pDst++ = __QSUB(0, in4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the result in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c deleted file mode 100644 index e1ba06dd..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q7.c -* -* Description: Negates Q7 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. - */ - -void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q7_t in; - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t input; /* Input values1-4 */ - q31_t zero = 0x00000000; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Read four inputs */ - input = *__SIMD32(pSrc)++; - - /* Store the Negated results in the destination buffer in a single cycle by packing the results */ - *__SIMD32(pDst)++ = __QSUB8(zero, input); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ \ - in = *pSrc++; - *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c deleted file mode 100644 index 4f3f593d..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c +++ /dev/null @@ -1,165 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_offset_f32.c -* -* Description: Floating-point vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup offset Vector Offset - * - * Adds a constant offset to each element of a vector. - * - * 
        
- *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        
- *
- * - * The functions support in-place computation allowing the source and - * destination pointers to reference the same memory buffer. - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - -void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - /* read samples from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - - /* add offset to input */ - in1 = in1 + offset; - - /* read samples from source */ - in3 = *(pSrc + 2); - - /* add offset to input */ - in2 = in2 + offset; - - /* read samples from source */ - in4 = *(pSrc + 3); - - /* add offset to input */ - in3 = in3 + offset; - - /* store result to destination */ - *pDst = in1; - - /* add offset to input */ - in4 = in4 + offset; - - /* store result to destination */ - *(pDst + 1) = in2; - - /* store result to destination */ - *(pDst + 2) = in3; - - /* store result to destination */ - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++) + offset; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of offset group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c deleted file mode 100644 index 81247533..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q15.c -* -* Description: Q15 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. - */ - -void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t offset_packed; /* Offset packed to 32 bit */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Offset is packed to 32 bit in order to use SIMD32 for addition */ - offset_packed = __PKHBT(offset, offset, 16); - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ - *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); - *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __QADD16(*pSrc++, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of offset group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c deleted file mode 100644 index 49516efb..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c +++ /dev/null @@ -1,140 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q31.c -* -* Description: Q31 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. - */ - -void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = __QADD(in1, offset); - *pDst++ = __QADD(in2, offset); - *pDst++ = __QADD(in3, offset); - *pDst++ = __QADD(in4, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = __QADD(*pSrc++, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of offset group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c deleted file mode 100644 index 111b9b42..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q7.c -* -* Description: Q7 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. - */ - -void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t offset_packed; /* Offset packed to 32 bit */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Offset is packed to 32 bit in order to use SIMD32 for addition */ - offset_packed = __PACKq7(offset, offset, offset, offset); - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ - *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of offset group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c deleted file mode 100644 index 2c4febc9..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c +++ /dev/null @@ -1,169 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_scale_f32.c -* -* Description: Multiplies a floating-point vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup scale Vector Scale - * - * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: - * - * 
        
- *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        
- *
- * - * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by - * a fractional multiplication scaleFract and an arithmetic shift shift. - * The shift allows the gain of the scaling operation to exceed 1.0. - * The algorithm used with fixed-point data is: - * - * 
        
- *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        
- *
- * - * The overall scale factor applied to the fixed-point data is - * 
        
- *     scale = scaleFract * 2^shift.        
- *
- * - * The functions support in-place computation allowing the source and destination - * pointers to reference the same memory buffer. - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - -void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variabels */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the results in the destination buffer. */ - /* read input samples from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - - /* multiply with scaling factor */ - in1 = in1 * scale; - - /* read input sample from source */ - in3 = *(pSrc + 2); - - /* multiply with scaling factor */ - in2 = in2 * scale; - - /* read input sample from source */ - in4 = *(pSrc + 3); - - /* multiply with scaling factor */ - in3 = in3 * scale; - in4 = in4 * scale; - /* store the result to destination */ - *pDst = in1; - *(pDst + 1) = in2; - *(pDst + 2) = in3; - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++) * scale; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of scale group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c deleted file mode 100644 index 4587cce2..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c +++ /dev/null @@ -1,162 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q15.c -* -* Description: Multiplies a Q15 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.15 format. - * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. - */ - - -void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = 15 - shift; /* shift to apply after scaling */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q15_t in1, in2, in3, in4; - q31_t inA1, inA2; /* Temporary variables */ - q31_t out1, out2, out3, out4; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Reading 2 inputs from memory */ - inA1 = *__SIMD32(pSrc)++; - inA2 = *__SIMD32(pSrc)++; - - /* C = A * scale */ - /* Scale the inputs and then store the 2 results in the destination buffer - * in single cycle by packing the outputs */ - out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); - out2 = (q31_t) ((q15_t) inA1 * scaleFract); - out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); - out4 = (q31_t) ((q15_t) inA2 * scaleFract); - - /* apply shifting */ - out1 = out1 >> kShift; - out2 = out2 >> kShift; - out3 = out3 >> kShift; - out4 = out4 >> kShift; - - /* saturate the output */ - in1 = (q15_t) (__SSAT(out1, 16)); - in2 = (q15_t) (__SSAT(out2, 16)); - in3 = (q15_t) (__SSAT(out3, 16)); - in4 = (q15_t) (__SSAT(out4, 16)); - - /* store the result to destination */ - *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16); - *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of scale group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c deleted file mode 100644 index 2dba5bd7..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c +++ /dev/null @@ -1,239 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q31.c -* -* Description: Multiplies a Q31 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.31 format. - * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. - */ - -void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = shift + 1; /* Shift to apply after scaling */ - int8_t sign = (kShift & 0x80); - uint32_t blkCnt; /* loop counter */ - q31_t in, out; - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t in1, in2, in3, in4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variabels */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read four inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* multiply input with scaler value */ - in1 = ((q63_t) in1 * scaleFract) >> 32; - in2 = ((q63_t) in2 * scaleFract) >> 32; - in3 = ((q63_t) in3 * scaleFract) >> 32; - in4 = ((q63_t) in4 * scaleFract) >> 32; - - /* apply shifting */ - out1 = in1 << kShift; - out2 = in2 << kShift; - - /* saturate the results. */ - if(in1 != (out1 >> kShift)) - out1 = 0x7FFFFFFF ^ (in1 >> 31); - - if(in2 != (out2 >> kShift)) - out2 = 0x7FFFFFFF ^ (in2 >> 31); - - out3 = in3 << kShift; - out4 = in4 << kShift; - - *pDst = out1; - *(pDst + 1) = out2; - - if(in3 != (out3 >> kShift)) - out3 = 0x7FFFFFFF ^ (in3 >> 31); - - if(in4 != (out4 >> kShift)) - out4 = 0x7FFFFFFF ^ (in4 >> 31); - - /* Store result destination */ - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update pointers to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - } - else - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read four inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* multiply input with scaler value */ - in1 = ((q63_t) in1 * scaleFract) >> 32; - in2 = ((q63_t) in2 * scaleFract) >> 32; - in3 = ((q63_t) in3 * scaleFract) >> 32; - in4 = ((q63_t) in4 * scaleFract) >> 32; - - /* apply shifting */ - out1 = in1 >> -kShift; - out2 = in2 >> -kShift; - - out3 = in3 >> -kShift; - out4 = in4 >> -kShift; - - /* Store result destination */ - *pDst = out1; - *(pDst + 1) = out2; - - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update pointers to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - } - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - if(sign == 0) - { - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - in = *pSrc++; - in = ((q63_t) in * scaleFract) >> 32; - - out = in << kShift; - - if(in != (out >> kShift)) - out = 0x7FFFFFFF ^ (in >> 31); - - *pDst++ = out; - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - in = *pSrc++; - in = ((q63_t) in * scaleFract) >> 32; - - out = in >> -kShift; - - *pDst++ = out; - - /* Decrement the loop counter */ - blkCnt--; - } - - } -} - -/** - * @} end of scale group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c deleted file mode 100644 index 330c739c..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c +++ /dev/null @@ -1,149 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q7.c -* -* Description: Multiplies a Q7 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.7 format. - * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. - */ - -void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = 7 - shift; /* shift to apply after scaling */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Reading 4 inputs from memory */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - /* C = A * scale */ - /* Scale the inputs and then store the results in the temporary variables. */ - out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); - out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); - out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); - out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); - - /* Packing the individual outputs into 32bit and storing in - * destination buffer in single write */ - *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of scale group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c deleted file mode 100644 index b2d27e60..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c +++ /dev/null @@ -1,248 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q15.c -* -* Description: Shifts the elements of a Q15 vector by a specified number of bits. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup shift - * @{ - */ - -/** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign; /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q15_t in1, in2; /* Temporary variables */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Read 2 inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - /* C = A << shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), - __SSAT((in2 << shiftBits), 16), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), - __SSAT((in1 << shiftBits), 16), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), - __SSAT((in2 << shiftBits), 16), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), - __SSAT((in1 << shiftBits), 16), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift and then store the results in the destination buffer. */ - *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Read 2 inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), - (in2 >> -shiftBits), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), - (in1 >> -shiftBits), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), - (in2 >> -shiftBits), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), - (in1 >> -shiftBits), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift and then store the results in the destination buffer. */ - *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of shift group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c deleted file mode 100644 index 59904911..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c +++ /dev/null @@ -1,203 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q31.c -* -* Description: Shifts the elements of a Q31 vector by a specified number of bits. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ -/** - * @defgroup shift Vector Shift - * - * Shifts the elements of a fixed-point vector by a specified number of bits. - * There are separate functions for Q7, Q15, and Q31 data types. - * The underlying algorithm used is: - * - * 
        
- *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        
- *
- * - * If shift is positive then the elements of the vector are shifted to the left. - * If shift is negative then the elements of the vector are shifted to the right. - * - * The functions support in-place computation allowing the source and destination - * pointers to reference the same memory buffer. - */ - -/** - * @addtogroup shift - * @{ - */ - -/** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0_FAMILY - - q31_t in1, in2, in3, in4; /* Temporary input variables */ - q31_t out1, out2, out3, out4; /* Temporary output variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the results in the destination buffer. */ - in1 = *pSrc; - in2 = *(pSrc + 1); - out1 = in1 << shiftBits; - in3 = *(pSrc + 2); - out2 = in2 << shiftBits; - in4 = *(pSrc + 3); - if(in1 != (out1 >> shiftBits)) - out1 = 0x7FFFFFFF ^ (in1 >> 31); - - if(in2 != (out2 >> shiftBits)) - out2 = 0x7FFFFFFF ^ (in2 >> 31); - - *pDst = out1; - out3 = in3 << shiftBits; - *(pDst + 1) = out2; - out4 = in4 << shiftBits; - - if(in3 != (out3 >> shiftBits)) - out3 = 0x7FFFFFFF ^ (in3 >> 31); - - if(in4 != (out4 >> shiftBits)) - out4 = 0x7FFFFFFF ^ (in4 >> 31); - - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update destination pointer to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the results in the destination buffer. */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - *pDst = (in1 >> -shiftBits); - *(pDst + 1) = (in2 >> -shiftBits); - *(pDst + 2) = (in3 >> -shiftBits); - *(pDst + 3) = (in4 >> -shiftBits); - - - pSrc += 4u; - pDst += 4u; - - blkCnt--; - } - - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - - while(blkCnt > 0u) - { - /* C = A (>> or <<) shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : - (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - - -} - -/** - * @} end of shift group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c deleted file mode 100644 index f9250540..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c +++ /dev/null @@ -1,220 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q7.c -* -* Description: Processing function for the Q7 Shifting -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup shift - * @{ - */ - - -/** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. - */ - -void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign; /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t in1; /* Input value1 */ - q7_t in2; /* Input value2 */ - q7_t in3; /* Input value3 */ - q7_t in4; /* Input value4 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Read 4 inputs */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ - *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), - __SSAT((in2 << shiftBits), 8), - __SSAT((in3 << shiftBits), 8), - __SSAT((in4 << shiftBits), 8)); - /* Update source pointer to process next sampels */ - pSrc += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - shiftBits = -shiftBits; - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Read 4 inputs */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ - *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits), - (in3 >> shiftBits), (in4 >> shiftBits)); - - - pSrc += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - in1 = *pSrc++; - *pDst++ = (in1 >> shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ -} - -/** - * @} end of shift group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c deleted file mode 100644 index e7ff234a..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c +++ /dev/null @@ -1,150 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_sub_f32.c -* -* Description: Floating-point vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicSub Vector Subtraction - * - * Element-by-element subtraction of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicSub - * @{ - */ - - -/** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary variables */ - float32_t inB1, inB2, inB3, inB4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - /* Read 4 input samples from sourceA and sourceB */ - inA1 = *pSrcA; - inB1 = *pSrcB; - inA2 = *(pSrcA + 1); - inB2 = *(pSrcB + 1); - inA3 = *(pSrcA + 2); - inB3 = *(pSrcB + 2); - inA4 = *(pSrcA + 3); - inB4 = *(pSrcB + 3); - - /* dst = srcA - srcB */ - /* subtract and store the result */ - *pDst = inA1 - inB1; - *(pDst + 1) = inA2 - inB2; - *(pDst + 2) = inA3 - inB3; - *(pDst + 3) = inA4 - inB4; - - - /* Update pointers to process next sampels */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - *pDst++ = (*pSrcA++) - (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicSub group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c deleted file mode 100644 index 420db7f7..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c +++ /dev/null @@ -1,140 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q15.c -* -* Description: Q15 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2; - q31_t inB1, inB2; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer two samples at a time. */ - inA1 = *__SIMD32(pSrcA)++; - inA2 = *__SIMD32(pSrcA)++; - inB1 = *__SIMD32(pSrcB)++; - inB2 = *__SIMD32(pSrcB)++; - - *__SIMD32(pDst)++ = __QSUB16(inA1, inB1); - *__SIMD32(pDst)++ = __QSUB16(inA2, inB2); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - -} - -/** - * @} end of BasicSub group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c deleted file mode 100644 index 40ee7e10..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c +++ /dev/null @@ -1,146 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q31.c -* -* Description: Q31 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - *pDst++ = __QSUB(inA1, inB1); - *pDst++ = __QSUB(inA2, inB2); - *pDst++ = __QSUB(inA3, inB3); - *pDst++ = __QSUB(inA4, inB4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = __QSUB(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - -} - -/** - * @} end of BasicSub group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c deleted file mode 100644 index 2a2cb5e3..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c +++ /dev/null @@ -1,131 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q7.c -* -* Description: Q7 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0_FAMILY - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer 4 samples at a time. */ - *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0_FAMILY */ - - -} - -/** - * @} end of BasicSub group - */ diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c deleted file mode 100644 index 79fe976e..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c +++ /dev/null @@ -1,27251 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.c -* -* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - - -#include "arm_math.h" -#include "arm_common_tables.h" - -/** - * @ingroup groupTransforms - */ - -/** - * @addtogroup CFFT_CIFFT Complex FFT Tables - * @{ - */ - -/** -* \par -* Pseudo code for Generation of Bit reversal Table is -* \par -* 
for(l=1;l <= N/4;l++)    
-* {    
-*   for(i=0;i> 1;    
-*  }
-* \par -* where N = 4096 logN2 = 12 -* \par -* N is the maximum FFT Size supported -*/ - -/* -* @brief Table for bit reversal process -*/ -const uint16_t armBitRevTable[1024] = { - 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x80, 0x480, 0x280, - 0x680, 0x180, 0x580, 0x380, 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, - 0x540, 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, - 0x7c0, 0x20, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0xa0, - 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, 0x260, - 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, - 0x5e0, 0x3e0, 0x7e0, 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, - 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x50, - 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, - 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, 0x630, 0x130, - 0x530, 0x330, 0x730, 0xb0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, - 0x7b0, 0x70, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0xf0, - 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x8, 0x408, 0x208, - 0x608, 0x108, 0x508, 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, - 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, - 0x748, 0xc8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, - 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, 0x4a8, 0x2a8, - 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x68, 0x468, 0x268, 0x668, 0x168, - 0x568, 0x368, 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, - 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x98, - 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, - 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, - 0x5d8, 0x3d8, 0x7d8, 0x38, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, - 0x738, 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x78, - 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, - 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, 0x104, - 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, - 0x784, 0x44, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, - 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x24, 0x424, 0x224, - 0x624, 0x124, 0x524, 0x324, 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, - 0x5a4, 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, - 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, - 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, 0x294, - 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, 0x454, 0x254, 0x654, 0x154, - 0x554, 0x354, 0x754, 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, - 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0xb4, - 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, - 0x674, 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, - 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, - 0x70c, 0x8c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x4c, - 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0xcc, 0x4cc, 0x2cc, - 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, - 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, - 0x7ac, 0x6c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, - 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, 0x41c, 0x21c, - 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, - 0x59c, 0x39c, 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, - 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x3c, - 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, - 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, 0x27c, 0x67c, 0x17c, - 0x57c, 0x37c, 0x77c, 0xfc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, - 0x7fc, 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x82, - 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x42, 0x442, 0x242, - 0x642, 0x142, 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, - 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, - 0x722, 0xa2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, - 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0xe2, 0x4e2, 0x2e2, - 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, - 0x512, 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, - 0x792, 0x52, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0xd2, - 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, 0x232, - 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, - 0x5b2, 0x3b2, 0x7b2, 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, - 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0xa, - 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, - 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, 0x64a, 0x14a, - 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, - 0x7ca, 0x2a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0xaa, - 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x6a, 0x46a, 0x26a, - 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, - 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, - 0x71a, 0x9a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, - 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, 0x4da, 0x2da, - 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, - 0x53a, 0x33a, 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, - 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0xfa, - 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206, - 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, 0x286, 0x686, 0x186, - 0x586, 0x386, 0x786, 0x46, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, - 0x746, 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x26, - 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, - 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, 0x166, - 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, - 0x7e6, 0x16, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96, - 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x56, 0x456, 0x256, - 0x656, 0x156, 0x556, 0x356, 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, - 0x5d6, 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, - 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, - 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, 0x2f6, - 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, 0x40e, 0x20e, 0x60e, 0x10e, - 0x50e, 0x30e, 0x70e, 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, - 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0xce, - 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, - 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, - 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, - 0x76e, 0xee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x1e, - 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x9e, 0x49e, 0x29e, - 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, - 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, - 0x7de, 0x3e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, - 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, 0x47e, 0x27e, - 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, - 0x5fe, 0x3fe, 0x7fe, 0x1 -}; - - -/* -* @brief Floating-point Twiddle factors Table Generation -*/ - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 16 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_16[32] = { - 1.000000000f, 0.000000000f, - 0.923879533f, 0.382683432f, - 0.707106781f, 0.707106781f, - 0.382683432f, 0.923879533f, - 0.000000000f, 1.000000000f, - -0.382683432f, 0.923879533f, - -0.707106781f, 0.707106781f, - -0.923879533f, 0.382683432f, - -1.000000000f, 0.000000000f, - -0.923879533f, -0.382683432f, - -0.707106781f, -0.707106781f, - -0.382683432f, -0.923879533f, - -0.000000000f, -1.000000000f, - 0.382683432f, -0.923879533f, - 0.707106781f, -0.707106781f, - 0.923879533f, -0.382683432f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 32 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_32[64] = { - 1.000000000f, 0.000000000f, - 0.980785280f, 0.195090322f, - 0.923879533f, 0.382683432f, - 0.831469612f, 0.555570233f, - 0.707106781f, 0.707106781f, - 0.555570233f, 0.831469612f, - 0.382683432f, 0.923879533f, - 0.195090322f, 0.980785280f, - 0.000000000f, 1.000000000f, - -0.195090322f, 0.980785280f, - -0.382683432f, 0.923879533f, - -0.555570233f, 0.831469612f, - -0.707106781f, 0.707106781f, - -0.831469612f, 0.555570233f, - -0.923879533f, 0.382683432f, - -0.980785280f, 0.195090322f, - -1.000000000f, 0.000000000f, - -0.980785280f, -0.195090322f, - -0.923879533f, -0.382683432f, - -0.831469612f, -0.555570233f, - -0.707106781f, -0.707106781f, - -0.555570233f, -0.831469612f, - -0.382683432f, -0.923879533f, - -0.195090322f, -0.980785280f, - -0.000000000f, -1.000000000f, - 0.195090322f, -0.980785280f, - 0.382683432f, -0.923879533f, - 0.555570233f, -0.831469612f, - 0.707106781f, -0.707106781f, - 0.831469612f, -0.555570233f, - 0.923879533f, -0.382683432f, - 0.980785280f, -0.195090322f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 64 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_64[128] = { - 1.000000000f, 0.000000000f, - 0.995184727f, 0.098017140f, - 0.980785280f, 0.195090322f, - 0.956940336f, 0.290284677f, - 0.923879533f, 0.382683432f, - 0.881921264f, 0.471396737f, - 0.831469612f, 0.555570233f, - 0.773010453f, 0.634393284f, - 0.707106781f, 0.707106781f, - 0.634393284f, 0.773010453f, - 0.555570233f, 0.831469612f, - 0.471396737f, 0.881921264f, - 0.382683432f, 0.923879533f, - 0.290284677f, 0.956940336f, - 0.195090322f, 0.980785280f, - 0.098017140f, 0.995184727f, - 0.000000000f, 1.000000000f, - -0.098017140f, 0.995184727f, - -0.195090322f, 0.980785280f, - -0.290284677f, 0.956940336f, - -0.382683432f, 0.923879533f, - -0.471396737f, 0.881921264f, - -0.555570233f, 0.831469612f, - -0.634393284f, 0.773010453f, - -0.707106781f, 0.707106781f, - -0.773010453f, 0.634393284f, - -0.831469612f, 0.555570233f, - -0.881921264f, 0.471396737f, - -0.923879533f, 0.382683432f, - -0.956940336f, 0.290284677f, - -0.980785280f, 0.195090322f, - -0.995184727f, 0.098017140f, - -1.000000000f, 0.000000000f, - -0.995184727f, -0.098017140f, - -0.980785280f, -0.195090322f, - -0.956940336f, -0.290284677f, - -0.923879533f, -0.382683432f, - -0.881921264f, -0.471396737f, - -0.831469612f, -0.555570233f, - -0.773010453f, -0.634393284f, - -0.707106781f, -0.707106781f, - -0.634393284f, -0.773010453f, - -0.555570233f, -0.831469612f, - -0.471396737f, -0.881921264f, - -0.382683432f, -0.923879533f, - -0.290284677f, -0.956940336f, - -0.195090322f, -0.980785280f, - -0.098017140f, -0.995184727f, - -0.000000000f, -1.000000000f, - 0.098017140f, -0.995184727f, - 0.195090322f, -0.980785280f, - 0.290284677f, -0.956940336f, - 0.382683432f, -0.923879533f, - 0.471396737f, -0.881921264f, - 0.555570233f, -0.831469612f, - 0.634393284f, -0.773010453f, - 0.707106781f, -0.707106781f, - 0.773010453f, -0.634393284f, - 0.831469612f, -0.555570233f, - 0.881921264f, -0.471396737f, - 0.923879533f, -0.382683432f, - 0.956940336f, -0.290284677f, - 0.980785280f, -0.195090322f, - 0.995184727f, -0.098017140f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 128 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ - -const float32_t twiddleCoef_128[256] = { - 1.000000000f , 0.000000000f , - 0.998795456f , 0.049067674f , - 0.995184727f , 0.098017140f , - 0.989176510f , 0.146730474f , - 0.980785280f , 0.195090322f , - 0.970031253f , 0.242980180f , - 0.956940336f , 0.290284677f , - 0.941544065f , 0.336889853f , - 0.923879533f , 0.382683432f , - 0.903989293f , 0.427555093f , - 0.881921264f , 0.471396737f , - 0.857728610f , 0.514102744f , - 0.831469612f , 0.555570233f , - 0.803207531f , 0.595699304f , - 0.773010453f , 0.634393284f , - 0.740951125f , 0.671558955f , - 0.707106781f , 0.707106781f , - 0.671558955f , 0.740951125f , - 0.634393284f , 0.773010453f , - 0.595699304f , 0.803207531f , - 0.555570233f , 0.831469612f , - 0.514102744f , 0.857728610f , - 0.471396737f , 0.881921264f , - 0.427555093f , 0.903989293f , - 0.382683432f , 0.923879533f , - 0.336889853f , 0.941544065f , - 0.290284677f , 0.956940336f , - 0.242980180f , 0.970031253f , - 0.195090322f , 0.980785280f , - 0.146730474f , 0.989176510f , - 0.098017140f , 0.995184727f , - 0.049067674f , 0.998795456f , - 0.000000000f , 1.000000000f , - -0.049067674f , 0.998795456f , - -0.098017140f , 0.995184727f , - -0.146730474f , 0.989176510f , - -0.195090322f , 0.980785280f , - -0.242980180f , 0.970031253f , - -0.290284677f , 0.956940336f , - -0.336889853f , 0.941544065f , - -0.382683432f , 0.923879533f , - -0.427555093f , 0.903989293f , - -0.471396737f , 0.881921264f , - -0.514102744f , 0.857728610f , - -0.555570233f , 0.831469612f , - -0.595699304f , 0.803207531f , - -0.634393284f , 0.773010453f , - -0.671558955f , 0.740951125f , - -0.707106781f , 0.707106781f , - -0.740951125f , 0.671558955f , - -0.773010453f , 0.634393284f , - -0.803207531f , 0.595699304f , - -0.831469612f , 0.555570233f , - -0.857728610f , 0.514102744f , - -0.881921264f , 0.471396737f , - -0.903989293f , 0.427555093f , - -0.923879533f , 0.382683432f , - -0.941544065f , 0.336889853f , - -0.956940336f , 0.290284677f , - -0.970031253f , 0.242980180f , - -0.980785280f , 0.195090322f , - -0.989176510f , 0.146730474f , - -0.995184727f , 0.098017140f , - -0.998795456f , 0.049067674f , - -1.000000000f , 0.000000000f , - -0.998795456f , -0.049067674f , - -0.995184727f , -0.098017140f , - -0.989176510f , -0.146730474f , - -0.980785280f , -0.195090322f , - -0.970031253f , -0.242980180f , - -0.956940336f , -0.290284677f , - -0.941544065f , -0.336889853f , - -0.923879533f , -0.382683432f , - -0.903989293f , -0.427555093f , - -0.881921264f , -0.471396737f , - -0.857728610f , -0.514102744f , - -0.831469612f , -0.555570233f , - -0.803207531f , -0.595699304f , - -0.773010453f , -0.634393284f , - -0.740951125f , -0.671558955f , - -0.707106781f , -0.707106781f , - -0.671558955f , -0.740951125f , - -0.634393284f , -0.773010453f , - -0.595699304f , -0.803207531f , - -0.555570233f , -0.831469612f , - -0.514102744f , -0.857728610f , - -0.471396737f , -0.881921264f , - -0.427555093f , -0.903989293f , - -0.382683432f , -0.923879533f , - -0.336889853f , -0.941544065f , - -0.290284677f , -0.956940336f , - -0.242980180f , -0.970031253f , - -0.195090322f , -0.980785280f , - -0.146730474f , -0.989176510f , - -0.098017140f , -0.995184727f , - -0.049067674f , -0.998795456f , - -0.000000000f , -1.000000000f , - 0.049067674f , -0.998795456f , - 0.098017140f , -0.995184727f , - 0.146730474f , -0.989176510f , - 0.195090322f , -0.980785280f , - 0.242980180f , -0.970031253f , - 0.290284677f , -0.956940336f , - 0.336889853f , -0.941544065f , - 0.382683432f , -0.923879533f , - 0.427555093f , -0.903989293f , - 0.471396737f , -0.881921264f , - 0.514102744f , -0.857728610f , - 0.555570233f , -0.831469612f , - 0.595699304f , -0.803207531f , - 0.634393284f , -0.773010453f , - 0.671558955f , -0.740951125f , - 0.707106781f , -0.707106781f , - 0.740951125f , -0.671558955f , - 0.773010453f , -0.634393284f , - 0.803207531f , -0.595699304f , - 0.831469612f , -0.555570233f , - 0.857728610f , -0.514102744f , - 0.881921264f , -0.471396737f , - 0.903989293f , -0.427555093f , - 0.923879533f , -0.382683432f , - 0.941544065f , -0.336889853f , - 0.956940336f , -0.290284677f , - 0.970031253f , -0.242980180f , - 0.980785280f , -0.195090322f , - 0.989176510f , -0.146730474f , - 0.995184727f , -0.098017140f , - 0.998795456f , -0.049067674f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 256 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_256[512] = { - 1.000000000f, 0.000000000f, - 0.999698819f, 0.024541229f, - 0.998795456f, 0.049067674f, - 0.997290457f, 0.073564564f, - 0.995184727f, 0.098017140f, - 0.992479535f, 0.122410675f, - 0.989176510f, 0.146730474f, - 0.985277642f, 0.170961889f, - 0.980785280f, 0.195090322f, - 0.975702130f, 0.219101240f, - 0.970031253f, 0.242980180f, - 0.963776066f, 0.266712757f, - 0.956940336f, 0.290284677f, - 0.949528181f, 0.313681740f, - 0.941544065f, 0.336889853f, - 0.932992799f, 0.359895037f, - 0.923879533f, 0.382683432f, - 0.914209756f, 0.405241314f, - 0.903989293f, 0.427555093f, - 0.893224301f, 0.449611330f, - 0.881921264f, 0.471396737f, - 0.870086991f, 0.492898192f, - 0.857728610f, 0.514102744f, - 0.844853565f, 0.534997620f, - 0.831469612f, 0.555570233f, - 0.817584813f, 0.575808191f, - 0.803207531f, 0.595699304f, - 0.788346428f, 0.615231591f, - 0.773010453f, 0.634393284f, - 0.757208847f, 0.653172843f, - 0.740951125f, 0.671558955f, - 0.724247083f, 0.689540545f, - 0.707106781f, 0.707106781f, - 0.689540545f, 0.724247083f, - 0.671558955f, 0.740951125f, - 0.653172843f, 0.757208847f, - 0.634393284f, 0.773010453f, - 0.615231591f, 0.788346428f, - 0.595699304f, 0.803207531f, - 0.575808191f, 0.817584813f, - 0.555570233f, 0.831469612f, - 0.534997620f, 0.844853565f, - 0.514102744f, 0.857728610f, - 0.492898192f, 0.870086991f, - 0.471396737f, 0.881921264f, - 0.449611330f, 0.893224301f, - 0.427555093f, 0.903989293f, - 0.405241314f, 0.914209756f, - 0.382683432f, 0.923879533f, - 0.359895037f, 0.932992799f, - 0.336889853f, 0.941544065f, - 0.313681740f, 0.949528181f, - 0.290284677f, 0.956940336f, - 0.266712757f, 0.963776066f, - 0.242980180f, 0.970031253f, - 0.219101240f, 0.975702130f, - 0.195090322f, 0.980785280f, - 0.170961889f, 0.985277642f, - 0.146730474f, 0.989176510f, - 0.122410675f, 0.992479535f, - 0.098017140f, 0.995184727f, - 0.073564564f, 0.997290457f, - 0.049067674f, 0.998795456f, - 0.024541229f, 0.999698819f, - 0.000000000f, 1.000000000f, - -0.024541229f, 0.999698819f, - -0.049067674f, 0.998795456f, - -0.073564564f, 0.997290457f, - -0.098017140f, 0.995184727f, - -0.122410675f, 0.992479535f, - -0.146730474f, 0.989176510f, - -0.170961889f, 0.985277642f, - -0.195090322f, 0.980785280f, - -0.219101240f, 0.975702130f, - -0.242980180f, 0.970031253f, - -0.266712757f, 0.963776066f, - -0.290284677f, 0.956940336f, - -0.313681740f, 0.949528181f, - -0.336889853f, 0.941544065f, - -0.359895037f, 0.932992799f, - -0.382683432f, 0.923879533f, - -0.405241314f, 0.914209756f, - -0.427555093f, 0.903989293f, - -0.449611330f, 0.893224301f, - -0.471396737f, 0.881921264f, - -0.492898192f, 0.870086991f, - -0.514102744f, 0.857728610f, - -0.534997620f, 0.844853565f, - -0.555570233f, 0.831469612f, - -0.575808191f, 0.817584813f, - -0.595699304f, 0.803207531f, - -0.615231591f, 0.788346428f, - -0.634393284f, 0.773010453f, - -0.653172843f, 0.757208847f, - -0.671558955f, 0.740951125f, - -0.689540545f, 0.724247083f, - -0.707106781f, 0.707106781f, - -0.724247083f, 0.689540545f, - -0.740951125f, 0.671558955f, - -0.757208847f, 0.653172843f, - -0.773010453f, 0.634393284f, - -0.788346428f, 0.615231591f, - -0.803207531f, 0.595699304f, - -0.817584813f, 0.575808191f, - -0.831469612f, 0.555570233f, - -0.844853565f, 0.534997620f, - -0.857728610f, 0.514102744f, - -0.870086991f, 0.492898192f, - -0.881921264f, 0.471396737f, - -0.893224301f, 0.449611330f, - -0.903989293f, 0.427555093f, - -0.914209756f, 0.405241314f, - -0.923879533f, 0.382683432f, - -0.932992799f, 0.359895037f, - -0.941544065f, 0.336889853f, - -0.949528181f, 0.313681740f, - -0.956940336f, 0.290284677f, - -0.963776066f, 0.266712757f, - -0.970031253f, 0.242980180f, - -0.975702130f, 0.219101240f, - -0.980785280f, 0.195090322f, - -0.985277642f, 0.170961889f, - -0.989176510f, 0.146730474f, - -0.992479535f, 0.122410675f, - -0.995184727f, 0.098017140f, - -0.997290457f, 0.073564564f, - -0.998795456f, 0.049067674f, - -0.999698819f, 0.024541229f, - -1.000000000f, 0.000000000f, - -0.999698819f, -0.024541229f, - -0.998795456f, -0.049067674f, - -0.997290457f, -0.073564564f, - -0.995184727f, -0.098017140f, - -0.992479535f, -0.122410675f, - -0.989176510f, -0.146730474f, - -0.985277642f, -0.170961889f, - -0.980785280f, -0.195090322f, - -0.975702130f, -0.219101240f, - -0.970031253f, -0.242980180f, - -0.963776066f, -0.266712757f, - -0.956940336f, -0.290284677f, - -0.949528181f, -0.313681740f, - -0.941544065f, -0.336889853f, - -0.932992799f, -0.359895037f, - -0.923879533f, -0.382683432f, - -0.914209756f, -0.405241314f, - -0.903989293f, -0.427555093f, - -0.893224301f, -0.449611330f, - -0.881921264f, -0.471396737f, - -0.870086991f, -0.492898192f, - -0.857728610f, -0.514102744f, - -0.844853565f, -0.534997620f, - -0.831469612f, -0.555570233f, - -0.817584813f, -0.575808191f, - -0.803207531f, -0.595699304f, - -0.788346428f, -0.615231591f, - -0.773010453f, -0.634393284f, - -0.757208847f, -0.653172843f, - -0.740951125f, -0.671558955f, - -0.724247083f, -0.689540545f, - -0.707106781f, -0.707106781f, - -0.689540545f, -0.724247083f, - -0.671558955f, -0.740951125f, - -0.653172843f, -0.757208847f, - -0.634393284f, -0.773010453f, - -0.615231591f, -0.788346428f, - -0.595699304f, -0.803207531f, - -0.575808191f, -0.817584813f, - -0.555570233f, -0.831469612f, - -0.534997620f, -0.844853565f, - -0.514102744f, -0.857728610f, - -0.492898192f, -0.870086991f, - -0.471396737f, -0.881921264f, - -0.449611330f, -0.893224301f, - -0.427555093f, -0.903989293f, - -0.405241314f, -0.914209756f, - -0.382683432f, -0.923879533f, - -0.359895037f, -0.932992799f, - -0.336889853f, -0.941544065f, - -0.313681740f, -0.949528181f, - -0.290284677f, -0.956940336f, - -0.266712757f, -0.963776066f, - -0.242980180f, -0.970031253f, - -0.219101240f, -0.975702130f, - -0.195090322f, -0.980785280f, - -0.170961889f, -0.985277642f, - -0.146730474f, -0.989176510f, - -0.122410675f, -0.992479535f, - -0.098017140f, -0.995184727f, - -0.073564564f, -0.997290457f, - -0.049067674f, -0.998795456f, - -0.024541229f, -0.999698819f, - -0.000000000f, -1.000000000f, - 0.024541229f, -0.999698819f, - 0.049067674f, -0.998795456f, - 0.073564564f, -0.997290457f, - 0.098017140f, -0.995184727f, - 0.122410675f, -0.992479535f, - 0.146730474f, -0.989176510f, - 0.170961889f, -0.985277642f, - 0.195090322f, -0.980785280f, - 0.219101240f, -0.975702130f, - 0.242980180f, -0.970031253f, - 0.266712757f, -0.963776066f, - 0.290284677f, -0.956940336f, - 0.313681740f, -0.949528181f, - 0.336889853f, -0.941544065f, - 0.359895037f, -0.932992799f, - 0.382683432f, -0.923879533f, - 0.405241314f, -0.914209756f, - 0.427555093f, -0.903989293f, - 0.449611330f, -0.893224301f, - 0.471396737f, -0.881921264f, - 0.492898192f, -0.870086991f, - 0.514102744f, -0.857728610f, - 0.534997620f, -0.844853565f, - 0.555570233f, -0.831469612f, - 0.575808191f, -0.817584813f, - 0.595699304f, -0.803207531f, - 0.615231591f, -0.788346428f, - 0.634393284f, -0.773010453f, - 0.653172843f, -0.757208847f, - 0.671558955f, -0.740951125f, - 0.689540545f, -0.724247083f, - 0.707106781f, -0.707106781f, - 0.724247083f, -0.689540545f, - 0.740951125f, -0.671558955f, - 0.757208847f, -0.653172843f, - 0.773010453f, -0.634393284f, - 0.788346428f, -0.615231591f, - 0.803207531f, -0.595699304f, - 0.817584813f, -0.575808191f, - 0.831469612f, -0.555570233f, - 0.844853565f, -0.534997620f, - 0.857728610f, -0.514102744f, - 0.870086991f, -0.492898192f, - 0.881921264f, -0.471396737f, - 0.893224301f, -0.449611330f, - 0.903989293f, -0.427555093f, - 0.914209756f, -0.405241314f, - 0.923879533f, -0.382683432f, - 0.932992799f, -0.359895037f, - 0.941544065f, -0.336889853f, - 0.949528181f, -0.313681740f, - 0.956940336f, -0.290284677f, - 0.963776066f, -0.266712757f, - 0.970031253f, -0.242980180f, - 0.975702130f, -0.219101240f, - 0.980785280f, -0.195090322f, - 0.985277642f, -0.170961889f, - 0.989176510f, -0.146730474f, - 0.992479535f, -0.122410675f, - 0.995184727f, -0.098017140f, - 0.997290457f, -0.073564564f, - 0.998795456f, -0.049067674f, - 0.999698819f, -0.024541229f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 512 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_512[1024] = { - 1.000000000f, 0.000000000f, - 0.999924702f, 0.012271538f, - 0.999698819f, 0.024541229f, - 0.999322385f, 0.036807223f, - 0.998795456f, 0.049067674f, - 0.998118113f, 0.061320736f, - 0.997290457f, 0.073564564f, - 0.996312612f, 0.085797312f, - 0.995184727f, 0.098017140f, - 0.993906970f, 0.110222207f, - 0.992479535f, 0.122410675f, - 0.990902635f, 0.134580709f, - 0.989176510f, 0.146730474f, - 0.987301418f, 0.158858143f, - 0.985277642f, 0.170961889f, - 0.983105487f, 0.183039888f, - 0.980785280f, 0.195090322f, - 0.978317371f, 0.207111376f, - 0.975702130f, 0.219101240f, - 0.972939952f, 0.231058108f, - 0.970031253f, 0.242980180f, - 0.966976471f, 0.254865660f, - 0.963776066f, 0.266712757f, - 0.960430519f, 0.278519689f, - 0.956940336f, 0.290284677f, - 0.953306040f, 0.302005949f, - 0.949528181f, 0.313681740f, - 0.945607325f, 0.325310292f, - 0.941544065f, 0.336889853f, - 0.937339012f, 0.348418680f, - 0.932992799f, 0.359895037f, - 0.928506080f, 0.371317194f, - 0.923879533f, 0.382683432f, - 0.919113852f, 0.393992040f, - 0.914209756f, 0.405241314f, - 0.909167983f, 0.416429560f, - 0.903989293f, 0.427555093f, - 0.898674466f, 0.438616239f, - 0.893224301f, 0.449611330f, - 0.887639620f, 0.460538711f, - 0.881921264f, 0.471396737f, - 0.876070094f, 0.482183772f, - 0.870086991f, 0.492898192f, - 0.863972856f, 0.503538384f, - 0.857728610f, 0.514102744f, - 0.851355193f, 0.524589683f, - 0.844853565f, 0.534997620f, - 0.838224706f, 0.545324988f, - 0.831469612f, 0.555570233f, - 0.824589303f, 0.565731811f, - 0.817584813f, 0.575808191f, - 0.810457198f, 0.585797857f, - 0.803207531f, 0.595699304f, - 0.795836905f, 0.605511041f, - 0.788346428f, 0.615231591f, - 0.780737229f, 0.624859488f, - 0.773010453f, 0.634393284f, - 0.765167266f, 0.643831543f, - 0.757208847f, 0.653172843f, - 0.749136395f, 0.662415778f, - 0.740951125f, 0.671558955f, - 0.732654272f, 0.680600998f, - 0.724247083f, 0.689540545f, - 0.715730825f, 0.698376249f, - 0.707106781f, 0.707106781f, - 0.698376249f, 0.715730825f, - 0.689540545f, 0.724247083f, - 0.680600998f, 0.732654272f, - 0.671558955f, 0.740951125f, - 0.662415778f, 0.749136395f, - 0.653172843f, 0.757208847f, - 0.643831543f, 0.765167266f, - 0.634393284f, 0.773010453f, - 0.624859488f, 0.780737229f, - 0.615231591f, 0.788346428f, - 0.605511041f, 0.795836905f, - 0.595699304f, 0.803207531f, - 0.585797857f, 0.810457198f, - 0.575808191f, 0.817584813f, - 0.565731811f, 0.824589303f, - 0.555570233f, 0.831469612f, - 0.545324988f, 0.838224706f, - 0.534997620f, 0.844853565f, - 0.524589683f, 0.851355193f, - 0.514102744f, 0.857728610f, - 0.503538384f, 0.863972856f, - 0.492898192f, 0.870086991f, - 0.482183772f, 0.876070094f, - 0.471396737f, 0.881921264f, - 0.460538711f, 0.887639620f, - 0.449611330f, 0.893224301f, - 0.438616239f, 0.898674466f, - 0.427555093f, 0.903989293f, - 0.416429560f, 0.909167983f, - 0.405241314f, 0.914209756f, - 0.393992040f, 0.919113852f, - 0.382683432f, 0.923879533f, - 0.371317194f, 0.928506080f, - 0.359895037f, 0.932992799f, - 0.348418680f, 0.937339012f, - 0.336889853f, 0.941544065f, - 0.325310292f, 0.945607325f, - 0.313681740f, 0.949528181f, - 0.302005949f, 0.953306040f, - 0.290284677f, 0.956940336f, - 0.278519689f, 0.960430519f, - 0.266712757f, 0.963776066f, - 0.254865660f, 0.966976471f, - 0.242980180f, 0.970031253f, - 0.231058108f, 0.972939952f, - 0.219101240f, 0.975702130f, - 0.207111376f, 0.978317371f, - 0.195090322f, 0.980785280f, - 0.183039888f, 0.983105487f, - 0.170961889f, 0.985277642f, - 0.158858143f, 0.987301418f, - 0.146730474f, 0.989176510f, - 0.134580709f, 0.990902635f, - 0.122410675f, 0.992479535f, - 0.110222207f, 0.993906970f, - 0.098017140f, 0.995184727f, - 0.085797312f, 0.996312612f, - 0.073564564f, 0.997290457f, - 0.061320736f, 0.998118113f, - 0.049067674f, 0.998795456f, - 0.036807223f, 0.999322385f, - 0.024541229f, 0.999698819f, - 0.012271538f, 0.999924702f, - 0.000000000f, 1.000000000f, - -0.012271538f, 0.999924702f, - -0.024541229f, 0.999698819f, - -0.036807223f, 0.999322385f, - -0.049067674f, 0.998795456f, - -0.061320736f, 0.998118113f, - -0.073564564f, 0.997290457f, - -0.085797312f, 0.996312612f, - -0.098017140f, 0.995184727f, - -0.110222207f, 0.993906970f, - -0.122410675f, 0.992479535f, - -0.134580709f, 0.990902635f, - -0.146730474f, 0.989176510f, - -0.158858143f, 0.987301418f, - -0.170961889f, 0.985277642f, - -0.183039888f, 0.983105487f, - -0.195090322f, 0.980785280f, - -0.207111376f, 0.978317371f, - -0.219101240f, 0.975702130f, - -0.231058108f, 0.972939952f, - -0.242980180f, 0.970031253f, - -0.254865660f, 0.966976471f, - -0.266712757f, 0.963776066f, - -0.278519689f, 0.960430519f, - -0.290284677f, 0.956940336f, - -0.302005949f, 0.953306040f, - -0.313681740f, 0.949528181f, - -0.325310292f, 0.945607325f, - -0.336889853f, 0.941544065f, - -0.348418680f, 0.937339012f, - -0.359895037f, 0.932992799f, - -0.371317194f, 0.928506080f, - -0.382683432f, 0.923879533f, - -0.393992040f, 0.919113852f, - -0.405241314f, 0.914209756f, - -0.416429560f, 0.909167983f, - -0.427555093f, 0.903989293f, - -0.438616239f, 0.898674466f, - -0.449611330f, 0.893224301f, - -0.460538711f, 0.887639620f, - -0.471396737f, 0.881921264f, - -0.482183772f, 0.876070094f, - -0.492898192f, 0.870086991f, - -0.503538384f, 0.863972856f, - -0.514102744f, 0.857728610f, - -0.524589683f, 0.851355193f, - -0.534997620f, 0.844853565f, - -0.545324988f, 0.838224706f, - -0.555570233f, 0.831469612f, - -0.565731811f, 0.824589303f, - -0.575808191f, 0.817584813f, - -0.585797857f, 0.810457198f, - -0.595699304f, 0.803207531f, - -0.605511041f, 0.795836905f, - -0.615231591f, 0.788346428f, - -0.624859488f, 0.780737229f, - -0.634393284f, 0.773010453f, - -0.643831543f, 0.765167266f, - -0.653172843f, 0.757208847f, - -0.662415778f, 0.749136395f, - -0.671558955f, 0.740951125f, - -0.680600998f, 0.732654272f, - -0.689540545f, 0.724247083f, - -0.698376249f, 0.715730825f, - -0.707106781f, 0.707106781f, - -0.715730825f, 0.698376249f, - -0.724247083f, 0.689540545f, - -0.732654272f, 0.680600998f, - -0.740951125f, 0.671558955f, - -0.749136395f, 0.662415778f, - -0.757208847f, 0.653172843f, - -0.765167266f, 0.643831543f, - -0.773010453f, 0.634393284f, - -0.780737229f, 0.624859488f, - -0.788346428f, 0.615231591f, - -0.795836905f, 0.605511041f, - -0.803207531f, 0.595699304f, - -0.810457198f, 0.585797857f, - -0.817584813f, 0.575808191f, - -0.824589303f, 0.565731811f, - -0.831469612f, 0.555570233f, - -0.838224706f, 0.545324988f, - -0.844853565f, 0.534997620f, - -0.851355193f, 0.524589683f, - -0.857728610f, 0.514102744f, - -0.863972856f, 0.503538384f, - -0.870086991f, 0.492898192f, - -0.876070094f, 0.482183772f, - -0.881921264f, 0.471396737f, - -0.887639620f, 0.460538711f, - -0.893224301f, 0.449611330f, - -0.898674466f, 0.438616239f, - -0.903989293f, 0.427555093f, - -0.909167983f, 0.416429560f, - -0.914209756f, 0.405241314f, - -0.919113852f, 0.393992040f, - -0.923879533f, 0.382683432f, - -0.928506080f, 0.371317194f, - -0.932992799f, 0.359895037f, - -0.937339012f, 0.348418680f, - -0.941544065f, 0.336889853f, - -0.945607325f, 0.325310292f, - -0.949528181f, 0.313681740f, - -0.953306040f, 0.302005949f, - -0.956940336f, 0.290284677f, - -0.960430519f, 0.278519689f, - -0.963776066f, 0.266712757f, - -0.966976471f, 0.254865660f, - -0.970031253f, 0.242980180f, - -0.972939952f, 0.231058108f, - -0.975702130f, 0.219101240f, - -0.978317371f, 0.207111376f, - -0.980785280f, 0.195090322f, - -0.983105487f, 0.183039888f, - -0.985277642f, 0.170961889f, - -0.987301418f, 0.158858143f, - -0.989176510f, 0.146730474f, - -0.990902635f, 0.134580709f, - -0.992479535f, 0.122410675f, - -0.993906970f, 0.110222207f, - -0.995184727f, 0.098017140f, - -0.996312612f, 0.085797312f, - -0.997290457f, 0.073564564f, - -0.998118113f, 0.061320736f, - -0.998795456f, 0.049067674f, - -0.999322385f, 0.036807223f, - -0.999698819f, 0.024541229f, - -0.999924702f, 0.012271538f, - -1.000000000f, 0.000000000f, - -0.999924702f, -0.012271538f, - -0.999698819f, -0.024541229f, - -0.999322385f, -0.036807223f, - -0.998795456f, -0.049067674f, - -0.998118113f, -0.061320736f, - -0.997290457f, -0.073564564f, - -0.996312612f, -0.085797312f, - -0.995184727f, -0.098017140f, - -0.993906970f, -0.110222207f, - -0.992479535f, -0.122410675f, - -0.990902635f, -0.134580709f, - -0.989176510f, -0.146730474f, - -0.987301418f, -0.158858143f, - -0.985277642f, -0.170961889f, - -0.983105487f, -0.183039888f, - -0.980785280f, -0.195090322f, - -0.978317371f, -0.207111376f, - -0.975702130f, -0.219101240f, - -0.972939952f, -0.231058108f, - -0.970031253f, -0.242980180f, - -0.966976471f, -0.254865660f, - -0.963776066f, -0.266712757f, - -0.960430519f, -0.278519689f, - -0.956940336f, -0.290284677f, - -0.953306040f, -0.302005949f, - -0.949528181f, -0.313681740f, - -0.945607325f, -0.325310292f, - -0.941544065f, -0.336889853f, - -0.937339012f, -0.348418680f, - -0.932992799f, -0.359895037f, - -0.928506080f, -0.371317194f, - -0.923879533f, -0.382683432f, - -0.919113852f, -0.393992040f, - -0.914209756f, -0.405241314f, - -0.909167983f, -0.416429560f, - -0.903989293f, -0.427555093f, - -0.898674466f, -0.438616239f, - -0.893224301f, -0.449611330f, - -0.887639620f, -0.460538711f, - -0.881921264f, -0.471396737f, - -0.876070094f, -0.482183772f, - -0.870086991f, -0.492898192f, - -0.863972856f, -0.503538384f, - -0.857728610f, -0.514102744f, - -0.851355193f, -0.524589683f, - -0.844853565f, -0.534997620f, - -0.838224706f, -0.545324988f, - -0.831469612f, -0.555570233f, - -0.824589303f, -0.565731811f, - -0.817584813f, -0.575808191f, - -0.810457198f, -0.585797857f, - -0.803207531f, -0.595699304f, - -0.795836905f, -0.605511041f, - -0.788346428f, -0.615231591f, - -0.780737229f, -0.624859488f, - -0.773010453f, -0.634393284f, - -0.765167266f, -0.643831543f, - -0.757208847f, -0.653172843f, - -0.749136395f, -0.662415778f, - -0.740951125f, -0.671558955f, - -0.732654272f, -0.680600998f, - -0.724247083f, -0.689540545f, - -0.715730825f, -0.698376249f, - -0.707106781f, -0.707106781f, - -0.698376249f, -0.715730825f, - -0.689540545f, -0.724247083f, - -0.680600998f, -0.732654272f, - -0.671558955f, -0.740951125f, - -0.662415778f, -0.749136395f, - -0.653172843f, -0.757208847f, - -0.643831543f, -0.765167266f, - -0.634393284f, -0.773010453f, - -0.624859488f, -0.780737229f, - -0.615231591f, -0.788346428f, - -0.605511041f, -0.795836905f, - -0.595699304f, -0.803207531f, - -0.585797857f, -0.810457198f, - -0.575808191f, -0.817584813f, - -0.565731811f, -0.824589303f, - -0.555570233f, -0.831469612f, - -0.545324988f, -0.838224706f, - -0.534997620f, -0.844853565f, - -0.524589683f, -0.851355193f, - -0.514102744f, -0.857728610f, - -0.503538384f, -0.863972856f, - -0.492898192f, -0.870086991f, - -0.482183772f, -0.876070094f, - -0.471396737f, -0.881921264f, - -0.460538711f, -0.887639620f, - -0.449611330f, -0.893224301f, - -0.438616239f, -0.898674466f, - -0.427555093f, -0.903989293f, - -0.416429560f, -0.909167983f, - -0.405241314f, -0.914209756f, - -0.393992040f, -0.919113852f, - -0.382683432f, -0.923879533f, - -0.371317194f, -0.928506080f, - -0.359895037f, -0.932992799f, - -0.348418680f, -0.937339012f, - -0.336889853f, -0.941544065f, - -0.325310292f, -0.945607325f, - -0.313681740f, -0.949528181f, - -0.302005949f, -0.953306040f, - -0.290284677f, -0.956940336f, - -0.278519689f, -0.960430519f, - -0.266712757f, -0.963776066f, - -0.254865660f, -0.966976471f, - -0.242980180f, -0.970031253f, - -0.231058108f, -0.972939952f, - -0.219101240f, -0.975702130f, - -0.207111376f, -0.978317371f, - -0.195090322f, -0.980785280f, - -0.183039888f, -0.983105487f, - -0.170961889f, -0.985277642f, - -0.158858143f, -0.987301418f, - -0.146730474f, -0.989176510f, - -0.134580709f, -0.990902635f, - -0.122410675f, -0.992479535f, - -0.110222207f, -0.993906970f, - -0.098017140f, -0.995184727f, - -0.085797312f, -0.996312612f, - -0.073564564f, -0.997290457f, - -0.061320736f, -0.998118113f, - -0.049067674f, -0.998795456f, - -0.036807223f, -0.999322385f, - -0.024541229f, -0.999698819f, - -0.012271538f, -0.999924702f, - -0.000000000f, -1.000000000f, - 0.012271538f, -0.999924702f, - 0.024541229f, -0.999698819f, - 0.036807223f, -0.999322385f, - 0.049067674f, -0.998795456f, - 0.061320736f, -0.998118113f, - 0.073564564f, -0.997290457f, - 0.085797312f, -0.996312612f, - 0.098017140f, -0.995184727f, - 0.110222207f, -0.993906970f, - 0.122410675f, -0.992479535f, - 0.134580709f, -0.990902635f, - 0.146730474f, -0.989176510f, - 0.158858143f, -0.987301418f, - 0.170961889f, -0.985277642f, - 0.183039888f, -0.983105487f, - 0.195090322f, -0.980785280f, - 0.207111376f, -0.978317371f, - 0.219101240f, -0.975702130f, - 0.231058108f, -0.972939952f, - 0.242980180f, -0.970031253f, - 0.254865660f, -0.966976471f, - 0.266712757f, -0.963776066f, - 0.278519689f, -0.960430519f, - 0.290284677f, -0.956940336f, - 0.302005949f, -0.953306040f, - 0.313681740f, -0.949528181f, - 0.325310292f, -0.945607325f, - 0.336889853f, -0.941544065f, - 0.348418680f, -0.937339012f, - 0.359895037f, -0.932992799f, - 0.371317194f, -0.928506080f, - 0.382683432f, -0.923879533f, - 0.393992040f, -0.919113852f, - 0.405241314f, -0.914209756f, - 0.416429560f, -0.909167983f, - 0.427555093f, -0.903989293f, - 0.438616239f, -0.898674466f, - 0.449611330f, -0.893224301f, - 0.460538711f, -0.887639620f, - 0.471396737f, -0.881921264f, - 0.482183772f, -0.876070094f, - 0.492898192f, -0.870086991f, - 0.503538384f, -0.863972856f, - 0.514102744f, -0.857728610f, - 0.524589683f, -0.851355193f, - 0.534997620f, -0.844853565f, - 0.545324988f, -0.838224706f, - 0.555570233f, -0.831469612f, - 0.565731811f, -0.824589303f, - 0.575808191f, -0.817584813f, - 0.585797857f, -0.810457198f, - 0.595699304f, -0.803207531f, - 0.605511041f, -0.795836905f, - 0.615231591f, -0.788346428f, - 0.624859488f, -0.780737229f, - 0.634393284f, -0.773010453f, - 0.643831543f, -0.765167266f, - 0.653172843f, -0.757208847f, - 0.662415778f, -0.749136395f, - 0.671558955f, -0.740951125f, - 0.680600998f, -0.732654272f, - 0.689540545f, -0.724247083f, - 0.698376249f, -0.715730825f, - 0.707106781f, -0.707106781f, - 0.715730825f, -0.698376249f, - 0.724247083f, -0.689540545f, - 0.732654272f, -0.680600998f, - 0.740951125f, -0.671558955f, - 0.749136395f, -0.662415778f, - 0.757208847f, -0.653172843f, - 0.765167266f, -0.643831543f, - 0.773010453f, -0.634393284f, - 0.780737229f, -0.624859488f, - 0.788346428f, -0.615231591f, - 0.795836905f, -0.605511041f, - 0.803207531f, -0.595699304f, - 0.810457198f, -0.585797857f, - 0.817584813f, -0.575808191f, - 0.824589303f, -0.565731811f, - 0.831469612f, -0.555570233f, - 0.838224706f, -0.545324988f, - 0.844853565f, -0.534997620f, - 0.851355193f, -0.524589683f, - 0.857728610f, -0.514102744f, - 0.863972856f, -0.503538384f, - 0.870086991f, -0.492898192f, - 0.876070094f, -0.482183772f, - 0.881921264f, -0.471396737f, - 0.887639620f, -0.460538711f, - 0.893224301f, -0.449611330f, - 0.898674466f, -0.438616239f, - 0.903989293f, -0.427555093f, - 0.909167983f, -0.416429560f, - 0.914209756f, -0.405241314f, - 0.919113852f, -0.393992040f, - 0.923879533f, -0.382683432f, - 0.928506080f, -0.371317194f, - 0.932992799f, -0.359895037f, - 0.937339012f, -0.348418680f, - 0.941544065f, -0.336889853f, - 0.945607325f, -0.325310292f, - 0.949528181f, -0.313681740f, - 0.953306040f, -0.302005949f, - 0.956940336f, -0.290284677f, - 0.960430519f, -0.278519689f, - 0.963776066f, -0.266712757f, - 0.966976471f, -0.254865660f, - 0.970031253f, -0.242980180f, - 0.972939952f, -0.231058108f, - 0.975702130f, -0.219101240f, - 0.978317371f, -0.207111376f, - 0.980785280f, -0.195090322f, - 0.983105487f, -0.183039888f, - 0.985277642f, -0.170961889f, - 0.987301418f, -0.158858143f, - 0.989176510f, -0.146730474f, - 0.990902635f, -0.134580709f, - 0.992479535f, -0.122410675f, - 0.993906970f, -0.110222207f, - 0.995184727f, -0.098017140f, - 0.996312612f, -0.085797312f, - 0.997290457f, -0.073564564f, - 0.998118113f, -0.061320736f, - 0.998795456f, -0.049067674f, - 0.999322385f, -0.036807223f, - 0.999698819f, -0.024541229f, - 0.999924702f, -0.012271538f -}; -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 1024 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_1024[2048] = { -1.000000000f , 0.000000000f , -0.999981175f , 0.006135885f , -0.999924702f , 0.012271538f , -0.999830582f , 0.018406730f , -0.999698819f , 0.024541229f , -0.999529418f , 0.030674803f , -0.999322385f , 0.036807223f , -0.999077728f , 0.042938257f , -0.998795456f , 0.049067674f , -0.998475581f , 0.055195244f , -0.998118113f , 0.061320736f , -0.997723067f , 0.067443920f , -0.997290457f , 0.073564564f , -0.996820299f , 0.079682438f , -0.996312612f , 0.085797312f , -0.995767414f , 0.091908956f , -0.995184727f , 0.098017140f , -0.994564571f , 0.104121634f , -0.993906970f , 0.110222207f , -0.993211949f , 0.116318631f , -0.992479535f , 0.122410675f , -0.991709754f , 0.128498111f , -0.990902635f , 0.134580709f , -0.990058210f , 0.140658239f , -0.989176510f , 0.146730474f , -0.988257568f , 0.152797185f , -0.987301418f , 0.158858143f , -0.986308097f , 0.164913120f , -0.985277642f , 0.170961889f , -0.984210092f , 0.177004220f , -0.983105487f , 0.183039888f , -0.981963869f , 0.189068664f , -0.980785280f , 0.195090322f , -0.979569766f , 0.201104635f , -0.978317371f , 0.207111376f , -0.977028143f , 0.213110320f , -0.975702130f , 0.219101240f , -0.974339383f , 0.225083911f , -0.972939952f , 0.231058108f , -0.971503891f , 0.237023606f , -0.970031253f , 0.242980180f , -0.968522094f , 0.248927606f , -0.966976471f , 0.254865660f , -0.965394442f , 0.260794118f , -0.963776066f , 0.266712757f , -0.962121404f , 0.272621355f , -0.960430519f , 0.278519689f , -0.958703475f , 0.284407537f , -0.956940336f , 0.290284677f , -0.955141168f , 0.296150888f , -0.953306040f , 0.302005949f , -0.951435021f , 0.307849640f , -0.949528181f , 0.313681740f , -0.947585591f , 0.319502031f , -0.945607325f , 0.325310292f , -0.943593458f , 0.331106306f , -0.941544065f , 0.336889853f , -0.939459224f , 0.342660717f , -0.937339012f , 0.348418680f , -0.935183510f , 0.354163525f , -0.932992799f , 0.359895037f , -0.930766961f , 0.365612998f , -0.928506080f , 0.371317194f , -0.926210242f , 0.377007410f , -0.923879533f , 0.382683432f , -0.921514039f , 0.388345047f , -0.919113852f , 0.393992040f , -0.916679060f , 0.399624200f , -0.914209756f , 0.405241314f , -0.911706032f , 0.410843171f , -0.909167983f , 0.416429560f , -0.906595705f , 0.422000271f , -0.903989293f , 0.427555093f , -0.901348847f , 0.433093819f , -0.898674466f , 0.438616239f , -0.895966250f , 0.444122145f , -0.893224301f , 0.449611330f , -0.890448723f , 0.455083587f , -0.887639620f , 0.460538711f , -0.884797098f , 0.465976496f , -0.881921264f , 0.471396737f , -0.879012226f , 0.476799230f , -0.876070094f , 0.482183772f , -0.873094978f , 0.487550160f , -0.870086991f , 0.492898192f , -0.867046246f , 0.498227667f , -0.863972856f , 0.503538384f , -0.860866939f , 0.508830143f , -0.857728610f , 0.514102744f , -0.854557988f , 0.519355990f , -0.851355193f , 0.524589683f , -0.848120345f , 0.529803625f , -0.844853565f , 0.534997620f , -0.841554977f , 0.540171473f , -0.838224706f , 0.545324988f , -0.834862875f , 0.550457973f , -0.831469612f , 0.555570233f , -0.828045045f , 0.560661576f , -0.824589303f , 0.565731811f , -0.821102515f , 0.570780746f , -0.817584813f , 0.575808191f , -0.814036330f , 0.580813958f , -0.810457198f , 0.585797857f , -0.806847554f , 0.590759702f , -0.803207531f , 0.595699304f , -0.799537269f , 0.600616479f , -0.795836905f , 0.605511041f , -0.792106577f , 0.610382806f , -0.788346428f , 0.615231591f , -0.784556597f , 0.620057212f , -0.780737229f , 0.624859488f , -0.776888466f , 0.629638239f , -0.773010453f , 0.634393284f , -0.769103338f , 0.639124445f , -0.765167266f , 0.643831543f , -0.761202385f , 0.648514401f , -0.757208847f , 0.653172843f , -0.753186799f , 0.657806693f , -0.749136395f , 0.662415778f , -0.745057785f , 0.666999922f , -0.740951125f , 0.671558955f , -0.736816569f , 0.676092704f , -0.732654272f , 0.680600998f , -0.728464390f , 0.685083668f , -0.724247083f , 0.689540545f , -0.720002508f , 0.693971461f , -0.715730825f , 0.698376249f , -0.711432196f , 0.702754744f , -0.707106781f , 0.707106781f , -0.702754744f , 0.711432196f , -0.698376249f , 0.715730825f , -0.693971461f , 0.720002508f , -0.689540545f , 0.724247083f , -0.685083668f , 0.728464390f , -0.680600998f , 0.732654272f , -0.676092704f , 0.736816569f , -0.671558955f , 0.740951125f , -0.666999922f , 0.745057785f , -0.662415778f , 0.749136395f , -0.657806693f , 0.753186799f , -0.653172843f , 0.757208847f , -0.648514401f , 0.761202385f , -0.643831543f , 0.765167266f , -0.639124445f , 0.769103338f , -0.634393284f , 0.773010453f , -0.629638239f , 0.776888466f , -0.624859488f , 0.780737229f , -0.620057212f , 0.784556597f , -0.615231591f , 0.788346428f , -0.610382806f , 0.792106577f , -0.605511041f , 0.795836905f , -0.600616479f , 0.799537269f , -0.595699304f , 0.803207531f , -0.590759702f , 0.806847554f , -0.585797857f , 0.810457198f , -0.580813958f , 0.814036330f , -0.575808191f , 0.817584813f , -0.570780746f , 0.821102515f , -0.565731811f , 0.824589303f , -0.560661576f , 0.828045045f , -0.555570233f , 0.831469612f , -0.550457973f , 0.834862875f , -0.545324988f , 0.838224706f , -0.540171473f , 0.841554977f , -0.534997620f , 0.844853565f , -0.529803625f , 0.848120345f , -0.524589683f , 0.851355193f , -0.519355990f , 0.854557988f , -0.514102744f , 0.857728610f , -0.508830143f , 0.860866939f , -0.503538384f , 0.863972856f , -0.498227667f , 0.867046246f , -0.492898192f , 0.870086991f , -0.487550160f , 0.873094978f , -0.482183772f , 0.876070094f , -0.476799230f , 0.879012226f , -0.471396737f , 0.881921264f , -0.465976496f , 0.884797098f , -0.460538711f , 0.887639620f , -0.455083587f , 0.890448723f , -0.449611330f , 0.893224301f , -0.444122145f , 0.895966250f , -0.438616239f , 0.898674466f , -0.433093819f , 0.901348847f , -0.427555093f , 0.903989293f , -0.422000271f , 0.906595705f , -0.416429560f , 0.909167983f , -0.410843171f , 0.911706032f , -0.405241314f , 0.914209756f , -0.399624200f , 0.916679060f , -0.393992040f , 0.919113852f , -0.388345047f , 0.921514039f , -0.382683432f , 0.923879533f , -0.377007410f , 0.926210242f , -0.371317194f , 0.928506080f , -0.365612998f , 0.930766961f , -0.359895037f , 0.932992799f , -0.354163525f , 0.935183510f , -0.348418680f , 0.937339012f , -0.342660717f , 0.939459224f , -0.336889853f , 0.941544065f , -0.331106306f , 0.943593458f , -0.325310292f , 0.945607325f , -0.319502031f , 0.947585591f , -0.313681740f , 0.949528181f , -0.307849640f , 0.951435021f , -0.302005949f , 0.953306040f , -0.296150888f , 0.955141168f , -0.290284677f , 0.956940336f , -0.284407537f , 0.958703475f , -0.278519689f , 0.960430519f , -0.272621355f , 0.962121404f , -0.266712757f , 0.963776066f , -0.260794118f , 0.965394442f , -0.254865660f , 0.966976471f , -0.248927606f , 0.968522094f , -0.242980180f , 0.970031253f , -0.237023606f , 0.971503891f , -0.231058108f , 0.972939952f , -0.225083911f , 0.974339383f , -0.219101240f , 0.975702130f , -0.213110320f , 0.977028143f , -0.207111376f , 0.978317371f , -0.201104635f , 0.979569766f , -0.195090322f , 0.980785280f , -0.189068664f , 0.981963869f , -0.183039888f , 0.983105487f , -0.177004220f , 0.984210092f , -0.170961889f , 0.985277642f , -0.164913120f , 0.986308097f , -0.158858143f , 0.987301418f , -0.152797185f , 0.988257568f , -0.146730474f , 0.989176510f , -0.140658239f , 0.990058210f , -0.134580709f , 0.990902635f , -0.128498111f , 0.991709754f , -0.122410675f , 0.992479535f , -0.116318631f , 0.993211949f , -0.110222207f , 0.993906970f , -0.104121634f , 0.994564571f , -0.098017140f , 0.995184727f , -0.091908956f , 0.995767414f , -0.085797312f , 0.996312612f , -0.079682438f , 0.996820299f , -0.073564564f , 0.997290457f , -0.067443920f , 0.997723067f , -0.061320736f , 0.998118113f , -0.055195244f , 0.998475581f , -0.049067674f , 0.998795456f , -0.042938257f , 0.999077728f , -0.036807223f , 0.999322385f , -0.030674803f , 0.999529418f , -0.024541229f , 0.999698819f , -0.018406730f , 0.999830582f , -0.012271538f , 0.999924702f , -0.006135885f , 0.999981175f , -0.000000000f , 1.000000000f , --0.006135885f , 0.999981175f , --0.012271538f , 0.999924702f , --0.018406730f , 0.999830582f , --0.024541229f , 0.999698819f , --0.030674803f , 0.999529418f , --0.036807223f , 0.999322385f , --0.042938257f , 0.999077728f , --0.049067674f , 0.998795456f , --0.055195244f , 0.998475581f , --0.061320736f , 0.998118113f , --0.067443920f , 0.997723067f , --0.073564564f , 0.997290457f , --0.079682438f , 0.996820299f , --0.085797312f , 0.996312612f , --0.091908956f , 0.995767414f , --0.098017140f , 0.995184727f , --0.104121634f , 0.994564571f , --0.110222207f , 0.993906970f , --0.116318631f , 0.993211949f , --0.122410675f , 0.992479535f , --0.128498111f , 0.991709754f , --0.134580709f , 0.990902635f , --0.140658239f , 0.990058210f , --0.146730474f , 0.989176510f , --0.152797185f , 0.988257568f , --0.158858143f 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--0.170961889f , -0.985277642f , --0.164913120f , -0.986308097f , --0.158858143f , -0.987301418f , --0.152797185f , -0.988257568f , --0.146730474f , -0.989176510f , --0.140658239f , -0.990058210f , --0.134580709f , -0.990902635f , --0.128498111f , -0.991709754f , --0.122410675f , -0.992479535f , --0.116318631f , -0.993211949f , --0.110222207f , -0.993906970f , --0.104121634f , -0.994564571f , --0.098017140f , -0.995184727f , --0.091908956f , -0.995767414f , --0.085797312f , -0.996312612f , --0.079682438f , -0.996820299f , --0.073564564f , -0.997290457f , --0.067443920f , -0.997723067f , --0.061320736f , -0.998118113f , --0.055195244f , -0.998475581f , --0.049067674f , -0.998795456f , --0.042938257f , -0.999077728f , --0.036807223f , -0.999322385f , --0.030674803f , -0.999529418f , --0.024541229f , -0.999698819f , --0.018406730f , -0.999830582f , --0.012271538f , -0.999924702f , --0.006135885f , -0.999981175f , --0.000000000f , -1.000000000f , -0.006135885f , -0.999981175f , -0.012271538f , -0.999924702f , -0.018406730f , -0.999830582f , -0.024541229f , -0.999698819f , -0.030674803f , -0.999529418f , -0.036807223f , -0.999322385f , -0.042938257f , -0.999077728f , -0.049067674f , -0.998795456f , -0.055195244f , -0.998475581f , -0.061320736f , -0.998118113f , -0.067443920f , -0.997723067f , -0.073564564f , -0.997290457f , -0.079682438f , -0.996820299f , -0.085797312f , -0.996312612f , -0.091908956f , -0.995767414f , -0.098017140f , -0.995184727f , -0.104121634f , -0.994564571f , -0.110222207f , -0.993906970f , -0.116318631f , -0.993211949f , -0.122410675f , -0.992479535f , -0.128498111f , -0.991709754f , -0.134580709f , -0.990902635f , -0.140658239f , -0.990058210f , -0.146730474f , -0.989176510f , -0.152797185f , -0.988257568f , -0.158858143f , -0.987301418f , -0.164913120f , -0.986308097f , -0.170961889f , -0.985277642f , -0.177004220f , -0.984210092f , -0.183039888f , -0.983105487f , -0.189068664f , -0.981963869f , -0.195090322f , -0.980785280f , -0.201104635f , -0.979569766f , -0.207111376f , -0.978317371f , -0.213110320f , -0.977028143f , -0.219101240f , -0.975702130f , -0.225083911f , -0.974339383f , -0.231058108f , -0.972939952f , -0.237023606f , -0.971503891f , -0.242980180f , -0.970031253f , -0.248927606f , -0.968522094f , -0.254865660f , -0.966976471f , -0.260794118f , -0.965394442f , -0.266712757f , -0.963776066f , -0.272621355f , -0.962121404f , -0.278519689f , -0.960430519f , -0.284407537f , -0.958703475f , -0.290284677f , -0.956940336f , -0.296150888f , -0.955141168f , -0.302005949f , -0.953306040f , -0.307849640f , -0.951435021f , -0.313681740f , -0.949528181f , -0.319502031f , -0.947585591f , -0.325310292f , -0.945607325f , -0.331106306f , -0.943593458f , -0.336889853f , -0.941544065f , -0.342660717f , -0.939459224f , -0.348418680f , -0.937339012f , -0.354163525f , -0.935183510f , -0.359895037f , -0.932992799f , -0.365612998f , -0.930766961f , -0.371317194f , -0.928506080f , -0.377007410f , -0.926210242f , -0.382683432f , -0.923879533f , -0.388345047f , -0.921514039f , -0.393992040f , -0.919113852f , -0.399624200f , -0.916679060f , -0.405241314f , -0.914209756f , -0.410843171f , -0.911706032f , -0.416429560f , -0.909167983f , -0.422000271f , -0.906595705f , -0.427555093f , -0.903989293f , -0.433093819f , -0.901348847f , -0.438616239f , -0.898674466f , -0.444122145f , -0.895966250f , -0.449611330f , -0.893224301f , -0.455083587f , -0.890448723f , -0.460538711f , -0.887639620f , -0.465976496f , -0.884797098f , -0.471396737f , -0.881921264f , -0.476799230f , -0.879012226f , -0.482183772f , -0.876070094f , -0.487550160f , -0.873094978f , -0.492898192f , -0.870086991f , -0.498227667f , -0.867046246f , -0.503538384f , -0.863972856f , -0.508830143f , -0.860866939f , -0.514102744f , -0.857728610f , -0.519355990f , -0.854557988f , -0.524589683f , -0.851355193f , -0.529803625f , -0.848120345f , -0.534997620f , -0.844853565f , -0.540171473f , -0.841554977f , -0.545324988f , -0.838224706f , -0.550457973f , -0.834862875f , -0.555570233f , -0.831469612f , -0.560661576f , -0.828045045f , -0.565731811f , -0.824589303f , -0.570780746f , -0.821102515f , -0.575808191f , -0.817584813f , -0.580813958f , -0.814036330f , -0.585797857f , -0.810457198f , -0.590759702f , -0.806847554f , -0.595699304f , -0.803207531f , -0.600616479f , -0.799537269f , -0.605511041f , -0.795836905f , -0.610382806f , -0.792106577f , -0.615231591f , -0.788346428f , -0.620057212f , -0.784556597f , -0.624859488f , -0.780737229f , -0.629638239f , -0.776888466f , -0.634393284f , -0.773010453f , -0.639124445f , -0.769103338f , -0.643831543f , -0.765167266f , -0.648514401f , -0.761202385f , -0.653172843f , -0.757208847f , -0.657806693f , -0.753186799f , -0.662415778f , -0.749136395f , -0.666999922f , -0.745057785f , -0.671558955f , -0.740951125f , -0.676092704f , -0.736816569f , -0.680600998f , -0.732654272f , -0.685083668f , -0.728464390f , -0.689540545f , -0.724247083f , -0.693971461f , -0.720002508f , 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-0.821102515f , -0.570780746f , -0.824589303f , -0.565731811f , -0.828045045f , -0.560661576f , -0.831469612f , -0.555570233f , -0.834862875f , -0.550457973f , -0.838224706f , -0.545324988f , -0.841554977f , -0.540171473f , -0.844853565f , -0.534997620f , -0.848120345f , -0.529803625f , -0.851355193f , -0.524589683f , -0.854557988f , -0.519355990f , -0.857728610f , -0.514102744f , -0.860866939f , -0.508830143f , -0.863972856f , -0.503538384f , -0.867046246f , -0.498227667f , -0.870086991f , -0.492898192f , -0.873094978f , -0.487550160f , -0.876070094f , -0.482183772f , -0.879012226f , -0.476799230f , -0.881921264f , -0.471396737f , -0.884797098f , -0.465976496f , -0.887639620f , -0.460538711f , -0.890448723f , -0.455083587f , -0.893224301f , -0.449611330f , -0.895966250f , -0.444122145f , -0.898674466f , -0.438616239f , -0.901348847f , -0.433093819f , -0.903989293f , -0.427555093f , -0.906595705f , -0.422000271f , -0.909167983f , -0.416429560f , -0.911706032f , -0.410843171f , -0.914209756f , -0.405241314f , -0.916679060f , -0.399624200f , -0.919113852f , -0.393992040f , -0.921514039f , -0.388345047f , -0.923879533f , -0.382683432f , -0.926210242f , -0.377007410f , -0.928506080f , -0.371317194f , -0.930766961f , -0.365612998f , -0.932992799f , -0.359895037f , -0.935183510f , -0.354163525f , -0.937339012f , -0.348418680f , -0.939459224f , -0.342660717f , -0.941544065f , -0.336889853f , -0.943593458f , -0.331106306f , -0.945607325f , -0.325310292f , -0.947585591f , -0.319502031f , -0.949528181f , -0.313681740f , -0.951435021f , -0.307849640f , -0.953306040f , -0.302005949f , -0.955141168f , -0.296150888f , -0.956940336f , -0.290284677f , -0.958703475f , -0.284407537f , -0.960430519f , -0.278519689f , -0.962121404f , -0.272621355f , -0.963776066f , -0.266712757f , -0.965394442f , -0.260794118f , -0.966976471f , -0.254865660f , -0.968522094f , -0.248927606f , -0.970031253f , -0.242980180f , -0.971503891f , -0.237023606f , -0.972939952f , -0.231058108f , -0.974339383f , -0.225083911f , -0.975702130f , -0.219101240f , -0.977028143f , -0.213110320f , -0.978317371f , -0.207111376f , -0.979569766f , -0.201104635f , -0.980785280f , -0.195090322f , -0.981963869f , -0.189068664f , -0.983105487f , -0.183039888f , -0.984210092f , -0.177004220f , -0.985277642f , -0.170961889f , -0.986308097f , -0.164913120f , -0.987301418f , -0.158858143f , -0.988257568f , -0.152797185f , -0.989176510f , -0.146730474f , -0.990058210f , -0.140658239f , -0.990902635f , -0.134580709f , -0.991709754f , -0.128498111f , -0.992479535f , -0.122410675f , -0.993211949f , -0.116318631f , -0.993906970f , -0.110222207f , -0.994564571f , -0.104121634f , -0.995184727f , -0.098017140f , -0.995767414f , -0.091908956f , -0.996312612f , -0.085797312f , -0.996820299f , -0.079682438f , -0.997290457f , -0.073564564f , -0.997723067f , -0.067443920f , -0.998118113f , -0.061320736f , -0.998475581f , -0.055195244f , -0.998795456f , -0.049067674f , -0.999077728f , -0.042938257f , -0.999322385f , -0.036807223f , -0.999529418f , -0.030674803f , -0.999698819f , -0.024541229f , -0.999830582f , -0.018406730f , -0.999924702f , -0.012271538f , -0.999981175f , -0.006135885f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 2048 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_2048[4096] = { - 1.000000000f, 0.000000000f, - 0.999995294f, 0.003067957f, - 0.999981175f, 0.006135885f, - 0.999957645f, 0.009203755f, - 0.999924702f, 0.012271538f, - 0.999882347f, 0.015339206f, - 0.999830582f, 0.018406730f, - 0.999769405f, 0.021474080f, - 0.999698819f, 0.024541229f, - 0.999618822f, 0.027608146f, - 0.999529418f, 0.030674803f, - 0.999430605f, 0.033741172f, - 0.999322385f, 0.036807223f, - 0.999204759f, 0.039872928f, - 0.999077728f, 0.042938257f, - 0.998941293f, 0.046003182f, - 0.998795456f, 0.049067674f, - 0.998640218f, 0.052131705f, - 0.998475581f, 0.055195244f, - 0.998301545f, 0.058258265f, - 0.998118113f, 0.061320736f, - 0.997925286f, 0.064382631f, - 0.997723067f, 0.067443920f, - 0.997511456f, 0.070504573f, - 0.997290457f, 0.073564564f, - 0.997060070f, 0.076623861f, - 0.996820299f, 0.079682438f, - 0.996571146f, 0.082740265f, - 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0.973644250f, -0.228072083f, - 0.974339383f, -0.225083911f, - 0.975025345f, -0.222093621f, - 0.975702130f, -0.219101240f, - 0.976369731f, -0.216106797f, - 0.977028143f, -0.213110320f, - 0.977677358f, -0.210111837f, - 0.978317371f, -0.207111376f, - 0.978948175f, -0.204108966f, - 0.979569766f, -0.201104635f, - 0.980182136f, -0.198098411f, - 0.980785280f, -0.195090322f, - 0.981379193f, -0.192080397f, - 0.981963869f, -0.189068664f, - 0.982539302f, -0.186055152f, - 0.983105487f, -0.183039888f, - 0.983662419f, -0.180022901f, - 0.984210092f, -0.177004220f, - 0.984748502f, -0.173983873f, - 0.985277642f, -0.170961889f, - 0.985797509f, -0.167938295f, - 0.986308097f, -0.164913120f, - 0.986809402f, -0.161886394f, - 0.987301418f, -0.158858143f, - 0.987784142f, -0.155828398f, - 0.988257568f, -0.152797185f, - 0.988721692f, -0.149764535f, - 0.989176510f, -0.146730474f, - 0.989622017f, -0.143695033f, - 0.990058210f, -0.140658239f, - 0.990485084f, -0.137620122f, - 0.990902635f, -0.134580709f, - 0.991310860f, -0.131540029f, - 0.991709754f, -0.128498111f, - 0.992099313f, -0.125454983f, - 0.992479535f, -0.122410675f, - 0.992850414f, -0.119365215f, - 0.993211949f, -0.116318631f, - 0.993564136f, -0.113270952f, - 0.993906970f, -0.110222207f, - 0.994240449f, -0.107172425f, - 0.994564571f, -0.104121634f, - 0.994879331f, -0.101069863f, - 0.995184727f, -0.098017140f, - 0.995480755f, -0.094963495f, - 0.995767414f, -0.091908956f, - 0.996044701f, -0.088853553f, - 0.996312612f, -0.085797312f, - 0.996571146f, -0.082740265f, - 0.996820299f, -0.079682438f, - 0.997060070f, -0.076623861f, - 0.997290457f, -0.073564564f, - 0.997511456f, -0.070504573f, - 0.997723067f, -0.067443920f, - 0.997925286f, -0.064382631f, - 0.998118113f, -0.061320736f, - 0.998301545f, -0.058258265f, - 0.998475581f, -0.055195244f, - 0.998640218f, -0.052131705f, - 0.998795456f, -0.049067674f, - 0.998941293f, -0.046003182f, - 0.999077728f, -0.042938257f, - 0.999204759f, -0.039872928f, - 0.999322385f, -0.036807223f, - 0.999430605f, -0.033741172f, - 0.999529418f, -0.030674803f, - 0.999618822f, -0.027608146f, - 0.999698819f, -0.024541229f, - 0.999769405f, -0.021474080f, - 0.999830582f, -0.018406730f, - 0.999882347f, -0.015339206f, - 0.999924702f, -0.012271538f, - 0.999957645f, -0.009203755f, - 0.999981175f, -0.006135885f, - 0.999995294f, -0.003067957f -}; - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< N/; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef_4096[8192] = { - 1.000000000f, 0.000000000f, - 0.999998823f, 0.001533980f, - 0.999995294f, 0.003067957f, - 0.999989411f, 0.004601926f, - 0.999981175f, 0.006135885f, - 0.999970586f, 0.007669829f, - 0.999957645f, 0.009203755f, - 0.999942350f, 0.010737659f, - 0.999924702f, 0.012271538f, - 0.999904701f, 0.013805389f, - 0.999882347f, 0.015339206f, - 0.999857641f, 0.016872988f, - 0.999830582f, 0.018406730f, - 0.999801170f, 0.019940429f, - 0.999769405f, 0.021474080f, - 0.999735288f, 0.023007681f, - 0.999698819f, 0.024541229f, - 0.999659997f, 0.026074718f, - 0.999618822f, 0.027608146f, - 0.999575296f, 0.029141509f, - 0.999529418f, 0.030674803f, - 0.999481187f, 0.032208025f, - 0.999430605f, 0.033741172f, - 0.999377670f, 0.035274239f, - 0.999322385f, 0.036807223f, - 0.999264747f, 0.038340120f, - 0.999204759f, 0.039872928f, - 0.999142419f, 0.041405641f, - 0.999077728f, 0.042938257f, - 0.999010686f, 0.044470772f, - 0.998941293f, 0.046003182f, - 0.998869550f, 0.047535484f, - 0.998795456f, 0.049067674f, - 0.998719012f, 0.050599749f, - 0.998640218f, 0.052131705f, - 0.998559074f, 0.053663538f, - 0.998475581f, 0.055195244f, - 0.998389737f, 0.056726821f, - 0.998301545f, 0.058258265f, - 0.998211003f, 0.059789571f, - 0.998118113f, 0.061320736f, - 0.998022874f, 0.062851758f, - 0.997925286f, 0.064382631f, - 0.997825350f, 0.065913353f, - 0.997723067f, 0.067443920f, - 0.997618435f, 0.068974328f, - 0.997511456f, 0.070504573f, - 0.997402130f, 0.072034653f, - 0.997290457f, 0.073564564f, - 0.997176437f, 0.075094301f, - 0.997060070f, 0.076623861f, - 0.996941358f, 0.078153242f, - 0.996820299f, 0.079682438f, - 0.996696895f, 0.081211447f, - 0.996571146f, 0.082740265f, - 0.996443051f, 0.084268888f, - 0.996312612f, 0.085797312f, - 0.996179829f, 0.087325535f, - 0.996044701f, 0.088853553f, - 0.995907229f, 0.090381361f, - 0.995767414f, 0.091908956f, - 0.995625256f, 0.093436336f, - 0.995480755f, 0.094963495f, - 0.995333912f, 0.096490431f, - 0.995184727f, 0.098017140f, - 0.995033199f, 0.099543619f, - 0.994879331f, 0.101069863f, - 0.994723121f, 0.102595869f, - 0.994564571f, 0.104121634f, - 0.994403680f, 0.105647154f, - 0.994240449f, 0.107172425f, - 0.994074879f, 0.108697444f, - 0.993906970f, 0.110222207f, - 0.993736722f, 0.111746711f, - 0.993564136f, 0.113270952f, - 0.993389211f, 0.114794927f, - 0.993211949f, 0.116318631f, - 0.993032350f, 0.117842062f, - 0.992850414f, 0.119365215f, - 0.992666142f, 0.120888087f, - 0.992479535f, 0.122410675f, - 0.992290591f, 0.123932975f, - 0.992099313f, 0.125454983f, - 0.991905700f, 0.126976696f, - 0.991709754f, 0.128498111f, - 0.991511473f, 0.130019223f, - 0.991310860f, 0.131540029f, - 0.991107914f, 0.133060525f, - 0.990902635f, 0.134580709f, - 0.990695025f, 0.136100575f, - 0.990485084f, 0.137620122f, - 0.990272812f, 0.139139344f, - 0.990058210f, 0.140658239f, - 0.989841278f, 0.142176804f, - 0.989622017f, 0.143695033f, - 0.989400428f, 0.145212925f, - 0.989176510f, 0.146730474f, - 0.988950265f, 0.148247679f, - 0.988721692f, 0.149764535f, - 0.988490793f, 0.151281038f, - 0.988257568f, 0.152797185f, - 0.988022017f, 0.154312973f, - 0.987784142f, 0.155828398f, - 0.987543942f, 0.157343456f, - 0.987301418f, 0.158858143f, - 0.987056571f, 0.160372457f, - 0.986809402f, 0.161886394f, - 0.986559910f, 0.163399949f, - 0.986308097f, 0.164913120f, - 0.986053963f, 0.166425904f, - 0.985797509f, 0.167938295f, - 0.985538735f, 0.169450291f, - 0.985277642f, 0.170961889f, - 0.985014231f, 0.172473084f, - 0.984748502f, 0.173983873f, - 0.984480455f, 0.175494253f, - 0.984210092f, 0.177004220f, - 0.983937413f, 0.178513771f, - 0.983662419f, 0.180022901f, - 0.983385110f, 0.181531608f, - 0.983105487f, 0.183039888f, - 0.982823551f, 0.184547737f, - 0.982539302f, 0.186055152f, - 0.982252741f, 0.187562129f, - 0.981963869f, 0.189068664f, - 0.981672686f, 0.190574755f, - 0.981379193f, 0.192080397f, - 0.981083391f, 0.193585587f, - 0.980785280f, 0.195090322f, - 0.980484862f, 0.196594598f, - 0.980182136f, 0.198098411f, - 0.979877104f, 0.199601758f, - 0.979569766f, 0.201104635f, - 0.979260123f, 0.202607039f, - 0.978948175f, 0.204108966f, - 0.978633924f, 0.205610413f, - 0.978317371f, 0.207111376f, - 0.977998515f, 0.208611852f, - 0.977677358f, 0.210111837f, - 0.977353900f, 0.211611327f, - 0.977028143f, 0.213110320f, - 0.976700086f, 0.214608811f, - 0.976369731f, 0.216106797f, - 0.976037079f, 0.217604275f, - 0.975702130f, 0.219101240f, - 0.975364885f, 0.220597690f, - 0.975025345f, 0.222093621f, - 0.974683511f, 0.223589029f, - 0.974339383f, 0.225083911f, - 0.973992962f, 0.226578264f, - 0.973644250f, 0.228072083f, - 0.973293246f, 0.229565366f, - 0.972939952f, 0.231058108f, - 0.972584369f, 0.232550307f, - 0.972226497f, 0.234041959f, - 0.971866337f, 0.235533059f, - 0.971503891f, 0.237023606f, - 0.971139158f, 0.238513595f, - 0.970772141f, 0.240003022f, - 0.970402839f, 0.241491885f, - 0.970031253f, 0.242980180f, - 0.969657385f, 0.244467903f, - 0.969281235f, 0.245955050f, - 0.968902805f, 0.247441619f, - 0.968522094f, 0.248927606f, - 0.968139105f, 0.250413007f, - 0.967753837f, 0.251897818f, - 0.967366292f, 0.253382037f, - 0.966976471f, 0.254865660f, - 0.966584374f, 0.256348682f, - 0.966190003f, 0.257831102f, - 0.965793359f, 0.259312915f, - 0.965394442f, 0.260794118f, - 0.964993253f, 0.262274707f, - 0.964589793f, 0.263754679f, - 0.964184064f, 0.265234030f, - 0.963776066f, 0.266712757f, - 0.963365800f, 0.268190857f, - 0.962953267f, 0.269668326f, - 0.962538468f, 0.271145160f, - 0.962121404f, 0.272621355f, - 0.961702077f, 0.274096910f, - 0.961280486f, 0.275571819f, - 0.960856633f, 0.277046080f, - 0.960430519f, 0.278519689f, - 0.960002146f, 0.279992643f, - 0.959571513f, 0.281464938f, - 0.959138622f, 0.282936570f, - 0.958703475f, 0.284407537f, - 0.958266071f, 0.285877835f, - 0.957826413f, 0.287347460f, - 0.957384501f, 0.288816408f, - 0.956940336f, 0.290284677f, - 0.956493919f, 0.291752263f, - 0.956045251f, 0.293219163f, - 0.955594334f, 0.294685372f, - 0.955141168f, 0.296150888f, - 0.954685755f, 0.297615707f, - 0.954228095f, 0.299079826f, - 0.953768190f, 0.300543241f, - 0.953306040f, 0.302005949f, - 0.952841648f, 0.303467947f, - 0.952375013f, 0.304929230f, - 0.951906137f, 0.306389795f, - 0.951435021f, 0.307849640f, - 0.950961666f, 0.309308760f, - 0.950486074f, 0.310767153f, - 0.950008245f, 0.312224814f, - 0.949528181f, 0.313681740f, - 0.949045882f, 0.315137929f, - 0.948561350f, 0.316593376f, - 0.948074586f, 0.318048077f, - 0.947585591f, 0.319502031f, - 0.947094366f, 0.320955232f, - 0.946600913f, 0.322407679f, - 0.946105232f, 0.323859367f, - 0.945607325f, 0.325310292f, - 0.945107193f, 0.326760452f, - 0.944604837f, 0.328209844f, - 0.944100258f, 0.329658463f, - 0.943593458f, 0.331106306f, - 0.943084437f, 0.332553370f, - 0.942573198f, 0.333999651f, - 0.942059740f, 0.335445147f, - 0.941544065f, 0.336889853f, - 0.941026175f, 0.338333767f, - 0.940506071f, 0.339776884f, - 0.939983753f, 0.341219202f, - 0.939459224f, 0.342660717f, - 0.938932484f, 0.344101426f, - 0.938403534f, 0.345541325f, - 0.937872376f, 0.346980411f, - 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0.985277642f, -0.170961889f, - 0.985538735f, -0.169450291f, - 0.985797509f, -0.167938295f, - 0.986053963f, -0.166425904f, - 0.986308097f, -0.164913120f, - 0.986559910f, -0.163399949f, - 0.986809402f, -0.161886394f, - 0.987056571f, -0.160372457f, - 0.987301418f, -0.158858143f, - 0.987543942f, -0.157343456f, - 0.987784142f, -0.155828398f, - 0.988022017f, -0.154312973f, - 0.988257568f, -0.152797185f, - 0.988490793f, -0.151281038f, - 0.988721692f, -0.149764535f, - 0.988950265f, -0.148247679f, - 0.989176510f, -0.146730474f, - 0.989400428f, -0.145212925f, - 0.989622017f, -0.143695033f, - 0.989841278f, -0.142176804f, - 0.990058210f, -0.140658239f, - 0.990272812f, -0.139139344f, - 0.990485084f, -0.137620122f, - 0.990695025f, -0.136100575f, - 0.990902635f, -0.134580709f, - 0.991107914f, -0.133060525f, - 0.991310860f, -0.131540029f, - 0.991511473f, -0.130019223f, - 0.991709754f, -0.128498111f, - 0.991905700f, -0.126976696f, - 0.992099313f, -0.125454983f, - 0.992290591f, -0.123932975f, - 0.992479535f, -0.122410675f, - 0.992666142f, -0.120888087f, - 0.992850414f, -0.119365215f, - 0.993032350f, -0.117842062f, - 0.993211949f, -0.116318631f, - 0.993389211f, -0.114794927f, - 0.993564136f, -0.113270952f, - 0.993736722f, -0.111746711f, - 0.993906970f, -0.110222207f, - 0.994074879f, -0.108697444f, - 0.994240449f, -0.107172425f, - 0.994403680f, -0.105647154f, - 0.994564571f, -0.104121634f, - 0.994723121f, -0.102595869f, - 0.994879331f, -0.101069863f, - 0.995033199f, -0.099543619f, - 0.995184727f, -0.098017140f, - 0.995333912f, -0.096490431f, - 0.995480755f, -0.094963495f, - 0.995625256f, -0.093436336f, - 0.995767414f, -0.091908956f, - 0.995907229f, -0.090381361f, - 0.996044701f, -0.088853553f, - 0.996179829f, -0.087325535f, - 0.996312612f, -0.085797312f, - 0.996443051f, -0.084268888f, - 0.996571146f, -0.082740265f, - 0.996696895f, -0.081211447f, - 0.996820299f, -0.079682438f, - 0.996941358f, -0.078153242f, - 0.997060070f, -0.076623861f, - 0.997176437f, -0.075094301f, - 0.997290457f, -0.073564564f, - 0.997402130f, -0.072034653f, - 0.997511456f, -0.070504573f, - 0.997618435f, -0.068974328f, - 0.997723067f, -0.067443920f, - 0.997825350f, -0.065913353f, - 0.997925286f, -0.064382631f, - 0.998022874f, -0.062851758f, - 0.998118113f, -0.061320736f, - 0.998211003f, -0.059789571f, - 0.998301545f, -0.058258265f, - 0.998389737f, -0.056726821f, - 0.998475581f, -0.055195244f, - 0.998559074f, -0.053663538f, - 0.998640218f, -0.052131705f, - 0.998719012f, -0.050599749f, - 0.998795456f, -0.049067674f, - 0.998869550f, -0.047535484f, - 0.998941293f, -0.046003182f, - 0.999010686f, -0.044470772f, - 0.999077728f, -0.042938257f, - 0.999142419f, -0.041405641f, - 0.999204759f, -0.039872928f, - 0.999264747f, -0.038340120f, - 0.999322385f, -0.036807223f, - 0.999377670f, -0.035274239f, - 0.999430605f, -0.033741172f, - 0.999481187f, -0.032208025f, - 0.999529418f, -0.030674803f, - 0.999575296f, -0.029141509f, - 0.999618822f, -0.027608146f, - 0.999659997f, -0.026074718f, - 0.999698819f, -0.024541229f, - 0.999735288f, -0.023007681f, - 0.999769405f, -0.021474080f, - 0.999801170f, -0.019940429f, - 0.999830582f, -0.018406730f, - 0.999857641f, -0.016872988f, - 0.999882347f, -0.015339206f, - 0.999904701f, -0.013805389f, - 0.999924702f, -0.012271538f, - 0.999942350f, -0.010737659f, - 0.999957645f, -0.009203755f, - 0.999970586f, -0.007669829f, - 0.999981175f, -0.006135885f, - 0.999989411f, -0.004601926f, - 0.999995294f, -0.003067957f, - 0.999998823f, -0.001533980f -}; - -/* -* @brief Q31 Twiddle factors Table -*/ - - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 16 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_16_q31[24] = { - 0x7FFFFFFF, 0x00000000, - 0x7641AF3C, 0x30FBC54D, - 0x5A82799A, 0x5A82799A, - 0x30FBC54D, 0x7641AF3C, - 0x00000000, 0x7FFFFFFF, - 0xCF043AB2, 0x7641AF3C, - 0xA57D8666, 0x5A82799A, - 0x89BE50C3, 0x30FBC54D, - 0x80000000, 0x00000000, - 0x89BE50C3, 0xCF043AB2, - 0xA57D8666, 0xA57D8666, - 0xCF043AB2, 0x89BE50C3 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 32 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_32_q31[48] = { - 0x7FFFFFFF, 0x00000000, - 0x7D8A5F3F, 0x18F8B83C, - 0x7641AF3C, 0x30FBC54D, - 0x6A6D98A4, 0x471CECE6, - 0x5A82799A, 0x5A82799A, - 0x471CECE6, 0x6A6D98A4, - 0x30FBC54D, 0x7641AF3C, - 0x18F8B83C, 0x7D8A5F3F, - 0x00000000, 0x7FFFFFFF, - 0xE70747C3, 0x7D8A5F3F, - 0xCF043AB2, 0x7641AF3C, - 0xB8E31319, 0x6A6D98A4, - 0xA57D8666, 0x5A82799A, - 0x9592675B, 0x471CECE6, - 0x89BE50C3, 0x30FBC54D, - 0x8275A0C0, 0x18F8B83C, - 0x80000000, 0x00000000, - 0x8275A0C0, 0xE70747C3, - 0x89BE50C3, 0xCF043AB2, - 0x9592675B, 0xB8E31319, - 0xA57D8666, 0xA57D8666, - 0xB8E31319, 0x9592675B, - 0xCF043AB2, 0x89BE50C3, - 0xE70747C3, 0x8275A0C0 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 64 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_64_q31[96] = { - 0x7FFFFFFF, 0x00000000, - 0x7F62368F, 0x0C8BD35E, - 0x7D8A5F3F, 0x18F8B83C, - 0x7A7D055B, 0x25280C5D, - 0x7641AF3C, 0x30FBC54D, - 0x70E2CBC6, 0x3C56BA70, - 0x6A6D98A4, 0x471CECE6, - 0x62F201AC, 0x5133CC94, - 0x5A82799A, 0x5A82799A, - 0x5133CC94, 0x62F201AC, - 0x471CECE6, 0x6A6D98A4, - 0x3C56BA70, 0x70E2CBC6, - 0x30FBC54D, 0x7641AF3C, - 0x25280C5D, 0x7A7D055B, - 0x18F8B83C, 0x7D8A5F3F, - 0x0C8BD35E, 0x7F62368F, - 0x00000000, 0x7FFFFFFF, - 0xF3742CA1, 0x7F62368F, - 0xE70747C3, 0x7D8A5F3F, - 0xDAD7F3A2, 0x7A7D055B, - 0xCF043AB2, 0x7641AF3C, - 0xC3A9458F, 0x70E2CBC6, - 0xB8E31319, 0x6A6D98A4, - 0xAECC336B, 0x62F201AC, - 0xA57D8666, 0x5A82799A, - 0x9D0DFE53, 0x5133CC94, - 0x9592675B, 0x471CECE6, - 0x8F1D343A, 0x3C56BA70, - 0x89BE50C3, 0x30FBC54D, - 0x8582FAA4, 0x25280C5D, - 0x8275A0C0, 0x18F8B83C, - 0x809DC970, 0x0C8BD35E, - 0x80000000, 0x00000000, - 0x809DC970, 0xF3742CA1, - 0x8275A0C0, 0xE70747C3, - 0x8582FAA4, 0xDAD7F3A2, - 0x89BE50C3, 0xCF043AB2, - 0x8F1D343A, 0xC3A9458F, - 0x9592675B, 0xB8E31319, - 0x9D0DFE53, 0xAECC336B, - 0xA57D8666, 0xA57D8666, - 0xAECC336B, 0x9D0DFE53, - 0xB8E31319, 0x9592675B, - 0xC3A9458F, 0x8F1D343A, - 0xCF043AB2, 0x89BE50C3, - 0xDAD7F3A2, 0x8582FAA4, - 0xE70747C3, 0x8275A0C0, - 0xF3742CA1, 0x809DC970 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 128 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_128_q31[192] = { - 0x7FFFFFFF, 0x00000000, - 0x7FD8878D, 0x0647D97C, - 0x7F62368F, 0x0C8BD35E, - 0x7E9D55FC, 0x12C8106E, - 0x7D8A5F3F, 0x18F8B83C, - 0x7C29FBEE, 0x1F19F97B, - 0x7A7D055B, 0x25280C5D, - 0x78848413, 0x2B1F34EB, - 0x7641AF3C, 0x30FBC54D, - 0x73B5EBD0, 0x36BA2013, - 0x70E2CBC6, 0x3C56BA70, - 0x6DCA0D14, 0x41CE1E64, - 0x6A6D98A4, 0x471CECE6, - 0x66CF811F, 0x4C3FDFF3, - 0x62F201AC, 0x5133CC94, - 0x5ED77C89, 0x55F5A4D2, - 0x5A82799A, 0x5A82799A, - 0x55F5A4D2, 0x5ED77C89, - 0x5133CC94, 0x62F201AC, - 0x4C3FDFF3, 0x66CF811F, - 0x471CECE6, 0x6A6D98A4, - 0x41CE1E64, 0x6DCA0D14, - 0x3C56BA70, 0x70E2CBC6, - 0x36BA2013, 0x73B5EBD0, - 0x30FBC54D, 0x7641AF3C, - 0x2B1F34EB, 0x78848413, - 0x25280C5D, 0x7A7D055B, - 0x1F19F97B, 0x7C29FBEE, - 0x18F8B83C, 0x7D8A5F3F, - 0x12C8106E, 0x7E9D55FC, - 0x0C8BD35E, 0x7F62368F, - 0x0647D97C, 0x7FD8878D, - 0x00000000, 0x7FFFFFFF, - 0xF9B82683, 0x7FD8878D, - 0xF3742CA1, 0x7F62368F, - 0xED37EF91, 0x7E9D55FC, - 0xE70747C3, 0x7D8A5F3F, - 0xE0E60684, 0x7C29FBEE, - 0xDAD7F3A2, 0x7A7D055B, - 0xD4E0CB14, 0x78848413, - 0xCF043AB2, 0x7641AF3C, - 0xC945DFEC, 0x73B5EBD0, - 0xC3A9458F, 0x70E2CBC6, - 0xBE31E19B, 0x6DCA0D14, - 0xB8E31319, 0x6A6D98A4, - 0xB3C0200C, 0x66CF811F, - 0xAECC336B, 0x62F201AC, - 0xAA0A5B2D, 0x5ED77C89, - 0xA57D8666, 0x5A82799A, - 0xA1288376, 0x55F5A4D2, - 0x9D0DFE53, 0x5133CC94, - 0x99307EE0, 0x4C3FDFF3, - 0x9592675B, 0x471CECE6, - 0x9235F2EB, 0x41CE1E64, - 0x8F1D343A, 0x3C56BA70, - 0x8C4A142F, 0x36BA2013, - 0x89BE50C3, 0x30FBC54D, - 0x877B7BEC, 0x2B1F34EB, - 0x8582FAA4, 0x25280C5D, - 0x83D60411, 0x1F19F97B, - 0x8275A0C0, 0x18F8B83C, - 0x8162AA03, 0x12C8106E, - 0x809DC970, 0x0C8BD35E, - 0x80277872, 0x0647D97C, - 0x80000000, 0x00000000, - 0x80277872, 0xF9B82683, - 0x809DC970, 0xF3742CA1, - 0x8162AA03, 0xED37EF91, - 0x8275A0C0, 0xE70747C3, - 0x83D60411, 0xE0E60684, - 0x8582FAA4, 0xDAD7F3A2, - 0x877B7BEC, 0xD4E0CB14, - 0x89BE50C3, 0xCF043AB2, - 0x8C4A142F, 0xC945DFEC, - 0x8F1D343A, 0xC3A9458F, - 0x9235F2EB, 0xBE31E19B, - 0x9592675B, 0xB8E31319, - 0x99307EE0, 0xB3C0200C, - 0x9D0DFE53, 0xAECC336B, - 0xA1288376, 0xAA0A5B2D, - 0xA57D8666, 0xA57D8666, - 0xAA0A5B2D, 0xA1288376, - 0xAECC336B, 0x9D0DFE53, - 0xB3C0200C, 0x99307EE0, - 0xB8E31319, 0x9592675B, - 0xBE31E19B, 0x9235F2EB, - 0xC3A9458F, 0x8F1D343A, - 0xC945DFEC, 0x8C4A142F, - 0xCF043AB2, 0x89BE50C3, - 0xD4E0CB14, 0x877B7BEC, - 0xDAD7F3A2, 0x8582FAA4, - 0xE0E60684, 0x83D60411, - 0xE70747C3, 0x8275A0C0, - 0xED37EF91, 0x8162AA03, - 0xF3742CA1, 0x809DC970, - 0xF9B82683, 0x80277872 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 256 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_256_q31[384] = { - 0x7FFFFFFF, 0x00000000, - 0x7FF62182, 0x03242ABF, - 0x7FD8878D, 0x0647D97C, - 0x7FA736B4, 0x096A9049, - 0x7F62368F, 0x0C8BD35E, - 0x7F0991C3, 0x0FAB272B, - 0x7E9D55FC, 0x12C8106E, - 0x7E1D93E9, 0x15E21444, - 0x7D8A5F3F, 0x18F8B83C, - 0x7CE3CEB1, 0x1C0B826A, - 0x7C29FBEE, 0x1F19F97B, - 0x7B5D039D, 0x2223A4C5, - 0x7A7D055B, 0x25280C5D, - 0x798A23B1, 0x2826B928, - 0x78848413, 0x2B1F34EB, - 0x776C4EDB, 0x2E110A62, - 0x7641AF3C, 0x30FBC54D, - 0x7504D345, 0x33DEF287, - 0x73B5EBD0, 0x36BA2013, - 0x72552C84, 0x398CDD32, - 0x70E2CBC6, 0x3C56BA70, - 0x6F5F02B1, 0x3F1749B7, - 0x6DCA0D14, 0x41CE1E64, - 0x6C242960, 0x447ACD50, - 0x6A6D98A4, 0x471CECE6, - 0x68A69E81, 0x49B41533, - 0x66CF811F, 0x4C3FDFF3, - 0x64E88926, 0x4EBFE8A4, - 0x62F201AC, 0x5133CC94, - 0x60EC3830, 0x539B2AEF, - 0x5ED77C89, 0x55F5A4D2, - 0x5CB420DF, 0x5842DD54, - 0x5A82799A, 0x5A82799A, - 0x5842DD54, 0x5CB420DF, - 0x55F5A4D2, 0x5ED77C89, - 0x539B2AEF, 0x60EC3830, - 0x5133CC94, 0x62F201AC, - 0x4EBFE8A4, 0x64E88926, - 0x4C3FDFF3, 0x66CF811F, - 0x49B41533, 0x68A69E81, - 0x471CECE6, 0x6A6D98A4, - 0x447ACD50, 0x6C242960, - 0x41CE1E64, 0x6DCA0D14, - 0x3F1749B7, 0x6F5F02B1, - 0x3C56BA70, 0x70E2CBC6, - 0x398CDD32, 0x72552C84, - 0x36BA2013, 0x73B5EBD0, - 0x33DEF287, 0x7504D345, - 0x30FBC54D, 0x7641AF3C, - 0x2E110A62, 0x776C4EDB, - 0x2B1F34EB, 0x78848413, - 0x2826B928, 0x798A23B1, - 0x25280C5D, 0x7A7D055B, - 0x2223A4C5, 0x7B5D039D, - 0x1F19F97B, 0x7C29FBEE, - 0x1C0B826A, 0x7CE3CEB1, - 0x18F8B83C, 0x7D8A5F3F, - 0x15E21444, 0x7E1D93E9, - 0x12C8106E, 0x7E9D55FC, - 0x0FAB272B, 0x7F0991C3, - 0x0C8BD35E, 0x7F62368F, - 0x096A9049, 0x7FA736B4, - 0x0647D97C, 0x7FD8878D, - 0x03242ABF, 0x7FF62182, - 0x00000000, 0x7FFFFFFF, - 0xFCDBD541, 0x7FF62182, - 0xF9B82683, 0x7FD8878D, - 0xF6956FB6, 0x7FA736B4, - 0xF3742CA1, 0x7F62368F, - 0xF054D8D4, 0x7F0991C3, - 0xED37EF91, 0x7E9D55FC, - 0xEA1DEBBB, 0x7E1D93E9, - 0xE70747C3, 0x7D8A5F3F, - 0xE3F47D95, 0x7CE3CEB1, - 0xE0E60684, 0x7C29FBEE, - 0xDDDC5B3A, 0x7B5D039D, - 0xDAD7F3A2, 0x7A7D055B, - 0xD7D946D7, 0x798A23B1, - 0xD4E0CB14, 0x78848413, - 0xD1EEF59E, 0x776C4EDB, - 0xCF043AB2, 0x7641AF3C, - 0xCC210D78, 0x7504D345, - 0xC945DFEC, 0x73B5EBD0, - 0xC67322CD, 0x72552C84, - 0xC3A9458F, 0x70E2CBC6, - 0xC0E8B648, 0x6F5F02B1, - 0xBE31E19B, 0x6DCA0D14, - 0xBB8532AF, 0x6C242960, - 0xB8E31319, 0x6A6D98A4, - 0xB64BEACC, 0x68A69E81, - 0xB3C0200C, 0x66CF811F, - 0xB140175B, 0x64E88926, - 0xAECC336B, 0x62F201AC, - 0xAC64D510, 0x60EC3830, - 0xAA0A5B2D, 0x5ED77C89, - 0xA7BD22AB, 0x5CB420DF, - 0xA57D8666, 0x5A82799A, - 0xA34BDF20, 0x5842DD54, - 0xA1288376, 0x55F5A4D2, - 0x9F13C7D0, 0x539B2AEF, - 0x9D0DFE53, 0x5133CC94, - 0x9B1776D9, 0x4EBFE8A4, - 0x99307EE0, 0x4C3FDFF3, - 0x9759617E, 0x49B41533, - 0x9592675B, 0x471CECE6, - 0x93DBD69F, 0x447ACD50, - 0x9235F2EB, 0x41CE1E64, - 0x90A0FD4E, 0x3F1749B7, - 0x8F1D343A, 0x3C56BA70, - 0x8DAAD37B, 0x398CDD32, - 0x8C4A142F, 0x36BA2013, - 0x8AFB2CBA, 0x33DEF287, - 0x89BE50C3, 0x30FBC54D, - 0x8893B124, 0x2E110A62, - 0x877B7BEC, 0x2B1F34EB, - 0x8675DC4E, 0x2826B928, - 0x8582FAA4, 0x25280C5D, - 0x84A2FC62, 0x2223A4C5, - 0x83D60411, 0x1F19F97B, - 0x831C314E, 0x1C0B826A, - 0x8275A0C0, 0x18F8B83C, - 0x81E26C16, 0x15E21444, - 0x8162AA03, 0x12C8106E, - 0x80F66E3C, 0x0FAB272B, - 0x809DC970, 0x0C8BD35E, - 0x8058C94C, 0x096A9049, - 0x80277872, 0x0647D97C, - 0x8009DE7D, 0x03242ABF, - 0x80000000, 0x00000000, - 0x8009DE7D, 0xFCDBD541, - 0x80277872, 0xF9B82683, - 0x8058C94C, 0xF6956FB6, - 0x809DC970, 0xF3742CA1, - 0x80F66E3C, 0xF054D8D4, - 0x8162AA03, 0xED37EF91, - 0x81E26C16, 0xEA1DEBBB, - 0x8275A0C0, 0xE70747C3, - 0x831C314E, 0xE3F47D95, - 0x83D60411, 0xE0E60684, - 0x84A2FC62, 0xDDDC5B3A, - 0x8582FAA4, 0xDAD7F3A2, - 0x8675DC4E, 0xD7D946D7, - 0x877B7BEC, 0xD4E0CB14, - 0x8893B124, 0xD1EEF59E, - 0x89BE50C3, 0xCF043AB2, - 0x8AFB2CBA, 0xCC210D78, - 0x8C4A142F, 0xC945DFEC, - 0x8DAAD37B, 0xC67322CD, - 0x8F1D343A, 0xC3A9458F, - 0x90A0FD4E, 0xC0E8B648, - 0x9235F2EB, 0xBE31E19B, - 0x93DBD69F, 0xBB8532AF, - 0x9592675B, 0xB8E31319, - 0x9759617E, 0xB64BEACC, - 0x99307EE0, 0xB3C0200C, - 0x9B1776D9, 0xB140175B, - 0x9D0DFE53, 0xAECC336B, - 0x9F13C7D0, 0xAC64D510, - 0xA1288376, 0xAA0A5B2D, - 0xA34BDF20, 0xA7BD22AB, - 0xA57D8666, 0xA57D8666, - 0xA7BD22AB, 0xA34BDF20, - 0xAA0A5B2D, 0xA1288376, - 0xAC64D510, 0x9F13C7D0, - 0xAECC336B, 0x9D0DFE53, - 0xB140175B, 0x9B1776D9, - 0xB3C0200C, 0x99307EE0, - 0xB64BEACC, 0x9759617E, - 0xB8E31319, 0x9592675B, - 0xBB8532AF, 0x93DBD69F, - 0xBE31E19B, 0x9235F2EB, - 0xC0E8B648, 0x90A0FD4E, - 0xC3A9458F, 0x8F1D343A, - 0xC67322CD, 0x8DAAD37B, - 0xC945DFEC, 0x8C4A142F, - 0xCC210D78, 0x8AFB2CBA, - 0xCF043AB2, 0x89BE50C3, - 0xD1EEF59E, 0x8893B124, - 0xD4E0CB14, 0x877B7BEC, - 0xD7D946D7, 0x8675DC4E, - 0xDAD7F3A2, 0x8582FAA4, - 0xDDDC5B3A, 0x84A2FC62, - 0xE0E60684, 0x83D60411, - 0xE3F47D95, 0x831C314E, - 0xE70747C3, 0x8275A0C0, - 0xEA1DEBBB, 0x81E26C16, - 0xED37EF91, 0x8162AA03, - 0xF054D8D4, 0x80F66E3C, - 0xF3742CA1, 0x809DC970, - 0xF6956FB6, 0x8058C94C, - 0xF9B82683, 0x80277872, - 0xFCDBD541, 0x8009DE7D -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 512 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_512_q31[768] = { - 0x7FFFFFFF, 0x00000000, - 0x7FFD885A, 0x01921D1F, - 0x7FF62182, 0x03242ABF, - 0x7FE9CBC0, 0x04B6195D, - 0x7FD8878D, 0x0647D97C, - 0x7FC25596, 0x07D95B9E, - 0x7FA736B4, 0x096A9049, - 0x7F872BF3, 0x0AFB6805, - 0x7F62368F, 0x0C8BD35E, - 0x7F3857F5, 0x0E1BC2E3, - 0x7F0991C3, 0x0FAB272B, - 0x7ED5E5C6, 0x1139F0CE, - 0x7E9D55FC, 0x12C8106E, - 0x7E5FE493, 0x145576B1, - 0x7E1D93E9, 0x15E21444, - 0x7DD6668E, 0x176DD9DE, - 0x7D8A5F3F, 0x18F8B83C, - 0x7D3980EC, 0x1A82A025, - 0x7CE3CEB1, 0x1C0B826A, - 0x7C894BDD, 0x1D934FE5, - 0x7C29FBEE, 0x1F19F97B, - 0x7BC5E28F, 0x209F701C, - 0x7B5D039D, 0x2223A4C5, - 0x7AEF6323, 0x23A6887E, - 0x7A7D055B, 0x25280C5D, - 0x7A05EEAD, 0x26A82185, - 0x798A23B1, 0x2826B928, - 0x7909A92C, 0x29A3C484, - 0x78848413, 0x2B1F34EB, - 0x77FAB988, 0x2C98FBBA, - 0x776C4EDB, 0x2E110A62, - 0x76D94988, 0x2F875262, - 0x7641AF3C, 0x30FBC54D, - 0x75A585CF, 0x326E54C7, - 0x7504D345, 0x33DEF287, - 0x745F9DD1, 0x354D9056, - 0x73B5EBD0, 0x36BA2013, - 0x7307C3D0, 0x382493B0, - 0x72552C84, 0x398CDD32, - 0x719E2CD2, 0x3AF2EEB7, - 0x70E2CBC6, 0x3C56BA70, - 0x70231099, 0x3DB832A5, - 0x6F5F02B1, 0x3F1749B7, - 0x6E96A99C, 0x4073F21D, - 0x6DCA0D14, 0x41CE1E64, - 0x6CF934FB, 0x4325C135, - 0x6C242960, 0x447ACD50, - 0x6B4AF278, 0x45CD358F, - 0x6A6D98A4, 0x471CECE6, - 0x698C246C, 0x4869E664, - 0x68A69E81, 0x49B41533, - 0x67BD0FBC, 0x4AFB6C97, - 0x66CF811F, 0x4C3FDFF3, - 0x65DDFBD3, 0x4D8162C4, - 0x64E88926, 0x4EBFE8A4, - 0x63EF328F, 0x4FFB654D, - 0x62F201AC, 0x5133CC94, - 0x61F1003E, 0x5269126E, - 0x60EC3830, 0x539B2AEF, - 0x5FE3B38D, 0x54CA0A4A, - 0x5ED77C89, 0x55F5A4D2, - 0x5DC79D7C, 0x571DEEF9, - 0x5CB420DF, 0x5842DD54, - 0x5B9D1153, 0x59646497, - 0x5A82799A, 0x5A82799A, - 0x59646497, 0x5B9D1153, - 0x5842DD54, 0x5CB420DF, - 0x571DEEF9, 0x5DC79D7C, - 0x55F5A4D2, 0x5ED77C89, - 0x54CA0A4A, 0x5FE3B38D, - 0x539B2AEF, 0x60EC3830, - 0x5269126E, 0x61F1003E, - 0x5133CC94, 0x62F201AC, - 0x4FFB654D, 0x63EF328F, - 0x4EBFE8A4, 0x64E88926, - 0x4D8162C4, 0x65DDFBD3, - 0x4C3FDFF3, 0x66CF811F, - 0x4AFB6C97, 0x67BD0FBC, - 0x49B41533, 0x68A69E81, - 0x4869E664, 0x698C246C, - 0x471CECE6, 0x6A6D98A4, - 0x45CD358F, 0x6B4AF278, - 0x447ACD50, 0x6C242960, - 0x4325C135, 0x6CF934FB, - 0x41CE1E64, 0x6DCA0D14, - 0x4073F21D, 0x6E96A99C, - 0x3F1749B7, 0x6F5F02B1, - 0x3DB832A5, 0x70231099, - 0x3C56BA70, 0x70E2CBC6, - 0x3AF2EEB7, 0x719E2CD2, - 0x398CDD32, 0x72552C84, - 0x382493B0, 0x7307C3D0, - 0x36BA2013, 0x73B5EBD0, - 0x354D9056, 0x745F9DD1, - 0x33DEF287, 0x7504D345, - 0x326E54C7, 0x75A585CF, - 0x30FBC54D, 0x7641AF3C, - 0x2F875262, 0x76D94988, - 0x2E110A62, 0x776C4EDB, - 0x2C98FBBA, 0x77FAB988, - 0x2B1F34EB, 0x78848413, - 0x29A3C484, 0x7909A92C, - 0x2826B928, 0x798A23B1, - 0x26A82185, 0x7A05EEAD, - 0x25280C5D, 0x7A7D055B, - 0x23A6887E, 0x7AEF6323, - 0x2223A4C5, 0x7B5D039D, - 0x209F701C, 0x7BC5E28F, - 0x1F19F97B, 0x7C29FBEE, - 0x1D934FE5, 0x7C894BDD, - 0x1C0B826A, 0x7CE3CEB1, - 0x1A82A025, 0x7D3980EC, - 0x18F8B83C, 0x7D8A5F3F, - 0x176DD9DE, 0x7DD6668E, - 0x15E21444, 0x7E1D93E9, - 0x145576B1, 0x7E5FE493, - 0x12C8106E, 0x7E9D55FC, - 0x1139F0CE, 0x7ED5E5C6, - 0x0FAB272B, 0x7F0991C3, - 0x0E1BC2E3, 0x7F3857F5, - 0x0C8BD35E, 0x7F62368F, - 0x0AFB6805, 0x7F872BF3, - 0x096A9049, 0x7FA736B4, - 0x07D95B9E, 0x7FC25596, - 0x0647D97C, 0x7FD8878D, - 0x04B6195D, 0x7FE9CBC0, - 0x03242ABF, 0x7FF62182, - 0x01921D1F, 0x7FFD885A, - 0x00000000, 0x7FFFFFFF, - 0xFE6DE2E0, 0x7FFD885A, - 0xFCDBD541, 0x7FF62182, - 0xFB49E6A2, 0x7FE9CBC0, - 0xF9B82683, 0x7FD8878D, - 0xF826A461, 0x7FC25596, - 0xF6956FB6, 0x7FA736B4, - 0xF50497FA, 0x7F872BF3, - 0xF3742CA1, 0x7F62368F, - 0xF1E43D1C, 0x7F3857F5, - 0xF054D8D4, 0x7F0991C3, - 0xEEC60F31, 0x7ED5E5C6, - 0xED37EF91, 0x7E9D55FC, - 0xEBAA894E, 0x7E5FE493, - 0xEA1DEBBB, 0x7E1D93E9, - 0xE8922621, 0x7DD6668E, - 0xE70747C3, 0x7D8A5F3F, - 0xE57D5FDA, 0x7D3980EC, - 0xE3F47D95, 0x7CE3CEB1, - 0xE26CB01A, 0x7C894BDD, - 0xE0E60684, 0x7C29FBEE, - 0xDF608FE3, 0x7BC5E28F, - 0xDDDC5B3A, 0x7B5D039D, - 0xDC597781, 0x7AEF6323, - 0xDAD7F3A2, 0x7A7D055B, - 0xD957DE7A, 0x7A05EEAD, - 0xD7D946D7, 0x798A23B1, - 0xD65C3B7B, 0x7909A92C, - 0xD4E0CB14, 0x78848413, - 0xD3670445, 0x77FAB988, - 0xD1EEF59E, 0x776C4EDB, - 0xD078AD9D, 0x76D94988, - 0xCF043AB2, 0x7641AF3C, - 0xCD91AB38, 0x75A585CF, - 0xCC210D78, 0x7504D345, - 0xCAB26FA9, 0x745F9DD1, - 0xC945DFEC, 0x73B5EBD0, - 0xC7DB6C50, 0x7307C3D0, - 0xC67322CD, 0x72552C84, - 0xC50D1148, 0x719E2CD2, - 0xC3A9458F, 0x70E2CBC6, - 0xC247CD5A, 0x70231099, - 0xC0E8B648, 0x6F5F02B1, - 0xBF8C0DE2, 0x6E96A99C, - 0xBE31E19B, 0x6DCA0D14, - 0xBCDA3ECA, 0x6CF934FB, - 0xBB8532AF, 0x6C242960, - 0xBA32CA70, 0x6B4AF278, - 0xB8E31319, 0x6A6D98A4, - 0xB796199B, 0x698C246C, - 0xB64BEACC, 0x68A69E81, - 0xB5049368, 0x67BD0FBC, - 0xB3C0200C, 0x66CF811F, - 0xB27E9D3B, 0x65DDFBD3, - 0xB140175B, 0x64E88926, - 0xB0049AB2, 0x63EF328F, - 0xAECC336B, 0x62F201AC, - 0xAD96ED91, 0x61F1003E, - 0xAC64D510, 0x60EC3830, - 0xAB35F5B5, 0x5FE3B38D, - 0xAA0A5B2D, 0x5ED77C89, - 0xA8E21106, 0x5DC79D7C, - 0xA7BD22AB, 0x5CB420DF, - 0xA69B9B68, 0x5B9D1153, - 0xA57D8666, 0x5A82799A, - 0xA462EEAC, 0x59646497, - 0xA34BDF20, 0x5842DD54, - 0xA2386283, 0x571DEEF9, - 0xA1288376, 0x55F5A4D2, - 0xA01C4C72, 0x54CA0A4A, - 0x9F13C7D0, 0x539B2AEF, - 0x9E0EFFC1, 0x5269126E, - 0x9D0DFE53, 0x5133CC94, - 0x9C10CD70, 0x4FFB654D, - 0x9B1776D9, 0x4EBFE8A4, - 0x9A22042C, 0x4D8162C4, - 0x99307EE0, 0x4C3FDFF3, - 0x9842F043, 0x4AFB6C97, - 0x9759617E, 0x49B41533, - 0x9673DB94, 0x4869E664, - 0x9592675B, 0x471CECE6, - 0x94B50D87, 0x45CD358F, - 0x93DBD69F, 0x447ACD50, - 0x9306CB04, 0x4325C135, - 0x9235F2EB, 0x41CE1E64, - 0x91695663, 0x4073F21D, - 0x90A0FD4E, 0x3F1749B7, - 0x8FDCEF66, 0x3DB832A5, - 0x8F1D343A, 0x3C56BA70, - 0x8E61D32D, 0x3AF2EEB7, - 0x8DAAD37B, 0x398CDD32, - 0x8CF83C30, 0x382493B0, - 0x8C4A142F, 0x36BA2013, - 0x8BA0622F, 0x354D9056, - 0x8AFB2CBA, 0x33DEF287, - 0x8A5A7A30, 0x326E54C7, - 0x89BE50C3, 0x30FBC54D, - 0x8926B677, 0x2F875262, - 0x8893B124, 0x2E110A62, - 0x88054677, 0x2C98FBBA, - 0x877B7BEC, 0x2B1F34EB, - 0x86F656D3, 0x29A3C484, - 0x8675DC4E, 0x2826B928, - 0x85FA1152, 0x26A82185, - 0x8582FAA4, 0x25280C5D, - 0x85109CDC, 0x23A6887E, - 0x84A2FC62, 0x2223A4C5, - 0x843A1D70, 0x209F701C, - 0x83D60411, 0x1F19F97B, - 0x8376B422, 0x1D934FE5, - 0x831C314E, 0x1C0B826A, - 0x82C67F13, 0x1A82A025, - 0x8275A0C0, 0x18F8B83C, - 0x82299971, 0x176DD9DE, - 0x81E26C16, 0x15E21444, - 0x81A01B6C, 0x145576B1, - 0x8162AA03, 0x12C8106E, - 0x812A1A39, 0x1139F0CE, - 0x80F66E3C, 0x0FAB272B, - 0x80C7A80A, 0x0E1BC2E3, - 0x809DC970, 0x0C8BD35E, - 0x8078D40D, 0x0AFB6805, - 0x8058C94C, 0x096A9049, - 0x803DAA69, 0x07D95B9E, - 0x80277872, 0x0647D97C, - 0x80163440, 0x04B6195D, - 0x8009DE7D, 0x03242ABF, - 0x800277A5, 0x01921D1F, - 0x80000000, 0x00000000, - 0x800277A5, 0xFE6DE2E0, - 0x8009DE7D, 0xFCDBD541, - 0x80163440, 0xFB49E6A2, - 0x80277872, 0xF9B82683, - 0x803DAA69, 0xF826A461, - 0x8058C94C, 0xF6956FB6, - 0x8078D40D, 0xF50497FA, - 0x809DC970, 0xF3742CA1, - 0x80C7A80A, 0xF1E43D1C, - 0x80F66E3C, 0xF054D8D4, - 0x812A1A39, 0xEEC60F31, - 0x8162AA03, 0xED37EF91, - 0x81A01B6C, 0xEBAA894E, - 0x81E26C16, 0xEA1DEBBB, - 0x82299971, 0xE8922621, - 0x8275A0C0, 0xE70747C3, - 0x82C67F13, 0xE57D5FDA, - 0x831C314E, 0xE3F47D95, - 0x8376B422, 0xE26CB01A, - 0x83D60411, 0xE0E60684, - 0x843A1D70, 0xDF608FE3, - 0x84A2FC62, 0xDDDC5B3A, - 0x85109CDC, 0xDC597781, - 0x8582FAA4, 0xDAD7F3A2, - 0x85FA1152, 0xD957DE7A, - 0x8675DC4E, 0xD7D946D7, - 0x86F656D3, 0xD65C3B7B, - 0x877B7BEC, 0xD4E0CB14, - 0x88054677, 0xD3670445, - 0x8893B124, 0xD1EEF59E, - 0x8926B677, 0xD078AD9D, - 0x89BE50C3, 0xCF043AB2, - 0x8A5A7A30, 0xCD91AB38, - 0x8AFB2CBA, 0xCC210D78, - 0x8BA0622F, 0xCAB26FA9, - 0x8C4A142F, 0xC945DFEC, - 0x8CF83C30, 0xC7DB6C50, - 0x8DAAD37B, 0xC67322CD, - 0x8E61D32D, 0xC50D1148, - 0x8F1D343A, 0xC3A9458F, - 0x8FDCEF66, 0xC247CD5A, - 0x90A0FD4E, 0xC0E8B648, - 0x91695663, 0xBF8C0DE2, - 0x9235F2EB, 0xBE31E19B, - 0x9306CB04, 0xBCDA3ECA, - 0x93DBD69F, 0xBB8532AF, - 0x94B50D87, 0xBA32CA70, - 0x9592675B, 0xB8E31319, - 0x9673DB94, 0xB796199B, - 0x9759617E, 0xB64BEACC, - 0x9842F043, 0xB5049368, - 0x99307EE0, 0xB3C0200C, - 0x9A22042C, 0xB27E9D3B, - 0x9B1776D9, 0xB140175B, - 0x9C10CD70, 0xB0049AB2, - 0x9D0DFE53, 0xAECC336B, - 0x9E0EFFC1, 0xAD96ED91, - 0x9F13C7D0, 0xAC64D510, - 0xA01C4C72, 0xAB35F5B5, - 0xA1288376, 0xAA0A5B2D, - 0xA2386283, 0xA8E21106, - 0xA34BDF20, 0xA7BD22AB, - 0xA462EEAC, 0xA69B9B68, - 0xA57D8666, 0xA57D8666, - 0xA69B9B68, 0xA462EEAC, - 0xA7BD22AB, 0xA34BDF20, - 0xA8E21106, 0xA2386283, - 0xAA0A5B2D, 0xA1288376, - 0xAB35F5B5, 0xA01C4C72, - 0xAC64D510, 0x9F13C7D0, - 0xAD96ED91, 0x9E0EFFC1, - 0xAECC336B, 0x9D0DFE53, - 0xB0049AB2, 0x9C10CD70, - 0xB140175B, 0x9B1776D9, - 0xB27E9D3B, 0x9A22042C, - 0xB3C0200C, 0x99307EE0, - 0xB5049368, 0x9842F043, - 0xB64BEACC, 0x9759617E, - 0xB796199B, 0x9673DB94, - 0xB8E31319, 0x9592675B, - 0xBA32CA70, 0x94B50D87, - 0xBB8532AF, 0x93DBD69F, - 0xBCDA3ECA, 0x9306CB04, - 0xBE31E19B, 0x9235F2EB, - 0xBF8C0DE2, 0x91695663, - 0xC0E8B648, 0x90A0FD4E, - 0xC247CD5A, 0x8FDCEF66, - 0xC3A9458F, 0x8F1D343A, - 0xC50D1148, 0x8E61D32D, - 0xC67322CD, 0x8DAAD37B, - 0xC7DB6C50, 0x8CF83C30, - 0xC945DFEC, 0x8C4A142F, - 0xCAB26FA9, 0x8BA0622F, - 0xCC210D78, 0x8AFB2CBA, - 0xCD91AB38, 0x8A5A7A30, - 0xCF043AB2, 0x89BE50C3, - 0xD078AD9D, 0x8926B677, - 0xD1EEF59E, 0x8893B124, - 0xD3670445, 0x88054677, - 0xD4E0CB14, 0x877B7BEC, - 0xD65C3B7B, 0x86F656D3, - 0xD7D946D7, 0x8675DC4E, - 0xD957DE7A, 0x85FA1152, - 0xDAD7F3A2, 0x8582FAA4, - 0xDC597781, 0x85109CDC, - 0xDDDC5B3A, 0x84A2FC62, - 0xDF608FE3, 0x843A1D70, - 0xE0E60684, 0x83D60411, - 0xE26CB01A, 0x8376B422, - 0xE3F47D95, 0x831C314E, - 0xE57D5FDA, 0x82C67F13, - 0xE70747C3, 0x8275A0C0, - 0xE8922621, 0x82299971, - 0xEA1DEBBB, 0x81E26C16, - 0xEBAA894E, 0x81A01B6C, - 0xED37EF91, 0x8162AA03, - 0xEEC60F31, 0x812A1A39, - 0xF054D8D4, 0x80F66E3C, - 0xF1E43D1C, 0x80C7A80A, - 0xF3742CA1, 0x809DC970, - 0xF50497FA, 0x8078D40D, - 0xF6956FB6, 0x8058C94C, - 0xF826A461, 0x803DAA69, - 0xF9B82683, 0x80277872, - 0xFB49E6A2, 0x80163440, - 0xFCDBD541, 0x8009DE7D, - 0xFE6DE2E0, 0x800277A5 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 1024 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_1024_q31[1536] = { - 0x7FFFFFFF, 0x00000000, - 0x7FFF6216, 0x00C90F88, - 0x7FFD885A, 0x01921D1F, - 0x7FFA72D1, 0x025B26D7, - 0x7FF62182, 0x03242ABF, - 0x7FF09477, 0x03ED26E6, - 0x7FE9CBC0, 0x04B6195D, - 0x7FE1C76B, 0x057F0034, - 0x7FD8878D, 0x0647D97C, - 0x7FCE0C3E, 0x0710A344, - 0x7FC25596, 0x07D95B9E, - 0x7FB563B2, 0x08A2009A, - 0x7FA736B4, 0x096A9049, - 0x7F97CEBC, 0x0A3308BC, - 0x7F872BF3, 0x0AFB6805, - 0x7F754E7F, 0x0BC3AC35, - 0x7F62368F, 0x0C8BD35E, - 0x7F4DE450, 0x0D53DB92, - 0x7F3857F5, 0x0E1BC2E3, - 0x7F2191B4, 0x0EE38765, - 0x7F0991C3, 0x0FAB272B, - 0x7EF0585F, 0x1072A047, - 0x7ED5E5C6, 0x1139F0CE, - 0x7EBA3A39, 0x120116D4, - 0x7E9D55FC, 0x12C8106E, - 0x7E7F3956, 0x138EDBB0, - 0x7E5FE493, 0x145576B1, - 0x7E3F57FE, 0x151BDF85, - 0x7E1D93E9, 0x15E21444, - 0x7DFA98A7, 0x16A81305, - 0x7DD6668E, 0x176DD9DE, - 0x7DB0FDF7, 0x183366E8, - 0x7D8A5F3F, 0x18F8B83C, - 0x7D628AC5, 0x19BDCBF2, - 0x7D3980EC, 0x1A82A025, - 0x7D0F4218, 0x1B4732EF, - 0x7CE3CEB1, 0x1C0B826A, - 0x7CB72724, 0x1CCF8CB3, - 0x7C894BDD, 0x1D934FE5, - 0x7C5A3D4F, 0x1E56CA1E, - 0x7C29FBEE, 0x1F19F97B, - 0x7BF88830, 0x1FDCDC1A, - 0x7BC5E28F, 0x209F701C, - 0x7B920B89, 0x2161B39F, - 0x7B5D039D, 0x2223A4C5, - 0x7B26CB4F, 0x22E541AE, - 0x7AEF6323, 0x23A6887E, - 0x7AB6CBA3, 0x24677757, - 0x7A7D055B, 0x25280C5D, - 0x7A4210D8, 0x25E845B5, - 0x7A05EEAD, 0x26A82185, - 0x79C89F6D, 0x27679DF4, - 0x798A23B1, 0x2826B928, - 0x794A7C11, 0x28E5714A, - 0x7909A92C, 0x29A3C484, - 0x78C7ABA1, 0x2A61B101, - 0x78848413, 0x2B1F34EB, - 0x78403328, 0x2BDC4E6F, - 0x77FAB988, 0x2C98FBBA, - 0x77B417DF, 0x2D553AFB, - 0x776C4EDB, 0x2E110A62, - 0x77235F2D, 0x2ECC681E, - 0x76D94988, 0x2F875262, - 0x768E0EA5, 0x3041C760, - 0x7641AF3C, 0x30FBC54D, - 0x75F42C0A, 0x31B54A5D, - 0x75A585CF, 0x326E54C7, - 0x7555BD4B, 0x3326E2C2, - 0x7504D345, 0x33DEF287, - 0x74B2C883, 0x3496824F, - 0x745F9DD1, 0x354D9056, - 0x740B53FA, 0x36041AD9, - 0x73B5EBD0, 0x36BA2013, - 0x735F6626, 0x376F9E46, - 0x7307C3D0, 0x382493B0, - 0x72AF05A6, 0x38D8FE93, - 0x72552C84, 0x398CDD32, - 0x71FA3948, 0x3A402DD1, - 0x719E2CD2, 0x3AF2EEB7, - 0x71410804, 0x3BA51E29, - 0x70E2CBC6, 0x3C56BA70, - 0x708378FE, 0x3D07C1D5, - 0x70231099, 0x3DB832A5, - 0x6FC19385, 0x3E680B2C, - 0x6F5F02B1, 0x3F1749B7, - 0x6EFB5F12, 0x3FC5EC97, - 0x6E96A99C, 0x4073F21D, - 0x6E30E349, 0x4121589A, - 0x6DCA0D14, 0x41CE1E64, - 0x6D6227FA, 0x427A41D0, - 0x6CF934FB, 0x4325C135, - 0x6C8F351C, 0x43D09AEC, - 0x6C242960, 0x447ACD50, - 0x6BB812D0, 0x452456BC, - 0x6B4AF278, 0x45CD358F, - 0x6ADCC964, 0x46756827, - 0x6A6D98A4, 0x471CECE6, - 0x69FD614A, 0x47C3C22E, - 0x698C246C, 0x4869E664, - 0x6919E320, 0x490F57EE, - 0x68A69E81, 0x49B41533, - 0x683257AA, 0x4A581C9D, - 0x67BD0FBC, 0x4AFB6C97, - 0x6746C7D7, 0x4B9E038F, - 0x66CF811F, 0x4C3FDFF3, - 0x66573CBB, 0x4CE10034, - 0x65DDFBD3, 0x4D8162C4, - 0x6563BF92, 0x4E210617, - 0x64E88926, 0x4EBFE8A4, - 0x646C59BF, 0x4F5E08E3, - 0x63EF328F, 0x4FFB654D, - 0x637114CC, 0x5097FC5E, - 0x62F201AC, 0x5133CC94, - 0x6271FA69, 0x51CED46E, - 0x61F1003E, 0x5269126E, - 0x616F146B, 0x53028517, - 0x60EC3830, 0x539B2AEF, - 0x60686CCE, 0x5433027D, - 0x5FE3B38D, 0x54CA0A4A, - 0x5F5E0DB3, 0x556040E2, - 0x5ED77C89, 0x55F5A4D2, - 0x5E50015D, 0x568A34A9, - 0x5DC79D7C, 0x571DEEF9, - 0x5D3E5236, 0x57B0D256, - 0x5CB420DF, 0x5842DD54, - 0x5C290ACC, 0x58D40E8C, - 0x5B9D1153, 0x59646497, - 0x5B1035CF, 0x59F3DE12, - 0x5A82799A, 0x5A82799A, - 0x59F3DE12, 0x5B1035CF, - 0x59646497, 0x5B9D1153, - 0x58D40E8C, 0x5C290ACC, - 0x5842DD54, 0x5CB420DF, - 0x57B0D256, 0x5D3E5236, - 0x571DEEF9, 0x5DC79D7C, - 0x568A34A9, 0x5E50015D, - 0x55F5A4D2, 0x5ED77C89, - 0x556040E2, 0x5F5E0DB3, - 0x54CA0A4A, 0x5FE3B38D, - 0x5433027D, 0x60686CCE, - 0x539B2AEF, 0x60EC3830, - 0x53028517, 0x616F146B, - 0x5269126E, 0x61F1003E, - 0x51CED46E, 0x6271FA69, - 0x5133CC94, 0x62F201AC, - 0x5097FC5E, 0x637114CC, - 0x4FFB654D, 0x63EF328F, - 0x4F5E08E3, 0x646C59BF, - 0x4EBFE8A4, 0x64E88926, - 0x4E210617, 0x6563BF92, - 0x4D8162C4, 0x65DDFBD3, - 0x4CE10034, 0x66573CBB, - 0x4C3FDFF3, 0x66CF811F, - 0x4B9E038F, 0x6746C7D7, - 0x4AFB6C97, 0x67BD0FBC, - 0x4A581C9D, 0x683257AA, - 0x49B41533, 0x68A69E81, - 0x490F57EE, 0x6919E320, - 0x4869E664, 0x698C246C, - 0x47C3C22E, 0x69FD614A, - 0x471CECE6, 0x6A6D98A4, - 0x46756827, 0x6ADCC964, - 0x45CD358F, 0x6B4AF278, - 0x452456BC, 0x6BB812D0, - 0x447ACD50, 0x6C242960, - 0x43D09AEC, 0x6C8F351C, - 0x4325C135, 0x6CF934FB, - 0x427A41D0, 0x6D6227FA, - 0x41CE1E64, 0x6DCA0D14, - 0x4121589A, 0x6E30E349, - 0x4073F21D, 0x6E96A99C, - 0x3FC5EC97, 0x6EFB5F12, - 0x3F1749B7, 0x6F5F02B1, - 0x3E680B2C, 0x6FC19385, - 0x3DB832A5, 0x70231099, - 0x3D07C1D5, 0x708378FE, - 0x3C56BA70, 0x70E2CBC6, - 0x3BA51E29, 0x71410804, - 0x3AF2EEB7, 0x719E2CD2, - 0x3A402DD1, 0x71FA3948, - 0x398CDD32, 0x72552C84, - 0x38D8FE93, 0x72AF05A6, - 0x382493B0, 0x7307C3D0, - 0x376F9E46, 0x735F6626, - 0x36BA2013, 0x73B5EBD0, - 0x36041AD9, 0x740B53FA, - 0x354D9056, 0x745F9DD1, - 0x3496824F, 0x74B2C883, - 0x33DEF287, 0x7504D345, - 0x3326E2C2, 0x7555BD4B, - 0x326E54C7, 0x75A585CF, - 0x31B54A5D, 0x75F42C0A, - 0x30FBC54D, 0x7641AF3C, - 0x3041C760, 0x768E0EA5, - 0x2F875262, 0x76D94988, - 0x2ECC681E, 0x77235F2D, - 0x2E110A62, 0x776C4EDB, - 0x2D553AFB, 0x77B417DF, - 0x2C98FBBA, 0x77FAB988, - 0x2BDC4E6F, 0x78403328, - 0x2B1F34EB, 0x78848413, - 0x2A61B101, 0x78C7ABA1, - 0x29A3C484, 0x7909A92C, - 0x28E5714A, 0x794A7C11, - 0x2826B928, 0x798A23B1, - 0x27679DF4, 0x79C89F6D, - 0x26A82185, 0x7A05EEAD, - 0x25E845B5, 0x7A4210D8, - 0x25280C5D, 0x7A7D055B, - 0x24677757, 0x7AB6CBA3, - 0x23A6887E, 0x7AEF6323, - 0x22E541AE, 0x7B26CB4F, - 0x2223A4C5, 0x7B5D039D, - 0x2161B39F, 0x7B920B89, - 0x209F701C, 0x7BC5E28F, - 0x1FDCDC1A, 0x7BF88830, - 0x1F19F97B, 0x7C29FBEE, - 0x1E56CA1E, 0x7C5A3D4F, - 0x1D934FE5, 0x7C894BDD, - 0x1CCF8CB3, 0x7CB72724, - 0x1C0B826A, 0x7CE3CEB1, - 0x1B4732EF, 0x7D0F4218, - 0x1A82A025, 0x7D3980EC, - 0x19BDCBF2, 0x7D628AC5, - 0x18F8B83C, 0x7D8A5F3F, - 0x183366E8, 0x7DB0FDF7, - 0x176DD9DE, 0x7DD6668E, - 0x16A81305, 0x7DFA98A7, - 0x15E21444, 0x7E1D93E9, - 0x151BDF85, 0x7E3F57FE, - 0x145576B1, 0x7E5FE493, - 0x138EDBB0, 0x7E7F3956, - 0x12C8106E, 0x7E9D55FC, - 0x120116D4, 0x7EBA3A39, - 0x1139F0CE, 0x7ED5E5C6, - 0x1072A047, 0x7EF0585F, - 0x0FAB272B, 0x7F0991C3, - 0x0EE38765, 0x7F2191B4, - 0x0E1BC2E3, 0x7F3857F5, - 0x0D53DB92, 0x7F4DE450, - 0x0C8BD35E, 0x7F62368F, - 0x0BC3AC35, 0x7F754E7F, - 0x0AFB6805, 0x7F872BF3, - 0x0A3308BC, 0x7F97CEBC, - 0x096A9049, 0x7FA736B4, - 0x08A2009A, 0x7FB563B2, - 0x07D95B9E, 0x7FC25596, - 0x0710A344, 0x7FCE0C3E, - 0x0647D97C, 0x7FD8878D, - 0x057F0034, 0x7FE1C76B, - 0x04B6195D, 0x7FE9CBC0, - 0x03ED26E6, 0x7FF09477, - 0x03242ABF, 0x7FF62182, - 0x025B26D7, 0x7FFA72D1, - 0x01921D1F, 0x7FFD885A, - 0x00C90F88, 0x7FFF6216, - 0x00000000, 0x7FFFFFFF, - 0xFF36F078, 0x7FFF6216, - 0xFE6DE2E0, 0x7FFD885A, - 0xFDA4D928, 0x7FFA72D1, - 0xFCDBD541, 0x7FF62182, - 0xFC12D919, 0x7FF09477, - 0xFB49E6A2, 0x7FE9CBC0, - 0xFA80FFCB, 0x7FE1C76B, - 0xF9B82683, 0x7FD8878D, - 0xF8EF5CBB, 0x7FCE0C3E, - 0xF826A461, 0x7FC25596, - 0xF75DFF65, 0x7FB563B2, - 0xF6956FB6, 0x7FA736B4, - 0xF5CCF743, 0x7F97CEBC, - 0xF50497FA, 0x7F872BF3, - 0xF43C53CA, 0x7F754E7F, - 0xF3742CA1, 0x7F62368F, - 0xF2AC246D, 0x7F4DE450, - 0xF1E43D1C, 0x7F3857F5, - 0xF11C789A, 0x7F2191B4, - 0xF054D8D4, 0x7F0991C3, - 0xEF8D5FB8, 0x7EF0585F, - 0xEEC60F31, 0x7ED5E5C6, - 0xEDFEE92B, 0x7EBA3A39, - 0xED37EF91, 0x7E9D55FC, - 0xEC71244F, 0x7E7F3956, - 0xEBAA894E, 0x7E5FE493, - 0xEAE4207A, 0x7E3F57FE, - 0xEA1DEBBB, 0x7E1D93E9, - 0xE957ECFB, 0x7DFA98A7, - 0xE8922621, 0x7DD6668E, - 0xE7CC9917, 0x7DB0FDF7, - 0xE70747C3, 0x7D8A5F3F, - 0xE642340D, 0x7D628AC5, - 0xE57D5FDA, 0x7D3980EC, - 0xE4B8CD10, 0x7D0F4218, - 0xE3F47D95, 0x7CE3CEB1, - 0xE330734C, 0x7CB72724, - 0xE26CB01A, 0x7C894BDD, - 0xE1A935E1, 0x7C5A3D4F, - 0xE0E60684, 0x7C29FBEE, - 0xE02323E5, 0x7BF88830, - 0xDF608FE3, 0x7BC5E28F, - 0xDE9E4C60, 0x7B920B89, - 0xDDDC5B3A, 0x7B5D039D, - 0xDD1ABE51, 0x7B26CB4F, - 0xDC597781, 0x7AEF6323, - 0xDB9888A8, 0x7AB6CBA3, - 0xDAD7F3A2, 0x7A7D055B, - 0xDA17BA4A, 0x7A4210D8, - 0xD957DE7A, 0x7A05EEAD, - 0xD898620C, 0x79C89F6D, - 0xD7D946D7, 0x798A23B1, - 0xD71A8EB5, 0x794A7C11, - 0xD65C3B7B, 0x7909A92C, - 0xD59E4EFE, 0x78C7ABA1, - 0xD4E0CB14, 0x78848413, - 0xD423B190, 0x78403328, - 0xD3670445, 0x77FAB988, - 0xD2AAC504, 0x77B417DF, - 0xD1EEF59E, 0x776C4EDB, - 0xD13397E1, 0x77235F2D, - 0xD078AD9D, 0x76D94988, - 0xCFBE389F, 0x768E0EA5, - 0xCF043AB2, 0x7641AF3C, - 0xCE4AB5A2, 0x75F42C0A, - 0xCD91AB38, 0x75A585CF, - 0xCCD91D3D, 0x7555BD4B, - 0xCC210D78, 0x7504D345, - 0xCB697DB0, 0x74B2C883, - 0xCAB26FA9, 0x745F9DD1, - 0xC9FBE527, 0x740B53FA, - 0xC945DFEC, 0x73B5EBD0, - 0xC89061BA, 0x735F6626, - 0xC7DB6C50, 0x7307C3D0, - 0xC727016C, 0x72AF05A6, - 0xC67322CD, 0x72552C84, - 0xC5BFD22E, 0x71FA3948, - 0xC50D1148, 0x719E2CD2, - 0xC45AE1D7, 0x71410804, - 0xC3A9458F, 0x70E2CBC6, - 0xC2F83E2A, 0x708378FE, - 0xC247CD5A, 0x70231099, - 0xC197F4D3, 0x6FC19385, - 0xC0E8B648, 0x6F5F02B1, - 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0x86F656D3, 0x29A3C484, - 0x86B583EE, 0x28E5714A, - 0x8675DC4E, 0x2826B928, - 0x86376092, 0x27679DF4, - 0x85FA1152, 0x26A82185, - 0x85BDEF27, 0x25E845B5, - 0x8582FAA4, 0x25280C5D, - 0x8549345C, 0x24677757, - 0x85109CDC, 0x23A6887E, - 0x84D934B0, 0x22E541AE, - 0x84A2FC62, 0x2223A4C5, - 0x846DF476, 0x2161B39F, - 0x843A1D70, 0x209F701C, - 0x840777CF, 0x1FDCDC1A, - 0x83D60411, 0x1F19F97B, - 0x83A5C2B0, 0x1E56CA1E, - 0x8376B422, 0x1D934FE5, - 0x8348D8DB, 0x1CCF8CB3, - 0x831C314E, 0x1C0B826A, - 0x82F0BDE8, 0x1B4732EF, - 0x82C67F13, 0x1A82A025, - 0x829D753A, 0x19BDCBF2, - 0x8275A0C0, 0x18F8B83C, - 0x824F0208, 0x183366E8, - 0x82299971, 0x176DD9DE, - 0x82056758, 0x16A81305, - 0x81E26C16, 0x15E21444, - 0x81C0A801, 0x151BDF85, - 0x81A01B6C, 0x145576B1, - 0x8180C6A9, 0x138EDBB0, - 0x8162AA03, 0x12C8106E, - 0x8145C5C6, 0x120116D4, - 0x812A1A39, 0x1139F0CE, - 0x810FA7A0, 0x1072A047, - 0x80F66E3C, 0x0FAB272B, - 0x80DE6E4C, 0x0EE38765, - 0x80C7A80A, 0x0E1BC2E3, - 0x80B21BAF, 0x0D53DB92, - 0x809DC970, 0x0C8BD35E, - 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0x8971F15A, 0xCFBE389F, - 0x89BE50C3, 0xCF043AB2, - 0x8A0BD3F5, 0xCE4AB5A2, - 0x8A5A7A30, 0xCD91AB38, - 0x8AAA42B4, 0xCCD91D3D, - 0x8AFB2CBA, 0xCC210D78, - 0x8B4D377C, 0xCB697DB0, - 0x8BA0622F, 0xCAB26FA9, - 0x8BF4AC05, 0xC9FBE527, - 0x8C4A142F, 0xC945DFEC, - 0x8CA099D9, 0xC89061BA, - 0x8CF83C30, 0xC7DB6C50, - 0x8D50FA59, 0xC727016C, - 0x8DAAD37B, 0xC67322CD, - 0x8E05C6B7, 0xC5BFD22E, - 0x8E61D32D, 0xC50D1148, - 0x8EBEF7FB, 0xC45AE1D7, - 0x8F1D343A, 0xC3A9458F, - 0x8F7C8701, 0xC2F83E2A, - 0x8FDCEF66, 0xC247CD5A, - 0x903E6C7A, 0xC197F4D3, - 0x90A0FD4E, 0xC0E8B648, - 0x9104A0ED, 0xC03A1368, - 0x91695663, 0xBF8C0DE2, - 0x91CF1CB6, 0xBEDEA765, - 0x9235F2EB, 0xBE31E19B, - 0x929DD805, 0xBD85BE2F, - 0x9306CB04, 0xBCDA3ECA, - 0x9370CAE4, 0xBC2F6513, - 0x93DBD69F, 0xBB8532AF, - 0x9447ED2F, 0xBADBA943, - 0x94B50D87, 0xBA32CA70, - 0x9523369B, 0xB98A97D8, - 0x9592675B, 0xB8E31319, - 0x96029EB5, 0xB83C3DD1, - 0x9673DB94, 0xB796199B, - 0x96E61CDF, 0xB6F0A811, - 0x9759617E, 0xB64BEACC, - 0x97CDA855, 0xB5A7E362, - 0x9842F043, 0xB5049368, - 0x98B93828, 0xB461FC70, - 0x99307EE0, 0xB3C0200C, - 0x99A8C344, 0xB31EFFCB, - 0x9A22042C, 0xB27E9D3B, - 0x9A9C406D, 0xB1DEF9E8, - 0x9B1776D9, 0xB140175B, - 0x9B93A640, 0xB0A1F71C, - 0x9C10CD70, 0xB0049AB2, - 0x9C8EEB33, 0xAF6803A1, - 0x9D0DFE53, 0xAECC336B, - 0x9D8E0596, 0xAE312B91, - 0x9E0EFFC1, 0xAD96ED91, - 0x9E90EB94, 0xACFD7AE8, - 0x9F13C7D0, 0xAC64D510, - 0x9F979331, 0xABCCFD82, - 0xA01C4C72, 0xAB35F5B5, - 0xA0A1F24C, 0xAA9FBF1D, - 0xA1288376, 0xAA0A5B2D, - 0xA1AFFEA2, 0xA975CB56, - 0xA2386283, 0xA8E21106, - 0xA2C1ADC9, 0xA84F2DA9, - 0xA34BDF20, 0xA7BD22AB, - 0xA3D6F533, 0xA72BF173, - 0xA462EEAC, 0xA69B9B68, - 0xA4EFCA31, 0xA60C21ED, - 0xA57D8666, 0xA57D8666, - 0xA60C21ED, 0xA4EFCA31, - 0xA69B9B68, 0xA462EEAC, - 0xA72BF173, 0xA3D6F533, - 0xA7BD22AB, 0xA34BDF20, - 0xA84F2DA9, 0xA2C1ADC9, - 0xA8E21106, 0xA2386283, - 0xA975CB56, 0xA1AFFEA2, - 0xAA0A5B2D, 0xA1288376, - 0xAA9FBF1D, 0xA0A1F24C, - 0xAB35F5B5, 0xA01C4C72, - 0xABCCFD82, 0x9F979331, - 0xAC64D510, 0x9F13C7D0, - 0xACFD7AE8, 0x9E90EB94, - 0xAD96ED91, 0x9E0EFFC1, - 0xAE312B91, 0x9D8E0596, - 0xAECC336B, 0x9D0DFE53, - 0xAF6803A1, 0x9C8EEB33, - 0xB0049AB2, 0x9C10CD70, - 0xB0A1F71C, 0x9B93A640, - 0xB140175B, 0x9B1776D9, - 0xB1DEF9E8, 0x9A9C406D, - 0xB27E9D3B, 0x9A22042C, - 0xB31EFFCB, 0x99A8C344, - 0xB3C0200C, 0x99307EE0, - 0xB461FC70, 0x98B93828, - 0xB5049368, 0x9842F043, - 0xB5A7E362, 0x97CDA855, - 0xB64BEACC, 0x9759617E, - 0xB6F0A811, 0x96E61CDF, - 0xB796199B, 0x9673DB94, - 0xB83C3DD1, 0x96029EB5, - 0xB8E31319, 0x9592675B, - 0xB98A97D8, 0x9523369B, - 0xBA32CA70, 0x94B50D87, - 0xBADBA943, 0x9447ED2F, - 0xBB8532AF, 0x93DBD69F, - 0xBC2F6513, 0x9370CAE4, - 0xBCDA3ECA, 0x9306CB04, - 0xBD85BE2F, 0x929DD805, - 0xBE31E19B, 0x9235F2EB, - 0xBEDEA765, 0x91CF1CB6, - 0xBF8C0DE2, 0x91695663, - 0xC03A1368, 0x9104A0ED, - 0xC0E8B648, 0x90A0FD4E, - 0xC197F4D3, 0x903E6C7A, - 0xC247CD5A, 0x8FDCEF66, - 0xC2F83E2A, 0x8F7C8701, - 0xC3A9458F, 0x8F1D343A, - 0xC45AE1D7, 0x8EBEF7FB, - 0xC50D1148, 0x8E61D32D, - 0xC5BFD22E, 0x8E05C6B7, - 0xC67322CD, 0x8DAAD37B, - 0xC727016C, 0x8D50FA59, - 0xC7DB6C50, 0x8CF83C30, - 0xC89061BA, 0x8CA099D9, - 0xC945DFEC, 0x8C4A142F, - 0xC9FBE527, 0x8BF4AC05, - 0xCAB26FA9, 0x8BA0622F, - 0xCB697DB0, 0x8B4D377C, - 0xCC210D78, 0x8AFB2CBA, - 0xCCD91D3D, 0x8AAA42B4, - 0xCD91AB38, 0x8A5A7A30, - 0xCE4AB5A2, 0x8A0BD3F5, - 0xCF043AB2, 0x89BE50C3, - 0xCFBE389F, 0x8971F15A, - 0xD078AD9D, 0x8926B677, - 0xD13397E1, 0x88DCA0D3, - 0xD1EEF59E, 0x8893B124, - 0xD2AAC504, 0x884BE820, - 0xD3670445, 0x88054677, - 0xD423B190, 0x87BFCCD7, - 0xD4E0CB14, 0x877B7BEC, - 0xD59E4EFE, 0x8738545E, - 0xD65C3B7B, 0x86F656D3, - 0xD71A8EB5, 0x86B583EE, - 0xD7D946D7, 0x8675DC4E, - 0xD898620C, 0x86376092, - 0xD957DE7A, 0x85FA1152, - 0xDA17BA4A, 0x85BDEF27, - 0xDAD7F3A2, 0x8582FAA4, - 0xDB9888A8, 0x8549345C, - 0xDC597781, 0x85109CDC, - 0xDD1ABE51, 0x84D934B0, - 0xDDDC5B3A, 0x84A2FC62, - 0xDE9E4C60, 0x846DF476, - 0xDF608FE3, 0x843A1D70, - 0xE02323E5, 0x840777CF, - 0xE0E60684, 0x83D60411, - 0xE1A935E1, 0x83A5C2B0, - 0xE26CB01A, 0x8376B422, - 0xE330734C, 0x8348D8DB, - 0xE3F47D95, 0x831C314E, - 0xE4B8CD10, 0x82F0BDE8, - 0xE57D5FDA, 0x82C67F13, - 0xE642340D, 0x829D753A, - 0xE70747C3, 0x8275A0C0, - 0xE7CC9917, 0x824F0208, - 0xE8922621, 0x82299971, - 0xE957ECFB, 0x82056758, - 0xEA1DEBBB, 0x81E26C16, - 0xEAE4207A, 0x81C0A801, - 0xEBAA894E, 0x81A01B6C, - 0xEC71244F, 0x8180C6A9, - 0xED37EF91, 0x8162AA03, - 0xEDFEE92B, 0x8145C5C6, - 0xEEC60F31, 0x812A1A39, - 0xEF8D5FB8, 0x810FA7A0, - 0xF054D8D4, 0x80F66E3C, - 0xF11C789A, 0x80DE6E4C, - 0xF1E43D1C, 0x80C7A80A, - 0xF2AC246D, 0x80B21BAF, - 0xF3742CA1, 0x809DC970, - 0xF43C53CA, 0x808AB180, - 0xF50497FA, 0x8078D40D, - 0xF5CCF743, 0x80683143, - 0xF6956FB6, 0x8058C94C, - 0xF75DFF65, 0x804A9C4D, - 0xF826A461, 0x803DAA69, - 0xF8EF5CBB, 0x8031F3C1, - 0xF9B82683, 0x80277872, - 0xFA80FFCB, 0x801E3894, - 0xFB49E6A2, 0x80163440, - 0xFC12D919, 0x800F6B88, - 0xFCDBD541, 0x8009DE7D, - 0xFDA4D928, 0x80058D2E, - 0xFE6DE2E0, 0x800277A5, - 0xFF36F078, 0x80009DE9 -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 2048 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_2048_q31[3072] = { - 0x7FFFFFFF, 0x00000000, - 0x7FFFD885, 0x006487E3, - 0x7FFF6216, 0x00C90F88, - 0x7FFE9CB2, 0x012D96B0, - 0x7FFD885A, 0x01921D1F, - 0x7FFC250F, 0x01F6A296, - 0x7FFA72D1, 0x025B26D7, - 0x7FF871A1, 0x02BFA9A4, - 0x7FF62182, 0x03242ABF, - 0x7FF38273, 0x0388A9E9, - 0x7FF09477, 0x03ED26E6, - 0x7FED5790, 0x0451A176, - 0x7FE9CBC0, 0x04B6195D, - 0x7FE5F108, 0x051A8E5C, - 0x7FE1C76B, 0x057F0034, - 0x7FDD4EEC, 0x05E36EA9, - 0x7FD8878D, 0x0647D97C, - 0x7FD37152, 0x06AC406F, - 0x7FCE0C3E, 0x0710A344, - 0x7FC85853, 0x077501BE, - 0x7FC25596, 0x07D95B9E, - 0x7FBC040A, 0x083DB0A7, - 0x7FB563B2, 0x08A2009A, - 0x7FAE7494, 0x09064B3A, - 0x7FA736B4, 0x096A9049, - 0x7F9FAA15, 0x09CECF89, - 0x7F97CEBC, 0x0A3308BC, - 0x7F8FA4AF, 0x0A973BA5, - 0x7F872BF3, 0x0AFB6805, - 0x7F7E648B, 0x0B5F8D9F, - 0x7F754E7F, 0x0BC3AC35, - 0x7F6BE9D4, 0x0C27C389, - 0x7F62368F, 0x0C8BD35E, - 0x7F5834B6, 0x0CEFDB75, - 0x7F4DE450, 0x0D53DB92, - 0x7F434563, 0x0DB7D376, - 0x7F3857F5, 0x0E1BC2E3, - 0x7F2D1C0E, 0x0E7FA99D, - 0x7F2191B4, 0x0EE38765, - 0x7F15B8EE, 0x0F475BFE, - 0x7F0991C3, 0x0FAB272B, - 0x7EFD1C3C, 0x100EE8AD, - 0x7EF0585F, 0x1072A047, - 0x7EE34635, 0x10D64DBC, - 0x7ED5E5C6, 0x1139F0CE, - 0x7EC8371A, 0x119D8940, - 0x7EBA3A39, 0x120116D4, - 0x7EABEF2C, 0x1264994E, - 0x7E9D55FC, 0x12C8106E, - 0x7E8E6EB1, 0x132B7BF9, - 0x7E7F3956, 0x138EDBB0, - 0x7E6FB5F3, 0x13F22F57, - 0x7E5FE493, 0x145576B1, - 0x7E4FC53E, 0x14B8B17F, - 0x7E3F57FE, 0x151BDF85, - 0x7E2E9CDF, 0x157F0086, - 0x7E1D93E9, 0x15E21444, - 0x7E0C3D29, 0x16451A83, - 0x7DFA98A7, 0x16A81305, - 0x7DE8A670, 0x170AFD8D, - 0x7DD6668E, 0x176DD9DE, - 0x7DC3D90D, 0x17D0A7BB, - 0x7DB0FDF7, 0x183366E8, - 0x7D9DD55A, 0x18961727, - 0x7D8A5F3F, 0x18F8B83C, - 0x7D769BB5, 0x195B49E9, - 0x7D628AC5, 0x19BDCBF2, - 0x7D4E2C7E, 0x1A203E1B, - 0x7D3980EC, 0x1A82A025, - 0x7D24881A, 0x1AE4F1D6, - 0x7D0F4218, 0x1B4732EF, - 0x7CF9AEF0, 0x1BA96334, - 0x7CE3CEB1, 0x1C0B826A, - 0x7CCDA168, 0x1C6D9053, - 0x7CB72724, 0x1CCF8CB3, - 0x7CA05FF1, 0x1D31774D, - 0x7C894BDD, 0x1D934FE5, - 0x7C71EAF8, 0x1DF5163F, - 0x7C5A3D4F, 0x1E56CA1E, - 0x7C4242F2, 0x1EB86B46, - 0x7C29FBEE, 0x1F19F97B, - 0x7C116853, 0x1F7B7480, - 0x7BF88830, 0x1FDCDC1A, - 0x7BDF5B94, 0x203E300D, - 0x7BC5E28F, 0x209F701C, - 0x7BAC1D31, 0x21009C0B, - 0x7B920B89, 0x2161B39F, - 0x7B77ADA8, 0x21C2B69C, - 0x7B5D039D, 0x2223A4C5, - 0x7B420D7A, 0x22847DDF, - 0x7B26CB4F, 0x22E541AE, - 0x7B0B3D2C, 0x2345EFF7, - 0x7AEF6323, 0x23A6887E, - 0x7AD33D45, 0x24070B07, - 0x7AB6CBA3, 0x24677757, - 0x7A9A0E4F, 0x24C7CD32, - 0x7A7D055B, 0x25280C5D, - 0x7A5FB0D8, 0x2588349D, - 0x7A4210D8, 0x25E845B5, - 0x7A24256E, 0x26483F6C, - 0x7A05EEAD, 0x26A82185, - 0x79E76CA6, 0x2707EBC6, - 0x79C89F6D, 0x27679DF4, - 0x79A98715, 0x27C737D2, - 0x798A23B1, 0x2826B928, - 0x796A7554, 0x288621B9, - 0x794A7C11, 0x28E5714A, - 0x792A37FE, 0x2944A7A2, - 0x7909A92C, 0x29A3C484, - 0x78E8CFB1, 0x2A02C7B8, - 0x78C7ABA1, 0x2A61B101, - 0x78A63D10, 0x2AC08025, - 0x78848413, 0x2B1F34EB, - 0x786280BF, 0x2B7DCF17, - 0x78403328, 0x2BDC4E6F, - 0x781D9B64, 0x2C3AB2B9, - 0x77FAB988, 0x2C98FBBA, - 0x77D78DAA, 0x2CF72939, - 0x77B417DF, 0x2D553AFB, - 0x7790583D, 0x2DB330C7, - 0x776C4EDB, 0x2E110A62, - 0x7747FBCE, 0x2E6EC792, - 0x77235F2D, 0x2ECC681E, - 0x76FE790E, 0x2F29EBCC, - 0x76D94988, 0x2F875262, - 0x76B3D0B3, 0x2FE49BA6, - 0x768E0EA5, 0x3041C760, - 0x76680376, 0x309ED555, - 0x7641AF3C, 0x30FBC54D, - 0x761B1211, 0x3158970D, - 0x75F42C0A, 0x31B54A5D, - 0x75CCFD42, 0x3211DF03, - 0x75A585CF, 0x326E54C7, - 0x757DC5CA, 0x32CAAB6F, - 0x7555BD4B, 0x3326E2C2, - 0x752D6C6C, 0x3382FA88, - 0x7504D345, 0x33DEF287, - 0x74DBF1EF, 0x343ACA87, - 0x74B2C883, 0x3496824F, - 0x7489571B, 0x34F219A7, - 0x745F9DD1, 0x354D9056, - 0x74359CBD, 0x35A8E624, - 0x740B53FA, 0x36041AD9, - 0x73E0C3A3, 0x365F2E3B, - 0x73B5EBD0, 0x36BA2013, - 0x738ACC9E, 0x3714F02A, - 0x735F6626, 0x376F9E46, - 0x7333B883, 0x37CA2A30, - 0x7307C3D0, 0x382493B0, - 0x72DB8828, 0x387EDA8E, - 0x72AF05A6, 0x38D8FE93, - 0x72823C66, 0x3932FF87, - 0x72552C84, 0x398CDD32, - 0x7227D61C, 0x39E6975D, - 0x71FA3948, 0x3A402DD1, - 0x71CC5626, 0x3A99A057, - 0x719E2CD2, 0x3AF2EEB7, - 0x716FBD68, 0x3B4C18BA, - 0x71410804, 0x3BA51E29, - 0x71120CC5, 0x3BFDFECD, - 0x70E2CBC6, 0x3C56BA70, - 0x70B34524, 0x3CAF50DA, - 0x708378FE, 0x3D07C1D5, - 0x70536771, 0x3D600D2B, - 0x70231099, 0x3DB832A5, - 0x6FF27496, 0x3E10320D, - 0x6FC19385, 0x3E680B2C, - 0x6F906D84, 0x3EBFBDCC, - 0x6F5F02B1, 0x3F1749B7, - 0x6F2D532C, 0x3F6EAEB8, - 0x6EFB5F12, 0x3FC5EC97, - 0x6EC92682, 0x401D0320, - 0x6E96A99C, 0x4073F21D, - 0x6E63E87F, 0x40CAB957, - 0x6E30E349, 0x4121589A, - 0x6DFD9A1B, 0x4177CFB0, - 0x6DCA0D14, 0x41CE1E64, - 0x6D963C54, 0x42244480, - 0x6D6227FA, 0x427A41D0, - 0x6D2DD027, 0x42D0161E, - 0x6CF934FB, 0x4325C135, - 0x6CC45697, 0x437B42E1, - 0x6C8F351C, 0x43D09AEC, - 0x6C59D0A9, 0x4425C923, - 0x6C242960, 0x447ACD50, - 0x6BEE3F62, 0x44CFA73F, - 0x6BB812D0, 0x452456BC, - 0x6B81A3CD, 0x4578DB93, - 0x6B4AF278, 0x45CD358F, - 0x6B13FEF5, 0x4621647C, - 0x6ADCC964, 0x46756827, - 0x6AA551E8, 0x46C9405C, - 0x6A6D98A4, 0x471CECE6, - 0x6A359DB9, 0x47706D93, - 0x69FD614A, 0x47C3C22E, - 0x69C4E37A, 0x4816EA85, - 0x698C246C, 0x4869E664, - 0x69532442, 0x48BCB598, - 0x6919E320, 0x490F57EE, - 0x68E06129, 0x4961CD32, - 0x68A69E81, 0x49B41533, - 0x686C9B4B, 0x4A062FBD, - 0x683257AA, 0x4A581C9D, - 0x67F7D3C4, 0x4AA9DBA1, - 0x67BD0FBC, 0x4AFB6C97, - 0x67820BB6, 0x4B4CCF4D, - 0x6746C7D7, 0x4B9E038F, - 0x670B4443, 0x4BEF092D, - 0x66CF811F, 0x4C3FDFF3, - 0x66937E90, 0x4C9087B1, - 0x66573CBB, 0x4CE10034, - 0x661ABBC5, 0x4D31494B, - 0x65DDFBD3, 0x4D8162C4, - 0x65A0FD0B, 0x4DD14C6E, - 0x6563BF92, 0x4E210617, - 0x6526438E, 0x4E708F8F, - 0x64E88926, 0x4EBFE8A4, - 0x64AA907F, 0x4F0F1126, - 0x646C59BF, 0x4F5E08E3, - 0x642DE50D, 0x4FACCFAB, - 0x63EF328F, 0x4FFB654D, - 0x63B0426D, 0x5049C999, - 0x637114CC, 0x5097FC5E, - 0x6331A9D4, 0x50E5FD6C, - 0x62F201AC, 0x5133CC94, - 0x62B21C7B, 0x518169A4, - 0x6271FA69, 0x51CED46E, - 0x62319B9D, 0x521C0CC1, - 0x61F1003E, 0x5269126E, - 0x61B02876, 0x52B5E545, - 0x616F146B, 0x53028517, - 0x612DC446, 0x534EF1B5, - 0x60EC3830, 0x539B2AEF, - 0x60AA704F, 0x53E73097, - 0x60686CCE, 0x5433027D, - 0x60262DD5, 0x547EA073, - 0x5FE3B38D, 0x54CA0A4A, - 0x5FA0FE1E, 0x55153FD4, - 0x5F5E0DB3, 0x556040E2, - 0x5F1AE273, 0x55AB0D46, - 0x5ED77C89, 0x55F5A4D2, - 0x5E93DC1F, 0x56400757, - 0x5E50015D, 0x568A34A9, - 0x5E0BEC6E, 0x56D42C99, - 0x5DC79D7C, 0x571DEEF9, - 0x5D8314B0, 0x57677B9D, - 0x5D3E5236, 0x57B0D256, - 0x5CF95638, 0x57F9F2F7, - 0x5CB420DF, 0x5842DD54, - 0x5C6EB258, 0x588B913F, - 0x5C290ACC, 0x58D40E8C, - 0x5BE32A67, 0x591C550E, - 0x5B9D1153, 0x59646497, - 0x5B56BFBD, 0x59AC3CFD, - 0x5B1035CF, 0x59F3DE12, - 0x5AC973B4, 0x5A3B47AA, - 0x5A82799A, 0x5A82799A, - 0x5A3B47AA, 0x5AC973B4, - 0x59F3DE12, 0x5B1035CF, - 0x59AC3CFD, 0x5B56BFBD, - 0x59646497, 0x5B9D1153, - 0x591C550E, 0x5BE32A67, - 0x58D40E8C, 0x5C290ACC, - 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0x8217598F, 0x170AFD8D, - 0x82056758, 0x16A81305, - 0x81F3C2D7, 0x16451A83, - 0x81E26C16, 0x15E21444, - 0x81D16320, 0x157F0086, - 0x81C0A801, 0x151BDF85, - 0x81B03AC1, 0x14B8B17F, - 0x81A01B6C, 0x145576B1, - 0x81904A0C, 0x13F22F57, - 0x8180C6A9, 0x138EDBB0, - 0x8171914E, 0x132B7BF9, - 0x8162AA03, 0x12C8106E, - 0x815410D3, 0x1264994E, - 0x8145C5C6, 0x120116D4, - 0x8137C8E6, 0x119D8940, - 0x812A1A39, 0x1139F0CE, - 0x811CB9CA, 0x10D64DBC, - 0x810FA7A0, 0x1072A047, - 0x8102E3C3, 0x100EE8AD, - 0x80F66E3C, 0x0FAB272B, - 0x80EA4712, 0x0F475BFE, - 0x80DE6E4C, 0x0EE38765, - 0x80D2E3F1, 0x0E7FA99D, - 0x80C7A80A, 0x0E1BC2E3, - 0x80BCBA9C, 0x0DB7D376, - 0x80B21BAF, 0x0D53DB92, - 0x80A7CB49, 0x0CEFDB75, - 0x809DC970, 0x0C8BD35E, - 0x8094162B, 0x0C27C389, - 0x808AB180, 0x0BC3AC35, - 0x80819B74, 0x0B5F8D9F, - 0x8078D40D, 0x0AFB6805, - 0x80705B50, 0x0A973BA5, - 0x80683143, 0x0A3308BC, - 0x806055EA, 0x09CECF89, - 0x8058C94C, 0x096A9049, - 0x80518B6B, 0x09064B3A, - 0x804A9C4D, 0x08A2009A, - 0x8043FBF6, 0x083DB0A7, - 0x803DAA69, 0x07D95B9E, - 0x8037A7AC, 0x077501BE, - 0x8031F3C1, 0x0710A344, - 0x802C8EAD, 0x06AC406F, - 0x80277872, 0x0647D97C, - 0x8022B113, 0x05E36EA9, - 0x801E3894, 0x057F0034, - 0x801A0EF7, 0x051A8E5C, - 0x80163440, 0x04B6195D, - 0x8012A86F, 0x0451A176, - 0x800F6B88, 0x03ED26E6, - 0x800C7D8C, 0x0388A9E9, - 0x8009DE7D, 0x03242ABF, - 0x80078E5E, 0x02BFA9A4, - 0x80058D2E, 0x025B26D7, - 0x8003DAF0, 0x01F6A296, - 0x800277A5, 0x01921D1F, - 0x8001634D, 0x012D96B0, - 0x80009DE9, 0x00C90F88, - 0x8000277A, 0x006487E3, - 0x80000000, 0x00000000, - 0x8000277A, 0xFF9B781D, - 0x80009DE9, 0xFF36F078, - 0x8001634D, 0xFED2694F, - 0x800277A5, 0xFE6DE2E0, - 0x8003DAF0, 0xFE095D69, - 0x80058D2E, 0xFDA4D928, - 0x80078E5E, 0xFD40565B, - 0x8009DE7D, 0xFCDBD541, - 0x800C7D8C, 0xFC775616, - 0x800F6B88, 0xFC12D919, - 0x8012A86F, 0xFBAE5E89, - 0x80163440, 0xFB49E6A2, - 0x801A0EF7, 0xFAE571A4, - 0x801E3894, 0xFA80FFCB, - 0x8022B113, 0xFA1C9156, - 0x80277872, 0xF9B82683, - 0x802C8EAD, 0xF953BF90, - 0x8031F3C1, 0xF8EF5CBB, - 0x8037A7AC, 0xF88AFE41, - 0x803DAA69, 0xF826A461, - 0x8043FBF6, 0xF7C24F58, - 0x804A9C4D, 0xF75DFF65, - 0x80518B6B, 0xF6F9B4C5, - 0x8058C94C, 0xF6956FB6, - 0x806055EA, 0xF6313076, - 0x80683143, 0xF5CCF743, - 0x80705B50, 0xF568C45A, - 0x8078D40D, 0xF50497FA, - 0x80819B74, 0xF4A07260, - 0x808AB180, 0xF43C53CA, - 0x8094162B, 0xF3D83C76, - 0x809DC970, 0xF3742CA1, - 0x80A7CB49, 0xF310248A, - 0x80B21BAF, 0xF2AC246D, - 0x80BCBA9C, 0xF2482C89, - 0x80C7A80A, 0xF1E43D1C, - 0x80D2E3F1, 0xF1805662, - 0x80DE6E4C, 0xF11C789A, - 0x80EA4712, 0xF0B8A401, - 0x80F66E3C, 0xF054D8D4, - 0x8102E3C3, 0xEFF11752, - 0x810FA7A0, 0xEF8D5FB8, - 0x811CB9CA, 0xEF29B243, - 0x812A1A39, 0xEEC60F31, - 0x8137C8E6, 0xEE6276BF, - 0x8145C5C6, 0xEDFEE92B, - 0x815410D3, 0xED9B66B2, - 0x8162AA03, 0xED37EF91, - 0x8171914E, 0xECD48406, - 0x8180C6A9, 0xEC71244F, - 0x81904A0C, 0xEC0DD0A8, - 0x81A01B6C, 0xEBAA894E, - 0x81B03AC1, 0xEB474E80, - 0x81C0A801, 0xEAE4207A, - 0x81D16320, 0xEA80FF79, - 0x81E26C16, 0xEA1DEBBB, - 0x81F3C2D7, 0xE9BAE57C, - 0x82056758, 0xE957ECFB, - 0x8217598F, 0xE8F50273, - 0x82299971, 0xE8922621, - 0x823C26F2, 0xE82F5844, - 0x824F0208, 0xE7CC9917, - 0x82622AA5, 0xE769E8D8, - 0x8275A0C0, 0xE70747C3, - 0x8289644A, 0xE6A4B616, - 0x829D753A, 0xE642340D, - 0x82B1D381, 0xE5DFC1E4, - 0x82C67F13, 0xE57D5FDA, - 0x82DB77E5, 0xE51B0E2A, - 0x82F0BDE8, 0xE4B8CD10, - 0x8306510F, 0xE4569CCB, - 0x831C314E, 0xE3F47D95, - 0x83325E97, 0xE3926FAC, - 0x8348D8DB, 0xE330734C, - 0x835FA00E, 0xE2CE88B2, - 0x8376B422, 0xE26CB01A, - 0x838E1507, 0xE20AE9C1, - 0x83A5C2B0, 0xE1A935E1, - 0x83BDBD0D, 0xE14794B9, - 0x83D60411, 0xE0E60684, - 0x83EE97AC, 0xE0848B7F, - 0x840777CF, 0xE02323E5, - 0x8420A46B, 0xDFC1CFF2, - 0x843A1D70, 0xDF608FE3, - 0x8453E2CE, 0xDEFF63F4, - 0x846DF476, 0xDE9E4C60, - 0x84885257, 0xDE3D4963, - 0x84A2FC62, 0xDDDC5B3A, - 0x84BDF285, 0xDD7B8220, - 0x84D934B0, 0xDD1ABE51, - 0x84F4C2D3, 0xDCBA1008, - 0x85109CDC, 0xDC597781, - 0x852CC2BA, 0xDBF8F4F8, - 0x8549345C, 0xDB9888A8, - 0x8565F1B0, 0xDB3832CD, - 0x8582FAA4, 0xDAD7F3A2, - 0x85A04F28, 0xDA77CB62, - 0x85BDEF27, 0xDA17BA4A, - 0x85DBDA91, 0xD9B7C093, - 0x85FA1152, 0xD957DE7A, - 0x86189359, 0xD8F81439, - 0x86376092, 0xD898620C, - 0x865678EA, 0xD838C82D, - 0x8675DC4E, 0xD7D946D7, - 0x86958AAB, 0xD779DE46, - 0x86B583EE, 0xD71A8EB5, - 0x86D5C802, 0xD6BB585D, - 0x86F656D3, 0xD65C3B7B, - 0x8717304E, 0xD5FD3847, - 0x8738545E, 0xD59E4EFE, - 0x8759C2EF, 0xD53F7FDA, - 0x877B7BEC, 0xD4E0CB14, - 0x879D7F40, 0xD48230E8, - 0x87BFCCD7, 0xD423B190, - 0x87E2649B, 0xD3C54D46, - 0x88054677, 0xD3670445, - 0x88287255, 0xD308D6C6, - 0x884BE820, 0xD2AAC504, - 0x886FA7C2, 0xD24CCF38, - 0x8893B124, 0xD1EEF59E, - 0x88B80431, 0xD191386D, - 0x88DCA0D3, 0xD13397E1, - 0x890186F1, 0xD0D61433, - 0x8926B677, 0xD078AD9D, - 0x894C2F4C, 0xD01B6459, - 0x8971F15A, 0xCFBE389F, - 0x8997FC89, 0xCF612AAA, - 0x89BE50C3, 0xCF043AB2, - 0x89E4EDEE, 0xCEA768F2, - 0x8A0BD3F5, 0xCE4AB5A2, - 0x8A3302BD, 0xCDEE20FC, - 0x8A5A7A30, 0xCD91AB38, - 0x8A823A35, 0xCD355490, - 0x8AAA42B4, 0xCCD91D3D, - 0x8AD29393, 0xCC7D0577, - 0x8AFB2CBA, 0xCC210D78, - 0x8B240E10, 0xCBC53578, - 0x8B4D377C, 0xCB697DB0, - 0x8B76A8E4, 0xCB0DE658, - 0x8BA0622F, 0xCAB26FA9, - 0x8BCA6342, 0xCA5719DB, - 0x8BF4AC05, 0xC9FBE527, - 0x8C1F3C5C, 0xC9A0D1C4, - 0x8C4A142F, 0xC945DFEC, - 0x8C753361, 0xC8EB0FD6, - 0x8CA099D9, 0xC89061BA, - 0x8CCC477D, 0xC835D5D0, - 0x8CF83C30, 0xC7DB6C50, - 0x8D2477D8, 0xC7812571, - 0x8D50FA59, 0xC727016C, - 0x8D7DC399, 0xC6CD0079, - 0x8DAAD37B, 0xC67322CD, - 0x8DD829E4, 0xC61968A2, - 0x8E05C6B7, 0xC5BFD22E, - 0x8E33A9D9, 0xC5665FA8, - 0x8E61D32D, 0xC50D1148, - 0x8E904298, 0xC4B3E746, - 0x8EBEF7FB, 0xC45AE1D7, - 0x8EEDF33B, 0xC4020132, - 0x8F1D343A, 0xC3A9458F, - 0x8F4CBADB, 0xC350AF25, - 0x8F7C8701, 0xC2F83E2A, - 0x8FAC988E, 0xC29FF2D4, - 0x8FDCEF66, 0xC247CD5A, - 0x900D8B69, 0xC1EFCDF2, - 0x903E6C7A, 0xC197F4D3, - 0x906F927B, 0xC1404233, - 0x90A0FD4E, 0xC0E8B648, - 0x90D2ACD3, 0xC0915147, - 0x9104A0ED, 0xC03A1368, - 0x9136D97D, 0xBFE2FCDF, - 0x91695663, 0xBF8C0DE2, - 0x919C1780, 0xBF3546A8, - 0x91CF1CB6, 0xBEDEA765, - 0x920265E4, 0xBE88304F, - 0x9235F2EB, 0xBE31E19B, - 0x9269C3AC, 0xBDDBBB7F, - 0x929DD805, 0xBD85BE2F, - 0x92D22FD8, 0xBD2FE9E1, - 0x9306CB04, 0xBCDA3ECA, - 0x933BA968, 0xBC84BD1E, - 0x9370CAE4, 0xBC2F6513, - 0x93A62F56, 0xBBDA36DC, - 0x93DBD69F, 0xBB8532AF, - 0x9411C09D, 0xBB3058C0, - 0x9447ED2F, 0xBADBA943, - 0x947E5C32, 0xBA87246C, - 0x94B50D87, 0xBA32CA70, - 0x94EC010B, 0xB9DE9B83, - 0x9523369B, 0xB98A97D8, - 0x955AAE17, 0xB936BFA3, - 0x9592675B, 0xB8E31319, - 0x95CA6246, 0xB88F926C, - 0x96029EB5, 0xB83C3DD1, - 0x963B1C85, 0xB7E9157A, - 0x9673DB94, 0xB796199B, - 0x96ACDBBD, 0xB7434A67, - 0x96E61CDF, 0xB6F0A811, - 0x971F9ED6, 0xB69E32CD, - 0x9759617E, 0xB64BEACC, - 0x979364B5, 0xB5F9D042, - 0x97CDA855, 0xB5A7E362, - 0x98082C3B, 0xB556245E, - 0x9842F043, 0xB5049368, - 0x987DF449, 0xB4B330B2, - 0x98B93828, 0xB461FC70, - 0x98F4BBBC, 0xB410F6D2, - 0x99307EE0, 0xB3C0200C, - 0x996C816F, 0xB36F784E, - 0x99A8C344, 0xB31EFFCB, - 0x99E5443A, 0xB2CEB6B5, - 0x9A22042C, 0xB27E9D3B, - 0x9A5F02F5, 0xB22EB392, - 0x9A9C406D, 0xB1DEF9E8, - 0x9AD9BC71, 0xB18F7070, - 0x9B1776D9, 0xB140175B, - 0x9B556F80, 0xB0F0EEDA, - 0x9B93A640, 0xB0A1F71C, - 0x9BD21AF2, 0xB0533055, - 0x9C10CD70, 0xB0049AB2, - 0x9C4FBD92, 0xAFB63667, - 0x9C8EEB33, 0xAF6803A1, - 0x9CCE562B, 0xAF1A0293, - 0x9D0DFE53, 0xAECC336B, - 0x9D4DE384, 0xAE7E965B, - 0x9D8E0596, 0xAE312B91, - 0x9DCE6462, 0xADE3F33E, - 0x9E0EFFC1, 0xAD96ED91, - 0x9E4FD789, 0xAD4A1ABA, - 0x9E90EB94, 0xACFD7AE8, - 0x9ED23BB9, 0xACB10E4A, - 0x9F13C7D0, 0xAC64D510, - 0x9F558FB0, 0xAC18CF68, - 0x9F979331, 0xABCCFD82, - 0x9FD9D22A, 0xAB815F8C, - 0xA01C4C72, 0xAB35F5B5, - 0xA05F01E1, 0xAAEAC02B, - 0xA0A1F24C, 0xAA9FBF1D, - 0xA0E51D8C, 0xAA54F2B9, - 0xA1288376, 0xAA0A5B2D, - 0xA16C23E1, 0xA9BFF8A8, - 0xA1AFFEA2, 0xA975CB56, - 0xA1F41391, 0xA92BD366, - 0xA2386283, 0xA8E21106, - 0xA27CEB4F, 0xA8988463, - 0xA2C1ADC9, 0xA84F2DA9, - 0xA306A9C7, 0xA8060D08, - 0xA34BDF20, 0xA7BD22AB, - 0xA3914DA7, 0xA7746EC0, - 0xA3D6F533, 0xA72BF173, - 0xA41CD598, 0xA6E3AAF2, - 0xA462EEAC, 0xA69B9B68, - 0xA4A94042, 0xA653C302, - 0xA4EFCA31, 0xA60C21ED, - 0xA5368C4B, 0xA5C4B855, - 0xA57D8666, 0xA57D8666, - 0xA5C4B855, 0xA5368C4B, - 0xA60C21ED, 0xA4EFCA31, - 0xA653C302, 0xA4A94042, - 0xA69B9B68, 0xA462EEAC, - 0xA6E3AAF2, 0xA41CD598, - 0xA72BF173, 0xA3D6F533, - 0xA7746EC0, 0xA3914DA7, - 0xA7BD22AB, 0xA34BDF20, - 0xA8060D08, 0xA306A9C7, - 0xA84F2DA9, 0xA2C1ADC9, - 0xA8988463, 0xA27CEB4F, - 0xA8E21106, 0xA2386283, - 0xA92BD366, 0xA1F41391, - 0xA975CB56, 0xA1AFFEA2, - 0xA9BFF8A8, 0xA16C23E1, - 0xAA0A5B2D, 0xA1288376, - 0xAA54F2B9, 0xA0E51D8C, - 0xAA9FBF1D, 0xA0A1F24C, - 0xAAEAC02B, 0xA05F01E1, - 0xAB35F5B5, 0xA01C4C72, - 0xAB815F8C, 0x9FD9D22A, - 0xABCCFD82, 0x9F979331, - 0xAC18CF68, 0x9F558FB0, - 0xAC64D510, 0x9F13C7D0, - 0xACB10E4A, 0x9ED23BB9, - 0xACFD7AE8, 0x9E90EB94, - 0xAD4A1ABA, 0x9E4FD789, - 0xAD96ED91, 0x9E0EFFC1, - 0xADE3F33E, 0x9DCE6462, - 0xAE312B91, 0x9D8E0596, - 0xAE7E965B, 0x9D4DE384, - 0xAECC336B, 0x9D0DFE53, - 0xAF1A0293, 0x9CCE562B, - 0xAF6803A1, 0x9C8EEB33, - 0xAFB63667, 0x9C4FBD92, - 0xB0049AB2, 0x9C10CD70, - 0xB0533055, 0x9BD21AF2, - 0xB0A1F71C, 0x9B93A640, - 0xB0F0EEDA, 0x9B556F80, - 0xB140175B, 0x9B1776D9, - 0xB18F7070, 0x9AD9BC71, - 0xB1DEF9E8, 0x9A9C406D, - 0xB22EB392, 0x9A5F02F5, - 0xB27E9D3B, 0x9A22042C, - 0xB2CEB6B5, 0x99E5443A, - 0xB31EFFCB, 0x99A8C344, - 0xB36F784E, 0x996C816F, - 0xB3C0200C, 0x99307EE0, - 0xB410F6D2, 0x98F4BBBC, - 0xB461FC70, 0x98B93828, - 0xB4B330B2, 0x987DF449, - 0xB5049368, 0x9842F043, - 0xB556245E, 0x98082C3B, - 0xB5A7E362, 0x97CDA855, - 0xB5F9D042, 0x979364B5, - 0xB64BEACC, 0x9759617E, - 0xB69E32CD, 0x971F9ED6, - 0xB6F0A811, 0x96E61CDF, - 0xB7434A67, 0x96ACDBBD, - 0xB796199B, 0x9673DB94, - 0xB7E9157A, 0x963B1C85, - 0xB83C3DD1, 0x96029EB5, - 0xB88F926C, 0x95CA6246, - 0xB8E31319, 0x9592675B, - 0xB936BFA3, 0x955AAE17, - 0xB98A97D8, 0x9523369B, - 0xB9DE9B83, 0x94EC010B, - 0xBA32CA70, 0x94B50D87, - 0xBA87246C, 0x947E5C32, - 0xBADBA943, 0x9447ED2F, - 0xBB3058C0, 0x9411C09D, - 0xBB8532AF, 0x93DBD69F, - 0xBBDA36DC, 0x93A62F56, - 0xBC2F6513, 0x9370CAE4, - 0xBC84BD1E, 0x933BA968, - 0xBCDA3ECA, 0x9306CB04, - 0xBD2FE9E1, 0x92D22FD8, - 0xBD85BE2F, 0x929DD805, - 0xBDDBBB7F, 0x9269C3AC, - 0xBE31E19B, 0x9235F2EB, - 0xBE88304F, 0x920265E4, - 0xBEDEA765, 0x91CF1CB6, - 0xBF3546A8, 0x919C1780, - 0xBF8C0DE2, 0x91695663, - 0xBFE2FCDF, 0x9136D97D, - 0xC03A1368, 0x9104A0ED, - 0xC0915147, 0x90D2ACD3, - 0xC0E8B648, 0x90A0FD4E, - 0xC1404233, 0x906F927B, - 0xC197F4D3, 0x903E6C7A, - 0xC1EFCDF2, 0x900D8B69, - 0xC247CD5A, 0x8FDCEF66, - 0xC29FF2D4, 0x8FAC988E, - 0xC2F83E2A, 0x8F7C8701, - 0xC350AF25, 0x8F4CBADB, - 0xC3A9458F, 0x8F1D343A, - 0xC4020132, 0x8EEDF33B, - 0xC45AE1D7, 0x8EBEF7FB, - 0xC4B3E746, 0x8E904298, - 0xC50D1148, 0x8E61D32D, - 0xC5665FA8, 0x8E33A9D9, - 0xC5BFD22E, 0x8E05C6B7, - 0xC61968A2, 0x8DD829E4, - 0xC67322CD, 0x8DAAD37B, - 0xC6CD0079, 0x8D7DC399, - 0xC727016C, 0x8D50FA59, - 0xC7812571, 0x8D2477D8, - 0xC7DB6C50, 0x8CF83C30, - 0xC835D5D0, 0x8CCC477D, - 0xC89061BA, 0x8CA099D9, - 0xC8EB0FD6, 0x8C753361, - 0xC945DFEC, 0x8C4A142F, - 0xC9A0D1C4, 0x8C1F3C5C, - 0xC9FBE527, 0x8BF4AC05, - 0xCA5719DB, 0x8BCA6342, - 0xCAB26FA9, 0x8BA0622F, - 0xCB0DE658, 0x8B76A8E4, - 0xCB697DB0, 0x8B4D377C, - 0xCBC53578, 0x8B240E10, - 0xCC210D78, 0x8AFB2CBA, - 0xCC7D0577, 0x8AD29393, - 0xCCD91D3D, 0x8AAA42B4, - 0xCD355490, 0x8A823A35, - 0xCD91AB38, 0x8A5A7A30, - 0xCDEE20FC, 0x8A3302BD, - 0xCE4AB5A2, 0x8A0BD3F5, - 0xCEA768F2, 0x89E4EDEE, - 0xCF043AB2, 0x89BE50C3, - 0xCF612AAA, 0x8997FC89, - 0xCFBE389F, 0x8971F15A, - 0xD01B6459, 0x894C2F4C, - 0xD078AD9D, 0x8926B677, - 0xD0D61433, 0x890186F1, - 0xD13397E1, 0x88DCA0D3, - 0xD191386D, 0x88B80431, - 0xD1EEF59E, 0x8893B124, - 0xD24CCF38, 0x886FA7C2, - 0xD2AAC504, 0x884BE820, - 0xD308D6C6, 0x88287255, - 0xD3670445, 0x88054677, - 0xD3C54D46, 0x87E2649B, - 0xD423B190, 0x87BFCCD7, - 0xD48230E8, 0x879D7F40, - 0xD4E0CB14, 0x877B7BEC, - 0xD53F7FDA, 0x8759C2EF, - 0xD59E4EFE, 0x8738545E, - 0xD5FD3847, 0x8717304E, - 0xD65C3B7B, 0x86F656D3, - 0xD6BB585D, 0x86D5C802, - 0xD71A8EB5, 0x86B583EE, - 0xD779DE46, 0x86958AAB, - 0xD7D946D7, 0x8675DC4E, - 0xD838C82D, 0x865678EA, - 0xD898620C, 0x86376092, - 0xD8F81439, 0x86189359, - 0xD957DE7A, 0x85FA1152, - 0xD9B7C093, 0x85DBDA91, - 0xDA17BA4A, 0x85BDEF27, - 0xDA77CB62, 0x85A04F28, - 0xDAD7F3A2, 0x8582FAA4, - 0xDB3832CD, 0x8565F1B0, - 0xDB9888A8, 0x8549345C, - 0xDBF8F4F8, 0x852CC2BA, - 0xDC597781, 0x85109CDC, - 0xDCBA1008, 0x84F4C2D3, - 0xDD1ABE51, 0x84D934B0, - 0xDD7B8220, 0x84BDF285, - 0xDDDC5B3A, 0x84A2FC62, - 0xDE3D4963, 0x84885257, - 0xDE9E4C60, 0x846DF476, - 0xDEFF63F4, 0x8453E2CE, - 0xDF608FE3, 0x843A1D70, - 0xDFC1CFF2, 0x8420A46B, - 0xE02323E5, 0x840777CF, - 0xE0848B7F, 0x83EE97AC, - 0xE0E60684, 0x83D60411, - 0xE14794B9, 0x83BDBD0D, - 0xE1A935E1, 0x83A5C2B0, - 0xE20AE9C1, 0x838E1507, - 0xE26CB01A, 0x8376B422, - 0xE2CE88B2, 0x835FA00E, - 0xE330734C, 0x8348D8DB, - 0xE3926FAC, 0x83325E97, - 0xE3F47D95, 0x831C314E, - 0xE4569CCB, 0x8306510F, - 0xE4B8CD10, 0x82F0BDE8, - 0xE51B0E2A, 0x82DB77E5, - 0xE57D5FDA, 0x82C67F13, - 0xE5DFC1E4, 0x82B1D381, - 0xE642340D, 0x829D753A, - 0xE6A4B616, 0x8289644A, - 0xE70747C3, 0x8275A0C0, - 0xE769E8D8, 0x82622AA5, - 0xE7CC9917, 0x824F0208, - 0xE82F5844, 0x823C26F2, - 0xE8922621, 0x82299971, - 0xE8F50273, 0x8217598F, - 0xE957ECFB, 0x82056758, - 0xE9BAE57C, 0x81F3C2D7, - 0xEA1DEBBB, 0x81E26C16, - 0xEA80FF79, 0x81D16320, - 0xEAE4207A, 0x81C0A801, - 0xEB474E80, 0x81B03AC1, - 0xEBAA894E, 0x81A01B6C, - 0xEC0DD0A8, 0x81904A0C, - 0xEC71244F, 0x8180C6A9, - 0xECD48406, 0x8171914E, - 0xED37EF91, 0x8162AA03, - 0xED9B66B2, 0x815410D3, - 0xEDFEE92B, 0x8145C5C6, - 0xEE6276BF, 0x8137C8E6, - 0xEEC60F31, 0x812A1A39, - 0xEF29B243, 0x811CB9CA, - 0xEF8D5FB8, 0x810FA7A0, - 0xEFF11752, 0x8102E3C3, - 0xF054D8D4, 0x80F66E3C, - 0xF0B8A401, 0x80EA4712, - 0xF11C789A, 0x80DE6E4C, - 0xF1805662, 0x80D2E3F1, - 0xF1E43D1C, 0x80C7A80A, - 0xF2482C89, 0x80BCBA9C, - 0xF2AC246D, 0x80B21BAF, - 0xF310248A, 0x80A7CB49, - 0xF3742CA1, 0x809DC970, - 0xF3D83C76, 0x8094162B, - 0xF43C53CA, 0x808AB180, - 0xF4A07260, 0x80819B74, - 0xF50497FA, 0x8078D40D, - 0xF568C45A, 0x80705B50, - 0xF5CCF743, 0x80683143, - 0xF6313076, 0x806055EA, - 0xF6956FB6, 0x8058C94C, - 0xF6F9B4C5, 0x80518B6B, - 0xF75DFF65, 0x804A9C4D, - 0xF7C24F58, 0x8043FBF6, - 0xF826A461, 0x803DAA69, - 0xF88AFE41, 0x8037A7AC, - 0xF8EF5CBB, 0x8031F3C1, - 0xF953BF90, 0x802C8EAD, - 0xF9B82683, 0x80277872, - 0xFA1C9156, 0x8022B113, - 0xFA80FFCB, 0x801E3894, - 0xFAE571A4, 0x801A0EF7, - 0xFB49E6A2, 0x80163440, - 0xFBAE5E89, 0x8012A86F, - 0xFC12D919, 0x800F6B88, - 0xFC775616, 0x800C7D8C, - 0xFCDBD541, 0x8009DE7D, - 0xFD40565B, 0x80078E5E, - 0xFDA4D928, 0x80058D2E, - 0xFE095D69, 0x8003DAF0, - 0xFE6DE2E0, 0x800277A5, - 0xFED2694F, 0x8001634D, - 0xFF36F078, 0x80009DE9, - 0xFF9B781D, 0x8000277A -}; - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ -const q31_t twiddleCoef_4096_q31[6144] = -{ - 0x7FFFFFFF, 0x00000000, - 0x7FFFF621, 0x003243F5, - 0x7FFFD885, 0x006487E3, - 0x7FFFA72C, 0x0096CBC1, - 0x7FFF6216, 0x00C90F88, - 0x7FFF0942, 0x00FB532F, - 0x7FFE9CB2, 0x012D96B0, - 0x7FFE1C64, 0x015FDA03, - 0x7FFD885A, 0x01921D1F, - 0x7FFCE093, 0x01C45FFE, - 0x7FFC250F, 0x01F6A296, - 0x7FFB55CE, 0x0228E4E1, - 0x7FFA72D1, 0x025B26D7, - 0x7FF97C17, 0x028D6870, - 0x7FF871A1, 0x02BFA9A4, - 0x7FF7536F, 0x02F1EA6B, - 0x7FF62182, 0x03242ABF, - 0x7FF4DBD8, 0x03566A96, - 0x7FF38273, 0x0388A9E9, - 0x7FF21553, 0x03BAE8B1, - 0x7FF09477, 0x03ED26E6, - 0x7FEEFFE1, 0x041F647F, - 0x7FED5790, 0x0451A176, - 0x7FEB9B85, 0x0483DDC3, - 0x7FE9CBC0, 0x04B6195D, - 0x7FE7E840, 0x04E8543D, - 0x7FE5F108, 0x051A8E5C, - 0x7FE3E616, 0x054CC7B0, - 0x7FE1C76B, 0x057F0034, - 0x7FDF9508, 0x05B137DF, - 0x7FDD4EEC, 0x05E36EA9, - 0x7FDAF518, 0x0615A48A, - 0x7FD8878D, 0x0647D97C, - 0x7FD6064B, 0x067A0D75, - 0x7FD37152, 0x06AC406F, - 0x7FD0C8A3, 0x06DE7261, - 0x7FCE0C3E, 0x0710A344, - 0x7FCB3C23, 0x0742D310, - 0x7FC85853, 0x077501BE, - 0x7FC560CF, 0x07A72F45, - 0x7FC25596, 0x07D95B9E, - 0x7FBF36A9, 0x080B86C1, - 0x7FBC040A, 0x083DB0A7, - 0x7FB8BDB7, 0x086FD947, - 0x7FB563B2, 0x08A2009A, - 0x7FB1F5FC, 0x08D42698, - 0x7FAE7494, 0x09064B3A, - 0x7FAADF7C, 0x09386E77, - 0x7FA736B4, 0x096A9049, - 0x7FA37A3C, 0x099CB0A7, - 0x7F9FAA15, 0x09CECF89, - 0x7F9BC63F, 0x0A00ECE8, - 0x7F97CEBC, 0x0A3308BC, - 0x7F93C38C, 0x0A6522FE, - 0x7F8FA4AF, 0x0A973BA5, - 0x7F8B7226, 0x0AC952AA, - 0x7F872BF3, 0x0AFB6805, - 0x7F82D214, 0x0B2D7BAE, - 0x7F7E648B, 0x0B5F8D9F, - 0x7F79E35A, 0x0B919DCE, - 0x7F754E7F, 0x0BC3AC35, - 0x7F70A5FD, 0x0BF5B8CB, - 0x7F6BE9D4, 0x0C27C389, - 0x7F671A04, 0x0C59CC67, - 0x7F62368F, 0x0C8BD35E, - 0x7F5D3F75, 0x0CBDD865, - 0x7F5834B6, 0x0CEFDB75, - 0x7F531654, 0x0D21DC87, - 0x7F4DE450, 0x0D53DB92, - 0x7F489EAA, 0x0D85D88F, - 0x7F434563, 0x0DB7D376, - 0x7F3DD87C, 0x0DE9CC3F, - 0x7F3857F5, 0x0E1BC2E3, - 0x7F32C3D0, 0x0E4DB75B, - 0x7F2D1C0E, 0x0E7FA99D, - 0x7F2760AF, 0x0EB199A3, - 0x7F2191B4, 0x0EE38765, - 0x7F1BAF1E, 0x0F1572DC, - 0x7F15B8EE, 0x0F475BFE, - 0x7F0FAF24, 0x0F7942C6, - 0x7F0991C3, 0x0FAB272B, - 0x7F0360CB, 0x0FDD0925, - 0x7EFD1C3C, 0x100EE8AD, - 0x7EF6C418, 0x1040C5BB, - 0x7EF0585F, 0x1072A047, - 0x7EE9D913, 0x10A4784A, - 0x7EE34635, 0x10D64DBC, - 0x7EDC9FC6, 0x11082096, - 0x7ED5E5C6, 0x1139F0CE, - 0x7ECF1837, 0x116BBE5F, - 0x7EC8371A, 0x119D8940, - 0x7EC1426F, 0x11CF516A, - 0x7EBA3A39, 0x120116D4, - 0x7EB31E77, 0x1232D978, - 0x7EABEF2C, 0x1264994E, - 0x7EA4AC58, 0x1296564D, - 0x7E9D55FC, 0x12C8106E, - 0x7E95EC19, 0x12F9C7AA, - 0x7E8E6EB1, 0x132B7BF9, - 0x7E86DDC5, 0x135D2D53, - 0x7E7F3956, 0x138EDBB0, - 0x7E778165, 0x13C0870A, - 0x7E6FB5F3, 0x13F22F57, - 0x7E67D702, 0x1423D492, - 0x7E5FE493, 0x145576B1, - 0x7E57DEA6, 0x148715AD, - 0x7E4FC53E, 0x14B8B17F, - 0x7E47985B, 0x14EA4A1F, - 0x7E3F57FE, 0x151BDF85, - 0x7E37042A, 0x154D71AA, - 0x7E2E9CDF, 0x157F0086, - 0x7E26221E, 0x15B08C11, - 0x7E1D93E9, 0x15E21444, - 0x7E14F242, 0x16139917, - 0x7E0C3D29, 0x16451A83, - 0x7E03749F, 0x1676987F, - 0x7DFA98A7, 0x16A81305, - 0x7DF1A942, 0x16D98A0C, - 0x7DE8A670, 0x170AFD8D, - 0x7DDF9034, 0x173C6D80, - 0x7DD6668E, 0x176DD9DE, - 0x7DCD2981, 0x179F429F, - 0x7DC3D90D, 0x17D0A7BB, - 0x7DBA7534, 0x1802092C, - 0x7DB0FDF7, 0x183366E8, - 0x7DA77359, 0x1864C0E9, - 0x7D9DD55A, 0x18961727, - 0x7D9423FB, 0x18C7699B, - 0x7D8A5F3F, 0x18F8B83C, - 0x7D808727, 0x192A0303, - 0x7D769BB5, 0x195B49E9, - 0x7D6C9CE9, 0x198C8CE6, - 0x7D628AC5, 0x19BDCBF2, - 0x7D58654C, 0x19EF0706, - 0x7D4E2C7E, 0x1A203E1B, - 0x7D43E05E, 0x1A517127, - 0x7D3980EC, 0x1A82A025, - 0x7D2F0E2A, 0x1AB3CB0C, - 0x7D24881A, 0x1AE4F1D6, - 0x7D19EEBE, 0x1B161479, - 0x7D0F4218, 0x1B4732EF, - 0x7D048228, 0x1B784D30, - 0x7CF9AEF0, 0x1BA96334, - 0x7CEEC873, 0x1BDA74F5, - 0x7CE3CEB1, 0x1C0B826A, - 0x7CD8C1AD, 0x1C3C8B8C, - 0x7CCDA168, 0x1C6D9053, - 0x7CC26DE5, 0x1C9E90B8, - 0x7CB72724, 0x1CCF8CB3, - 0x7CABCD27, 0x1D00843C, - 0x7CA05FF1, 0x1D31774D, - 0x7C94DF82, 0x1D6265DD, - 0x7C894BDD, 0x1D934FE5, - 0x7C7DA504, 0x1DC4355D, - 0x7C71EAF8, 0x1DF5163F, - 0x7C661DBB, 0x1E25F281, - 0x7C5A3D4F, 0x1E56CA1E, - 0x7C4E49B6, 0x1E879D0C, - 0x7C4242F2, 0x1EB86B46, - 0x7C362904, 0x1EE934C2, - 0x7C29FBEE, 0x1F19F97B, - 0x7C1DBBB2, 0x1F4AB967, - 0x7C116853, 0x1F7B7480, - 0x7C0501D1, 0x1FAC2ABF, - 0x7BF88830, 0x1FDCDC1A, - 0x7BEBFB70, 0x200D888C, - 0x7BDF5B94, 0x203E300D, - 0x7BD2A89E, 0x206ED295, - 0x7BC5E28F, 0x209F701C, - 0x7BB9096A, 0x20D0089B, - 0x7BAC1D31, 0x21009C0B, - 0x7B9F1DE5, 0x21312A65, - 0x7B920B89, 0x2161B39F, - 0x7B84E61E, 0x219237B4, - 0x7B77ADA8, 0x21C2B69C, - 0x7B6A6227, 0x21F3304E, - 0x7B5D039D, 0x2223A4C5, - 0x7B4F920E, 0x225413F8, - 0x7B420D7A, 0x22847DDF, - 0x7B3475E4, 0x22B4E274, - 0x7B26CB4F, 0x22E541AE, - 0x7B190DBB, 0x23159B87, - 0x7B0B3D2C, 0x2345EFF7, - 0x7AFD59A3, 0x23763EF7, - 0x7AEF6323, 0x23A6887E, - 0x7AE159AE, 0x23D6CC86, - 0x7AD33D45, 0x24070B07, - 0x7AC50DEB, 0x243743FA, - 0x7AB6CBA3, 0x24677757, - 0x7AA8766E, 0x2497A517, - 0x7A9A0E4F, 0x24C7CD32, - 0x7A8B9348, 0x24F7EFA1, - 0x7A7D055B, 0x25280C5D, - 0x7A6E648A, 0x2558235E, - 0x7A5FB0D8, 0x2588349D, - 0x7A50EA46, 0x25B84012, - 0x7A4210D8, 0x25E845B5, - 0x7A33248F, 0x26184581, - 0x7A24256E, 0x26483F6C, - 0x7A151377, 0x26783370, - 0x7A05EEAD, 0x26A82185, - 0x79F6B711, 0x26D809A5, - 0x79E76CA6, 0x2707EBC6, - 0x79D80F6F, 0x2737C7E3, - 0x79C89F6D, 0x27679DF4, - 0x79B91CA4, 0x27976DF1, - 0x79A98715, 0x27C737D2, - 0x7999DEC3, 0x27F6FB92, - 0x798A23B1, 0x2826B928, - 0x797A55E0, 0x2856708C, - 0x796A7554, 0x288621B9, - 0x795A820E, 0x28B5CCA5, - 0x794A7C11, 0x28E5714A, - 0x793A6360, 0x29150FA1, - 0x792A37FE, 0x2944A7A2, - 0x7919F9EB, 0x29743945, - 0x7909A92C, 0x29A3C484, - 0x78F945C3, 0x29D34958, - 0x78E8CFB1, 0x2A02C7B8, - 0x78D846FB, 0x2A323F9D, - 0x78C7ABA1, 0x2A61B101, - 0x78B6FDA8, 0x2A911BDB, - 0x78A63D10, 0x2AC08025, - 0x789569DE, 0x2AEFDDD8, - 0x78848413, 0x2B1F34EB, - 0x78738BB3, 0x2B4E8558, - 0x786280BF, 0x2B7DCF17, - 0x7851633B, 0x2BAD1221, - 0x78403328, 0x2BDC4E6F, - 0x782EF08B, 0x2C0B83F9, - 0x781D9B64, 0x2C3AB2B9, - 0x780C33B8, 0x2C69DAA6, - 0x77FAB988, 0x2C98FBBA, - 0x77E92CD8, 0x2CC815ED, - 0x77D78DAA, 0x2CF72939, - 0x77C5DC01, 0x2D263595, - 0x77B417DF, 0x2D553AFB, - 0x77A24148, 0x2D843963, - 0x7790583D, 0x2DB330C7, - 0x777E5CC3, 0x2DE2211E, - 0x776C4EDB, 0x2E110A62, - 0x775A2E88, 0x2E3FEC8B, - 0x7747FBCE, 0x2E6EC792, - 0x7735B6AE, 0x2E9D9B70, - 0x77235F2D, 0x2ECC681E, - 0x7710F54B, 0x2EFB2D94, - 0x76FE790E, 0x2F29EBCC, - 0x76EBEA77, 0x2F58A2BD, - 0x76D94988, 0x2F875262, - 0x76C69646, 0x2FB5FAB2, - 0x76B3D0B3, 0x2FE49BA6, - 0x76A0F8D2, 0x30133538, - 0x768E0EA5, 0x3041C760, - 0x767B1230, 0x30705217, - 0x76680376, 0x309ED555, - 0x7654E279, 0x30CD5114, - 0x7641AF3C, 0x30FBC54D, - 0x762E69C3, 0x312A31F8, - 0x761B1211, 0x3158970D, - 0x7607A827, 0x3186F487, - 0x75F42C0A, 0x31B54A5D, - 0x75E09DBD, 0x31E39889, - 0x75CCFD42, 0x3211DF03, - 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0xFC45174E, 0x7FF21553, - 0xFC12D919, 0x7FF09477, - 0xFBE09B80, 0x7FEEFFE1, - 0xFBAE5E89, 0x7FED5790, - 0xFB7C223C, 0x7FEB9B85, - 0xFB49E6A2, 0x7FE9CBC0, - 0xFB17ABC2, 0x7FE7E840, - 0xFAE571A4, 0x7FE5F108, - 0xFAB3384F, 0x7FE3E616, - 0xFA80FFCB, 0x7FE1C76B, - 0xFA4EC820, 0x7FDF9508, - 0xFA1C9156, 0x7FDD4EEC, - 0xF9EA5B75, 0x7FDAF518, - 0xF9B82683, 0x7FD8878D, - 0xF985F28A, 0x7FD6064B, - 0xF953BF90, 0x7FD37152, - 0xF9218D9E, 0x7FD0C8A3, - 0xF8EF5CBB, 0x7FCE0C3E, - 0xF8BD2CEF, 0x7FCB3C23, - 0xF88AFE41, 0x7FC85853, - 0xF858D0BA, 0x7FC560CF, - 0xF826A461, 0x7FC25596, - 0xF7F4793E, 0x7FBF36A9, - 0xF7C24F58, 0x7FBC040A, - 0xF79026B8, 0x7FB8BDB7, - 0xF75DFF65, 0x7FB563B2, - 0xF72BD967, 0x7FB1F5FC, - 0xF6F9B4C5, 0x7FAE7494, - 0xF6C79188, 0x7FAADF7C, - 0xF6956FB6, 0x7FA736B4, - 0xF6634F58, 0x7FA37A3C, - 0xF6313076, 0x7F9FAA15, - 0xF5FF1317, 0x7F9BC63F, - 0xF5CCF743, 0x7F97CEBC, - 0xF59ADD01, 0x7F93C38C, - 0xF568C45A, 0x7F8FA4AF, - 0xF536AD55, 0x7F8B7226, - 0xF50497FA, 0x7F872BF3, - 0xF4D28451, 0x7F82D214, - 0xF4A07260, 0x7F7E648B, - 0xF46E6231, 0x7F79E35A, - 0xF43C53CA, 0x7F754E7F, - 0xF40A4734, 0x7F70A5FD, - 0xF3D83C76, 0x7F6BE9D4, - 0xF3A63398, 0x7F671A04, - 0xF3742CA1, 0x7F62368F, - 0xF342279A, 0x7F5D3F75, - 0xF310248A, 0x7F5834B6, - 0xF2DE2378, 0x7F531654, - 0xF2AC246D, 0x7F4DE450, - 0xF27A2770, 0x7F489EAA, - 0xF2482C89, 0x7F434563, - 0xF21633C0, 0x7F3DD87C, - 0xF1E43D1C, 0x7F3857F5, - 0xF1B248A5, 0x7F32C3D0, - 0xF1805662, 0x7F2D1C0E, - 0xF14E665C, 0x7F2760AF, - 0xF11C789A, 0x7F2191B4, - 0xF0EA8D23, 0x7F1BAF1E, - 0xF0B8A401, 0x7F15B8EE, - 0xF086BD39, 0x7F0FAF24, - 0xF054D8D4, 0x7F0991C3, - 0xF022F6DA, 0x7F0360CB, - 0xEFF11752, 0x7EFD1C3C, - 0xEFBF3A44, 0x7EF6C418, - 0xEF8D5FB8, 0x7EF0585F, - 0xEF5B87B5, 0x7EE9D913, - 0xEF29B243, 0x7EE34635, - 0xEEF7DF6A, 0x7EDC9FC6, - 0xEEC60F31, 0x7ED5E5C6, - 0xEE9441A0, 0x7ECF1837, - 0xEE6276BF, 0x7EC8371A, - 0xEE30AE95, 0x7EC1426F, - 0xEDFEE92B, 0x7EBA3A39, - 0xEDCD2687, 0x7EB31E77, - 0xED9B66B2, 0x7EABEF2C, - 0xED69A9B2, 0x7EA4AC58, - 0xED37EF91, 0x7E9D55FC, - 0xED063855, 0x7E95EC19, - 0xECD48406, 0x7E8E6EB1, - 0xECA2D2AC, 0x7E86DDC5, - 0xEC71244F, 0x7E7F3956, - 0xEC3F78F5, 0x7E778165, - 0xEC0DD0A8, 0x7E6FB5F3, - 0xEBDC2B6D, 0x7E67D702, - 0xEBAA894E, 0x7E5FE493, - 0xEB78EA52, 0x7E57DEA6, - 0xEB474E80, 0x7E4FC53E, - 0xEB15B5E0, 0x7E47985B, - 0xEAE4207A, 0x7E3F57FE, - 0xEAB28E55, 0x7E37042A, - 0xEA80FF79, 0x7E2E9CDF, - 0xEA4F73EE, 0x7E26221E, - 0xEA1DEBBB, 0x7E1D93E9, - 0xE9EC66E8, 0x7E14F242, - 0xE9BAE57C, 0x7E0C3D29, - 0xE9896780, 0x7E03749F, - 0xE957ECFB, 0x7DFA98A7, - 0xE92675F4, 0x7DF1A942, - 0xE8F50273, 0x7DE8A670, - 0xE8C3927F, 0x7DDF9034, - 0xE8922621, 0x7DD6668E, - 0xE860BD60, 0x7DCD2981, - 0xE82F5844, 0x7DC3D90D, - 0xE7FDF6D3, 0x7DBA7534, - 0xE7CC9917, 0x7DB0FDF7, - 0xE79B3F16, 0x7DA77359, - 0xE769E8D8, 0x7D9DD55A, - 0xE7389664, 0x7D9423FB, - 0xE70747C3, 0x7D8A5F3F, - 0xE6D5FCFC, 0x7D808727, - 0xE6A4B616, 0x7D769BB5, - 0xE6737319, 0x7D6C9CE9, - 0xE642340D, 0x7D628AC5, - 0xE610F8F9, 0x7D58654C, - 0xE5DFC1E4, 0x7D4E2C7E, - 0xE5AE8ED8, 0x7D43E05E, - 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0xABA72806, 0x9FB8AB41, - 0xABCCFD82, 0x9F979331, - 0xABF2DFFA, 0x9F7689FF, - 0xAC18CF68, 0x9F558FB0, - 0xAC3ECBC7, 0x9F34A449, - 0xAC64D510, 0x9F13C7D0, - 0xAC8AEB3E, 0x9EF2FA48, - 0xACB10E4A, 0x9ED23BB9, - 0xACD73E30, 0x9EB18C26, - 0xACFD7AE8, 0x9E90EB94, - 0xAD23C46D, 0x9E705A09, - 0xAD4A1ABA, 0x9E4FD789, - 0xAD707DC8, 0x9E2F641A, - 0xAD96ED91, 0x9E0EFFC1, - 0xADBD6A10, 0x9DEEAA82, - 0xADE3F33E, 0x9DCE6462, - 0xAE0A8916, 0x9DAE2D68, - 0xAE312B91, 0x9D8E0596, - 0xAE57DAAA, 0x9D6DECF4, - 0xAE7E965B, 0x9D4DE384, - 0xAEA55E9D, 0x9D2DE94D, - 0xAECC336B, 0x9D0DFE53, - 0xAEF314BF, 0x9CEE229C, - 0xAF1A0293, 0x9CCE562B, - 0xAF40FCE0, 0x9CAE9907, - 0xAF6803A1, 0x9C8EEB33, - 0xAF8F16D0, 0x9C6F4CB5, - 0xAFB63667, 0x9C4FBD92, - 0xAFDD625F, 0x9C303DCF, - 0xB0049AB2, 0x9C10CD70, - 0xB02BDF5C, 0x9BF16C7A, - 0xB0533055, 0x9BD21AF2, - 0xB07A8D97, 0x9BB2D8DD, - 0xB0A1F71C, 0x9B93A640, - 0xB0C96CDF, 0x9B748320, - 0xB0F0EEDA, 0x9B556F80, - 0xB1187D05, 0x9B366B67, - 0xB140175B, 0x9B1776D9, - 0xB167BDD6, 0x9AF891DB, - 0xB18F7070, 0x9AD9BC71, - 0xB1B72F23, 0x9ABAF6A0, - 0xB1DEF9E8, 0x9A9C406D, - 0xB206D0BA, 0x9A7D99DD, - 0xB22EB392, 0x9A5F02F5, - 0xB256A26A, 0x9A407BB8, - 0xB27E9D3B, 0x9A22042C, - 0xB2A6A401, 0x9A039C56, - 0xB2CEB6B5, 0x99E5443A, - 0xB2F6D54F, 0x99C6FBDE, - 0xB31EFFCB, 0x99A8C344, - 0xB3473622, 0x998A9A73, - 0xB36F784E, 0x996C816F, - 0xB397C649, 0x994E783C, - 0xB3C0200C, 0x99307EE0, - 0xB3E88591, 0x9912955E, - 0xB410F6D2, 0x98F4BBBC, - 0xB43973C9, 0x98D6F1FE, - 0xB461FC70, 0x98B93828, - 0xB48A90C0, 0x989B8E3F, - 0xB4B330B2, 0x987DF449, - 0xB4DBDC42, 0x98606A48, - 0xB5049368, 0x9842F043, - 0xB52D561E, 0x9825863D, - 0xB556245E, 0x98082C3B, - 0xB57EFE21, 0x97EAE241, - 0xB5A7E362, 0x97CDA855, - 0xB5D0D41A, 0x97B07E7A, - 0xB5F9D042, 0x979364B5, - 0xB622D7D5, 0x97765B0A, - 0xB64BEACC, 0x9759617E, - 0xB6750921, 0x973C7816, - 0xB69E32CD, 0x971F9ED6, - 0xB6C767CA, 0x9702D5C2, - 0xB6F0A811, 0x96E61CDF, - 0xB719F39D, 0x96C97431, - 0xB7434A67, 0x96ACDBBD, - 0xB76CAC68, 0x96905387, - 0xB796199B, 0x9673DB94, - 0xB7BF91F8, 0x965773E7, - 0xB7E9157A, 0x963B1C85, - 0xB812A419, 0x961ED573, - 0xB83C3DD1, 0x96029EB5, - 0xB865E299, 0x95E6784F, - 0xB88F926C, 0x95CA6246, - 0xB8B94D44, 0x95AE5C9E, - 0xB8E31319, 0x9592675B, - 0xB90CE3E6, 0x95768282, - 0xB936BFA3, 0x955AAE17, - 0xB960A64B, 0x953EEA1E, - 0xB98A97D8, 0x9523369B, - 0xB9B49442, 0x95079393, - 0xB9DE9B83, 0x94EC010B, - 0xBA08AD94, 0x94D07F05, - 0xBA32CA70, 0x94B50D87, - 0xBA5CF210, 0x9499AC95, - 0xBA87246C, 0x947E5C32, - 0xBAB1617F, 0x94631C64, - 0xBADBA943, 0x9447ED2F, - 0xBB05FBB0, 0x942CCE95, - 0xBB3058C0, 0x9411C09D, - 0xBB5AC06C, 0x93F6C34A, - 0xBB8532AF, 0x93DBD69F, - 0xBBAFAF81, 0x93C0FAA2, - 0xBBDA36DC, 0x93A62F56, - 0xBC04C8BA, 0x938B74C0, - 0xBC2F6513, 0x9370CAE4, - 0xBC5A0BE1, 0x935631C5, - 0xBC84BD1E, 0x933BA968, - 0xBCAF78C3, 0x932131D1, - 0xBCDA3ECA, 0x9306CB04, - 0xBD050F2C, 0x92EC7505, - 0xBD2FE9E1, 0x92D22FD8, - 0xBD5ACEE5, 0x92B7FB82, - 0xBD85BE2F, 0x929DD805, - 0xBDB0B7BA, 0x9283C567, - 0xBDDBBB7F, 0x9269C3AC, - 0xBE06C977, 0x924FD2D6, - 0xBE31E19B, 0x9235F2EB, - 0xBE5D03E5, 0x921C23EE, - 0xBE88304F, 0x920265E4, - 0xBEB366D1, 0x91E8B8D0, - 0xBEDEA765, 0x91CF1CB6, - 0xBF09F204, 0x91B5919A, - 0xBF3546A8, 0x919C1780, - 0xBF60A54A, 0x9182AE6C, - 0xBF8C0DE2, 0x91695663, - 0xBFB7806C, 0x91500F67, - 0xBFE2FCDF, 0x9136D97D, - 0xC00E8335, 0x911DB4A8, - 0xC03A1368, 0x9104A0ED, - 0xC065AD70, 0x90EB9E50, - 0xC0915147, 0x90D2ACD3, - 0xC0BCFEE7, 0x90B9CC7C, - 0xC0E8B648, 0x90A0FD4E, - 0xC1147763, 0x90883F4C, - 0xC1404233, 0x906F927B, - 0xC16C16B0, 0x9056F6DF, - 0xC197F4D3, 0x903E6C7A, - 0xC1C3DC96, 0x9025F352, - 0xC1EFCDF2, 0x900D8B69, - 0xC21BC8E0, 0x8FF534C4, - 0xC247CD5A, 0x8FDCEF66, - 0xC273DB58, 0x8FC4BB53, - 0xC29FF2D4, 0x8FAC988E, - 0xC2CC13C7, 0x8F94871D, - 0xC2F83E2A, 0x8F7C8701, - 0xC32471F6, 0x8F64983F, - 0xC350AF25, 0x8F4CBADB, - 0xC37CF5B0, 0x8F34EED8, - 0xC3A9458F, 0x8F1D343A, - 0xC3D59EBD, 0x8F058B04, - 0xC4020132, 0x8EEDF33B, - 0xC42E6CE8, 0x8ED66CE1, - 0xC45AE1D7, 0x8EBEF7FB, - 0xC4875FF8, 0x8EA7948C, - 0xC4B3E746, 0x8E904298, - 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0xCBC53578, 0x8B240E10, - 0xCBF31D75, 0x8B0F9461, - 0xCC210D78, 0x8AFB2CBA, - 0xCC4F057B, 0x8AE6D71F, - 0xCC7D0577, 0x8AD29393, - 0xCCAB0D65, 0x8ABE6219, - 0xCCD91D3D, 0x8AAA42B4, - 0xCD0734F8, 0x8A963567, - 0xCD355490, 0x8A823A35, - 0xCD637BFD, 0x8A6E5122, - 0xCD91AB38, 0x8A5A7A30, - 0xCDBFE23A, 0x8A46B563, - 0xCDEE20FC, 0x8A3302BD, - 0xCE1C6776, 0x8A1F6242, - 0xCE4AB5A2, 0x8A0BD3F5, - 0xCE790B78, 0x89F857D8, - 0xCEA768F2, 0x89E4EDEE, - 0xCED5CE08, 0x89D1963C, - 0xCF043AB2, 0x89BE50C3, - 0xCF32AEEB, 0x89AB1D86, - 0xCF612AAA, 0x8997FC89, - 0xCF8FADE8, 0x8984EDCF, - 0xCFBE389F, 0x8971F15A, - 0xCFECCAC7, 0x895F072D, - 0xD01B6459, 0x894C2F4C, - 0xD04A054D, 0x893969B9, - 0xD078AD9D, 0x8926B677, - 0xD0A75D42, 0x89141589, - 0xD0D61433, 0x890186F1, - 0xD104D26B, 0x88EF0AB4, - 0xD13397E1, 0x88DCA0D3, - 0xD162648F, 0x88CA4951, - 0xD191386D, 0x88B80431, - 0xD1C01374, 0x88A5D177, - 0xD1EEF59E, 0x8893B124, - 0xD21DDEE1, 0x8881A33C, - 0xD24CCF38, 0x886FA7C2, - 0xD27BC69C, 0x885DBEB7, - 0xD2AAC504, 0x884BE820, - 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0xE17862F3, 0x83B1B649, - 0xE1A935E1, 0x83A5C2B0, - 0xE1DA0D7E, 0x8399E244, - 0xE20AE9C1, 0x838E1507, - 0xE23BCAA2, 0x83825AFB, - 0xE26CB01A, 0x8376B422, - 0xE29D9A22, 0x836B207D, - 0xE2CE88B2, 0x835FA00E, - 0xE2FF7BC3, 0x835432D8, - 0xE330734C, 0x8348D8DB, - 0xE3616F47, 0x833D921A, - 0xE3926FAC, 0x83325E97, - 0xE3C37473, 0x83273E52, - 0xE3F47D95, 0x831C314E, - 0xE4258B0A, 0x8311378C, - 0xE4569CCB, 0x8306510F, - 0xE487B2CF, 0x82FB7DD8, - 0xE4B8CD10, 0x82F0BDE8, - 0xE4E9EB86, 0x82E61141, - 0xE51B0E2A, 0x82DB77E5, - 0xE54C34F3, 0x82D0F1D5, - 0xE57D5FDA, 0x82C67F13, - 0xE5AE8ED8, 0x82BC1FA1, - 0xE5DFC1E4, 0x82B1D381, - 0xE610F8F9, 0x82A79AB3, - 0xE642340D, 0x829D753A, - 0xE6737319, 0x82936316, - 0xE6A4B616, 0x8289644A, - 0xE6D5FCFC, 0x827F78D8, - 0xE70747C3, 0x8275A0C0, - 0xE7389664, 0x826BDC04, - 0xE769E8D8, 0x82622AA5, - 0xE79B3F16, 0x82588CA6, - 0xE7CC9917, 0x824F0208, - 0xE7FDF6D3, 0x82458ACB, - 0xE82F5844, 0x823C26F2, - 0xE860BD60, 0x8232D67E, - 0xE8922621, 0x82299971, - 0xE8C3927F, 0x82206FCB, - 0xE8F50273, 0x8217598F, - 0xE92675F4, 0x820E56BE, - 0xE957ECFB, 0x82056758, - 0xE9896780, 0x81FC8B60, - 0xE9BAE57C, 0x81F3C2D7, - 0xE9EC66E8, 0x81EB0DBD, - 0xEA1DEBBB, 0x81E26C16, - 0xEA4F73EE, 0x81D9DDE1, - 0xEA80FF79, 0x81D16320, - 0xEAB28E55, 0x81C8FBD5, - 0xEAE4207A, 0x81C0A801, - 0xEB15B5E0, 0x81B867A4, - 0xEB474E80, 0x81B03AC1, - 0xEB78EA52, 0x81A82159, - 0xEBAA894E, 0x81A01B6C, - 0xEBDC2B6D, 0x819828FD, - 0xEC0DD0A8, 0x81904A0C, - 0xEC3F78F5, 0x81887E9A, - 0xEC71244F, 0x8180C6A9, - 0xECA2D2AC, 0x8179223A, - 0xECD48406, 0x8171914E, - 0xED063855, 0x816A13E6, - 0xED37EF91, 0x8162AA03, - 0xED69A9B2, 0x815B53A8, - 0xED9B66B2, 0x815410D3, - 0xEDCD2687, 0x814CE188, - 0xEDFEE92B, 0x8145C5C6, - 0xEE30AE95, 0x813EBD90, - 0xEE6276BF, 0x8137C8E6, - 0xEE9441A0, 0x8130E7C8, - 0xEEC60F31, 0x812A1A39, - 0xEEF7DF6A, 0x81236039, - 0xEF29B243, 0x811CB9CA, - 0xEF5B87B5, 0x811626EC, - 0xEF8D5FB8, 0x810FA7A0, - 0xEFBF3A44, 0x81093BE8, - 0xEFF11752, 0x8102E3C3, - 0xF022F6DA, 0x80FC9F35, - 0xF054D8D4, 0x80F66E3C, - 0xF086BD39, 0x80F050DB, - 0xF0B8A401, 0x80EA4712, - 0xF0EA8D23, 0x80E450E2, - 0xF11C789A, 0x80DE6E4C, - 0xF14E665C, 0x80D89F51, - 0xF1805662, 0x80D2E3F1, - 0xF1B248A5, 0x80CD3C2F, - 0xF1E43D1C, 0x80C7A80A, - 0xF21633C0, 0x80C22783, - 0xF2482C89, 0x80BCBA9C, - 0xF27A2770, 0x80B76155, - 0xF2AC246D, 0x80B21BAF, - 0xF2DE2378, 0x80ACE9AB, - 0xF310248A, 0x80A7CB49, - 0xF342279A, 0x80A2C08B, - 0xF3742CA1, 0x809DC970, - 0xF3A63398, 0x8098E5FB, - 0xF3D83C76, 0x8094162B, - 0xF40A4734, 0x808F5A02, - 0xF43C53CA, 0x808AB180, - 0xF46E6231, 0x80861CA5, - 0xF4A07260, 0x80819B74, - 0xF4D28451, 0x807D2DEB, - 0xF50497FA, 0x8078D40D, - 0xF536AD55, 0x80748DD9, - 0xF568C45A, 0x80705B50, - 0xF59ADD01, 0x806C3C73, - 0xF5CCF743, 0x80683143, - 0xF5FF1317, 0x806439C0, - 0xF6313076, 0x806055EA, - 0xF6634F58, 0x805C85C3, - 0xF6956FB6, 0x8058C94C, - 0xF6C79188, 0x80552083, - 0xF6F9B4C5, 0x80518B6B, - 0xF72BD967, 0x804E0A03, - 0xF75DFF65, 0x804A9C4D, - 0xF79026B8, 0x80474248, - 0xF7C24F58, 0x8043FBF6, - 0xF7F4793E, 0x8040C956, - 0xF826A461, 0x803DAA69, - 0xF858D0BA, 0x803A9F31, - 0xF88AFE41, 0x8037A7AC, - 0xF8BD2CEF, 0x8034C3DC, - 0xF8EF5CBB, 0x8031F3C1, - 0xF9218D9E, 0x802F375C, - 0xF953BF90, 0x802C8EAD, - 0xF985F28A, 0x8029F9B4, - 0xF9B82683, 0x80277872, - 0xF9EA5B75, 0x80250AE7, - 0xFA1C9156, 0x8022B113, - 0xFA4EC820, 0x80206AF8, - 0xFA80FFCB, 0x801E3894, - 0xFAB3384F, 0x801C19E9, - 0xFAE571A4, 0x801A0EF7, - 0xFB17ABC2, 0x801817BF, - 0xFB49E6A2, 0x80163440, - 0xFB7C223C, 0x8014647A, - 0xFBAE5E89, 0x8012A86F, - 0xFBE09B80, 0x8011001E, - 0xFC12D919, 0x800F6B88, - 0xFC45174E, 0x800DEAAC, - 0xFC775616, 0x800C7D8C, - 0xFCA99569, 0x800B2427, - 0xFCDBD541, 0x8009DE7D, - 0xFD0E1594, 0x8008AC90, - 0xFD40565B, 0x80078E5E, - 0xFD72978F, 0x800683E8, - 0xFDA4D928, 0x80058D2E, - 0xFDD71B1E, 0x8004AA31, - 0xFE095D69, 0x8003DAF0, - 0xFE3BA001, 0x80031F6C, - 0xFE6DE2E0, 0x800277A5, - 0xFEA025FC, 0x8001E39B, - 0xFED2694F, 0x8001634D, - 0xFF04ACD0, 0x8000F6BD, - 0xFF36F078, 0x80009DE9, - 0xFF69343E, 0x800058D3, - 0xFF9B781D, 0x8000277A, - 0xFFCDBC0A, 0x800009DE -}; - - - -/* -* @brief q15 Twiddle factors Table -*/ - - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 16 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_16_q15[24] = { - 0x7FFF, 0x0000, - 0x7641, 0x30FB, - 0x5A82, 0x5A82, - 0x30FB, 0x7641, - 0x0000, 0x7FFF, - 0xCF04, 0x7641, - 0xA57D, 0x5A82, - 0x89BE, 0x30FB, - 0x8000, 0x0000, - 0x89BE, 0xCF04, - 0xA57D, 0xA57D, - 0xCF04, 0x89BE -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 32 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_32_q15[48] = { - 0x7FFF, 0x0000, - 0x7D8A, 0x18F8, - 0x7641, 0x30FB, - 0x6A6D, 0x471C, - 0x5A82, 0x5A82, - 0x471C, 0x6A6D, - 0x30FB, 0x7641, - 0x18F8, 0x7D8A, - 0x0000, 0x7FFF, - 0xE707, 0x7D8A, - 0xCF04, 0x7641, - 0xB8E3, 0x6A6D, - 0xA57D, 0x5A82, - 0x9592, 0x471C, - 0x89BE, 0x30FB, - 0x8275, 0x18F8, - 0x8000, 0x0000, - 0x8275, 0xE707, - 0x89BE, 0xCF04, - 0x9592, 0xB8E3, - 0xA57D, 0xA57D, - 0xB8E3, 0x9592, - 0xCF04, 0x89BE, - 0xE707, 0x8275 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 64 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_64_q15[96] = { - 0x7FFF, 0x0000, - 0x7F62, 0x0C8B, - 0x7D8A, 0x18F8, - 0x7A7D, 0x2528, - 0x7641, 0x30FB, - 0x70E2, 0x3C56, - 0x6A6D, 0x471C, - 0x62F2, 0x5133, - 0x5A82, 0x5A82, - 0x5133, 0x62F2, - 0x471C, 0x6A6D, - 0x3C56, 0x70E2, - 0x30FB, 0x7641, - 0x2528, 0x7A7D, - 0x18F8, 0x7D8A, - 0x0C8B, 0x7F62, - 0x0000, 0x7FFF, - 0xF374, 0x7F62, - 0xE707, 0x7D8A, - 0xDAD7, 0x7A7D, - 0xCF04, 0x7641, - 0xC3A9, 0x70E2, - 0xB8E3, 0x6A6D, - 0xAECC, 0x62F2, - 0xA57D, 0x5A82, - 0x9D0D, 0x5133, - 0x9592, 0x471C, - 0x8F1D, 0x3C56, - 0x89BE, 0x30FB, - 0x8582, 0x2528, - 0x8275, 0x18F8, - 0x809D, 0x0C8B, - 0x8000, 0x0000, - 0x809D, 0xF374, - 0x8275, 0xE707, - 0x8582, 0xDAD7, - 0x89BE, 0xCF04, - 0x8F1D, 0xC3A9, - 0x9592, 0xB8E3, - 0x9D0D, 0xAECC, - 0xA57D, 0xA57D, - 0xAECC, 0x9D0D, - 0xB8E3, 0x9592, - 0xC3A9, 0x8F1D, - 0xCF04, 0x89BE, - 0xDAD7, 0x8582, - 0xE707, 0x8275, - 0xF374, 0x809D -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 128 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_128_q15[192] = { - 0x7FFF, 0x0000, - 0x7FD8, 0x0647, - 0x7F62, 0x0C8B, - 0x7E9D, 0x12C8, - 0x7D8A, 0x18F8, - 0x7C29, 0x1F19, - 0x7A7D, 0x2528, - 0x7884, 0x2B1F, - 0x7641, 0x30FB, - 0x73B5, 0x36BA, - 0x70E2, 0x3C56, - 0x6DCA, 0x41CE, - 0x6A6D, 0x471C, - 0x66CF, 0x4C3F, - 0x62F2, 0x5133, - 0x5ED7, 0x55F5, - 0x5A82, 0x5A82, - 0x55F5, 0x5ED7, - 0x5133, 0x62F2, - 0x4C3F, 0x66CF, - 0x471C, 0x6A6D, - 0x41CE, 0x6DCA, - 0x3C56, 0x70E2, - 0x36BA, 0x73B5, - 0x30FB, 0x7641, - 0x2B1F, 0x7884, - 0x2528, 0x7A7D, - 0x1F19, 0x7C29, - 0x18F8, 0x7D8A, - 0x12C8, 0x7E9D, - 0x0C8B, 0x7F62, - 0x0647, 0x7FD8, - 0x0000, 0x7FFF, - 0xF9B8, 0x7FD8, - 0xF374, 0x7F62, - 0xED37, 0x7E9D, - 0xE707, 0x7D8A, - 0xE0E6, 0x7C29, - 0xDAD7, 0x7A7D, - 0xD4E0, 0x7884, - 0xCF04, 0x7641, - 0xC945, 0x73B5, - 0xC3A9, 0x70E2, - 0xBE31, 0x6DCA, - 0xB8E3, 0x6A6D, - 0xB3C0, 0x66CF, - 0xAECC, 0x62F2, - 0xAA0A, 0x5ED7, - 0xA57D, 0x5A82, - 0xA128, 0x55F5, - 0x9D0D, 0x5133, - 0x9930, 0x4C3F, - 0x9592, 0x471C, - 0x9235, 0x41CE, - 0x8F1D, 0x3C56, - 0x8C4A, 0x36BA, - 0x89BE, 0x30FB, - 0x877B, 0x2B1F, - 0x8582, 0x2528, - 0x83D6, 0x1F19, - 0x8275, 0x18F8, - 0x8162, 0x12C8, - 0x809D, 0x0C8B, - 0x8027, 0x0647, - 0x8000, 0x0000, - 0x8027, 0xF9B8, - 0x809D, 0xF374, - 0x8162, 0xED37, - 0x8275, 0xE707, - 0x83D6, 0xE0E6, - 0x8582, 0xDAD7, - 0x877B, 0xD4E0, - 0x89BE, 0xCF04, - 0x8C4A, 0xC945, - 0x8F1D, 0xC3A9, - 0x9235, 0xBE31, - 0x9592, 0xB8E3, - 0x9930, 0xB3C0, - 0x9D0D, 0xAECC, - 0xA128, 0xAA0A, - 0xA57D, 0xA57D, - 0xAA0A, 0xA128, - 0xAECC, 0x9D0D, - 0xB3C0, 0x9930, - 0xB8E3, 0x9592, - 0xBE31, 0x9235, - 0xC3A9, 0x8F1D, - 0xC945, 0x8C4A, - 0xCF04, 0x89BE, - 0xD4E0, 0x877B, - 0xDAD7, 0x8582, - 0xE0E6, 0x83D6, - 0xE707, 0x8275, - 0xED37, 0x8162, - 0xF374, 0x809D, - 0xF9B8, 0x8027 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 256 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_256_q15[384] = { - 0x7FFF, 0x0000, - 0x7FF6, 0x0324, - 0x7FD8, 0x0647, - 0x7FA7, 0x096A, - 0x7F62, 0x0C8B, - 0x7F09, 0x0FAB, - 0x7E9D, 0x12C8, - 0x7E1D, 0x15E2, - 0x7D8A, 0x18F8, - 0x7CE3, 0x1C0B, - 0x7C29, 0x1F19, - 0x7B5D, 0x2223, - 0x7A7D, 0x2528, - 0x798A, 0x2826, - 0x7884, 0x2B1F, - 0x776C, 0x2E11, - 0x7641, 0x30FB, - 0x7504, 0x33DE, - 0x73B5, 0x36BA, - 0x7255, 0x398C, - 0x70E2, 0x3C56, - 0x6F5F, 0x3F17, - 0x6DCA, 0x41CE, - 0x6C24, 0x447A, - 0x6A6D, 0x471C, - 0x68A6, 0x49B4, - 0x66CF, 0x4C3F, - 0x64E8, 0x4EBF, - 0x62F2, 0x5133, - 0x60EC, 0x539B, - 0x5ED7, 0x55F5, - 0x5CB4, 0x5842, - 0x5A82, 0x5A82, - 0x5842, 0x5CB4, - 0x55F5, 0x5ED7, - 0x539B, 0x60EC, - 0x5133, 0x62F2, - 0x4EBF, 0x64E8, - 0x4C3F, 0x66CF, - 0x49B4, 0x68A6, - 0x471C, 0x6A6D, - 0x447A, 0x6C24, - 0x41CE, 0x6DCA, - 0x3F17, 0x6F5F, - 0x3C56, 0x70E2, - 0x398C, 0x7255, - 0x36BA, 0x73B5, - 0x33DE, 0x7504, - 0x30FB, 0x7641, - 0x2E11, 0x776C, - 0x2B1F, 0x7884, - 0x2826, 0x798A, - 0x2528, 0x7A7D, - 0x2223, 0x7B5D, - 0x1F19, 0x7C29, - 0x1C0B, 0x7CE3, - 0x18F8, 0x7D8A, - 0x15E2, 0x7E1D, - 0x12C8, 0x7E9D, - 0x0FAB, 0x7F09, - 0x0C8B, 0x7F62, - 0x096A, 0x7FA7, - 0x0647, 0x7FD8, - 0x0324, 0x7FF6, - 0x0000, 0x7FFF, - 0xFCDB, 0x7FF6, - 0xF9B8, 0x7FD8, - 0xF695, 0x7FA7, - 0xF374, 0x7F62, - 0xF054, 0x7F09, - 0xED37, 0x7E9D, - 0xEA1D, 0x7E1D, - 0xE707, 0x7D8A, - 0xE3F4, 0x7CE3, - 0xE0E6, 0x7C29, - 0xDDDC, 0x7B5D, - 0xDAD7, 0x7A7D, - 0xD7D9, 0x798A, - 0xD4E0, 0x7884, - 0xD1EE, 0x776C, - 0xCF04, 0x7641, - 0xCC21, 0x7504, - 0xC945, 0x73B5, - 0xC673, 0x7255, - 0xC3A9, 0x70E2, - 0xC0E8, 0x6F5F, - 0xBE31, 0x6DCA, - 0xBB85, 0x6C24, - 0xB8E3, 0x6A6D, - 0xB64B, 0x68A6, - 0xB3C0, 0x66CF, - 0xB140, 0x64E8, - 0xAECC, 0x62F2, - 0xAC64, 0x60EC, - 0xAA0A, 0x5ED7, - 0xA7BD, 0x5CB4, - 0xA57D, 0x5A82, - 0xA34B, 0x5842, - 0xA128, 0x55F5, - 0x9F13, 0x539B, - 0x9D0D, 0x5133, - 0x9B17, 0x4EBF, - 0x9930, 0x4C3F, - 0x9759, 0x49B4, - 0x9592, 0x471C, - 0x93DB, 0x447A, - 0x9235, 0x41CE, - 0x90A0, 0x3F17, - 0x8F1D, 0x3C56, - 0x8DAA, 0x398C, - 0x8C4A, 0x36BA, - 0x8AFB, 0x33DE, - 0x89BE, 0x30FB, - 0x8893, 0x2E11, - 0x877B, 0x2B1F, - 0x8675, 0x2826, - 0x8582, 0x2528, - 0x84A2, 0x2223, - 0x83D6, 0x1F19, - 0x831C, 0x1C0B, - 0x8275, 0x18F8, - 0x81E2, 0x15E2, - 0x8162, 0x12C8, - 0x80F6, 0x0FAB, - 0x809D, 0x0C8B, - 0x8058, 0x096A, - 0x8027, 0x0647, - 0x8009, 0x0324, - 0x8000, 0x0000, - 0x8009, 0xFCDB, - 0x8027, 0xF9B8, - 0x8058, 0xF695, - 0x809D, 0xF374, - 0x80F6, 0xF054, - 0x8162, 0xED37, - 0x81E2, 0xEA1D, - 0x8275, 0xE707, - 0x831C, 0xE3F4, - 0x83D6, 0xE0E6, - 0x84A2, 0xDDDC, - 0x8582, 0xDAD7, - 0x8675, 0xD7D9, - 0x877B, 0xD4E0, - 0x8893, 0xD1EE, - 0x89BE, 0xCF04, - 0x8AFB, 0xCC21, - 0x8C4A, 0xC945, - 0x8DAA, 0xC673, - 0x8F1D, 0xC3A9, - 0x90A0, 0xC0E8, - 0x9235, 0xBE31, - 0x93DB, 0xBB85, - 0x9592, 0xB8E3, - 0x9759, 0xB64B, - 0x9930, 0xB3C0, - 0x9B17, 0xB140, - 0x9D0D, 0xAECC, - 0x9F13, 0xAC64, - 0xA128, 0xAA0A, - 0xA34B, 0xA7BD, - 0xA57D, 0xA57D, - 0xA7BD, 0xA34B, - 0xAA0A, 0xA128, - 0xAC64, 0x9F13, - 0xAECC, 0x9D0D, - 0xB140, 0x9B17, - 0xB3C0, 0x9930, - 0xB64B, 0x9759, - 0xB8E3, 0x9592, - 0xBB85, 0x93DB, - 0xBE31, 0x9235, - 0xC0E8, 0x90A0, - 0xC3A9, 0x8F1D, - 0xC673, 0x8DAA, - 0xC945, 0x8C4A, - 0xCC21, 0x8AFB, - 0xCF04, 0x89BE, - 0xD1EE, 0x8893, - 0xD4E0, 0x877B, - 0xD7D9, 0x8675, - 0xDAD7, 0x8582, - 0xDDDC, 0x84A2, - 0xE0E6, 0x83D6, - 0xE3F4, 0x831C, - 0xE707, 0x8275, - 0xEA1D, 0x81E2, - 0xED37, 0x8162, - 0xF054, 0x80F6, - 0xF374, 0x809D, - 0xF695, 0x8058, - 0xF9B8, 0x8027, - 0xFCDB, 0x8009 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 512 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_512_q15[768] = { - 0x7FFF, 0x0000, - 0x7FFD, 0x0192, - 0x7FF6, 0x0324, - 0x7FE9, 0x04B6, - 0x7FD8, 0x0647, - 0x7FC2, 0x07D9, - 0x7FA7, 0x096A, - 0x7F87, 0x0AFB, - 0x7F62, 0x0C8B, - 0x7F38, 0x0E1B, - 0x7F09, 0x0FAB, - 0x7ED5, 0x1139, - 0x7E9D, 0x12C8, - 0x7E5F, 0x1455, - 0x7E1D, 0x15E2, - 0x7DD6, 0x176D, - 0x7D8A, 0x18F8, - 0x7D39, 0x1A82, - 0x7CE3, 0x1C0B, - 0x7C89, 0x1D93, - 0x7C29, 0x1F19, - 0x7BC5, 0x209F, - 0x7B5D, 0x2223, - 0x7AEF, 0x23A6, - 0x7A7D, 0x2528, - 0x7A05, 0x26A8, - 0x798A, 0x2826, - 0x7909, 0x29A3, - 0x7884, 0x2B1F, - 0x77FA, 0x2C98, - 0x776C, 0x2E11, - 0x76D9, 0x2F87, - 0x7641, 0x30FB, - 0x75A5, 0x326E, - 0x7504, 0x33DE, - 0x745F, 0x354D, - 0x73B5, 0x36BA, - 0x7307, 0x3824, - 0x7255, 0x398C, - 0x719E, 0x3AF2, - 0x70E2, 0x3C56, - 0x7023, 0x3DB8, - 0x6F5F, 0x3F17, - 0x6E96, 0x4073, - 0x6DCA, 0x41CE, - 0x6CF9, 0x4325, - 0x6C24, 0x447A, - 0x6B4A, 0x45CD, - 0x6A6D, 0x471C, - 0x698C, 0x4869, - 0x68A6, 0x49B4, - 0x67BD, 0x4AFB, - 0x66CF, 0x4C3F, - 0x65DD, 0x4D81, - 0x64E8, 0x4EBF, - 0x63EF, 0x4FFB, - 0x62F2, 0x5133, - 0x61F1, 0x5269, - 0x60EC, 0x539B, - 0x5FE3, 0x54CA, - 0x5ED7, 0x55F5, - 0x5DC7, 0x571D, - 0x5CB4, 0x5842, - 0x5B9D, 0x5964, - 0x5A82, 0x5A82, - 0x5964, 0x5B9D, - 0x5842, 0x5CB4, - 0x571D, 0x5DC7, - 0x55F5, 0x5ED7, - 0x54CA, 0x5FE3, - 0x539B, 0x60EC, - 0x5269, 0x61F1, - 0x5133, 0x62F2, - 0x4FFB, 0x63EF, - 0x4EBF, 0x64E8, - 0x4D81, 0x65DD, - 0x4C3F, 0x66CF, - 0x4AFB, 0x67BD, - 0x49B4, 0x68A6, - 0x4869, 0x698C, - 0x471C, 0x6A6D, - 0x45CD, 0x6B4A, - 0x447A, 0x6C24, - 0x4325, 0x6CF9, - 0x41CE, 0x6DCA, - 0x4073, 0x6E96, - 0x3F17, 0x6F5F, - 0x3DB8, 0x7023, - 0x3C56, 0x70E2, - 0x3AF2, 0x719E, - 0x398C, 0x7255, - 0x3824, 0x7307, - 0x36BA, 0x73B5, - 0x354D, 0x745F, - 0x33DE, 0x7504, - 0x326E, 0x75A5, - 0x30FB, 0x7641, - 0x2F87, 0x76D9, - 0x2E11, 0x776C, - 0x2C98, 0x77FA, - 0x2B1F, 0x7884, - 0x29A3, 0x7909, - 0x2826, 0x798A, - 0x26A8, 0x7A05, - 0x2528, 0x7A7D, - 0x23A6, 0x7AEF, - 0x2223, 0x7B5D, - 0x209F, 0x7BC5, - 0x1F19, 0x7C29, - 0x1D93, 0x7C89, - 0x1C0B, 0x7CE3, - 0x1A82, 0x7D39, - 0x18F8, 0x7D8A, - 0x176D, 0x7DD6, - 0x15E2, 0x7E1D, - 0x1455, 0x7E5F, - 0x12C8, 0x7E9D, - 0x1139, 0x7ED5, - 0x0FAB, 0x7F09, - 0x0E1B, 0x7F38, - 0x0C8B, 0x7F62, - 0x0AFB, 0x7F87, - 0x096A, 0x7FA7, - 0x07D9, 0x7FC2, - 0x0647, 0x7FD8, - 0x04B6, 0x7FE9, - 0x0324, 0x7FF6, - 0x0192, 0x7FFD, - 0x0000, 0x7FFF, - 0xFE6D, 0x7FFD, - 0xFCDB, 0x7FF6, - 0xFB49, 0x7FE9, - 0xF9B8, 0x7FD8, - 0xF826, 0x7FC2, - 0xF695, 0x7FA7, - 0xF504, 0x7F87, - 0xF374, 0x7F62, - 0xF1E4, 0x7F38, - 0xF054, 0x7F09, - 0xEEC6, 0x7ED5, - 0xED37, 0x7E9D, - 0xEBAA, 0x7E5F, - 0xEA1D, 0x7E1D, - 0xE892, 0x7DD6, - 0xE707, 0x7D8A, - 0xE57D, 0x7D39, - 0xE3F4, 0x7CE3, - 0xE26C, 0x7C89, - 0xE0E6, 0x7C29, - 0xDF60, 0x7BC5, - 0xDDDC, 0x7B5D, - 0xDC59, 0x7AEF, - 0xDAD7, 0x7A7D, - 0xD957, 0x7A05, - 0xD7D9, 0x798A, - 0xD65C, 0x7909, - 0xD4E0, 0x7884, - 0xD367, 0x77FA, - 0xD1EE, 0x776C, - 0xD078, 0x76D9, - 0xCF04, 0x7641, - 0xCD91, 0x75A5, - 0xCC21, 0x7504, - 0xCAB2, 0x745F, - 0xC945, 0x73B5, - 0xC7DB, 0x7307, - 0xC673, 0x7255, - 0xC50D, 0x719E, - 0xC3A9, 0x70E2, - 0xC247, 0x7023, - 0xC0E8, 0x6F5F, - 0xBF8C, 0x6E96, - 0xBE31, 0x6DCA, - 0xBCDA, 0x6CF9, - 0xBB85, 0x6C24, - 0xBA32, 0x6B4A, - 0xB8E3, 0x6A6D, - 0xB796, 0x698C, - 0xB64B, 0x68A6, - 0xB504, 0x67BD, - 0xB3C0, 0x66CF, - 0xB27E, 0x65DD, - 0xB140, 0x64E8, - 0xB004, 0x63EF, - 0xAECC, 0x62F2, - 0xAD96, 0x61F1, - 0xAC64, 0x60EC, - 0xAB35, 0x5FE3, - 0xAA0A, 0x5ED7, - 0xA8E2, 0x5DC7, - 0xA7BD, 0x5CB4, - 0xA69B, 0x5B9D, - 0xA57D, 0x5A82, - 0xA462, 0x5964, - 0xA34B, 0x5842, - 0xA238, 0x571D, - 0xA128, 0x55F5, - 0xA01C, 0x54CA, - 0x9F13, 0x539B, - 0x9E0E, 0x5269, - 0x9D0D, 0x5133, - 0x9C10, 0x4FFB, - 0x9B17, 0x4EBF, - 0x9A22, 0x4D81, - 0x9930, 0x4C3F, - 0x9842, 0x4AFB, - 0x9759, 0x49B4, - 0x9673, 0x4869, - 0x9592, 0x471C, - 0x94B5, 0x45CD, - 0x93DB, 0x447A, - 0x9306, 0x4325, - 0x9235, 0x41CE, - 0x9169, 0x4073, - 0x90A0, 0x3F17, - 0x8FDC, 0x3DB8, - 0x8F1D, 0x3C56, - 0x8E61, 0x3AF2, - 0x8DAA, 0x398C, - 0x8CF8, 0x3824, - 0x8C4A, 0x36BA, - 0x8BA0, 0x354D, - 0x8AFB, 0x33DE, - 0x8A5A, 0x326E, - 0x89BE, 0x30FB, - 0x8926, 0x2F87, - 0x8893, 0x2E11, - 0x8805, 0x2C98, - 0x877B, 0x2B1F, - 0x86F6, 0x29A3, - 0x8675, 0x2826, - 0x85FA, 0x26A8, - 0x8582, 0x2528, - 0x8510, 0x23A6, - 0x84A2, 0x2223, - 0x843A, 0x209F, - 0x83D6, 0x1F19, - 0x8376, 0x1D93, - 0x831C, 0x1C0B, - 0x82C6, 0x1A82, - 0x8275, 0x18F8, - 0x8229, 0x176D, - 0x81E2, 0x15E2, - 0x81A0, 0x1455, - 0x8162, 0x12C8, - 0x812A, 0x1139, - 0x80F6, 0x0FAB, - 0x80C7, 0x0E1B, - 0x809D, 0x0C8B, - 0x8078, 0x0AFB, - 0x8058, 0x096A, - 0x803D, 0x07D9, - 0x8027, 0x0647, - 0x8016, 0x04B6, - 0x8009, 0x0324, - 0x8002, 0x0192, - 0x8000, 0x0000, - 0x8002, 0xFE6D, - 0x8009, 0xFCDB, - 0x8016, 0xFB49, - 0x8027, 0xF9B8, - 0x803D, 0xF826, - 0x8058, 0xF695, - 0x8078, 0xF504, - 0x809D, 0xF374, - 0x80C7, 0xF1E4, - 0x80F6, 0xF054, - 0x812A, 0xEEC6, - 0x8162, 0xED37, - 0x81A0, 0xEBAA, - 0x81E2, 0xEA1D, - 0x8229, 0xE892, - 0x8275, 0xE707, - 0x82C6, 0xE57D, - 0x831C, 0xE3F4, - 0x8376, 0xE26C, - 0x83D6, 0xE0E6, - 0x843A, 0xDF60, - 0x84A2, 0xDDDC, - 0x8510, 0xDC59, - 0x8582, 0xDAD7, - 0x85FA, 0xD957, - 0x8675, 0xD7D9, - 0x86F6, 0xD65C, - 0x877B, 0xD4E0, - 0x8805, 0xD367, - 0x8893, 0xD1EE, - 0x8926, 0xD078, - 0x89BE, 0xCF04, - 0x8A5A, 0xCD91, - 0x8AFB, 0xCC21, - 0x8BA0, 0xCAB2, - 0x8C4A, 0xC945, - 0x8CF8, 0xC7DB, - 0x8DAA, 0xC673, - 0x8E61, 0xC50D, - 0x8F1D, 0xC3A9, - 0x8FDC, 0xC247, - 0x90A0, 0xC0E8, - 0x9169, 0xBF8C, - 0x9235, 0xBE31, - 0x9306, 0xBCDA, - 0x93DB, 0xBB85, - 0x94B5, 0xBA32, - 0x9592, 0xB8E3, - 0x9673, 0xB796, - 0x9759, 0xB64B, - 0x9842, 0xB504, - 0x9930, 0xB3C0, - 0x9A22, 0xB27E, - 0x9B17, 0xB140, - 0x9C10, 0xB004, - 0x9D0D, 0xAECC, - 0x9E0E, 0xAD96, - 0x9F13, 0xAC64, - 0xA01C, 0xAB35, - 0xA128, 0xAA0A, - 0xA238, 0xA8E2, - 0xA34B, 0xA7BD, - 0xA462, 0xA69B, - 0xA57D, 0xA57D, - 0xA69B, 0xA462, - 0xA7BD, 0xA34B, - 0xA8E2, 0xA238, - 0xAA0A, 0xA128, - 0xAB35, 0xA01C, - 0xAC64, 0x9F13, - 0xAD96, 0x9E0E, - 0xAECC, 0x9D0D, - 0xB004, 0x9C10, - 0xB140, 0x9B17, - 0xB27E, 0x9A22, - 0xB3C0, 0x9930, - 0xB504, 0x9842, - 0xB64B, 0x9759, - 0xB796, 0x9673, - 0xB8E3, 0x9592, - 0xBA32, 0x94B5, - 0xBB85, 0x93DB, - 0xBCDA, 0x9306, - 0xBE31, 0x9235, - 0xBF8C, 0x9169, - 0xC0E8, 0x90A0, - 0xC247, 0x8FDC, - 0xC3A9, 0x8F1D, - 0xC50D, 0x8E61, - 0xC673, 0x8DAA, - 0xC7DB, 0x8CF8, - 0xC945, 0x8C4A, - 0xCAB2, 0x8BA0, - 0xCC21, 0x8AFB, - 0xCD91, 0x8A5A, - 0xCF04, 0x89BE, - 0xD078, 0x8926, - 0xD1EE, 0x8893, - 0xD367, 0x8805, - 0xD4E0, 0x877B, - 0xD65C, 0x86F6, - 0xD7D9, 0x8675, - 0xD957, 0x85FA, - 0xDAD7, 0x8582, - 0xDC59, 0x8510, - 0xDDDC, 0x84A2, - 0xDF60, 0x843A, - 0xE0E6, 0x83D6, - 0xE26C, 0x8376, - 0xE3F4, 0x831C, - 0xE57D, 0x82C6, - 0xE707, 0x8275, - 0xE892, 0x8229, - 0xEA1D, 0x81E2, - 0xEBAA, 0x81A0, - 0xED37, 0x8162, - 0xEEC6, 0x812A, - 0xF054, 0x80F6, - 0xF1E4, 0x80C7, - 0xF374, 0x809D, - 0xF504, 0x8078, - 0xF695, 0x8058, - 0xF826, 0x803D, - 0xF9B8, 0x8027, - 0xFB49, 0x8016, - 0xFCDB, 0x8009, - 0xFE6D, 0x8002 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 1024 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_1024_q15[1536] = { - 0x7FFF, 0x0000, - 0x7FFF, 0x00C9, - 0x7FFD, 0x0192, - 0x7FFA, 0x025B, - 0x7FF6, 0x0324, - 0x7FF0, 0x03ED, - 0x7FE9, 0x04B6, - 0x7FE1, 0x057F, - 0x7FD8, 0x0647, - 0x7FCE, 0x0710, - 0x7FC2, 0x07D9, - 0x7FB5, 0x08A2, - 0x7FA7, 0x096A, - 0x7F97, 0x0A33, - 0x7F87, 0x0AFB, - 0x7F75, 0x0BC3, - 0x7F62, 0x0C8B, - 0x7F4D, 0x0D53, - 0x7F38, 0x0E1B, - 0x7F21, 0x0EE3, - 0x7F09, 0x0FAB, - 0x7EF0, 0x1072, - 0x7ED5, 0x1139, - 0x7EBA, 0x1201, - 0x7E9D, 0x12C8, - 0x7E7F, 0x138E, - 0x7E5F, 0x1455, - 0x7E3F, 0x151B, - 0x7E1D, 0x15E2, - 0x7DFA, 0x16A8, - 0x7DD6, 0x176D, - 0x7DB0, 0x1833, - 0x7D8A, 0x18F8, - 0x7D62, 0x19BD, - 0x7D39, 0x1A82, - 0x7D0F, 0x1B47, - 0x7CE3, 0x1C0B, - 0x7CB7, 0x1CCF, - 0x7C89, 0x1D93, - 0x7C5A, 0x1E56, - 0x7C29, 0x1F19, - 0x7BF8, 0x1FDC, - 0x7BC5, 0x209F, - 0x7B92, 0x2161, - 0x7B5D, 0x2223, - 0x7B26, 0x22E5, - 0x7AEF, 0x23A6, - 0x7AB6, 0x2467, - 0x7A7D, 0x2528, - 0x7A42, 0x25E8, - 0x7A05, 0x26A8, - 0x79C8, 0x2767, - 0x798A, 0x2826, - 0x794A, 0x28E5, - 0x7909, 0x29A3, - 0x78C7, 0x2A61, - 0x7884, 0x2B1F, - 0x7840, 0x2BDC, - 0x77FA, 0x2C98, - 0x77B4, 0x2D55, - 0x776C, 0x2E11, - 0x7723, 0x2ECC, - 0x76D9, 0x2F87, - 0x768E, 0x3041, - 0x7641, 0x30FB, - 0x75F4, 0x31B5, - 0x75A5, 0x326E, - 0x7555, 0x3326, - 0x7504, 0x33DE, - 0x74B2, 0x3496, - 0x745F, 0x354D, - 0x740B, 0x3604, - 0x73B5, 0x36BA, - 0x735F, 0x376F, - 0x7307, 0x3824, - 0x72AF, 0x38D8, - 0x7255, 0x398C, - 0x71FA, 0x3A40, - 0x719E, 0x3AF2, - 0x7141, 0x3BA5, - 0x70E2, 0x3C56, - 0x7083, 0x3D07, - 0x7023, 0x3DB8, - 0x6FC1, 0x3E68, - 0x6F5F, 0x3F17, - 0x6EFB, 0x3FC5, - 0x6E96, 0x4073, - 0x6E30, 0x4121, - 0x6DCA, 0x41CE, - 0x6D62, 0x427A, - 0x6CF9, 0x4325, - 0x6C8F, 0x43D0, - 0x6C24, 0x447A, - 0x6BB8, 0x4524, - 0x6B4A, 0x45CD, - 0x6ADC, 0x4675, - 0x6A6D, 0x471C, - 0x69FD, 0x47C3, - 0x698C, 0x4869, - 0x6919, 0x490F, - 0x68A6, 0x49B4, - 0x6832, 0x4A58, - 0x67BD, 0x4AFB, - 0x6746, 0x4B9E, - 0x66CF, 0x4C3F, - 0x6657, 0x4CE1, - 0x65DD, 0x4D81, - 0x6563, 0x4E21, - 0x64E8, 0x4EBF, - 0x646C, 0x4F5E, - 0x63EF, 0x4FFB, - 0x6371, 0x5097, - 0x62F2, 0x5133, - 0x6271, 0x51CE, - 0x61F1, 0x5269, - 0x616F, 0x5302, - 0x60EC, 0x539B, - 0x6068, 0x5433, - 0x5FE3, 0x54CA, - 0x5F5E, 0x5560, - 0x5ED7, 0x55F5, - 0x5E50, 0x568A, - 0x5DC7, 0x571D, - 0x5D3E, 0x57B0, - 0x5CB4, 0x5842, - 0x5C29, 0x58D4, - 0x5B9D, 0x5964, - 0x5B10, 0x59F3, - 0x5A82, 0x5A82, - 0x59F3, 0x5B10, - 0x5964, 0x5B9D, - 0x58D4, 0x5C29, - 0x5842, 0x5CB4, - 0x57B0, 0x5D3E, - 0x571D, 0x5DC7, - 0x568A, 0x5E50, - 0x55F5, 0x5ED7, - 0x5560, 0x5F5E, - 0x54CA, 0x5FE3, - 0x5433, 0x6068, - 0x539B, 0x60EC, - 0x5302, 0x616F, - 0x5269, 0x61F1, - 0x51CE, 0x6271, - 0x5133, 0x62F2, - 0x5097, 0x6371, - 0x4FFB, 0x63EF, - 0x4F5E, 0x646C, - 0x4EBF, 0x64E8, - 0x4E21, 0x6563, - 0x4D81, 0x65DD, - 0x4CE1, 0x6657, - 0x4C3F, 0x66CF, - 0x4B9E, 0x6746, - 0x4AFB, 0x67BD, - 0x4A58, 0x6832, - 0x49B4, 0x68A6, - 0x490F, 0x6919, - 0x4869, 0x698C, - 0x47C3, 0x69FD, - 0x471C, 0x6A6D, - 0x4675, 0x6ADC, - 0x45CD, 0x6B4A, - 0x4524, 0x6BB8, - 0x447A, 0x6C24, - 0x43D0, 0x6C8F, - 0x4325, 0x6CF9, - 0x427A, 0x6D62, - 0x41CE, 0x6DCA, - 0x4121, 0x6E30, - 0x4073, 0x6E96, - 0x3FC5, 0x6EFB, - 0x3F17, 0x6F5F, - 0x3E68, 0x6FC1, - 0x3DB8, 0x7023, - 0x3D07, 0x7083, - 0x3C56, 0x70E2, - 0x3BA5, 0x7141, - 0x3AF2, 0x719E, - 0x3A40, 0x71FA, - 0x398C, 0x7255, - 0x38D8, 0x72AF, - 0x3824, 0x7307, - 0x376F, 0x735F, - 0x36BA, 0x73B5, - 0x3604, 0x740B, - 0x354D, 0x745F, - 0x3496, 0x74B2, - 0x33DE, 0x7504, - 0x3326, 0x7555, - 0x326E, 0x75A5, - 0x31B5, 0x75F4, - 0x30FB, 0x7641, - 0x3041, 0x768E, - 0x2F87, 0x76D9, - 0x2ECC, 0x7723, - 0x2E11, 0x776C, - 0x2D55, 0x77B4, - 0x2C98, 0x77FA, - 0x2BDC, 0x7840, - 0x2B1F, 0x7884, - 0x2A61, 0x78C7, - 0x29A3, 0x7909, - 0x28E5, 0x794A, - 0x2826, 0x798A, - 0x2767, 0x79C8, - 0x26A8, 0x7A05, - 0x25E8, 0x7A42, - 0x2528, 0x7A7D, - 0x2467, 0x7AB6, - 0x23A6, 0x7AEF, - 0x22E5, 0x7B26, - 0x2223, 0x7B5D, - 0x2161, 0x7B92, - 0x209F, 0x7BC5, - 0x1FDC, 0x7BF8, - 0x1F19, 0x7C29, - 0x1E56, 0x7C5A, - 0x1D93, 0x7C89, - 0x1CCF, 0x7CB7, - 0x1C0B, 0x7CE3, - 0x1B47, 0x7D0F, - 0x1A82, 0x7D39, - 0x19BD, 0x7D62, - 0x18F8, 0x7D8A, - 0x1833, 0x7DB0, - 0x176D, 0x7DD6, - 0x16A8, 0x7DFA, - 0x15E2, 0x7E1D, - 0x151B, 0x7E3F, - 0x1455, 0x7E5F, - 0x138E, 0x7E7F, - 0x12C8, 0x7E9D, - 0x1201, 0x7EBA, - 0x1139, 0x7ED5, - 0x1072, 0x7EF0, - 0x0FAB, 0x7F09, - 0x0EE3, 0x7F21, - 0x0E1B, 0x7F38, - 0x0D53, 0x7F4D, - 0x0C8B, 0x7F62, - 0x0BC3, 0x7F75, - 0x0AFB, 0x7F87, - 0x0A33, 0x7F97, - 0x096A, 0x7FA7, - 0x08A2, 0x7FB5, - 0x07D9, 0x7FC2, - 0x0710, 0x7FCE, - 0x0647, 0x7FD8, - 0x057F, 0x7FE1, - 0x04B6, 0x7FE9, - 0x03ED, 0x7FF0, - 0x0324, 0x7FF6, - 0x025B, 0x7FFA, - 0x0192, 0x7FFD, - 0x00C9, 0x7FFF, - 0x0000, 0x7FFF, - 0xFF36, 0x7FFF, - 0xFE6D, 0x7FFD, - 0xFDA4, 0x7FFA, - 0xFCDB, 0x7FF6, - 0xFC12, 0x7FF0, - 0xFB49, 0x7FE9, - 0xFA80, 0x7FE1, - 0xF9B8, 0x7FD8, - 0xF8EF, 0x7FCE, - 0xF826, 0x7FC2, - 0xF75D, 0x7FB5, - 0xF695, 0x7FA7, - 0xF5CC, 0x7F97, - 0xF504, 0x7F87, - 0xF43C, 0x7F75, - 0xF374, 0x7F62, - 0xF2AC, 0x7F4D, - 0xF1E4, 0x7F38, - 0xF11C, 0x7F21, - 0xF054, 0x7F09, - 0xEF8D, 0x7EF0, - 0xEEC6, 0x7ED5, - 0xEDFE, 0x7EBA, - 0xED37, 0x7E9D, - 0xEC71, 0x7E7F, - 0xEBAA, 0x7E5F, - 0xEAE4, 0x7E3F, - 0xEA1D, 0x7E1D, - 0xE957, 0x7DFA, - 0xE892, 0x7DD6, - 0xE7CC, 0x7DB0, - 0xE707, 0x7D8A, - 0xE642, 0x7D62, - 0xE57D, 0x7D39, - 0xE4B8, 0x7D0F, - 0xE3F4, 0x7CE3, - 0xE330, 0x7CB7, - 0xE26C, 0x7C89, - 0xE1A9, 0x7C5A, - 0xE0E6, 0x7C29, - 0xE023, 0x7BF8, - 0xDF60, 0x7BC5, - 0xDE9E, 0x7B92, - 0xDDDC, 0x7B5D, - 0xDD1A, 0x7B26, - 0xDC59, 0x7AEF, - 0xDB98, 0x7AB6, - 0xDAD7, 0x7A7D, - 0xDA17, 0x7A42, - 0xD957, 0x7A05, - 0xD898, 0x79C8, - 0xD7D9, 0x798A, - 0xD71A, 0x794A, - 0xD65C, 0x7909, - 0xD59E, 0x78C7, - 0xD4E0, 0x7884, - 0xD423, 0x7840, - 0xD367, 0x77FA, - 0xD2AA, 0x77B4, - 0xD1EE, 0x776C, - 0xD133, 0x7723, - 0xD078, 0x76D9, - 0xCFBE, 0x768E, - 0xCF04, 0x7641, - 0xCE4A, 0x75F4, - 0xCD91, 0x75A5, - 0xCCD9, 0x7555, - 0xCC21, 0x7504, - 0xCB69, 0x74B2, - 0xCAB2, 0x745F, - 0xC9FB, 0x740B, - 0xC945, 0x73B5, - 0xC890, 0x735F, - 0xC7DB, 0x7307, - 0xC727, 0x72AF, - 0xC673, 0x7255, - 0xC5BF, 0x71FA, - 0xC50D, 0x719E, - 0xC45A, 0x7141, - 0xC3A9, 0x70E2, - 0xC2F8, 0x7083, - 0xC247, 0x7023, - 0xC197, 0x6FC1, - 0xC0E8, 0x6F5F, - 0xC03A, 0x6EFB, - 0xBF8C, 0x6E96, - 0xBEDE, 0x6E30, - 0xBE31, 0x6DCA, - 0xBD85, 0x6D62, - 0xBCDA, 0x6CF9, - 0xBC2F, 0x6C8F, - 0xBB85, 0x6C24, - 0xBADB, 0x6BB8, - 0xBA32, 0x6B4A, - 0xB98A, 0x6ADC, - 0xB8E3, 0x6A6D, - 0xB83C, 0x69FD, - 0xB796, 0x698C, - 0xB6F0, 0x6919, - 0xB64B, 0x68A6, - 0xB5A7, 0x6832, - 0xB504, 0x67BD, - 0xB461, 0x6746, - 0xB3C0, 0x66CF, - 0xB31E, 0x6657, - 0xB27E, 0x65DD, - 0xB1DE, 0x6563, - 0xB140, 0x64E8, - 0xB0A1, 0x646C, - 0xB004, 0x63EF, - 0xAF68, 0x6371, - 0xAECC, 0x62F2, - 0xAE31, 0x6271, - 0xAD96, 0x61F1, - 0xACFD, 0x616F, - 0xAC64, 0x60EC, - 0xABCC, 0x6068, - 0xAB35, 0x5FE3, - 0xAA9F, 0x5F5E, - 0xAA0A, 0x5ED7, - 0xA975, 0x5E50, - 0xA8E2, 0x5DC7, - 0xA84F, 0x5D3E, - 0xA7BD, 0x5CB4, - 0xA72B, 0x5C29, - 0xA69B, 0x5B9D, - 0xA60C, 0x5B10, - 0xA57D, 0x5A82, - 0xA4EF, 0x59F3, - 0xA462, 0x5964, - 0xA3D6, 0x58D4, - 0xA34B, 0x5842, - 0xA2C1, 0x57B0, - 0xA238, 0x571D, - 0xA1AF, 0x568A, - 0xA128, 0x55F5, - 0xA0A1, 0x5560, - 0xA01C, 0x54CA, - 0x9F97, 0x5433, - 0x9F13, 0x539B, - 0x9E90, 0x5302, - 0x9E0E, 0x5269, - 0x9D8E, 0x51CE, - 0x9D0D, 0x5133, - 0x9C8E, 0x5097, - 0x9C10, 0x4FFB, - 0x9B93, 0x4F5E, - 0x9B17, 0x4EBF, - 0x9A9C, 0x4E21, - 0x9A22, 0x4D81, - 0x99A8, 0x4CE1, - 0x9930, 0x4C3F, - 0x98B9, 0x4B9E, - 0x9842, 0x4AFB, - 0x97CD, 0x4A58, - 0x9759, 0x49B4, - 0x96E6, 0x490F, - 0x9673, 0x4869, - 0x9602, 0x47C3, - 0x9592, 0x471C, - 0x9523, 0x4675, - 0x94B5, 0x45CD, - 0x9447, 0x4524, - 0x93DB, 0x447A, - 0x9370, 0x43D0, - 0x9306, 0x4325, - 0x929D, 0x427A, - 0x9235, 0x41CE, - 0x91CF, 0x4121, - 0x9169, 0x4073, - 0x9104, 0x3FC5, - 0x90A0, 0x3F17, - 0x903E, 0x3E68, - 0x8FDC, 0x3DB8, - 0x8F7C, 0x3D07, - 0x8F1D, 0x3C56, - 0x8EBE, 0x3BA5, - 0x8E61, 0x3AF2, - 0x8E05, 0x3A40, - 0x8DAA, 0x398C, - 0x8D50, 0x38D8, - 0x8CF8, 0x3824, - 0x8CA0, 0x376F, - 0x8C4A, 0x36BA, - 0x8BF4, 0x3604, - 0x8BA0, 0x354D, - 0x8B4D, 0x3496, - 0x8AFB, 0x33DE, - 0x8AAA, 0x3326, - 0x8A5A, 0x326E, - 0x8A0B, 0x31B5, - 0x89BE, 0x30FB, - 0x8971, 0x3041, - 0x8926, 0x2F87, - 0x88DC, 0x2ECC, - 0x8893, 0x2E11, - 0x884B, 0x2D55, - 0x8805, 0x2C98, - 0x87BF, 0x2BDC, - 0x877B, 0x2B1F, - 0x8738, 0x2A61, - 0x86F6, 0x29A3, - 0x86B5, 0x28E5, - 0x8675, 0x2826, - 0x8637, 0x2767, - 0x85FA, 0x26A8, - 0x85BD, 0x25E8, - 0x8582, 0x2528, - 0x8549, 0x2467, - 0x8510, 0x23A6, - 0x84D9, 0x22E5, - 0x84A2, 0x2223, - 0x846D, 0x2161, - 0x843A, 0x209F, - 0x8407, 0x1FDC, - 0x83D6, 0x1F19, - 0x83A5, 0x1E56, - 0x8376, 0x1D93, - 0x8348, 0x1CCF, - 0x831C, 0x1C0B, - 0x82F0, 0x1B47, - 0x82C6, 0x1A82, - 0x829D, 0x19BD, - 0x8275, 0x18F8, - 0x824F, 0x1833, - 0x8229, 0x176D, - 0x8205, 0x16A8, - 0x81E2, 0x15E2, - 0x81C0, 0x151B, - 0x81A0, 0x1455, - 0x8180, 0x138E, - 0x8162, 0x12C8, - 0x8145, 0x1201, - 0x812A, 0x1139, - 0x810F, 0x1072, - 0x80F6, 0x0FAB, - 0x80DE, 0x0EE3, - 0x80C7, 0x0E1B, - 0x80B2, 0x0D53, - 0x809D, 0x0C8B, - 0x808A, 0x0BC3, - 0x8078, 0x0AFB, - 0x8068, 0x0A33, - 0x8058, 0x096A, - 0x804A, 0x08A2, - 0x803D, 0x07D9, - 0x8031, 0x0710, - 0x8027, 0x0647, - 0x801E, 0x057F, - 0x8016, 0x04B6, - 0x800F, 0x03ED, - 0x8009, 0x0324, - 0x8005, 0x025B, - 0x8002, 0x0192, - 0x8000, 0x00C9, - 0x8000, 0x0000, - 0x8000, 0xFF36, - 0x8002, 0xFE6D, - 0x8005, 0xFDA4, - 0x8009, 0xFCDB, - 0x800F, 0xFC12, - 0x8016, 0xFB49, - 0x801E, 0xFA80, - 0x8027, 0xF9B8, - 0x8031, 0xF8EF, - 0x803D, 0xF826, - 0x804A, 0xF75D, - 0x8058, 0xF695, - 0x8068, 0xF5CC, - 0x8078, 0xF504, - 0x808A, 0xF43C, - 0x809D, 0xF374, - 0x80B2, 0xF2AC, - 0x80C7, 0xF1E4, - 0x80DE, 0xF11C, - 0x80F6, 0xF054, - 0x810F, 0xEF8D, - 0x812A, 0xEEC6, - 0x8145, 0xEDFE, - 0x8162, 0xED37, - 0x8180, 0xEC71, - 0x81A0, 0xEBAA, - 0x81C0, 0xEAE4, - 0x81E2, 0xEA1D, - 0x8205, 0xE957, - 0x8229, 0xE892, - 0x824F, 0xE7CC, - 0x8275, 0xE707, - 0x829D, 0xE642, - 0x82C6, 0xE57D, - 0x82F0, 0xE4B8, - 0x831C, 0xE3F4, - 0x8348, 0xE330, - 0x8376, 0xE26C, - 0x83A5, 0xE1A9, - 0x83D6, 0xE0E6, - 0x8407, 0xE023, - 0x843A, 0xDF60, - 0x846D, 0xDE9E, - 0x84A2, 0xDDDC, - 0x84D9, 0xDD1A, - 0x8510, 0xDC59, - 0x8549, 0xDB98, - 0x8582, 0xDAD7, - 0x85BD, 0xDA17, - 0x85FA, 0xD957, - 0x8637, 0xD898, - 0x8675, 0xD7D9, - 0x86B5, 0xD71A, - 0x86F6, 0xD65C, - 0x8738, 0xD59E, - 0x877B, 0xD4E0, - 0x87BF, 0xD423, - 0x8805, 0xD367, - 0x884B, 0xD2AA, - 0x8893, 0xD1EE, - 0x88DC, 0xD133, - 0x8926, 0xD078, - 0x8971, 0xCFBE, - 0x89BE, 0xCF04, - 0x8A0B, 0xCE4A, - 0x8A5A, 0xCD91, - 0x8AAA, 0xCCD9, - 0x8AFB, 0xCC21, - 0x8B4D, 0xCB69, - 0x8BA0, 0xCAB2, - 0x8BF4, 0xC9FB, - 0x8C4A, 0xC945, - 0x8CA0, 0xC890, - 0x8CF8, 0xC7DB, - 0x8D50, 0xC727, - 0x8DAA, 0xC673, - 0x8E05, 0xC5BF, - 0x8E61, 0xC50D, - 0x8EBE, 0xC45A, - 0x8F1D, 0xC3A9, - 0x8F7C, 0xC2F8, - 0x8FDC, 0xC247, - 0x903E, 0xC197, - 0x90A0, 0xC0E8, - 0x9104, 0xC03A, - 0x9169, 0xBF8C, - 0x91CF, 0xBEDE, - 0x9235, 0xBE31, - 0x929D, 0xBD85, - 0x9306, 0xBCDA, - 0x9370, 0xBC2F, - 0x93DB, 0xBB85, - 0x9447, 0xBADB, - 0x94B5, 0xBA32, - 0x9523, 0xB98A, - 0x9592, 0xB8E3, - 0x9602, 0xB83C, - 0x9673, 0xB796, - 0x96E6, 0xB6F0, - 0x9759, 0xB64B, - 0x97CD, 0xB5A7, - 0x9842, 0xB504, - 0x98B9, 0xB461, - 0x9930, 0xB3C0, - 0x99A8, 0xB31E, - 0x9A22, 0xB27E, - 0x9A9C, 0xB1DE, - 0x9B17, 0xB140, - 0x9B93, 0xB0A1, - 0x9C10, 0xB004, - 0x9C8E, 0xAF68, - 0x9D0D, 0xAECC, - 0x9D8E, 0xAE31, - 0x9E0E, 0xAD96, - 0x9E90, 0xACFD, - 0x9F13, 0xAC64, - 0x9F97, 0xABCC, - 0xA01C, 0xAB35, - 0xA0A1, 0xAA9F, - 0xA128, 0xAA0A, - 0xA1AF, 0xA975, - 0xA238, 0xA8E2, - 0xA2C1, 0xA84F, - 0xA34B, 0xA7BD, - 0xA3D6, 0xA72B, - 0xA462, 0xA69B, - 0xA4EF, 0xA60C, - 0xA57D, 0xA57D, - 0xA60C, 0xA4EF, - 0xA69B, 0xA462, - 0xA72B, 0xA3D6, - 0xA7BD, 0xA34B, - 0xA84F, 0xA2C1, - 0xA8E2, 0xA238, - 0xA975, 0xA1AF, - 0xAA0A, 0xA128, - 0xAA9F, 0xA0A1, - 0xAB35, 0xA01C, - 0xABCC, 0x9F97, - 0xAC64, 0x9F13, - 0xACFD, 0x9E90, - 0xAD96, 0x9E0E, - 0xAE31, 0x9D8E, - 0xAECC, 0x9D0D, - 0xAF68, 0x9C8E, - 0xB004, 0x9C10, - 0xB0A1, 0x9B93, - 0xB140, 0x9B17, - 0xB1DE, 0x9A9C, - 0xB27E, 0x9A22, - 0xB31E, 0x99A8, - 0xB3C0, 0x9930, - 0xB461, 0x98B9, - 0xB504, 0x9842, - 0xB5A7, 0x97CD, - 0xB64B, 0x9759, - 0xB6F0, 0x96E6, - 0xB796, 0x9673, - 0xB83C, 0x9602, - 0xB8E3, 0x9592, - 0xB98A, 0x9523, - 0xBA32, 0x94B5, - 0xBADB, 0x9447, - 0xBB85, 0x93DB, - 0xBC2F, 0x9370, - 0xBCDA, 0x9306, - 0xBD85, 0x929D, - 0xBE31, 0x9235, - 0xBEDE, 0x91CF, - 0xBF8C, 0x9169, - 0xC03A, 0x9104, - 0xC0E8, 0x90A0, - 0xC197, 0x903E, - 0xC247, 0x8FDC, - 0xC2F8, 0x8F7C, - 0xC3A9, 0x8F1D, - 0xC45A, 0x8EBE, - 0xC50D, 0x8E61, - 0xC5BF, 0x8E05, - 0xC673, 0x8DAA, - 0xC727, 0x8D50, - 0xC7DB, 0x8CF8, - 0xC890, 0x8CA0, - 0xC945, 0x8C4A, - 0xC9FB, 0x8BF4, - 0xCAB2, 0x8BA0, - 0xCB69, 0x8B4D, - 0xCC21, 0x8AFB, - 0xCCD9, 0x8AAA, - 0xCD91, 0x8A5A, - 0xCE4A, 0x8A0B, - 0xCF04, 0x89BE, - 0xCFBE, 0x8971, - 0xD078, 0x8926, - 0xD133, 0x88DC, - 0xD1EE, 0x8893, - 0xD2AA, 0x884B, - 0xD367, 0x8805, - 0xD423, 0x87BF, - 0xD4E0, 0x877B, - 0xD59E, 0x8738, - 0xD65C, 0x86F6, - 0xD71A, 0x86B5, - 0xD7D9, 0x8675, - 0xD898, 0x8637, - 0xD957, 0x85FA, - 0xDA17, 0x85BD, - 0xDAD7, 0x8582, - 0xDB98, 0x8549, - 0xDC59, 0x8510, - 0xDD1A, 0x84D9, - 0xDDDC, 0x84A2, - 0xDE9E, 0x846D, - 0xDF60, 0x843A, - 0xE023, 0x8407, - 0xE0E6, 0x83D6, - 0xE1A9, 0x83A5, - 0xE26C, 0x8376, - 0xE330, 0x8348, - 0xE3F4, 0x831C, - 0xE4B8, 0x82F0, - 0xE57D, 0x82C6, - 0xE642, 0x829D, - 0xE707, 0x8275, - 0xE7CC, 0x824F, - 0xE892, 0x8229, - 0xE957, 0x8205, - 0xEA1D, 0x81E2, - 0xEAE4, 0x81C0, - 0xEBAA, 0x81A0, - 0xEC71, 0x8180, - 0xED37, 0x8162, - 0xEDFE, 0x8145, - 0xEEC6, 0x812A, - 0xEF8D, 0x810F, - 0xF054, 0x80F6, - 0xF11C, 0x80DE, - 0xF1E4, 0x80C7, - 0xF2AC, 0x80B2, - 0xF374, 0x809D, - 0xF43C, 0x808A, - 0xF504, 0x8078, - 0xF5CC, 0x8068, - 0xF695, 0x8058, - 0xF75D, 0x804A, - 0xF826, 0x803D, - 0xF8EF, 0x8031, - 0xF9B8, 0x8027, - 0xFA80, 0x801E, - 0xFB49, 0x8016, - 0xFC12, 0x800F, - 0xFCDB, 0x8009, - 0xFDA4, 0x8005, - 0xFE6D, 0x8002, - 0xFF36, 0x8000 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 2048 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_2048_q15[3072] = { - 0x7FFF, 0x0000, - 0x7FFF, 0x0064, - 0x7FFF, 0x00C9, - 0x7FFE, 0x012D, - 0x7FFD, 0x0192, - 0x7FFC, 0x01F6, - 0x7FFA, 0x025B, - 0x7FF8, 0x02BF, - 0x7FF6, 0x0324, - 0x7FF3, 0x0388, - 0x7FF0, 0x03ED, - 0x7FED, 0x0451, - 0x7FE9, 0x04B6, - 0x7FE5, 0x051A, - 0x7FE1, 0x057F, - 0x7FDD, 0x05E3, - 0x7FD8, 0x0647, - 0x7FD3, 0x06AC, - 0x7FCE, 0x0710, - 0x7FC8, 0x0775, - 0x7FC2, 0x07D9, - 0x7FBC, 0x083D, - 0x7FB5, 0x08A2, - 0x7FAE, 0x0906, - 0x7FA7, 0x096A, - 0x7F9F, 0x09CE, - 0x7F97, 0x0A33, - 0x7F8F, 0x0A97, - 0x7F87, 0x0AFB, - 0x7F7E, 0x0B5F, - 0x7F75, 0x0BC3, - 0x7F6B, 0x0C27, - 0x7F62, 0x0C8B, - 0x7F58, 0x0CEF, - 0x7F4D, 0x0D53, - 0x7F43, 0x0DB7, - 0x7F38, 0x0E1B, - 0x7F2D, 0x0E7F, - 0x7F21, 0x0EE3, - 0x7F15, 0x0F47, - 0x7F09, 0x0FAB, - 0x7EFD, 0x100E, - 0x7EF0, 0x1072, - 0x7EE3, 0x10D6, - 0x7ED5, 0x1139, - 0x7EC8, 0x119D, - 0x7EBA, 0x1201, - 0x7EAB, 0x1264, - 0x7E9D, 0x12C8, - 0x7E8E, 0x132B, - 0x7E7F, 0x138E, - 0x7E6F, 0x13F2, - 0x7E5F, 0x1455, - 0x7E4F, 0x14B8, - 0x7E3F, 0x151B, - 0x7E2E, 0x157F, - 0x7E1D, 0x15E2, - 0x7E0C, 0x1645, - 0x7DFA, 0x16A8, - 0x7DE8, 0x170A, - 0x7DD6, 0x176D, - 0x7DC3, 0x17D0, - 0x7DB0, 0x1833, - 0x7D9D, 0x1896, - 0x7D8A, 0x18F8, - 0x7D76, 0x195B, - 0x7D62, 0x19BD, - 0x7D4E, 0x1A20, - 0x7D39, 0x1A82, - 0x7D24, 0x1AE4, - 0x7D0F, 0x1B47, - 0x7CF9, 0x1BA9, - 0x7CE3, 0x1C0B, - 0x7CCD, 0x1C6D, - 0x7CB7, 0x1CCF, - 0x7CA0, 0x1D31, - 0x7C89, 0x1D93, - 0x7C71, 0x1DF5, - 0x7C5A, 0x1E56, - 0x7C42, 0x1EB8, - 0x7C29, 0x1F19, - 0x7C11, 0x1F7B, - 0x7BF8, 0x1FDC, - 0x7BDF, 0x203E, - 0x7BC5, 0x209F, - 0x7BAC, 0x2100, - 0x7B92, 0x2161, - 0x7B77, 0x21C2, - 0x7B5D, 0x2223, - 0x7B42, 0x2284, - 0x7B26, 0x22E5, - 0x7B0B, 0x2345, - 0x7AEF, 0x23A6, - 0x7AD3, 0x2407, - 0x7AB6, 0x2467, - 0x7A9A, 0x24C7, - 0x7A7D, 0x2528, - 0x7A5F, 0x2588, - 0x7A42, 0x25E8, - 0x7A24, 0x2648, - 0x7A05, 0x26A8, - 0x79E7, 0x2707, - 0x79C8, 0x2767, - 0x79A9, 0x27C7, - 0x798A, 0x2826, - 0x796A, 0x2886, - 0x794A, 0x28E5, - 0x792A, 0x2944, - 0x7909, 0x29A3, - 0x78E8, 0x2A02, - 0x78C7, 0x2A61, - 0x78A6, 0x2AC0, - 0x7884, 0x2B1F, - 0x7862, 0x2B7D, - 0x7840, 0x2BDC, - 0x781D, 0x2C3A, - 0x77FA, 0x2C98, - 0x77D7, 0x2CF7, - 0x77B4, 0x2D55, - 0x7790, 0x2DB3, - 0x776C, 0x2E11, - 0x7747, 0x2E6E, - 0x7723, 0x2ECC, - 0x76FE, 0x2F29, - 0x76D9, 0x2F87, - 0x76B3, 0x2FE4, - 0x768E, 0x3041, - 0x7668, 0x309E, - 0x7641, 0x30FB, - 0x761B, 0x3158, - 0x75F4, 0x31B5, - 0x75CC, 0x3211, - 0x75A5, 0x326E, - 0x757D, 0x32CA, - 0x7555, 0x3326, - 0x752D, 0x3382, - 0x7504, 0x33DE, - 0x74DB, 0x343A, - 0x74B2, 0x3496, - 0x7489, 0x34F2, - 0x745F, 0x354D, - 0x7435, 0x35A8, - 0x740B, 0x3604, - 0x73E0, 0x365F, - 0x73B5, 0x36BA, - 0x738A, 0x3714, - 0x735F, 0x376F, - 0x7333, 0x37CA, - 0x7307, 0x3824, - 0x72DB, 0x387E, - 0x72AF, 0x38D8, - 0x7282, 0x3932, - 0x7255, 0x398C, - 0x7227, 0x39E6, - 0x71FA, 0x3A40, - 0x71CC, 0x3A99, - 0x719E, 0x3AF2, - 0x716F, 0x3B4C, - 0x7141, 0x3BA5, - 0x7112, 0x3BFD, - 0x70E2, 0x3C56, - 0x70B3, 0x3CAF, - 0x7083, 0x3D07, - 0x7053, 0x3D60, - 0x7023, 0x3DB8, - 0x6FF2, 0x3E10, - 0x6FC1, 0x3E68, - 0x6F90, 0x3EBF, - 0x6F5F, 0x3F17, - 0x6F2D, 0x3F6E, - 0x6EFB, 0x3FC5, - 0x6EC9, 0x401D, - 0x6E96, 0x4073, - 0x6E63, 0x40CA, - 0x6E30, 0x4121, - 0x6DFD, 0x4177, - 0x6DCA, 0x41CE, - 0x6D96, 0x4224, - 0x6D62, 0x427A, - 0x6D2D, 0x42D0, - 0x6CF9, 0x4325, - 0x6CC4, 0x437B, - 0x6C8F, 0x43D0, - 0x6C59, 0x4425, - 0x6C24, 0x447A, - 0x6BEE, 0x44CF, - 0x6BB8, 0x4524, - 0x6B81, 0x4578, - 0x6B4A, 0x45CD, - 0x6B13, 0x4621, - 0x6ADC, 0x4675, - 0x6AA5, 0x46C9, - 0x6A6D, 0x471C, - 0x6A35, 0x4770, - 0x69FD, 0x47C3, - 0x69C4, 0x4816, - 0x698C, 0x4869, - 0x6953, 0x48BC, - 0x6919, 0x490F, - 0x68E0, 0x4961, - 0x68A6, 0x49B4, - 0x686C, 0x4A06, - 0x6832, 0x4A58, - 0x67F7, 0x4AA9, - 0x67BD, 0x4AFB, - 0x6782, 0x4B4C, - 0x6746, 0x4B9E, - 0x670B, 0x4BEF, - 0x66CF, 0x4C3F, - 0x6693, 0x4C90, - 0x6657, 0x4CE1, - 0x661A, 0x4D31, - 0x65DD, 0x4D81, - 0x65A0, 0x4DD1, - 0x6563, 0x4E21, - 0x6526, 0x4E70, - 0x64E8, 0x4EBF, - 0x64AA, 0x4F0F, - 0x646C, 0x4F5E, - 0x642D, 0x4FAC, - 0x63EF, 0x4FFB, - 0x63B0, 0x5049, - 0x6371, 0x5097, - 0x6331, 0x50E5, - 0x62F2, 0x5133, - 0x62B2, 0x5181, - 0x6271, 0x51CE, - 0x6231, 0x521C, - 0x61F1, 0x5269, - 0x61B0, 0x52B5, - 0x616F, 0x5302, - 0x612D, 0x534E, - 0x60EC, 0x539B, - 0x60AA, 0x53E7, - 0x6068, 0x5433, - 0x6026, 0x547E, - 0x5FE3, 0x54CA, - 0x5FA0, 0x5515, - 0x5F5E, 0x5560, - 0x5F1A, 0x55AB, - 0x5ED7, 0x55F5, - 0x5E93, 0x5640, - 0x5E50, 0x568A, - 0x5E0B, 0x56D4, - 0x5DC7, 0x571D, - 0x5D83, 0x5767, - 0x5D3E, 0x57B0, - 0x5CF9, 0x57F9, - 0x5CB4, 0x5842, - 0x5C6E, 0x588B, - 0x5C29, 0x58D4, - 0x5BE3, 0x591C, - 0x5B9D, 0x5964, - 0x5B56, 0x59AC, - 0x5B10, 0x59F3, - 0x5AC9, 0x5A3B, - 0x5A82, 0x5A82, - 0x5A3B, 0x5AC9, - 0x59F3, 0x5B10, - 0x59AC, 0x5B56, - 0x5964, 0x5B9D, - 0x591C, 0x5BE3, - 0x58D4, 0x5C29, - 0x588B, 0x5C6E, - 0x5842, 0x5CB4, - 0x57F9, 0x5CF9, - 0x57B0, 0x5D3E, - 0x5767, 0x5D83, - 0x571D, 0x5DC7, - 0x56D4, 0x5E0B, - 0x568A, 0x5E50, - 0x5640, 0x5E93, - 0x55F5, 0x5ED7, - 0x55AB, 0x5F1A, - 0x5560, 0x5F5E, - 0x5515, 0x5FA0, - 0x54CA, 0x5FE3, - 0x547E, 0x6026, - 0x5433, 0x6068, - 0x53E7, 0x60AA, - 0x539B, 0x60EC, - 0x534E, 0x612D, - 0x5302, 0x616F, - 0x52B5, 0x61B0, - 0x5269, 0x61F1, - 0x521C, 0x6231, - 0x51CE, 0x6271, - 0x5181, 0x62B2, - 0x5133, 0x62F2, - 0x50E5, 0x6331, - 0x5097, 0x6371, - 0x5049, 0x63B0, - 0x4FFB, 0x63EF, - 0x4FAC, 0x642D, - 0x4F5E, 0x646C, - 0x4F0F, 0x64AA, - 0x4EBF, 0x64E8, - 0x4E70, 0x6526, - 0x4E21, 0x6563, - 0x4DD1, 0x65A0, - 0x4D81, 0x65DD, - 0x4D31, 0x661A, - 0x4CE1, 0x6657, - 0x4C90, 0x6693, - 0x4C3F, 0x66CF, - 0x4BEF, 0x670B, - 0x4B9E, 0x6746, - 0x4B4C, 0x6782, - 0x4AFB, 0x67BD, - 0x4AA9, 0x67F7, - 0x4A58, 0x6832, - 0x4A06, 0x686C, - 0x49B4, 0x68A6, - 0x4961, 0x68E0, - 0x490F, 0x6919, - 0x48BC, 0x6953, - 0x4869, 0x698C, - 0x4816, 0x69C4, - 0x47C3, 0x69FD, - 0x4770, 0x6A35, - 0x471C, 0x6A6D, - 0x46C9, 0x6AA5, - 0x4675, 0x6ADC, - 0x4621, 0x6B13, - 0x45CD, 0x6B4A, - 0x4578, 0x6B81, - 0x4524, 0x6BB8, - 0x44CF, 0x6BEE, - 0x447A, 0x6C24, - 0x4425, 0x6C59, - 0x43D0, 0x6C8F, - 0x437B, 0x6CC4, - 0x4325, 0x6CF9, - 0x42D0, 0x6D2D, - 0x427A, 0x6D62, - 0x4224, 0x6D96, - 0x41CE, 0x6DCA, - 0x4177, 0x6DFD, - 0x4121, 0x6E30, - 0x40CA, 0x6E63, - 0x4073, 0x6E96, - 0x401D, 0x6EC9, - 0x3FC5, 0x6EFB, - 0x3F6E, 0x6F2D, - 0x3F17, 0x6F5F, - 0x3EBF, 0x6F90, - 0x3E68, 0x6FC1, - 0x3E10, 0x6FF2, - 0x3DB8, 0x7023, - 0x3D60, 0x7053, - 0x3D07, 0x7083, - 0x3CAF, 0x70B3, - 0x3C56, 0x70E2, - 0x3BFD, 0x7112, - 0x3BA5, 0x7141, - 0x3B4C, 0x716F, - 0x3AF2, 0x719E, - 0x3A99, 0x71CC, - 0x3A40, 0x71FA, - 0x39E6, 0x7227, - 0x398C, 0x7255, - 0x3932, 0x7282, - 0x38D8, 0x72AF, - 0x387E, 0x72DB, - 0x3824, 0x7307, - 0x37CA, 0x7333, - 0x376F, 0x735F, - 0x3714, 0x738A, - 0x36BA, 0x73B5, - 0x365F, 0x73E0, - 0x3604, 0x740B, - 0x35A8, 0x7435, - 0x354D, 0x745F, - 0x34F2, 0x7489, - 0x3496, 0x74B2, - 0x343A, 0x74DB, - 0x33DE, 0x7504, - 0x3382, 0x752D, - 0x3326, 0x7555, - 0x32CA, 0x757D, - 0x326E, 0x75A5, - 0x3211, 0x75CC, - 0x31B5, 0x75F4, - 0x3158, 0x761B, - 0x30FB, 0x7641, - 0x309E, 0x7668, - 0x3041, 0x768E, - 0x2FE4, 0x76B3, - 0x2F87, 0x76D9, - 0x2F29, 0x76FE, - 0x2ECC, 0x7723, - 0x2E6E, 0x7747, - 0x2E11, 0x776C, - 0x2DB3, 0x7790, - 0x2D55, 0x77B4, - 0x2CF7, 0x77D7, - 0x2C98, 0x77FA, - 0x2C3A, 0x781D, - 0x2BDC, 0x7840, - 0x2B7D, 0x7862, - 0x2B1F, 0x7884, - 0x2AC0, 0x78A6, - 0x2A61, 0x78C7, - 0x2A02, 0x78E8, - 0x29A3, 0x7909, - 0x2944, 0x792A, - 0x28E5, 0x794A, - 0x2886, 0x796A, - 0x2826, 0x798A, - 0x27C7, 0x79A9, - 0x2767, 0x79C8, - 0x2707, 0x79E7, - 0x26A8, 0x7A05, - 0x2648, 0x7A24, - 0x25E8, 0x7A42, - 0x2588, 0x7A5F, - 0x2528, 0x7A7D, - 0x24C7, 0x7A9A, - 0x2467, 0x7AB6, - 0x2407, 0x7AD3, - 0x23A6, 0x7AEF, - 0x2345, 0x7B0B, - 0x22E5, 0x7B26, - 0x2284, 0x7B42, - 0x2223, 0x7B5D, - 0x21C2, 0x7B77, - 0x2161, 0x7B92, - 0x2100, 0x7BAC, - 0x209F, 0x7BC5, - 0x203E, 0x7BDF, - 0x1FDC, 0x7BF8, - 0x1F7B, 0x7C11, - 0x1F19, 0x7C29, - 0x1EB8, 0x7C42, - 0x1E56, 0x7C5A, - 0x1DF5, 0x7C71, - 0x1D93, 0x7C89, - 0x1D31, 0x7CA0, - 0x1CCF, 0x7CB7, - 0x1C6D, 0x7CCD, - 0x1C0B, 0x7CE3, - 0x1BA9, 0x7CF9, - 0x1B47, 0x7D0F, - 0x1AE4, 0x7D24, - 0x1A82, 0x7D39, - 0x1A20, 0x7D4E, - 0x19BD, 0x7D62, - 0x195B, 0x7D76, - 0x18F8, 0x7D8A, - 0x1896, 0x7D9D, - 0x1833, 0x7DB0, - 0x17D0, 0x7DC3, - 0x176D, 0x7DD6, - 0x170A, 0x7DE8, - 0x16A8, 0x7DFA, - 0x1645, 0x7E0C, - 0x15E2, 0x7E1D, - 0x157F, 0x7E2E, - 0x151B, 0x7E3F, - 0x14B8, 0x7E4F, - 0x1455, 0x7E5F, - 0x13F2, 0x7E6F, - 0x138E, 0x7E7F, - 0x132B, 0x7E8E, - 0x12C8, 0x7E9D, - 0x1264, 0x7EAB, - 0x1201, 0x7EBA, - 0x119D, 0x7EC8, - 0x1139, 0x7ED5, - 0x10D6, 0x7EE3, - 0x1072, 0x7EF0, - 0x100E, 0x7EFD, - 0x0FAB, 0x7F09, - 0x0F47, 0x7F15, - 0x0EE3, 0x7F21, - 0x0E7F, 0x7F2D, - 0x0E1B, 0x7F38, - 0x0DB7, 0x7F43, - 0x0D53, 0x7F4D, - 0x0CEF, 0x7F58, - 0x0C8B, 0x7F62, - 0x0C27, 0x7F6B, - 0x0BC3, 0x7F75, - 0x0B5F, 0x7F7E, - 0x0AFB, 0x7F87, - 0x0A97, 0x7F8F, - 0x0A33, 0x7F97, - 0x09CE, 0x7F9F, - 0x096A, 0x7FA7, - 0x0906, 0x7FAE, - 0x08A2, 0x7FB5, - 0x083D, 0x7FBC, - 0x07D9, 0x7FC2, - 0x0775, 0x7FC8, - 0x0710, 0x7FCE, - 0x06AC, 0x7FD3, - 0x0647, 0x7FD8, - 0x05E3, 0x7FDD, - 0x057F, 0x7FE1, - 0x051A, 0x7FE5, - 0x04B6, 0x7FE9, - 0x0451, 0x7FED, - 0x03ED, 0x7FF0, - 0x0388, 0x7FF3, - 0x0324, 0x7FF6, - 0x02BF, 0x7FF8, - 0x025B, 0x7FFA, - 0x01F6, 0x7FFC, - 0x0192, 0x7FFD, - 0x012D, 0x7FFE, - 0x00C9, 0x7FFF, - 0x0064, 0x7FFF, - 0x0000, 0x7FFF, - 0xFF9B, 0x7FFF, - 0xFF36, 0x7FFF, - 0xFED2, 0x7FFE, - 0xFE6D, 0x7FFD, - 0xFE09, 0x7FFC, - 0xFDA4, 0x7FFA, - 0xFD40, 0x7FF8, - 0xFCDB, 0x7FF6, - 0xFC77, 0x7FF3, - 0xFC12, 0x7FF0, - 0xFBAE, 0x7FED, - 0xFB49, 0x7FE9, - 0xFAE5, 0x7FE5, - 0xFA80, 0x7FE1, - 0xFA1C, 0x7FDD, - 0xF9B8, 0x7FD8, - 0xF953, 0x7FD3, - 0xF8EF, 0x7FCE, - 0xF88A, 0x7FC8, - 0xF826, 0x7FC2, - 0xF7C2, 0x7FBC, - 0xF75D, 0x7FB5, - 0xF6F9, 0x7FAE, - 0xF695, 0x7FA7, - 0xF631, 0x7F9F, - 0xF5CC, 0x7F97, - 0xF568, 0x7F8F, - 0xF504, 0x7F87, - 0xF4A0, 0x7F7E, - 0xF43C, 0x7F75, - 0xF3D8, 0x7F6B, - 0xF374, 0x7F62, - 0xF310, 0x7F58, - 0xF2AC, 0x7F4D, - 0xF248, 0x7F43, - 0xF1E4, 0x7F38, - 0xF180, 0x7F2D, - 0xF11C, 0x7F21, - 0xF0B8, 0x7F15, - 0xF054, 0x7F09, - 0xEFF1, 0x7EFD, - 0xEF8D, 0x7EF0, - 0xEF29, 0x7EE3, - 0xEEC6, 0x7ED5, - 0xEE62, 0x7EC8, - 0xEDFE, 0x7EBA, - 0xED9B, 0x7EAB, - 0xED37, 0x7E9D, - 0xECD4, 0x7E8E, - 0xEC71, 0x7E7F, - 0xEC0D, 0x7E6F, - 0xEBAA, 0x7E5F, - 0xEB47, 0x7E4F, - 0xEAE4, 0x7E3F, - 0xEA80, 0x7E2E, - 0xEA1D, 0x7E1D, - 0xE9BA, 0x7E0C, - 0xE957, 0x7DFA, - 0xE8F5, 0x7DE8, - 0xE892, 0x7DD6, - 0xE82F, 0x7DC3, - 0xE7CC, 0x7DB0, - 0xE769, 0x7D9D, - 0xE707, 0x7D8A, - 0xE6A4, 0x7D76, - 0xE642, 0x7D62, - 0xE5DF, 0x7D4E, - 0xE57D, 0x7D39, - 0xE51B, 0x7D24, - 0xE4B8, 0x7D0F, - 0xE456, 0x7CF9, - 0xE3F4, 0x7CE3, - 0xE392, 0x7CCD, - 0xE330, 0x7CB7, - 0xE2CE, 0x7CA0, - 0xE26C, 0x7C89, - 0xE20A, 0x7C71, - 0xE1A9, 0x7C5A, - 0xE147, 0x7C42, - 0xE0E6, 0x7C29, - 0xE084, 0x7C11, - 0xE023, 0x7BF8, - 0xDFC1, 0x7BDF, - 0xDF60, 0x7BC5, - 0xDEFF, 0x7BAC, - 0xDE9E, 0x7B92, - 0xDE3D, 0x7B77, - 0xDDDC, 0x7B5D, - 0xDD7B, 0x7B42, - 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0x8068, 0xF5CC, - 0x8070, 0xF568, - 0x8078, 0xF504, - 0x8081, 0xF4A0, - 0x808A, 0xF43C, - 0x8094, 0xF3D8, - 0x809D, 0xF374, - 0x80A7, 0xF310, - 0x80B2, 0xF2AC, - 0x80BC, 0xF248, - 0x80C7, 0xF1E4, - 0x80D2, 0xF180, - 0x80DE, 0xF11C, - 0x80EA, 0xF0B8, - 0x80F6, 0xF054, - 0x8102, 0xEFF1, - 0x810F, 0xEF8D, - 0x811C, 0xEF29, - 0x812A, 0xEEC6, - 0x8137, 0xEE62, - 0x8145, 0xEDFE, - 0x8154, 0xED9B, - 0x8162, 0xED37, - 0x8171, 0xECD4, - 0x8180, 0xEC71, - 0x8190, 0xEC0D, - 0x81A0, 0xEBAA, - 0x81B0, 0xEB47, - 0x81C0, 0xEAE4, - 0x81D1, 0xEA80, - 0x81E2, 0xEA1D, - 0x81F3, 0xE9BA, - 0x8205, 0xE957, - 0x8217, 0xE8F5, - 0x8229, 0xE892, - 0x823C, 0xE82F, - 0x824F, 0xE7CC, - 0x8262, 0xE769, - 0x8275, 0xE707, - 0x8289, 0xE6A4, - 0x829D, 0xE642, - 0x82B1, 0xE5DF, - 0x82C6, 0xE57D, - 0x82DB, 0xE51B, - 0x82F0, 0xE4B8, - 0x8306, 0xE456, - 0x831C, 0xE3F4, - 0x8332, 0xE392, - 0x8348, 0xE330, - 0x835F, 0xE2CE, - 0x8376, 0xE26C, - 0x838E, 0xE20A, - 0x83A5, 0xE1A9, - 0x83BD, 0xE147, - 0x83D6, 0xE0E6, - 0x83EE, 0xE084, - 0x8407, 0xE023, - 0x8420, 0xDFC1, - 0x843A, 0xDF60, - 0x8453, 0xDEFF, - 0x846D, 0xDE9E, - 0x8488, 0xDE3D, - 0x84A2, 0xDDDC, - 0x84BD, 0xDD7B, - 0x84D9, 0xDD1A, - 0x84F4, 0xDCBA, - 0x8510, 0xDC59, - 0x852C, 0xDBF8, - 0x8549, 0xDB98, - 0x8565, 0xDB38, - 0x8582, 0xDAD7, - 0x85A0, 0xDA77, - 0x85BD, 0xDA17, - 0x85DB, 0xD9B7, - 0x85FA, 0xD957, - 0x8618, 0xD8F8, - 0x8637, 0xD898, - 0x8656, 0xD838, - 0x8675, 0xD7D9, - 0x8695, 0xD779, - 0x86B5, 0xD71A, - 0x86D5, 0xD6BB, - 0x86F6, 0xD65C, - 0x8717, 0xD5FD, - 0x8738, 0xD59E, - 0x8759, 0xD53F, - 0x877B, 0xD4E0, - 0x879D, 0xD482, - 0x87BF, 0xD423, - 0x87E2, 0xD3C5, - 0x8805, 0xD367, - 0x8828, 0xD308, - 0x884B, 0xD2AA, - 0x886F, 0xD24C, - 0x8893, 0xD1EE, - 0x88B8, 0xD191, - 0x88DC, 0xD133, - 0x8901, 0xD0D6, - 0x8926, 0xD078, - 0x894C, 0xD01B, - 0x8971, 0xCFBE, - 0x8997, 0xCF61, - 0x89BE, 0xCF04, - 0x89E4, 0xCEA7, - 0x8A0B, 0xCE4A, - 0x8A33, 0xCDEE, - 0x8A5A, 0xCD91, - 0x8A82, 0xCD35, - 0x8AAA, 0xCCD9, - 0x8AD2, 0xCC7D, - 0x8AFB, 0xCC21, - 0x8B24, 0xCBC5, - 0x8B4D, 0xCB69, - 0x8B76, 0xCB0D, - 0x8BA0, 0xCAB2, - 0x8BCA, 0xCA57, - 0x8BF4, 0xC9FB, - 0x8C1F, 0xC9A0, - 0x8C4A, 0xC945, - 0x8C75, 0xC8EB, - 0x8CA0, 0xC890, - 0x8CCC, 0xC835, - 0x8CF8, 0xC7DB, - 0x8D24, 0xC781, - 0x8D50, 0xC727, - 0x8D7D, 0xC6CD, - 0x8DAA, 0xC673, - 0x8DD8, 0xC619, - 0x8E05, 0xC5BF, - 0x8E33, 0xC566, - 0x8E61, 0xC50D, - 0x8E90, 0xC4B3, - 0x8EBE, 0xC45A, - 0x8EED, 0xC402, - 0x8F1D, 0xC3A9, - 0x8F4C, 0xC350, - 0x8F7C, 0xC2F8, - 0x8FAC, 0xC29F, - 0x8FDC, 0xC247, - 0x900D, 0xC1EF, - 0x903E, 0xC197, - 0x906F, 0xC140, - 0x90A0, 0xC0E8, - 0x90D2, 0xC091, - 0x9104, 0xC03A, - 0x9136, 0xBFE2, - 0x9169, 0xBF8C, - 0x919C, 0xBF35, - 0x91CF, 0xBEDE, - 0x9202, 0xBE88, - 0x9235, 0xBE31, - 0x9269, 0xBDDB, - 0x929D, 0xBD85, - 0x92D2, 0xBD2F, - 0x9306, 0xBCDA, - 0x933B, 0xBC84, - 0x9370, 0xBC2F, - 0x93A6, 0xBBDA, - 0x93DB, 0xBB85, - 0x9411, 0xBB30, - 0x9447, 0xBADB, - 0x947E, 0xBA87, - 0x94B5, 0xBA32, - 0x94EC, 0xB9DE, - 0x9523, 0xB98A, - 0x955A, 0xB936, - 0x9592, 0xB8E3, - 0x95CA, 0xB88F, - 0x9602, 0xB83C, - 0x963B, 0xB7E9, - 0x9673, 0xB796, - 0x96AC, 0xB743, - 0x96E6, 0xB6F0, - 0x971F, 0xB69E, - 0x9759, 0xB64B, - 0x9793, 0xB5F9, - 0x97CD, 0xB5A7, - 0x9808, 0xB556, - 0x9842, 0xB504, - 0x987D, 0xB4B3, - 0x98B9, 0xB461, - 0x98F4, 0xB410, - 0x9930, 0xB3C0, - 0x996C, 0xB36F, - 0x99A8, 0xB31E, - 0x99E5, 0xB2CE, - 0x9A22, 0xB27E, - 0x9A5F, 0xB22E, - 0x9A9C, 0xB1DE, - 0x9AD9, 0xB18F, - 0x9B17, 0xB140, - 0x9B55, 0xB0F0, - 0x9B93, 0xB0A1, - 0x9BD2, 0xB053, - 0x9C10, 0xB004, - 0x9C4F, 0xAFB6, - 0x9C8E, 0xAF68, - 0x9CCE, 0xAF1A, - 0x9D0D, 0xAECC, - 0x9D4D, 0xAE7E, - 0x9D8E, 0xAE31, - 0x9DCE, 0xADE3, - 0x9E0E, 0xAD96, - 0x9E4F, 0xAD4A, - 0x9E90, 0xACFD, - 0x9ED2, 0xACB1, - 0x9F13, 0xAC64, - 0x9F55, 0xAC18, - 0x9F97, 0xABCC, - 0x9FD9, 0xAB81, - 0xA01C, 0xAB35, - 0xA05F, 0xAAEA, - 0xA0A1, 0xAA9F, - 0xA0E5, 0xAA54, - 0xA128, 0xAA0A, - 0xA16C, 0xA9BF, - 0xA1AF, 0xA975, - 0xA1F4, 0xA92B, - 0xA238, 0xA8E2, - 0xA27C, 0xA898, - 0xA2C1, 0xA84F, - 0xA306, 0xA806, - 0xA34B, 0xA7BD, - 0xA391, 0xA774, - 0xA3D6, 0xA72B, - 0xA41C, 0xA6E3, - 0xA462, 0xA69B, - 0xA4A9, 0xA653, - 0xA4EF, 0xA60C, - 0xA536, 0xA5C4, - 0xA57D, 0xA57D, - 0xA5C4, 0xA536, - 0xA60C, 0xA4EF, - 0xA653, 0xA4A9, - 0xA69B, 0xA462, - 0xA6E3, 0xA41C, - 0xA72B, 0xA3D6, - 0xA774, 0xA391, - 0xA7BD, 0xA34B, - 0xA806, 0xA306, - 0xA84F, 0xA2C1, - 0xA898, 0xA27C, - 0xA8E2, 0xA238, - 0xA92B, 0xA1F4, - 0xA975, 0xA1AF, - 0xA9BF, 0xA16C, - 0xAA0A, 0xA128, - 0xAA54, 0xA0E5, - 0xAA9F, 0xA0A1, - 0xAAEA, 0xA05F, - 0xAB35, 0xA01C, - 0xAB81, 0x9FD9, - 0xABCC, 0x9F97, - 0xAC18, 0x9F55, - 0xAC64, 0x9F13, - 0xACB1, 0x9ED2, - 0xACFD, 0x9E90, - 0xAD4A, 0x9E4F, - 0xAD96, 0x9E0E, - 0xADE3, 0x9DCE, - 0xAE31, 0x9D8E, - 0xAE7E, 0x9D4D, - 0xAECC, 0x9D0D, - 0xAF1A, 0x9CCE, - 0xAF68, 0x9C8E, - 0xAFB6, 0x9C4F, - 0xB004, 0x9C10, - 0xB053, 0x9BD2, - 0xB0A1, 0x9B93, - 0xB0F0, 0x9B55, - 0xB140, 0x9B17, - 0xB18F, 0x9AD9, - 0xB1DE, 0x9A9C, - 0xB22E, 0x9A5F, - 0xB27E, 0x9A22, - 0xB2CE, 0x99E5, - 0xB31E, 0x99A8, - 0xB36F, 0x996C, - 0xB3C0, 0x9930, - 0xB410, 0x98F4, - 0xB461, 0x98B9, - 0xB4B3, 0x987D, - 0xB504, 0x9842, - 0xB556, 0x9808, - 0xB5A7, 0x97CD, - 0xB5F9, 0x9793, - 0xB64B, 0x9759, - 0xB69E, 0x971F, - 0xB6F0, 0x96E6, - 0xB743, 0x96AC, - 0xB796, 0x9673, - 0xB7E9, 0x963B, - 0xB83C, 0x9602, - 0xB88F, 0x95CA, - 0xB8E3, 0x9592, - 0xB936, 0x955A, - 0xB98A, 0x9523, - 0xB9DE, 0x94EC, - 0xBA32, 0x94B5, - 0xBA87, 0x947E, - 0xBADB, 0x9447, - 0xBB30, 0x9411, - 0xBB85, 0x93DB, - 0xBBDA, 0x93A6, - 0xBC2F, 0x9370, - 0xBC84, 0x933B, - 0xBCDA, 0x9306, - 0xBD2F, 0x92D2, - 0xBD85, 0x929D, - 0xBDDB, 0x9269, - 0xBE31, 0x9235, - 0xBE88, 0x9202, - 0xBEDE, 0x91CF, - 0xBF35, 0x919C, - 0xBF8C, 0x9169, - 0xBFE2, 0x9136, - 0xC03A, 0x9104, - 0xC091, 0x90D2, - 0xC0E8, 0x90A0, - 0xC140, 0x906F, - 0xC197, 0x903E, - 0xC1EF, 0x900D, - 0xC247, 0x8FDC, - 0xC29F, 0x8FAC, - 0xC2F8, 0x8F7C, - 0xC350, 0x8F4C, - 0xC3A9, 0x8F1D, - 0xC402, 0x8EED, - 0xC45A, 0x8EBE, - 0xC4B3, 0x8E90, - 0xC50D, 0x8E61, - 0xC566, 0x8E33, - 0xC5BF, 0x8E05, - 0xC619, 0x8DD8, - 0xC673, 0x8DAA, - 0xC6CD, 0x8D7D, - 0xC727, 0x8D50, - 0xC781, 0x8D24, - 0xC7DB, 0x8CF8, - 0xC835, 0x8CCC, - 0xC890, 0x8CA0, - 0xC8EB, 0x8C75, - 0xC945, 0x8C4A, - 0xC9A0, 0x8C1F, - 0xC9FB, 0x8BF4, - 0xCA57, 0x8BCA, - 0xCAB2, 0x8BA0, - 0xCB0D, 0x8B76, - 0xCB69, 0x8B4D, - 0xCBC5, 0x8B24, - 0xCC21, 0x8AFB, - 0xCC7D, 0x8AD2, - 0xCCD9, 0x8AAA, - 0xCD35, 0x8A82, - 0xCD91, 0x8A5A, - 0xCDEE, 0x8A33, - 0xCE4A, 0x8A0B, - 0xCEA7, 0x89E4, - 0xCF04, 0x89BE, - 0xCF61, 0x8997, - 0xCFBE, 0x8971, - 0xD01B, 0x894C, - 0xD078, 0x8926, - 0xD0D6, 0x8901, - 0xD133, 0x88DC, - 0xD191, 0x88B8, - 0xD1EE, 0x8893, - 0xD24C, 0x886F, - 0xD2AA, 0x884B, - 0xD308, 0x8828, - 0xD367, 0x8805, - 0xD3C5, 0x87E2, - 0xD423, 0x87BF, - 0xD482, 0x879D, - 0xD4E0, 0x877B, - 0xD53F, 0x8759, - 0xD59E, 0x8738, - 0xD5FD, 0x8717, - 0xD65C, 0x86F6, - 0xD6BB, 0x86D5, - 0xD71A, 0x86B5, - 0xD779, 0x8695, - 0xD7D9, 0x8675, - 0xD838, 0x8656, - 0xD898, 0x8637, - 0xD8F8, 0x8618, - 0xD957, 0x85FA, - 0xD9B7, 0x85DB, - 0xDA17, 0x85BD, - 0xDA77, 0x85A0, - 0xDAD7, 0x8582, - 0xDB38, 0x8565, - 0xDB98, 0x8549, - 0xDBF8, 0x852C, - 0xDC59, 0x8510, - 0xDCBA, 0x84F4, - 0xDD1A, 0x84D9, - 0xDD7B, 0x84BD, - 0xDDDC, 0x84A2, - 0xDE3D, 0x8488, - 0xDE9E, 0x846D, - 0xDEFF, 0x8453, - 0xDF60, 0x843A, - 0xDFC1, 0x8420, - 0xE023, 0x8407, - 0xE084, 0x83EE, - 0xE0E6, 0x83D6, - 0xE147, 0x83BD, - 0xE1A9, 0x83A5, - 0xE20A, 0x838E, - 0xE26C, 0x8376, - 0xE2CE, 0x835F, - 0xE330, 0x8348, - 0xE392, 0x8332, - 0xE3F4, 0x831C, - 0xE456, 0x8306, - 0xE4B8, 0x82F0, - 0xE51B, 0x82DB, - 0xE57D, 0x82C6, - 0xE5DF, 0x82B1, - 0xE642, 0x829D, - 0xE6A4, 0x8289, - 0xE707, 0x8275, - 0xE769, 0x8262, - 0xE7CC, 0x824F, - 0xE82F, 0x823C, - 0xE892, 0x8229, - 0xE8F5, 0x8217, - 0xE957, 0x8205, - 0xE9BA, 0x81F3, - 0xEA1D, 0x81E2, - 0xEA80, 0x81D1, - 0xEAE4, 0x81C0, - 0xEB47, 0x81B0, - 0xEBAA, 0x81A0, - 0xEC0D, 0x8190, - 0xEC71, 0x8180, - 0xECD4, 0x8171, - 0xED37, 0x8162, - 0xED9B, 0x8154, - 0xEDFE, 0x8145, - 0xEE62, 0x8137, - 0xEEC6, 0x812A, - 0xEF29, 0x811C, - 0xEF8D, 0x810F, - 0xEFF1, 0x8102, - 0xF054, 0x80F6, - 0xF0B8, 0x80EA, - 0xF11C, 0x80DE, - 0xF180, 0x80D2, - 0xF1E4, 0x80C7, - 0xF248, 0x80BC, - 0xF2AC, 0x80B2, - 0xF310, 0x80A7, - 0xF374, 0x809D, - 0xF3D8, 0x8094, - 0xF43C, 0x808A, - 0xF4A0, 0x8081, - 0xF504, 0x8078, - 0xF568, 0x8070, - 0xF5CC, 0x8068, - 0xF631, 0x8060, - 0xF695, 0x8058, - 0xF6F9, 0x8051, - 0xF75D, 0x804A, - 0xF7C2, 0x8043, - 0xF826, 0x803D, - 0xF88A, 0x8037, - 0xF8EF, 0x8031, - 0xF953, 0x802C, - 0xF9B8, 0x8027, - 0xFA1C, 0x8022, - 0xFA80, 0x801E, - 0xFAE5, 0x801A, - 0xFB49, 0x8016, - 0xFBAE, 0x8012, - 0xFC12, 0x800F, - 0xFC77, 0x800C, - 0xFCDB, 0x8009, - 0xFD40, 0x8007, - 0xFDA4, 0x8005, - 0xFE09, 0x8003, - 0xFE6D, 0x8002, - 0xFED2, 0x8001, - 0xFF36, 0x8000, - 0xFF9B, 0x8000 -}; - -/** -* \par -* Example code for q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefq15[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefq15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to q15(Fixed point 1.15): -* round(twiddleCoefq15(i) * pow(2, 15)) -* -*/ -const q15_t twiddleCoef_4096_q15[6144] = -{ - 0x7FFF, 0x0000, - 0x7FFF, 0x0032, - 0x7FFF, 0x0064, - 0x7FFF, 0x0096, - 0x7FFF, 0x00C9, - 0x7FFF, 0x00FB, - 0x7FFE, 0x012D, - 0x7FFE, 0x015F, - 0x7FFD, 0x0192, - 0x7FFC, 0x01C4, - 0x7FFC, 0x01F6, - 0x7FFB, 0x0228, - 0x7FFA, 0x025B, - 0x7FF9, 0x028D, - 0x7FF8, 0x02BF, - 0x7FF7, 0x02F1, - 0x7FF6, 0x0324, - 0x7FF4, 0x0356, - 0x7FF3, 0x0388, - 0x7FF2, 0x03BA, - 0x7FF0, 0x03ED, - 0x7FEE, 0x041F, - 0x7FED, 0x0451, - 0x7FEB, 0x0483, - 0x7FE9, 0x04B6, - 0x7FE7, 0x04E8, - 0x7FE5, 0x051A, - 0x7FE3, 0x054C, - 0x7FE1, 0x057F, - 0x7FDF, 0x05B1, - 0x7FDD, 0x05E3, - 0x7FDA, 0x0615, - 0x7FD8, 0x0647, - 0x7FD6, 0x067A, - 0x7FD3, 0x06AC, - 0x7FD0, 0x06DE, - 0x7FCE, 0x0710, - 0x7FCB, 0x0742, - 0x7FC8, 0x0775, - 0x7FC5, 0x07A7, - 0x7FC2, 0x07D9, - 0x7FBF, 0x080B, - 0x7FBC, 0x083D, - 0x7FB8, 0x086F, - 0x7FB5, 0x08A2, - 0x7FB1, 0x08D4, - 0x7FAE, 0x0906, - 0x7FAA, 0x0938, - 0x7FA7, 0x096A, - 0x7FA3, 0x099C, - 0x7F9F, 0x09CE, - 0x7F9B, 0x0A00, - 0x7F97, 0x0A33, - 0x7F93, 0x0A65, - 0x7F8F, 0x0A97, - 0x7F8B, 0x0AC9, - 0x7F87, 0x0AFB, - 0x7F82, 0x0B2D, - 0x7F7E, 0x0B5F, - 0x7F79, 0x0B91, - 0x7F75, 0x0BC3, - 0x7F70, 0x0BF5, - 0x7F6B, 0x0C27, - 0x7F67, 0x0C59, - 0x7F62, 0x0C8B, - 0x7F5D, 0x0CBD, - 0x7F58, 0x0CEF, - 0x7F53, 0x0D21, - 0x7F4D, 0x0D53, - 0x7F48, 0x0D85, - 0x7F43, 0x0DB7, - 0x7F3D, 0x0DE9, - 0x7F38, 0x0E1B, - 0x7F32, 0x0E4D, - 0x7F2D, 0x0E7F, - 0x7F27, 0x0EB1, - 0x7F21, 0x0EE3, - 0x7F1B, 0x0F15, - 0x7F15, 0x0F47, - 0x7F0F, 0x0F79, - 0x7F09, 0x0FAB, - 0x7F03, 0x0FDD, - 0x7EFD, 0x100E, - 0x7EF6, 0x1040, - 0x7EF0, 0x1072, - 0x7EE9, 0x10A4, - 0x7EE3, 0x10D6, - 0x7EDC, 0x1108, - 0x7ED5, 0x1139, - 0x7ECF, 0x116B, - 0x7EC8, 0x119D, - 0x7EC1, 0x11CF, - 0x7EBA, 0x1201, - 0x7EB3, 0x1232, - 0x7EAB, 0x1264, - 0x7EA4, 0x1296, - 0x7E9D, 0x12C8, - 0x7E95, 0x12F9, - 0x7E8E, 0x132B, - 0x7E86, 0x135D, - 0x7E7F, 0x138E, - 0x7E77, 0x13C0, - 0x7E6F, 0x13F2, - 0x7E67, 0x1423, - 0x7E5F, 0x1455, - 0x7E57, 0x1487, - 0x7E4F, 0x14B8, - 0x7E47, 0x14EA, - 0x7E3F, 0x151B, - 0x7E37, 0x154D, - 0x7E2E, 0x157F, - 0x7E26, 0x15B0, - 0x7E1D, 0x15E2, - 0x7E14, 0x1613, - 0x7E0C, 0x1645, - 0x7E03, 0x1676, - 0x7DFA, 0x16A8, - 0x7DF1, 0x16D9, - 0x7DE8, 0x170A, - 0x7DDF, 0x173C, - 0x7DD6, 0x176D, - 0x7DCD, 0x179F, - 0x7DC3, 0x17D0, - 0x7DBA, 0x1802, - 0x7DB0, 0x1833, - 0x7DA7, 0x1864, - 0x7D9D, 0x1896, - 0x7D94, 0x18C7, - 0x7D8A, 0x18F8, - 0x7D80, 0x192A, - 0x7D76, 0x195B, - 0x7D6C, 0x198C, - 0x7D62, 0x19BD, - 0x7D58, 0x19EF, - 0x7D4E, 0x1A20, - 0x7D43, 0x1A51, - 0x7D39, 0x1A82, - 0x7D2F, 0x1AB3, - 0x7D24, 0x1AE4, - 0x7D19, 0x1B16, - 0x7D0F, 0x1B47, - 0x7D04, 0x1B78, - 0x7CF9, 0x1BA9, - 0x7CEE, 0x1BDA, - 0x7CE3, 0x1C0B, - 0x7CD8, 0x1C3C, - 0x7CCD, 0x1C6D, - 0x7CC2, 0x1C9E, - 0x7CB7, 0x1CCF, - 0x7CAB, 0x1D00, - 0x7CA0, 0x1D31, - 0x7C94, 0x1D62, - 0x7C89, 0x1D93, - 0x7C7D, 0x1DC4, - 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0xBFE2, 0x9136, - 0xC00E, 0x911D, - 0xC03A, 0x9104, - 0xC065, 0x90EB, - 0xC091, 0x90D2, - 0xC0BC, 0x90B9, - 0xC0E8, 0x90A0, - 0xC114, 0x9088, - 0xC140, 0x906F, - 0xC16C, 0x9056, - 0xC197, 0x903E, - 0xC1C3, 0x9025, - 0xC1EF, 0x900D, - 0xC21B, 0x8FF5, - 0xC247, 0x8FDC, - 0xC273, 0x8FC4, - 0xC29F, 0x8FAC, - 0xC2CC, 0x8F94, - 0xC2F8, 0x8F7C, - 0xC324, 0x8F64, - 0xC350, 0x8F4C, - 0xC37C, 0x8F34, - 0xC3A9, 0x8F1D, - 0xC3D5, 0x8F05, - 0xC402, 0x8EED, - 0xC42E, 0x8ED6, - 0xC45A, 0x8EBE, - 0xC487, 0x8EA7, - 0xC4B3, 0x8E90, - 0xC4E0, 0x8E79, - 0xC50D, 0x8E61, - 0xC539, 0x8E4A, - 0xC566, 0x8E33, - 0xC593, 0x8E1C, - 0xC5BF, 0x8E05, - 0xC5EC, 0x8DEE, - 0xC619, 0x8DD8, - 0xC646, 0x8DC1, - 0xC673, 0x8DAA, - 0xC6A0, 0x8D94, - 0xC6CD, 0x8D7D, - 0xC6F9, 0x8D67, - 0xC727, 0x8D50, - 0xC754, 0x8D3A, - 0xC781, 0x8D24, - 0xC7AE, 0x8D0E, - 0xC7DB, 0x8CF8, - 0xC808, 0x8CE2, - 0xC835, 0x8CCC, - 0xC863, 0x8CB6, - 0xC890, 0x8CA0, - 0xC8BD, 0x8C8A, - 0xC8EB, 0x8C75, - 0xC918, 0x8C5F, - 0xC945, 0x8C4A, - 0xC973, 0x8C34, - 0xC9A0, 0x8C1F, - 0xC9CE, 0x8C09, - 0xC9FB, 0x8BF4, - 0xCA29, 0x8BDF, - 0xCA57, 0x8BCA, - 0xCA84, 0x8BB5, - 0xCAB2, 0x8BA0, - 0xCAE0, 0x8B8B, - 0xCB0D, 0x8B76, - 0xCB3B, 0x8B61, - 0xCB69, 0x8B4D, - 0xCB97, 0x8B38, - 0xCBC5, 0x8B24, - 0xCBF3, 0x8B0F, - 0xCC21, 0x8AFB, - 0xCC4F, 0x8AE6, - 0xCC7D, 0x8AD2, - 0xCCAB, 0x8ABE, - 0xCCD9, 0x8AAA, - 0xCD07, 0x8A96, - 0xCD35, 0x8A82, - 0xCD63, 0x8A6E, - 0xCD91, 0x8A5A, - 0xCDBF, 0x8A46, - 0xCDEE, 0x8A33, - 0xCE1C, 0x8A1F, - 0xCE4A, 0x8A0B, - 0xCE79, 0x89F8, - 0xCEA7, 0x89E4, - 0xCED5, 0x89D1, - 0xCF04, 0x89BE, - 0xCF32, 0x89AB, - 0xCF61, 0x8997, - 0xCF8F, 0x8984, - 0xCFBE, 0x8971, - 0xCFEC, 0x895F, - 0xD01B, 0x894C, - 0xD04A, 0x8939, - 0xD078, 0x8926, - 0xD0A7, 0x8914, - 0xD0D6, 0x8901, - 0xD104, 0x88EF, - 0xD133, 0x88DC, - 0xD162, 0x88CA, - 0xD191, 0x88B8, - 0xD1C0, 0x88A5, - 0xD1EE, 0x8893, - 0xD21D, 0x8881, - 0xD24C, 0x886F, - 0xD27B, 0x885D, - 0xD2AA, 0x884B, - 0xD2D9, 0x883A, - 0xD308, 0x8828, - 0xD337, 0x8816, - 0xD367, 0x8805, - 0xD396, 0x87F3, - 0xD3C5, 0x87E2, - 0xD3F4, 0x87D1, - 0xD423, 0x87BF, - 0xD452, 0x87AE, - 0xD482, 0x879D, - 0xD4B1, 0x878C, - 0xD4E0, 0x877B, - 0xD510, 0x876A, - 0xD53F, 0x8759, - 0xD56E, 0x8749, - 0xD59E, 0x8738, - 0xD5CD, 0x8727, - 0xD5FD, 0x8717, - 0xD62C, 0x8706, - 0xD65C, 0x86F6, - 0xD68B, 0x86E6, - 0xD6BB, 0x86D5, - 0xD6EA, 0x86C5, - 0xD71A, 0x86B5, - 0xD74A, 0x86A5, - 0xD779, 0x8695, - 0xD7A9, 0x8685, - 0xD7D9, 0x8675, - 0xD809, 0x8666, - 0xD838, 0x8656, - 0xD868, 0x8646, - 0xD898, 0x8637, - 0xD8C8, 0x8627, - 0xD8F8, 0x8618, - 0xD927, 0x8609, - 0xD957, 0x85FA, - 0xD987, 0x85EA, - 0xD9B7, 0x85DB, - 0xD9E7, 0x85CC, - 0xDA17, 0x85BD, - 0xDA47, 0x85AF, - 0xDA77, 0x85A0, - 0xDAA7, 0x8591, - 0xDAD7, 0x8582, - 0xDB08, 0x8574, - 0xDB38, 0x8565, - 0xDB68, 0x8557, - 0xDB98, 0x8549, - 0xDBC8, 0x853A, - 0xDBF8, 0x852C, - 0xDC29, 0x851E, - 0xDC59, 0x8510, - 0xDC89, 0x8502, - 0xDCBA, 0x84F4, - 0xDCEA, 0x84E6, - 0xDD1A, 0x84D9, - 0xDD4B, 0x84CB, - 0xDD7B, 0x84BD, - 0xDDAB, 0x84B0, - 0xDDDC, 0x84A2, - 0xDE0C, 0x8495, - 0xDE3D, 0x8488, - 0xDE6D, 0x847B, - 0xDE9E, 0x846D, - 0xDECE, 0x8460, - 0xDEFF, 0x8453, - 0xDF2F, 0x8446, - 0xDF60, 0x843A, - 0xDF91, 0x842D, - 0xDFC1, 0x8420, - 0xDFF2, 0x8414, - 0xE023, 0x8407, - 0xE053, 0x83FA, - 0xE084, 0x83EE, - 0xE0B5, 0x83E2, - 0xE0E6, 0x83D6, - 0xE116, 0x83C9, - 0xE147, 0x83BD, - 0xE178, 0x83B1, - 0xE1A9, 0x83A5, - 0xE1DA, 0x8399, - 0xE20A, 0x838E, - 0xE23B, 0x8382, - 0xE26C, 0x8376, - 0xE29D, 0x836B, - 0xE2CE, 0x835F, - 0xE2FF, 0x8354, - 0xE330, 0x8348, - 0xE361, 0x833D, - 0xE392, 0x8332, - 0xE3C3, 0x8327, - 0xE3F4, 0x831C, - 0xE425, 0x8311, - 0xE456, 0x8306, - 0xE487, 0x82FB, - 0xE4B8, 0x82F0, - 0xE4E9, 0x82E6, - 0xE51B, 0x82DB, - 0xE54C, 0x82D0, - 0xE57D, 0x82C6, - 0xE5AE, 0x82BC, - 0xE5DF, 0x82B1, - 0xE610, 0x82A7, - 0xE642, 0x829D, - 0xE673, 0x8293, - 0xE6A4, 0x8289, - 0xE6D5, 0x827F, - 0xE707, 0x8275, - 0xE738, 0x826B, - 0xE769, 0x8262, - 0xE79B, 0x8258, - 0xE7CC, 0x824F, - 0xE7FD, 0x8245, - 0xE82F, 0x823C, - 0xE860, 0x8232, - 0xE892, 0x8229, - 0xE8C3, 0x8220, - 0xE8F5, 0x8217, - 0xE926, 0x820E, - 0xE957, 0x8205, - 0xE989, 0x81FC, - 0xE9BA, 0x81F3, - 0xE9EC, 0x81EB, - 0xEA1D, 0x81E2, - 0xEA4F, 0x81D9, - 0xEA80, 0x81D1, - 0xEAB2, 0x81C8, - 0xEAE4, 0x81C0, - 0xEB15, 0x81B8, - 0xEB47, 0x81B0, - 0xEB78, 0x81A8, - 0xEBAA, 0x81A0, - 0xEBDC, 0x8198, - 0xEC0D, 0x8190, - 0xEC3F, 0x8188, - 0xEC71, 0x8180, - 0xECA2, 0x8179, - 0xECD4, 0x8171, - 0xED06, 0x816A, - 0xED37, 0x8162, - 0xED69, 0x815B, - 0xED9B, 0x8154, - 0xEDCD, 0x814C, - 0xEDFE, 0x8145, - 0xEE30, 0x813E, - 0xEE62, 0x8137, - 0xEE94, 0x8130, - 0xEEC6, 0x812A, - 0xEEF7, 0x8123, - 0xEF29, 0x811C, - 0xEF5B, 0x8116, - 0xEF8D, 0x810F, - 0xEFBF, 0x8109, - 0xEFF1, 0x8102, - 0xF022, 0x80FC, - 0xF054, 0x80F6, - 0xF086, 0x80F0, - 0xF0B8, 0x80EA, - 0xF0EA, 0x80E4, - 0xF11C, 0x80DE, - 0xF14E, 0x80D8, - 0xF180, 0x80D2, - 0xF1B2, 0x80CD, - 0xF1E4, 0x80C7, - 0xF216, 0x80C2, - 0xF248, 0x80BC, - 0xF27A, 0x80B7, - 0xF2AC, 0x80B2, - 0xF2DE, 0x80AC, - 0xF310, 0x80A7, - 0xF342, 0x80A2, - 0xF374, 0x809D, - 0xF3A6, 0x8098, - 0xF3D8, 0x8094, - 0xF40A, 0x808F, - 0xF43C, 0x808A, - 0xF46E, 0x8086, - 0xF4A0, 0x8081, - 0xF4D2, 0x807D, - 0xF504, 0x8078, - 0xF536, 0x8074, - 0xF568, 0x8070, - 0xF59A, 0x806C, - 0xF5CC, 0x8068, - 0xF5FF, 0x8064, - 0xF631, 0x8060, - 0xF663, 0x805C, - 0xF695, 0x8058, - 0xF6C7, 0x8055, - 0xF6F9, 0x8051, - 0xF72B, 0x804E, - 0xF75D, 0x804A, - 0xF790, 0x8047, - 0xF7C2, 0x8043, - 0xF7F4, 0x8040, - 0xF826, 0x803D, - 0xF858, 0x803A, - 0xF88A, 0x8037, - 0xF8BD, 0x8034, - 0xF8EF, 0x8031, - 0xF921, 0x802F, - 0xF953, 0x802C, - 0xF985, 0x8029, - 0xF9B8, 0x8027, - 0xF9EA, 0x8025, - 0xFA1C, 0x8022, - 0xFA4E, 0x8020, - 0xFA80, 0x801E, - 0xFAB3, 0x801C, - 0xFAE5, 0x801A, - 0xFB17, 0x8018, - 0xFB49, 0x8016, - 0xFB7C, 0x8014, - 0xFBAE, 0x8012, - 0xFBE0, 0x8011, - 0xFC12, 0x800F, - 0xFC45, 0x800D, - 0xFC77, 0x800C, - 0xFCA9, 0x800B, - 0xFCDB, 0x8009, - 0xFD0E, 0x8008, - 0xFD40, 0x8007, - 0xFD72, 0x8006, - 0xFDA4, 0x8005, - 0xFDD7, 0x8004, - 0xFE09, 0x8003, - 0xFE3B, 0x8003, - 0xFE6D, 0x8002, - 0xFEA0, 0x8001, - 0xFED2, 0x8001, - 0xFF04, 0x8000, - 0xFF36, 0x8000, - 0xFF69, 0x8000, - 0xFF9B, 0x8000, - 0xFFCD, 0x8000 -}; - - -/** -* @} end of CFFT_CIFFT group -*/ - -/* -* @brief Q15 table for reciprocal -*/ -const q15_t ALIGN4 armRecipTableQ15[64] = { - 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, - 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, - 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, - 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, - 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, - 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, - 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, - 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, - 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, - 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, - 0x41CC, 0x4146, 0x40C2, 0x4040 -}; - -/* -* @brief Q31 table for reciprocal -*/ -const q31_t armRecipTableQ31[64] = { - 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, - 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, - 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, - 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, - 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, - 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, - 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, - 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, - 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, - 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, - 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 -}; - -const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] = -{ - //8x2, size 20 - 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 -}; - -const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] = -{ - //8x4, size 48 - 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, - 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, - 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 -}; - -const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] = -{ - //radix 8, size 56 - 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, - 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, - 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, - 368,424, 376,488, 440,496 -}; - -const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = -{ - //8x2, size 208 - 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, - 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, - 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, - 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, - 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, - 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, - 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, - 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, - 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, - 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, - 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, - 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, - 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 -}; - -const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = -{ - //8x4, size 440 - 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, - 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, - 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, - 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, - 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, - 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, - 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, - 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, - 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, - 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, - 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, - 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, - 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, - 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, - 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, - 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, - 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, - 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, - 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, - 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, - 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, - 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, - 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, - 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, - 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, - 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, - 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, - 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, - 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, - 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, - 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, - 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, - 1960,1968, 2008,2032, 1992,2016, 2024,2032 -}; - -const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = -{ - //radix 8, size 448 - 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, - 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, - 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, - 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, - 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, - 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, - 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, - 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, - 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, - 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, - 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, - 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, - 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, - 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, - 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, - 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, - 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, - 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, - 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, - 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, - 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, - 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, - 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, - 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, - 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, - 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, - 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, - 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, - 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, - 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, - 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, - 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, - 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, - 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, - 3448,3952, 3512,4016, 3576,4080 -}; - -const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] = -{ - //8x2, size 1800 - 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, - 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, - 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, - 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, - 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, - 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, - 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, - 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, - 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, - 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, - 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, - 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, - 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, - 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, - 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, - 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, - 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, - 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, - 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, - 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, - 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, - 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, - 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, - 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, - 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, - 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, - 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, - 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, - 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, - 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, - 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, - 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, - 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, - 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, - 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, - 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, - 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, - 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, - 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, - 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, - 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, - 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, - 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, - 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, - 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, - 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, - 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, - 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, - 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, - 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, - 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, - 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, - 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, - 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, - 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, - 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, - 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, - 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, - 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, - 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, - 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, - 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, - 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, - 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, - 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, - 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, - 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, - 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, - 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, - 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, - 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, - 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, - 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, - 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, - 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, - 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, - 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, - 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, - 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, - 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, - 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, - 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, - 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, - 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, - 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, - 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, - 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, - 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, - 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, - 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, - 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, - 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, - 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, - 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, - 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, - 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, - 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, - 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, - 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, - 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, - 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, - 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, - 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, - 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, - 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, - 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, - 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, - 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, - 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, - 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, - 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, - 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, - 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, - 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, - 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, - 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, - 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, - 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, - 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, - 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, - 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, - 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, - 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, - 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, - 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, - 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, - 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, - 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, - 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, - 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, - 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, - 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, - 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, - 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, - 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, - 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, - 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, - 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, - 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, - 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, - 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, - 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, - 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, - 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, - 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, - 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, - 8112,8136, 8120,8168, 8136,8160, 8152,8176 -}; - -const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] = -{ - //8x2, size 3808 - 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, - 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, - 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, - 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, - 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, - 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, - 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, - 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, - 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, - 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, - 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, - 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, - 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, - 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, - 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, - 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, - 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, - 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, - 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, - 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, - 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, - 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, - 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, - 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, - 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, - 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, - 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, - 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, - 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, - 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, - 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, - 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, - 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, - 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, - 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, - 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, - 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, - 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, - 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, - 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, - 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, - 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, - 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, - 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, - 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, - 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, - 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, - 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, - 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, - 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, - 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, - 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, - 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, - 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, - 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, - 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, - 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, - 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, - 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, - 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, - 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, - 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, - 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, - 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, - 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, - 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, - 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, - 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, - 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, - 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, - 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, - 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, - 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, - 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, - 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, - 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, - 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, - 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, - 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, - 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208, - 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624, - 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208, - 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448, - 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744, - 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, - 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, - 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, - 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, - 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, - 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, - 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, - 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, - 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, - 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, - 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, - 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, - 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, - 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, - 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, - 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, - 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, - 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, - 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, - 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, - 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, - 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, - 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, - 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, - 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, - 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, - 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, - 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, - 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, - 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, - 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, - 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, - 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, - 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, - 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, - 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, - 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, - 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, - 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, - 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, - 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, - 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240, - 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296, - 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776, - 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680, - 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280, - 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568, - 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816, - 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448, - 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352, - 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336, - 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856, - 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720, - 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392, - 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600, - 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928, - 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488, - 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432, - 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368, - 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968, - 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752, - 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472, - 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608, - 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008, - 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488, - 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544, - 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376, - 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048, - 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760, - 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584, - 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640, - 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120, - 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528, - 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624, - 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408, - 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160, - 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792, - 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664, - 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680, - 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200, - 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560, - 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736, - 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320, - 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448, - 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760, - 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464, - 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392, - 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576, - 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896, - 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688, - 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432, - 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736, - 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968, - 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376, - 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472, - 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424, - 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008, - 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536, - 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512, - 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736, - 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048, - 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728, - 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584, - 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248, - 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408, - 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112, - 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040, - 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616, - 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640, - 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664, - 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688, - 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616, - 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312, - 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336, - 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392, - 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656, - 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408, - 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192, - 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584, - 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760, - 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208, - 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816, - 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664, - 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816, - 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328, - 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296, - 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400, - 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480, - 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304, - 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912, - 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296, - 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360, - 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464, - 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440, - 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344, - 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800, - 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464, - 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968, - 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368, - 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440, - 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488, - 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528, - 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400, - 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440, - 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552, - 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056, - 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424, - 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760, - 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008, - 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408, - 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648, - 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120, - 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440, - 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656, - 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552, - 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160, - 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720, - 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760, - 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672, - 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624, - 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728, - 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736, - 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608, - 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512, - 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760, - 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296, - 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664, - 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712, - 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816, - 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824, - 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696, - 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832, - 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544, - 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584, - 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496, - 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688, - 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920, - 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344, - 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576, - 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400, - 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448, - 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696, - 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816, - 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344, - 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976, - 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416, - 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496, - 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488, - 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536, - 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592, - 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736, - 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664, - 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064, - 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464, - 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816, - 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768, - 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576, - 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592, - 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536, - 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664, - 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616, - 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704, - 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728, - 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488, - 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384, - 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560, - 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392, - 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528, - 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464, - 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, - 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, - 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, - 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, - 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, - 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, - 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, - 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, - 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, - 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, - 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928, - 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, - 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, - 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, - 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, - 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, - 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, - 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, - 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, - 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, - 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, - 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, - 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, - 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, - 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, - 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, - 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, - 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, - 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, - 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, - 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, - 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, - 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, - 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, - 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, - 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, - 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, - 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, - 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, - 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, - 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, - 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, - 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, - 16328,16352, 16360,16368 -}; - -const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] = -{ - //radix 8, size 4032 - 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, - 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, - 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, - 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, - 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, - 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, - 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, - 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, - 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, - 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, - 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, - 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, - 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, - 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, - 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, - 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, - 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, - 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, - 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, - 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, - 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, - 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, - 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, - 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, - 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, - 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, - 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, - 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, - 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, - 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, - 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, - 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, - 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, - 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, - 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, - 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, - 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, - 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, - 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, - 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, - 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, - 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, - 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, - 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, - 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, - 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, - 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, - 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, - 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, - 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, - 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, - 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, - 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, - 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, - 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, - 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, - 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, - 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, - 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, - 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, - 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, - 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, - 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, - 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, - 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, - 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, - 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, - 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, - 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, - 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, - 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, - 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, - 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, - 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, - 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, - 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, - 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, - 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, - 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, - 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, - 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15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, - 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, - 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, - 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, - 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, - 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, - 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, - 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, - 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, - 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, - 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, - 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, - 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, - 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, - 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, - 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, - 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, - 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, - 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, - 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, - 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, - 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, - 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, - 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, - 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, - 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, - 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, - 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, - 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, - 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, - 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, - 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, - 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, - 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, - 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, - 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, - 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, - 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, - 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, - 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, - 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, - 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, - 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, - 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, - 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, - 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, - 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, - 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, - 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, - 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, - 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, - 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, - 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, - 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, - 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, - 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, - 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, - 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, - 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, - 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, - 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, - 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, - 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, - 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, - 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, - 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, - 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, - 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, - 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, - 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, - 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, - 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, - 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, - 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, - 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, - 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, - 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, - 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, - 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, - 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, - 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, - 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, - 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, - 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, - 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, - 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, - 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, - 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, - 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, - 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, - 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, - 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, - 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, - 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, - 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, - 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, - 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, - 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, - 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, - 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, - 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, - 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, - 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, - 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, - 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, - 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, - 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, - 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, - 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, - 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, - 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, - 32248,32696 -}; - - -const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH] = -{ - //radix 4, size 12 - 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 -}; - -const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH] = -{ - //4x2, size 24 - 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, - 88,208, 104,176, 120,240, 152,200, 184,232 -}; - -const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH] = -{ - //radix 4, size 56 - 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, - 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, - 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 -}; - -const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH] = -{ - //4x2, size 112 - 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, - 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, - 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, - 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, - 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, - 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 -}; - -const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH] = -{ - //radix 4, size 240 - 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, - 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, - 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, - 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, - 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, - 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, - 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, - 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, - 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, - 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, - 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, - 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, - 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, - 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 -}; - -const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH] = -{ - //4x2, size 480 - 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, - 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, - 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, - 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, - 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, - 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, - 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, - 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, - 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, - 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, - 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, - 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, - 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, - 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, - 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, - 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, - 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, - 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, - 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, - 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, - 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, - 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, - 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, - 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, - 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, - 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, - 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, - 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, - 3512,3800, 3576,4056, 3704,3896, 3832,4024 -}; - -const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = -{ - //radix 4, size 992 - 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, - 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, - 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, - 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, - 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, - 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, - 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, - 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, - 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, - 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, - 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, - 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, - 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, - 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, - 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, - 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, - 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, - 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, - 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, - 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, - 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, - 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, - 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, - 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, - 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, - 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, - 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, - 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, - 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, - 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, - 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, - 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, - 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, - 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, - 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, - 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, - 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, - 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, - 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, - 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, - 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, - 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, - 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, - 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, - 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, - 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, - 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, - 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, - 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, - 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, - 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, - 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, - 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, - 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, - 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, - 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, - 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, - 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, - 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, - 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, - 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, - 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, - 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, - 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, - 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, - 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, - 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, - 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, - 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 -}; - -const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = -{ - //4x2, size 1984 - 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, - 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, - 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, - 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, - 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, - 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, - 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, - 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, - 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, - 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, - 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, - 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, - 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, - 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, - 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, - 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, - 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, - 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, - 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, - 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, - 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, - 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, - 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, - 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, - 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, - 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, - 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, - 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, - 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, - 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, - 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, - 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, - 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, - 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, - 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, - 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, - 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, - 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, - 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, - 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, - 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, - 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, - 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, - 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, - 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, - 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, - 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, - 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, - 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, - 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, - 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, - 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, - 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, - 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, - 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, - 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, - 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, - 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, - 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, - 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, - 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, - 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, - 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, - 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, - 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, - 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, - 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, - 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, - 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, - 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, - 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, - 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, - 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, - 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, - 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, - 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, - 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, - 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, - 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, - 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, - 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, - 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, - 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, - 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, - 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, - 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, - 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, - 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, - 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, - 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, - 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, - 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, - 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, - 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, - 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, - 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, - 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, - 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, - 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, - 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, - 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, - 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, - 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, - 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, - 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, - 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, - 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, - 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, - 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, - 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, - 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, - 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, - 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, - 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, - 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, - 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, - 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, - 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, - 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, - 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, - 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, - 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, - 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, - 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, - 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, - 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, - 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, - 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, - 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, - 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, - 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, - 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, - 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, - 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, - 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, - 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, - 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, - 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, - 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, - 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, - 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, - 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, - 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, - 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, - 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, - 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, - 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, - 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, - 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, - 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, - 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 -}; - -const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = -{ - //radix 4, size 4032 - 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, - 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, - 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, - 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, - 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, - 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, - 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, - 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, - 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, - 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, - 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, - 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, - 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, - 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, - 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, - 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, - 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, - 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, - 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, - 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, - 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, - 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, - 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, - 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, - 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, - 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, - 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, - 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, - 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, - 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, - 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, - 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, - 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, - 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, - 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, - 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, - 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, - 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, - 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, - 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, - 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, - 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, - 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, - 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, - 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, - 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, - 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, - 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, - 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, - 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, - 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, - 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, - 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, - 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, - 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, - 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, - 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, - 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, - 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, - 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, - 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, - 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, - 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, - 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, - 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, - 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, - 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, - 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, - 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, - 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, - 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, - 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, - 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, - 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, - 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, - 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, - 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, - 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, - 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, - 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, - 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, - 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, - 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, - 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, - 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, - 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, - 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, - 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, - 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, - 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, - 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, - 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, - 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, - 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, - 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, - 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, - 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, - 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, - 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, - 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, - 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, - 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, - 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, - 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, - 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, - 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, - 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, - 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, - 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, - 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, - 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, - 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, - 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, - 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, - 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, - 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, - 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, - 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, - 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, - 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, - 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, - 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, - 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, - 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, - 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, - 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, - 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, - 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, - 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, - 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, - 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, - 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, - 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, - 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, - 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, - 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, - 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, - 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, - 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, - 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, - 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, - 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, - 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, - 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, - 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, - 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, - 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, - 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, - 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, - 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, - 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, - 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, - 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, - 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, - 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, - 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, - 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, - 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, - 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, - 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, - 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, - 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, - 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, - 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, - 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, - 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, - 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, - 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, - 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, - 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, - 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, - 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, - 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, - 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, - 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, - 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, - 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, - 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, - 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, - 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, - 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, - 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, - 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, - 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, - 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, - 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, - 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, - 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, - 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, - 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, - 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, - 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, - 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, - 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, - 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, - 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, - 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, - 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, - 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, - 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, - 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, - 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, - 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, - 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, - 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, - 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, - 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, - 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, - 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, - 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, - 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, - 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, - 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, - 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, - 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, - 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, - 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, - 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, - 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, - 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, - 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, - 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, - 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, - 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, - 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, - 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, - 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, - 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, - 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, - 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, - 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, - 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, - 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, - 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, - 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, - 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, - 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, - 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, - 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, - 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, - 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, - 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, - 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, - 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, - 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, - 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, - 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, - 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, - 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, - 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, - 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, - 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, - 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, - 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, - 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, - 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, - 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, - 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, - 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, - 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, - 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, - 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, - 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, - 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, - 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, - 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, - 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, - 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, - 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, - 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, - 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, - 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, - 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, - 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, - 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, - 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, - 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, - 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, - 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, - 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, - 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, - 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, - 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, - 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, - 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, - 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, - 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, - 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, - 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, - 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, - 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, - 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, - 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, - 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, - 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, - 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, - 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, - 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, - 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, - 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, - 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, - 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, - 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, - 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, - 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, - 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, - 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, - 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, - 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, - 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, - 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, - 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, - 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, - 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, - 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, - 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, - 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, - 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, - 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, - 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, - 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, - 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, - 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, - 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, - 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, - 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, - 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, - 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, - 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, - 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, - 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, - 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, - 31480,32120, 31736,32632, 32248,32504 -}; - -/** -* \par -* Example code for Floating-point RFFT Twiddle factors Generation: -* \par -* 
TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).'
-* \par -* Real and Imag values are in interleaved fashion -*/ -const float32_t twiddleCoef_rfft_32[32] = { -0.0f , 1.0f , -0.195090322f , 0.98078528f , -0.382683432f , 0.923879533f , -0.555570233f , 0.831469612f , -0.707106781f , 0.707106781f , -0.831469612f , 0.555570233f , -0.923879533f , 0.382683432f , -0.98078528f , 0.195090322f , -1.0f , 0.0f , -0.98078528f , -0.195090322f , -0.923879533f , -0.382683432f , -0.831469612f , -0.555570233f , -0.707106781f , -0.707106781f , -0.555570233f , -0.831469612f , -0.382683432f , -0.923879533f , -0.195090322f , -0.98078528f -}; - -const float32_t twiddleCoef_rfft_64[64] = { -0.0f, 1.0f, -0.098017140329561f, 0.995184726672197f, -0.195090322016128f, 0.98078528040323f, -0.290284677254462f, 0.956940335732209f, -0.38268343236509f, 0.923879532511287f, -0.471396736825998f, 0.881921264348355f, -0.555570233019602f, 0.831469612302545f, -0.634393284163645f, 0.773010453362737f, -0.707106781186547f, 0.707106781186548f, -0.773010453362737f, 0.634393284163645f, -0.831469612302545f, 0.555570233019602f, -0.881921264348355f, 0.471396736825998f, -0.923879532511287f, 0.38268343236509f, -0.956940335732209f, 0.290284677254462f, -0.98078528040323f, 0.195090322016128f, -0.995184726672197f, 0.098017140329561f, -1.0f, 0.0f, -0.995184726672197f, -0.098017140329561f, -0.98078528040323f, -0.195090322016128f, -0.956940335732209f, -0.290284677254462f, -0.923879532511287f, -0.38268343236509f, -0.881921264348355f, -0.471396736825998f, -0.831469612302545f, -0.555570233019602f, -0.773010453362737f, -0.634393284163645f, -0.707106781186548f, -0.707106781186547f, -0.634393284163645f, -0.773010453362737f, -0.555570233019602f, -0.831469612302545f, -0.471396736825998f, -0.881921264348355f, -0.38268343236509f, -0.923879532511287f, -0.290284677254462f, -0.956940335732209f, -0.195090322016129f, -0.98078528040323f, -0.098017140329561f, -0.995184726672197f -}; - -const float32_t twiddleCoef_rfft_128[128] = { - 0.000000000f, 1.000000000f, - 0.049067674f, 0.998795456f, - 0.098017140f, 0.995184727f, - 0.146730474f, 0.989176510f, - 0.195090322f, 0.980785280f, - 0.242980180f, 0.970031253f, - 0.290284677f, 0.956940336f, - 0.336889853f, 0.941544065f, - 0.382683432f, 0.923879533f, - 0.427555093f, 0.903989293f, - 0.471396737f, 0.881921264f, - 0.514102744f, 0.857728610f, - 0.555570233f, 0.831469612f, - 0.595699304f, 0.803207531f, - 0.634393284f, 0.773010453f, - 0.671558955f, 0.740951125f, - 0.707106781f, 0.707106781f, - 0.740951125f, 0.671558955f, - 0.773010453f, 0.634393284f, - 0.803207531f, 0.595699304f, - 0.831469612f, 0.555570233f, - 0.857728610f, 0.514102744f, - 0.881921264f, 0.471396737f, - 0.903989293f, 0.427555093f, - 0.923879533f, 0.382683432f, - 0.941544065f, 0.336889853f, - 0.956940336f, 0.290284677f, - 0.970031253f, 0.242980180f, - 0.980785280f, 0.195090322f, - 0.989176510f, 0.146730474f, - 0.995184727f, 0.098017140f, - 0.998795456f, 0.049067674f, - 1.000000000f, 0.000000000f, - 0.998795456f, -0.049067674f, - 0.995184727f, -0.098017140f, - 0.989176510f, -0.146730474f, - 0.980785280f, -0.195090322f, - 0.970031253f, -0.242980180f, - 0.956940336f, -0.290284677f, - 0.941544065f, -0.336889853f, - 0.923879533f, -0.382683432f, - 0.903989293f, -0.427555093f, - 0.881921264f, -0.471396737f, - 0.857728610f, -0.514102744f, - 0.831469612f, -0.555570233f, - 0.803207531f, -0.595699304f, - 0.773010453f, -0.634393284f, - 0.740951125f, -0.671558955f, - 0.707106781f, -0.707106781f, - 0.671558955f, -0.740951125f, - 0.634393284f, -0.773010453f, - 0.595699304f, -0.803207531f, - 0.555570233f, -0.831469612f, - 0.514102744f, -0.857728610f, - 0.471396737f, -0.881921264f, - 0.427555093f, -0.903989293f, - 0.382683432f, -0.923879533f, - 0.336889853f, -0.941544065f, - 0.290284677f, -0.956940336f, - 0.242980180f, -0.970031253f, - 0.195090322f, -0.980785280f, - 0.146730474f, -0.989176510f, - 0.098017140f, -0.995184727f, - 0.049067674f, -0.998795456f -}; - -const float32_t twiddleCoef_rfft_256[256] = { - 0.000000000f, 1.000000000f, - 0.024541229f, 0.999698819f, - 0.049067674f, 0.998795456f, - 0.073564564f, 0.997290457f, - 0.098017140f, 0.995184727f, - 0.122410675f, 0.992479535f, - 0.146730474f, 0.989176510f, - 0.170961889f, 0.985277642f, - 0.195090322f, 0.980785280f, - 0.219101240f, 0.975702130f, - 0.242980180f, 0.970031253f, - 0.266712757f, 0.963776066f, - 0.290284677f, 0.956940336f, - 0.313681740f, 0.949528181f, - 0.336889853f, 0.941544065f, - 0.359895037f, 0.932992799f, - 0.382683432f, 0.923879533f, - 0.405241314f, 0.914209756f, - 0.427555093f, 0.903989293f, - 0.449611330f, 0.893224301f, - 0.471396737f, 0.881921264f, - 0.492898192f, 0.870086991f, - 0.514102744f, 0.857728610f, - 0.534997620f, 0.844853565f, - 0.555570233f, 0.831469612f, - 0.575808191f, 0.817584813f, - 0.595699304f, 0.803207531f, - 0.615231591f, 0.788346428f, - 0.634393284f, 0.773010453f, - 0.653172843f, 0.757208847f, - 0.671558955f, 0.740951125f, - 0.689540545f, 0.724247083f, - 0.707106781f, 0.707106781f, - 0.724247083f, 0.689540545f, - 0.740951125f, 0.671558955f, - 0.757208847f, 0.653172843f, - 0.773010453f, 0.634393284f, - 0.788346428f, 0.615231591f, - 0.803207531f, 0.595699304f, - 0.817584813f, 0.575808191f, - 0.831469612f, 0.555570233f, - 0.844853565f, 0.534997620f, - 0.857728610f, 0.514102744f, - 0.870086991f, 0.492898192f, - 0.881921264f, 0.471396737f, - 0.893224301f, 0.449611330f, - 0.903989293f, 0.427555093f, - 0.914209756f, 0.405241314f, - 0.923879533f, 0.382683432f, - 0.932992799f, 0.359895037f, - 0.941544065f, 0.336889853f, - 0.949528181f, 0.313681740f, - 0.956940336f, 0.290284677f, - 0.963776066f, 0.266712757f, - 0.970031253f, 0.242980180f, - 0.975702130f, 0.219101240f, - 0.980785280f, 0.195090322f, - 0.985277642f, 0.170961889f, - 0.989176510f, 0.146730474f, - 0.992479535f, 0.122410675f, - 0.995184727f, 0.098017140f, - 0.997290457f, 0.073564564f, - 0.998795456f, 0.049067674f, - 0.999698819f, 0.024541229f, - 1.000000000f, 0.000000000f, - 0.999698819f, -0.024541229f, - 0.998795456f, -0.049067674f, - 0.997290457f, -0.073564564f, - 0.995184727f, -0.098017140f, - 0.992479535f, -0.122410675f, - 0.989176510f, -0.146730474f, - 0.985277642f, -0.170961889f, - 0.980785280f, -0.195090322f, - 0.975702130f, -0.219101240f, - 0.970031253f, -0.242980180f, - 0.963776066f, -0.266712757f, - 0.956940336f, -0.290284677f, - 0.949528181f, -0.313681740f, - 0.941544065f, -0.336889853f, - 0.932992799f, -0.359895037f, - 0.923879533f, -0.382683432f, - 0.914209756f, -0.405241314f, - 0.903989293f, -0.427555093f, - 0.893224301f, -0.449611330f, - 0.881921264f, -0.471396737f, - 0.870086991f, -0.492898192f, - 0.857728610f, -0.514102744f, - 0.844853565f, -0.534997620f, - 0.831469612f, -0.555570233f, - 0.817584813f, -0.575808191f, - 0.803207531f, -0.595699304f, - 0.788346428f, -0.615231591f, - 0.773010453f, -0.634393284f, - 0.757208847f, -0.653172843f, - 0.740951125f, -0.671558955f, - 0.724247083f, -0.689540545f, - 0.707106781f, -0.707106781f, - 0.689540545f, -0.724247083f, - 0.671558955f, -0.740951125f, - 0.653172843f, -0.757208847f, - 0.634393284f, -0.773010453f, - 0.615231591f, -0.788346428f, - 0.595699304f, -0.803207531f, - 0.575808191f, -0.817584813f, - 0.555570233f, -0.831469612f, - 0.534997620f, -0.844853565f, - 0.514102744f, -0.857728610f, - 0.492898192f, -0.870086991f, - 0.471396737f, -0.881921264f, - 0.449611330f, -0.893224301f, - 0.427555093f, -0.903989293f, - 0.405241314f, -0.914209756f, - 0.382683432f, -0.923879533f, - 0.359895037f, -0.932992799f, - 0.336889853f, -0.941544065f, - 0.313681740f, -0.949528181f, - 0.290284677f, -0.956940336f, - 0.266712757f, -0.963776066f, - 0.242980180f, -0.970031253f, - 0.219101240f, -0.975702130f, - 0.195090322f, -0.980785280f, - 0.170961889f, -0.985277642f, - 0.146730474f, -0.989176510f, - 0.122410675f, -0.992479535f, - 0.098017140f, -0.995184727f, - 0.073564564f, -0.997290457f, - 0.049067674f, -0.998795456f, - 0.024541229f, -0.999698819f -}; - -const float32_t twiddleCoef_rfft_512[512] = { - 0.000000000f, 1.000000000f, - 0.012271538f, 0.999924702f, - 0.024541229f, 0.999698819f, - 0.036807223f, 0.999322385f, - 0.049067674f, 0.998795456f, - 0.061320736f, 0.998118113f, - 0.073564564f, 0.997290457f, - 0.085797312f, 0.996312612f, - 0.098017140f, 0.995184727f, - 0.110222207f, 0.993906970f, - 0.122410675f, 0.992479535f, - 0.134580709f, 0.990902635f, - 0.146730474f, 0.989176510f, - 0.158858143f, 0.987301418f, - 0.170961889f, 0.985277642f, - 0.183039888f, 0.983105487f, - 0.195090322f, 0.980785280f, - 0.207111376f, 0.978317371f, - 0.219101240f, 0.975702130f, - 0.231058108f, 0.972939952f, - 0.242980180f, 0.970031253f, - 0.254865660f, 0.966976471f, - 0.266712757f, 0.963776066f, - 0.278519689f, 0.960430519f, - 0.290284677f, 0.956940336f, - 0.302005949f, 0.953306040f, - 0.313681740f, 0.949528181f, - 0.325310292f, 0.945607325f, - 0.336889853f, 0.941544065f, - 0.348418680f, 0.937339012f, - 0.359895037f, 0.932992799f, - 0.371317194f, 0.928506080f, - 0.382683432f, 0.923879533f, - 0.393992040f, 0.919113852f, - 0.405241314f, 0.914209756f, - 0.416429560f, 0.909167983f, - 0.427555093f, 0.903989293f, - 0.438616239f, 0.898674466f, - 0.449611330f, 0.893224301f, - 0.460538711f, 0.887639620f, - 0.471396737f, 0.881921264f, - 0.482183772f, 0.876070094f, - 0.492898192f, 0.870086991f, - 0.503538384f, 0.863972856f, - 0.514102744f, 0.857728610f, - 0.524589683f, 0.851355193f, - 0.534997620f, 0.844853565f, - 0.545324988f, 0.838224706f, - 0.555570233f, 0.831469612f, - 0.565731811f, 0.824589303f, - 0.575808191f, 0.817584813f, - 0.585797857f, 0.810457198f, - 0.595699304f, 0.803207531f, - 0.605511041f, 0.795836905f, - 0.615231591f, 0.788346428f, - 0.624859488f, 0.780737229f, - 0.634393284f, 0.773010453f, - 0.643831543f, 0.765167266f, - 0.653172843f, 0.757208847f, - 0.662415778f, 0.749136395f, - 0.671558955f, 0.740951125f, - 0.680600998f, 0.732654272f, - 0.689540545f, 0.724247083f, - 0.698376249f, 0.715730825f, - 0.707106781f, 0.707106781f, - 0.715730825f, 0.698376249f, - 0.724247083f, 0.689540545f, - 0.732654272f, 0.680600998f, - 0.740951125f, 0.671558955f, - 0.749136395f, 0.662415778f, - 0.757208847f, 0.653172843f, - 0.765167266f, 0.643831543f, - 0.773010453f, 0.634393284f, - 0.780737229f, 0.624859488f, - 0.788346428f, 0.615231591f, - 0.795836905f, 0.605511041f, - 0.803207531f, 0.595699304f, - 0.810457198f, 0.585797857f, - 0.817584813f, 0.575808191f, - 0.824589303f, 0.565731811f, - 0.831469612f, 0.555570233f, - 0.838224706f, 0.545324988f, - 0.844853565f, 0.534997620f, - 0.851355193f, 0.524589683f, - 0.857728610f, 0.514102744f, - 0.863972856f, 0.503538384f, - 0.870086991f, 0.492898192f, - 0.876070094f, 0.482183772f, - 0.881921264f, 0.471396737f, - 0.887639620f, 0.460538711f, - 0.893224301f, 0.449611330f, - 0.898674466f, 0.438616239f, - 0.903989293f, 0.427555093f, - 0.909167983f, 0.416429560f, - 0.914209756f, 0.405241314f, - 0.919113852f, 0.393992040f, - 0.923879533f, 0.382683432f, - 0.928506080f, 0.371317194f, - 0.932992799f, 0.359895037f, - 0.937339012f, 0.348418680f, - 0.941544065f, 0.336889853f, - 0.945607325f, 0.325310292f, - 0.949528181f, 0.313681740f, - 0.953306040f, 0.302005949f, - 0.956940336f, 0.290284677f, - 0.960430519f, 0.278519689f, - 0.963776066f, 0.266712757f, - 0.966976471f, 0.254865660f, - 0.970031253f, 0.242980180f, - 0.972939952f, 0.231058108f, - 0.975702130f, 0.219101240f, - 0.978317371f, 0.207111376f, - 0.980785280f, 0.195090322f, - 0.983105487f, 0.183039888f, - 0.985277642f, 0.170961889f, - 0.987301418f, 0.158858143f, - 0.989176510f, 0.146730474f, - 0.990902635f, 0.134580709f, - 0.992479535f, 0.122410675f, - 0.993906970f, 0.110222207f, - 0.995184727f, 0.098017140f, - 0.996312612f, 0.085797312f, - 0.997290457f, 0.073564564f, - 0.998118113f, 0.061320736f, - 0.998795456f, 0.049067674f, - 0.999322385f, 0.036807223f, - 0.999698819f, 0.024541229f, - 0.999924702f, 0.012271538f, - 1.000000000f, 0.000000000f, - 0.999924702f, -0.012271538f, - 0.999698819f, -0.024541229f, - 0.999322385f, -0.036807223f, - 0.998795456f, -0.049067674f, - 0.998118113f, -0.061320736f, - 0.997290457f, -0.073564564f, - 0.996312612f, -0.085797312f, - 0.995184727f, -0.098017140f, - 0.993906970f, -0.110222207f, - 0.992479535f, -0.122410675f, - 0.990902635f, -0.134580709f, - 0.989176510f, -0.146730474f, - 0.987301418f, -0.158858143f, - 0.985277642f, -0.170961889f, - 0.983105487f, -0.183039888f, - 0.980785280f, -0.195090322f, - 0.978317371f, -0.207111376f, - 0.975702130f, -0.219101240f, - 0.972939952f, -0.231058108f, - 0.970031253f, -0.242980180f, - 0.966976471f, -0.254865660f, - 0.963776066f, -0.266712757f, - 0.960430519f, -0.278519689f, - 0.956940336f, -0.290284677f, - 0.953306040f, -0.302005949f, - 0.949528181f, -0.313681740f, - 0.945607325f, -0.325310292f, - 0.941544065f, -0.336889853f, - 0.937339012f, -0.348418680f, - 0.932992799f, -0.359895037f, - 0.928506080f, -0.371317194f, - 0.923879533f, -0.382683432f, - 0.919113852f, -0.393992040f, - 0.914209756f, -0.405241314f, - 0.909167983f, -0.416429560f, - 0.903989293f, -0.427555093f, - 0.898674466f, -0.438616239f, - 0.893224301f, -0.449611330f, - 0.887639620f, -0.460538711f, - 0.881921264f, -0.471396737f, - 0.876070094f, -0.482183772f, - 0.870086991f, -0.492898192f, - 0.863972856f, -0.503538384f, - 0.857728610f, -0.514102744f, - 0.851355193f, -0.524589683f, - 0.844853565f, -0.534997620f, - 0.838224706f, -0.545324988f, - 0.831469612f, -0.555570233f, - 0.824589303f, -0.565731811f, - 0.817584813f, -0.575808191f, - 0.810457198f, -0.585797857f, - 0.803207531f, -0.595699304f, - 0.795836905f, -0.605511041f, - 0.788346428f, -0.615231591f, - 0.780737229f, -0.624859488f, - 0.773010453f, -0.634393284f, - 0.765167266f, -0.643831543f, - 0.757208847f, -0.653172843f, - 0.749136395f, -0.662415778f, - 0.740951125f, -0.671558955f, - 0.732654272f, -0.680600998f, - 0.724247083f, -0.689540545f, - 0.715730825f, -0.698376249f, - 0.707106781f, -0.707106781f, - 0.698376249f, -0.715730825f, - 0.689540545f, -0.724247083f, - 0.680600998f, -0.732654272f, - 0.671558955f, -0.740951125f, - 0.662415778f, -0.749136395f, - 0.653172843f, -0.757208847f, - 0.643831543f, -0.765167266f, - 0.634393284f, -0.773010453f, - 0.624859488f, -0.780737229f, - 0.615231591f, -0.788346428f, - 0.605511041f, -0.795836905f, - 0.595699304f, -0.803207531f, - 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0.189068664f, -0.981963869f, - 0.187562129f, -0.982252741f, - 0.186055152f, -0.982539302f, - 0.184547737f, -0.982823551f, - 0.183039888f, -0.983105487f, - 0.181531608f, -0.983385110f, - 0.180022901f, -0.983662419f, - 0.178513771f, -0.983937413f, - 0.177004220f, -0.984210092f, - 0.175494253f, -0.984480455f, - 0.173983873f, -0.984748502f, - 0.172473084f, -0.985014231f, - 0.170961889f, -0.985277642f, - 0.169450291f, -0.985538735f, - 0.167938295f, -0.985797509f, - 0.166425904f, -0.986053963f, - 0.164913120f, -0.986308097f, - 0.163399949f, -0.986559910f, - 0.161886394f, -0.986809402f, - 0.160372457f, -0.987056571f, - 0.158858143f, -0.987301418f, - 0.157343456f, -0.987543942f, - 0.155828398f, -0.987784142f, - 0.154312973f, -0.988022017f, - 0.152797185f, -0.988257568f, - 0.151281038f, -0.988490793f, - 0.149764535f, -0.988721692f, - 0.148247679f, -0.988950265f, - 0.146730474f, -0.989176510f, - 0.145212925f, -0.989400428f, - 0.143695033f, -0.989622017f, - 0.142176804f, -0.989841278f, - 0.140658239f, -0.990058210f, - 0.139139344f, -0.990272812f, - 0.137620122f, -0.990485084f, - 0.136100575f, -0.990695025f, - 0.134580709f, -0.990902635f, - 0.133060525f, -0.991107914f, - 0.131540029f, -0.991310860f, - 0.130019223f, -0.991511473f, - 0.128498111f, -0.991709754f, - 0.126976696f, -0.991905700f, - 0.125454983f, -0.992099313f, - 0.123932975f, -0.992290591f, - 0.122410675f, -0.992479535f, - 0.120888087f, -0.992666142f, - 0.119365215f, -0.992850414f, - 0.117842062f, -0.993032350f, - 0.116318631f, -0.993211949f, - 0.114794927f, -0.993389211f, - 0.113270952f, -0.993564136f, - 0.111746711f, -0.993736722f, - 0.110222207f, -0.993906970f, - 0.108697444f, -0.994074879f, - 0.107172425f, -0.994240449f, - 0.105647154f, -0.994403680f, - 0.104121634f, -0.994564571f, - 0.102595869f, -0.994723121f, - 0.101069863f, -0.994879331f, - 0.099543619f, -0.995033199f, - 0.098017140f, -0.995184727f, - 0.096490431f, -0.995333912f, - 0.094963495f, -0.995480755f, - 0.093436336f, -0.995625256f, - 0.091908956f, -0.995767414f, - 0.090381361f, -0.995907229f, - 0.088853553f, -0.996044701f, - 0.087325535f, -0.996179829f, - 0.085797312f, -0.996312612f, - 0.084268888f, -0.996443051f, - 0.082740265f, -0.996571146f, - 0.081211447f, -0.996696895f, - 0.079682438f, -0.996820299f, - 0.078153242f, -0.996941358f, - 0.076623861f, -0.997060070f, - 0.075094301f, -0.997176437f, - 0.073564564f, -0.997290457f, - 0.072034653f, -0.997402130f, - 0.070504573f, -0.997511456f, - 0.068974328f, -0.997618435f, - 0.067443920f, -0.997723067f, - 0.065913353f, -0.997825350f, - 0.064382631f, -0.997925286f, - 0.062851758f, -0.998022874f, - 0.061320736f, -0.998118113f, - 0.059789571f, -0.998211003f, - 0.058258265f, -0.998301545f, - 0.056726821f, -0.998389737f, - 0.055195244f, -0.998475581f, - 0.053663538f, -0.998559074f, - 0.052131705f, -0.998640218f, - 0.050599749f, -0.998719012f, - 0.049067674f, -0.998795456f, - 0.047535484f, -0.998869550f, - 0.046003182f, -0.998941293f, - 0.044470772f, -0.999010686f, - 0.042938257f, -0.999077728f, - 0.041405641f, -0.999142419f, - 0.039872928f, -0.999204759f, - 0.038340120f, -0.999264747f, - 0.036807223f, -0.999322385f, - 0.035274239f, -0.999377670f, - 0.033741172f, -0.999430605f, - 0.032208025f, -0.999481187f, - 0.030674803f, -0.999529418f, - 0.029141509f, -0.999575296f, - 0.027608146f, -0.999618822f, - 0.026074718f, -0.999659997f, - 0.024541229f, -0.999698819f, - 0.023007681f, -0.999735288f, - 0.021474080f, -0.999769405f, - 0.019940429f, -0.999801170f, - 0.018406730f, -0.999830582f, - 0.016872988f, -0.999857641f, - 0.015339206f, -0.999882347f, - 0.013805389f, -0.999904701f, - 0.012271538f, -0.999924702f, - 0.010737659f, -0.999942350f, - 0.009203755f, -0.999957645f, - 0.007669829f, -0.999970586f, - 0.006135885f, -0.999981175f, - 0.004601926f, -0.999989411f, - 0.003067957f, -0.999995294f, - 0.001533980f, -0.999998823f -}; - - -/** - * \par - * Example code for the generation of the floating-point sine table: - * 
- * tableSize = 512;    
- * for(n = 0; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n]=sin(2*pi*n/tableSize);    
- * }
- * \par - * where pi value is 3.14159265358979 - */ - -const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { - 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, - 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, - 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, - 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, - 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, - 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, - 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, - 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, - 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, - 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, - 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, - 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, - 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, - 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, - 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, - 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, - 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, - 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, - 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, - 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, - 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, - 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, - 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, - 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, - 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, - 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, - 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, - 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, - 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, - 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, - 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, - 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, - 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, - 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, - 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, - 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, - 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, - 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, - 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, - 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, - 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, - 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, - 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, - -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, - -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, - -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, - -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, - -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, - -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, - -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, - -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, - -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, - -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, - -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, - -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, - -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, - -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, - -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, - -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, - -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, - -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, - -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, - -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, - -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, - -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, - -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, - -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, - -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, - -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, - -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, - -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, - -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, - -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, - -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, - -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, - -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, - -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, - -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, - -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, - -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, - -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, - -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, - -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, - -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, - -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, - -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, - -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, - -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, - -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, - -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, - -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, - -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, - -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, - -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f -}; - -/** - * \par - * Table values are in Q31 (1.31 fixed-point format) and generation is done in - * three steps. First, generate sin values in floating point: - * 
- * tableSize = 512;      
- * for(n = 0; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n]= sin(2*pi*n/tableSize);    
- * }
- * where pi value is 3.14159265358979 - * \par - * Second, convert floating-point to Q31 (Fixed point): - * (sinTable[i] * pow(2, 31)) - * \par - * Finally, round to the nearest integer value: - * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); - */ -const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { - 0x00000000, 0x01921D20, 0x03242ABF, 0x04B6195D, 0x0647D97C, 0x07D95B9E, - 0x096A9049, 0x0AFB6805, 0x0C8BD35E, 0x0E1BC2E4, 0x0FAB272B, 0x1139F0CF, - 0x12C8106F, 0x145576B1, 0x15E21445, 0x176DD9DE, 0x18F8B83C, 0x1A82A026, - 0x1C0B826A, 0x1D934FE5, 0x1F19F97B, 0x209F701C, 0x2223A4C5, 0x23A6887F, - 0x25280C5E, 0x26A82186, 0x2826B928, 0x29A3C485, 0x2B1F34EB, 0x2C98FBBA, - 0x2E110A62, 0x2F875262, 0x30FBC54D, 0x326E54C7, 0x33DEF287, 0x354D9057, - 0x36BA2014, 0x382493B0, 0x398CDD32, 0x3AF2EEB7, 0x3C56BA70, 0x3DB832A6, - 0x3F1749B8, 0x4073F21D, 0x41CE1E65, 0x4325C135, 0x447ACD50, 0x45CD358F, - 0x471CECE7, 0x4869E665, 0x49B41533, 0x4AFB6C98, 0x4C3FDFF4, 0x4D8162C4, - 0x4EBFE8A5, 0x4FFB654D, 0x5133CC94, 0x5269126E, 0x539B2AF0, 0x54CA0A4B, - 0x55F5A4D2, 0x571DEEFA, 0x5842DD54, 0x59646498, 0x5A82799A, 0x5B9D1154, - 0x5CB420E0, 0x5DC79D7C, 0x5ED77C8A, 0x5FE3B38D, 0x60EC3830, 0x61F1003F, - 0x62F201AC, 0x63EF3290, 0x64E88926, 0x65DDFBD3, 0x66CF8120, 0x67BD0FBD, - 0x68A69E81, 0x698C246C, 0x6A6D98A4, 0x6B4AF279, 0x6C242960, 0x6CF934FC, - 0x6DCA0D14, 0x6E96A99D, 0x6F5F02B2, 0x7023109A, 0x70E2CBC6, 0x719E2CD2, - 0x72552C85, 0x7307C3D0, 0x73B5EBD1, 0x745F9DD1, 0x7504D345, 0x75A585CF, - 0x7641AF3D, 0x76D94989, 0x776C4EDB, 0x77FAB989, 0x78848414, 0x7909A92D, - 0x798A23B1, 0x7A05EEAD, 0x7A7D055B, 0x7AEF6323, 0x7B5D039E, 0x7BC5E290, - 0x7C29FBEE, 0x7C894BDE, 0x7CE3CEB2, 0x7D3980EC, 0x7D8A5F40, 0x7DD6668F, - 0x7E1D93EA, 0x7E5FE493, 0x7E9D55FC, 0x7ED5E5C6, 0x7F0991C4, 0x7F3857F6, - 0x7F62368F, 0x7F872BF3, 0x7FA736B4, 0x7FC25596, 0x7FD8878E, 0x7FE9CBC0, - 0x7FF62182, 0x7FFD885A, 0x7FFFFFFF, 0x7FFD885A, 0x7FF62182, 0x7FE9CBC0, - 0x7FD8878E, 0x7FC25596, 0x7FA736B4, 0x7F872BF3, 0x7F62368F, 0x7F3857F6, - 0x7F0991C4, 0x7ED5E5C6, 0x7E9D55FC, 0x7E5FE493, 0x7E1D93EA, 0x7DD6668F, - 0x7D8A5F40, 0x7D3980EC, 0x7CE3CEB2, 0x7C894BDE, 0x7C29FBEE, 0x7BC5E290, - 0x7B5D039E, 0x7AEF6323, 0x7A7D055B, 0x7A05EEAD, 0x798A23B1, 0x7909A92D, - 0x78848414, 0x77FAB989, 0x776C4EDB, 0x76D94989, 0x7641AF3D, 0x75A585CF, - 0x7504D345, 0x745F9DD1, 0x73B5EBD1, 0x7307C3D0, 0x72552C85, 0x719E2CD2, - 0x70E2CBC6, 0x7023109A, 0x6F5F02B2, 0x6E96A99D, 0x6DCA0D14, 0x6CF934FC, - 0x6C242960, 0x6B4AF279, 0x6A6D98A4, 0x698C246C, 0x68A69E81, 0x67BD0FBD, - 0x66CF8120, 0x65DDFBD3, 0x64E88926, 0x63EF3290, 0x62F201AC, 0x61F1003F, - 0x60EC3830, 0x5FE3B38D, 0x5ED77C8A, 0x5DC79D7C, 0x5CB420E0, 0x5B9D1154, - 0x5A82799A, 0x59646498, 0x5842DD54, 0x571DEEFA, 0x55F5A4D2, 0x54CA0A4B, - 0x539B2AF0, 0x5269126E, 0x5133CC94, 0x4FFB654D, 0x4EBFE8A5, 0x4D8162C4, - 0x4C3FDFF4, 0x4AFB6C98, 0x49B41533, 0x4869E665, 0x471CECE7, 0x45CD358F, - 0x447ACD50, 0x4325C135, 0x41CE1E65, 0x4073F21D, 0x3F1749B8, 0x3DB832A6, - 0x3C56BA70, 0x3AF2EEB7, 0x398CDD32, 0x382493B0, 0x36BA2014, 0x354D9057, - 0x33DEF287, 0x326E54C7, 0x30FBC54D, 0x2F875262, 0x2E110A62, 0x2C98FBBA, - 0x2B1F34EB, 0x29A3C485, 0x2826B928, 0x26A82186, 0x25280C5E, 0x23A6887F, - 0x2223A4C5, 0x209F701C, 0x1F19F97B, 0x1D934FE5, 0x1C0B826A, 0x1A82A026, - 0x18F8B83C, 0x176DD9DE, 0x15E21445, 0x145576B1, 0x12C8106F, 0x1139F0CF, - 0x0FAB272B, 0x0E1BC2E4, 0x0C8BD35E, 0x0AFB6805, 0x096A9049, 0x07D95B9E, - 0x0647D97C, 0x04B6195D, 0x03242ABF, 0x01921D20, 0x00000000, 0xFE6DE2E0, - 0xFCDBD541, 0xFB49E6A3, 0xF9B82684, 0xF826A462, 0xF6956FB7, 0xF50497FB, - 0xF3742CA2, 0xF1E43D1C, 0xF054D8D5, 0xEEC60F31, 0xED37EF91, 0xEBAA894F, - 0xEA1DEBBB, 0xE8922622, 0xE70747C4, 0xE57D5FDA, 0xE3F47D96, 0xE26CB01B, - 0xE0E60685, 0xDF608FE4, 0xDDDC5B3B, 0xDC597781, 0xDAD7F3A2, 0xD957DE7A, - 0xD7D946D8, 0xD65C3B7B, 0xD4E0CB15, 0xD3670446, 0xD1EEF59E, 0xD078AD9E, - 0xCF043AB3, 0xCD91AB39, 0xCC210D79, 0xCAB26FA9, 0xC945DFEC, 0xC7DB6C50, - 0xC67322CE, 0xC50D1149, 0xC3A94590, 0xC247CD5A, 0xC0E8B648, 0xBF8C0DE3, - 0xBE31E19B, 0xBCDA3ECB, 0xBB8532B0, 0xBA32CA71, 0xB8E31319, 0xB796199B, - 0xB64BEACD, 0xB5049368, 0xB3C0200C, 0xB27E9D3C, 0xB140175B, 0xB0049AB3, - 0xAECC336C, 0xAD96ED92, 0xAC64D510, 0xAB35F5B5, 0xAA0A5B2E, 0xA8E21106, - 0xA7BD22AC, 0xA69B9B68, 0xA57D8666, 0xA462EEAC, 0xA34BDF20, 0xA2386284, - 0xA1288376, 0xA01C4C73, 0x9F13C7D0, 0x9E0EFFC1, 0x9D0DFE54, 0x9C10CD70, - 0x9B1776DA, 0x9A22042D, 0x99307EE0, 0x9842F043, 0x9759617F, 0x9673DB94, - 0x9592675C, 0x94B50D87, 0x93DBD6A0, 0x9306CB04, 0x9235F2EC, 0x91695663, - 0x90A0FD4E, 0x8FDCEF66, 0x8F1D343A, 0x8E61D32E, 0x8DAAD37B, 0x8CF83C30, - 0x8C4A142F, 0x8BA0622F, 0x8AFB2CBB, 0x8A5A7A31, 0x89BE50C3, 0x8926B677, - 0x8893B125, 0x88054677, 0x877B7BEC, 0x86F656D3, 0x8675DC4F, 0x85FA1153, - 0x8582FAA5, 0x85109CDD, 0x84A2FC62, 0x843A1D70, 0x83D60412, 0x8376B422, - 0x831C314E, 0x82C67F14, 0x8275A0C0, 0x82299971, 0x81E26C16, 0x81A01B6D, - 0x8162AA04, 0x812A1A3A, 0x80F66E3C, 0x80C7A80A, 0x809DC971, 0x8078D40D, - 0x8058C94C, 0x803DAA6A, 0x80277872, 0x80163440, 0x8009DE7E, 0x800277A6, - 0x80000000, 0x800277A6, 0x8009DE7E, 0x80163440, 0x80277872, 0x803DAA6A, - 0x8058C94C, 0x8078D40D, 0x809DC971, 0x80C7A80A, 0x80F66E3C, 0x812A1A3A, - 0x8162AA04, 0x81A01B6D, 0x81E26C16, 0x82299971, 0x8275A0C0, 0x82C67F14, - 0x831C314E, 0x8376B422, 0x83D60412, 0x843A1D70, 0x84A2FC62, 0x85109CDD, - 0x8582FAA5, 0x85FA1153, 0x8675DC4F, 0x86F656D3, 0x877B7BEC, 0x88054677, - 0x8893B125, 0x8926B677, 0x89BE50C3, 0x8A5A7A31, 0x8AFB2CBB, 0x8BA0622F, - 0x8C4A142F, 0x8CF83C30, 0x8DAAD37B, 0x8E61D32E, 0x8F1D343A, 0x8FDCEF66, - 0x90A0FD4E, 0x91695663, 0x9235F2EC, 0x9306CB04, 0x93DBD6A0, 0x94B50D87, - 0x9592675C, 0x9673DB94, 0x9759617F, 0x9842F043, 0x99307EE0, 0x9A22042D, - 0x9B1776DA, 0x9C10CD70, 0x9D0DFE54, 0x9E0EFFC1, 0x9F13C7D0, 0xA01C4C73, - 0xA1288376, 0xA2386284, 0xA34BDF20, 0xA462EEAC, 0xA57D8666, 0xA69B9B68, - 0xA7BD22AC, 0xA8E21106, 0xAA0A5B2E, 0xAB35F5B5, 0xAC64D510, 0xAD96ED92, - 0xAECC336C, 0xB0049AB3, 0xB140175B, 0xB27E9D3C, 0xB3C0200C, 0xB5049368, - 0xB64BEACD, 0xB796199B, 0xB8E31319, 0xBA32CA71, 0xBB8532B0, 0xBCDA3ECB, - 0xBE31E19B, 0xBF8C0DE3, 0xC0E8B648, 0xC247CD5A, 0xC3A94590, 0xC50D1149, - 0xC67322CE, 0xC7DB6C50, 0xC945DFEC, 0xCAB26FA9, 0xCC210D79, 0xCD91AB39, - 0xCF043AB3, 0xD078AD9E, 0xD1EEF59E, 0xD3670446, 0xD4E0CB15, 0xD65C3B7B, - 0xD7D946D8, 0xD957DE7A, 0xDAD7F3A2, 0xDC597781, 0xDDDC5B3B, 0xDF608FE4, - 0xE0E60685, 0xE26CB01B, 0xE3F47D96, 0xE57D5FDA, 0xE70747C4, 0xE8922622, - 0xEA1DEBBB, 0xEBAA894F, 0xED37EF91, 0xEEC60F31, 0xF054D8D5, 0xF1E43D1C, - 0xF3742CA2, 0xF50497FB, 0xF6956FB7, 0xF826A462, 0xF9B82684, 0xFB49E6A3, - 0xFCDBD541, 0xFE6DE2E0, 0x00000000 -}; - -/** - * \par - * Table values are in Q15 (1.15 fixed-point format) and generation is done in - * three steps. First, generate sin values in floating point: - * 
- * tableSize = 512;      
- * for(n = 0; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n]= sin(2*pi*n/tableSize);    
- * }
- * where pi value is 3.14159265358979 - * \par - * Second, convert floating-point to Q15 (Fixed point): - * (sinTable[i] * pow(2, 15)) - * \par - * Finally, round to the nearest integer value: - * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); - */ -const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { - 0x0000, 0x0192, 0x0324, 0x04B6, 0x0648, 0x07D9, 0x096B, 0x0AFB, 0x0C8C, 0x0E1C, 0x0FAB, 0x113A, 0x12C8, - 0x1455, 0x15E2, 0x176E, 0x18F9, 0x1A83, 0x1C0C, 0x1D93, 0x1F1A, 0x209F, 0x2224, 0x23A7, 0x2528, 0x26A8, - 0x2827, 0x29A4, 0x2B1F, 0x2C99, 0x2E11, 0x2F87, 0x30FC, 0x326E, 0x33DF, 0x354E, 0x36BA, 0x3825, 0x398D, - 0x3AF3, 0x3C57, 0x3DB8, 0x3F17, 0x4074, 0x41CE, 0x4326, 0x447B, 0x45CD, 0x471D, 0x486A, 0x49B4, 0x4AFB, - 0x4C40, 0x4D81, 0x4EC0, 0x4FFB, 0x5134, 0x5269, 0x539B, 0x54CA, 0x55F6, 0x571E, 0x5843, 0x5964, 0x5A82, - 0x5B9D, 0x5CB4, 0x5DC8, 0x5ED7, 0x5FE4, 0x60EC, 0x61F1, 0x62F2, 0x63EF, 0x64E9, 0x65DE, 0x66D0, 0x67BD, - 0x68A7, 0x698C, 0x6A6E, 0x6B4B, 0x6C24, 0x6CF9, 0x6DCA, 0x6E97, 0x6F5F, 0x7023, 0x70E3, 0x719E, 0x7255, - 0x7308, 0x73B6, 0x7460, 0x7505, 0x75A6, 0x7642, 0x76D9, 0x776C, 0x77FB, 0x7885, 0x790A, 0x798A, 0x7A06, - 0x7A7D, 0x7AEF, 0x7B5D, 0x7BC6, 0x7C2A, 0x7C89, 0x7CE4, 0x7D3A, 0x7D8A, 0x7DD6, 0x7E1E, 0x7E60, 0x7E9D, - 0x7ED6, 0x7F0A, 0x7F38, 0x7F62, 0x7F87, 0x7FA7, 0x7FC2, 0x7FD9, 0x7FEA, 0x7FF6, 0x7FFE, 0x7FFF, 0x7FFE, - 0x7FF6, 0x7FEA, 0x7FD9, 0x7FC2, 0x7FA7, 0x7F87, 0x7F62, 0x7F38, 0x7F0A, 0x7ED6, 0x7E9D, 0x7E60, 0x7E1E, - 0x7DD6, 0x7D8A, 0x7D3A, 0x7CE4, 0x7C89, 0x7C2A, 0x7BC6, 0x7B5D, 0x7AEF, 0x7A7D, 0x7A06, 0x798A, 0x790A, - 0x7885, 0x77FB, 0x776C, 0x76D9, 0x7642, 0x75A6, 0x7505, 0x7460, 0x73B6, 0x7308, 0x7255, 0x719E, 0x70E3, - 0x7023, 0x6F5F, 0x6E97, 0x6DCA, 0x6CF9, 0x6C24, 0x6B4B, 0x6A6E, 0x698C, 0x68A7, 0x67BD, 0x66D0, 0x65DE, - 0x64E9, 0x63EF, 0x62F2, 0x61F1, 0x60EC, 0x5FE4, 0x5ED7, 0x5DC8, 0x5CB4, 0x5B9D, 0x5A82, 0x5964, 0x5843, - 0x571E, 0x55F6, 0x54CA, 0x539B, 0x5269, 0x5134, 0x4FFB, 0x4EC0, 0x4D81, 0x4C40, 0x4AFB, 0x49B4, 0x486A, - 0x471D, 0x45CD, 0x447B, 0x4326, 0x41CE, 0x4074, 0x3F17, 0x3DB8, 0x3C57, 0x3AF3, 0x398D, 0x3825, 0x36BA, - 0x354E, 0x33DF, 0x326E, 0x30FC, 0x2F87, 0x2E11, 0x2C99, 0x2B1F, 0x29A4, 0x2827, 0x26A8, 0x2528, 0x23A7, - 0x2224, 0x209F, 0x1F1A, 0x1D93, 0x1C0C, 0x1A83, 0x18F9, 0x176E, 0x15E2, 0x1455, 0x12C8, 0x113A, 0x0FAB, - 0x0E1C, 0x0C8C, 0x0AFB, 0x096B, 0x07D9, 0x0648, 0x04B6, 0x0324, 0x0192, 0x0000, 0xFE6E, 0xFCDC, 0xFB4A, - 0xF9B8, 0xF827, 0xF695, 0xF505, 0xF374, 0xF1E4, 0xF055, 0xEEC6, 0xED38, 0xEBAB, 0xEA1E, 0xE892, 0xE707, - 0xE57D, 0xE3F4, 0xE26D, 0xE0E6, 0xDF61, 0xDDDC, 0xDC59, 0xDAD8, 0xD958, 0xD7D9, 0xD65C, 0xD4E1, 0xD367, - 0xD1EF, 0xD079, 0xCF04, 0xCD92, 0xCC21, 0xCAB2, 0xC946, 0xC7DB, 0xC673, 0xC50D, 0xC3A9, 0xC248, 0xC0E9, - 0xBF8C, 0xBE32, 0xBCDA, 0xBB85, 0xBA33, 0xB8E3, 0xB796, 0xB64C, 0xB505, 0xB3C0, 0xB27F, 0xB140, 0xB005, - 0xAECC, 0xAD97, 0xAC65, 0xAB36, 0xAA0A, 0xA8E2, 0xA7BD, 0xA69C, 0xA57E, 0xA463, 0xA34C, 0xA238, 0xA129, - 0xA01C, 0x9F14, 0x9E0F, 0x9D0E, 0x9C11, 0x9B17, 0x9A22, 0x9930, 0x9843, 0x9759, 0x9674, 0x9592, 0x94B5, - 0x93DC, 0x9307, 0x9236, 0x9169, 0x90A1, 0x8FDD, 0x8F1D, 0x8E62, 0x8DAB, 0x8CF8, 0x8C4A, 0x8BA0, 0x8AFB, - 0x8A5A, 0x89BE, 0x8927, 0x8894, 0x8805, 0x877B, 0x86F6, 0x8676, 0x85FA, 0x8583, 0x8511, 0x84A3, 0x843A, - 0x83D6, 0x8377, 0x831C, 0x82C6, 0x8276, 0x822A, 0x81E2, 0x81A0, 0x8163, 0x812A, 0x80F6, 0x80C8, 0x809E, - 0x8079, 0x8059, 0x803E, 0x8027, 0x8016, 0x800A, 0x8002, 0x8000, 0x8002, 0x800A, 0x8016, 0x8027, 0x803E, - 0x8059, 0x8079, 0x809E, 0x80C8, 0x80F6, 0x812A, 0x8163, 0x81A0, 0x81E2, 0x822A, 0x8276, 0x82C6, 0x831C, - 0x8377, 0x83D6, 0x843A, 0x84A3, 0x8511, 0x8583, 0x85FA, 0x8676, 0x86F6, 0x877B, 0x8805, 0x8894, 0x8927, - 0x89BE, 0x8A5A, 0x8AFB, 0x8BA0, 0x8C4A, 0x8CF8, 0x8DAB, 0x8E62, 0x8F1D, 0x8FDD, 0x90A1, 0x9169, 0x9236, - 0x9307, 0x93DC, 0x94B5, 0x9592, 0x9674, 0x9759, 0x9843, 0x9930, 0x9A22, 0x9B17, 0x9C11, 0x9D0E, 0x9E0F, - 0x9F14, 0xA01C, 0xA129, 0xA238, 0xA34C, 0xA463, 0xA57E, 0xA69C, 0xA7BD, 0xA8E2, 0xAA0A, 0xAB36, 0xAC65, - 0xAD97, 0xAECC, 0xB005, 0xB140, 0xB27F, 0xB3C0, 0xB505, 0xB64C, 0xB796, 0xB8E3, 0xBA33, 0xBB85, 0xBCDA, - 0xBE32, 0xBF8C, 0xC0E9, 0xC248, 0xC3A9, 0xC50D, 0xC673, 0xC7DB, 0xC946, 0xCAB2, 0xCC21, 0xCD92, 0xCF04, - 0xD079, 0xD1EF, 0xD367, 0xD4E1, 0xD65C, 0xD7D9, 0xD958, 0xDAD8, 0xDC59, 0xDDDC, 0xDF61, 0xE0E6, 0xE26D, - 0xE3F4, 0xE57D, 0xE707, 0xE892, 0xEA1E, 0xEBAB, 0xED38, 0xEEC6, 0xF055, 0xF1E4, 0xF374, 0xF505, 0xF695, - 0xF827, 0xF9B8, 0xFB4A, 0xFCDC, 0xFE6E, 0x0000 -}; diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c deleted file mode 100644 index f05c1c2f..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c +++ /dev/null @@ -1,156 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.c -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#include "arm_const_structs.h" - -//Floating-point structs - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { - 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { - 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { - 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { - 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { - 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { - 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { - 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { - 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH -}; - -const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { - 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH -}; - -//Fixed-point structs - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { - 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { - 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { - 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { - 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { - 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { - 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { - 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { - 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH -}; - -const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { - 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH -}; - - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { - 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { - 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { - 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { - 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { - 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { - 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { - 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { - 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH -}; - -const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { - 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH -}; diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c deleted file mode 100644 index c54ae41d..00000000 --- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c +++ /dev/null @@ -1,182 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_cmplx_conj_f32.c -* -* Description: Floating-point complex conjugate. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* ---------------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupCmplxMath - */ - -/** - * @defgroup cmplx_conj Complex Conjugate - * - * Conjugates the elements of a complex data vector. - * - * The pSrc points to the source data and - * pDst points to the where the result should be written. - * numSamples specifies the number of complex samples - * and the data in each array is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * Each array has a total of 2*numSamples values. - * The underlying algorithm is used: - * - * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup cmplx_conj        
- * @{        
- */
-
-/**        
- * @brief  Floating-point complex conjugate.        
- * @param  *pSrc points to the input vector        
- * @param  *pDst points to the output vector        
- * @param  numSamples number of complex samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t inR1, inR2, inR3, inR4;
-  float32_t inI1, inI2, inI3, inI4;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* read real input samples */
-    inR1 = pSrc[0];
-    /* store real samples to destination */
-    pDst[0] = inR1;
-    inR2 = pSrc[2];
-    pDst[2] = inR2;
-    inR3 = pSrc[4];
-    pDst[4] = inR3;
-    inR4 = pSrc[6];
-    pDst[6] = inR4;
-
-    /* read imaginary input samples */
-    inI1 = pSrc[1];
-    inI2 = pSrc[3];
-
-    /* conjugate input */
-    inI1 = -inI1;
-
-    /* read imaginary input samples */
-    inI3 = pSrc[5];
-
-    /* conjugate input */
-    inI2 = -inI2;
-
-    /* read imaginary input samples */
-    inI4 = pSrc[7];
-
-    /* conjugate input */
-    inI3 = -inI3;
-
-    /* store imaginary samples to destination */
-    pDst[1] = inI1;
-    pDst[3] = inI2;
-
-    /* conjugate input */
-    inI4 = -inI4;
-
-    /* store imaginary samples to destination */
-    pDst[5] = inI3;
-
-    /* increment source pointer by 8 to process next sampels */
-    pSrc += 8u;
-
-    /* store imaginary sample to destination */
-    pDst[7] = inI4;
-
-    /* increment destination pointer by 8 to store next samples */
-    pDst += 8u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    *pDst++ = -*pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_conj group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
deleted file mode 100644
index 62e82f31..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_conj_q15.c    
-*    
-* Description:	Q15 complex conjugate.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_conj    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex conjugate.    
- * @param  *pSrc points to the input vector    
- * @param  *pDst points to the output vector    
- * @param  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    
- */
-
-void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t zero = 0;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    in1 = __QASX(zero, in1);
-    in2 = __QASX(zero, in2);
-    in3 = __QASX(zero, in3);
-    in4 = __QASX(zero, in4);
-
-#else
-
-    in1 = __QSAX(zero, in1);
-    in2 = __QSAX(zero, in2);
-    in3 = __QSAX(zero, in3);
-    in4 = __QSAX(zero, in4);
-
-#endif //       #ifndef ARM_MATH_BIG_ENDIAN
-
-    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
-    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
-    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
-    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
-
-    *__SIMD32(pDst)++ = in1;
-    *__SIMD32(pDst)++ = in2;
-    *__SIMD32(pDst)++ = in3;
-    *__SIMD32(pDst)++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    *pDst++ = __SSAT(-*pSrc++, 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  q15_t in;
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    in = *pSrc++;
-    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of cmplx_conj group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
deleted file mode 100644
index f882f4cd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_conj_q31.c    
-*    
-* Description:	Q31 complex conjugate.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @addtogroup cmplx_conj        
- * @{        
- */
-
-/**        
- * @brief  Q31 complex conjugate.        
- * @param  *pSrc points to the input vector        
- * @param  *pDst points to the output vector        
- * @param  numSamples number of complex samples in each vector        
- * @return none.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function uses saturating arithmetic.        
- * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.        
- */
-
-void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in;                                      /* Input value */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */
-  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
-    /* read real input sample */
-    inR1 = pSrc[0];
-    /* store real input sample */
-    pDst[0] = inR1;
-
-    /* read imaginary input sample */
-    inI1 = pSrc[1];
-
-    /* read real input sample */
-    inR2 = pSrc[2];
-    /* store real input sample */
-    pDst[2] = inR2;
-
-    /* read imaginary input sample */
-    inI2 = pSrc[3];
-
-    /* negate imaginary input sample */
-    inI1 = __QSUB(0, inI1);
-
-    /* read real input sample */
-    inR3 = pSrc[4];
-    /* store real input sample */
-    pDst[4] = inR3;
-
-    /* read imaginary input sample */
-    inI3 = pSrc[5];
-
-    /* negate imaginary input sample */
-    inI2 = __QSUB(0, inI2);
-
-    /* read real input sample */
-    inR4 = pSrc[6];
-    /* store real input sample */
-    pDst[6] = inR4;
-
-    /* negate imaginary input sample */
-    inI3 = __QSUB(0, inI3);
-
-    /* store imaginary input sample */
-    inI4 = pSrc[7];
-
-    /* store imaginary input samples */
-    pDst[1] = inI1;
-
-    /* negate imaginary input sample */
-    inI4 = __QSUB(0, inI4);
-
-    /* store imaginary input samples */
-    pDst[3] = inI2;
-
-    /* increment source pointer by 8 to proecess next samples */
-    pSrc += 8u;
-
-    /* store imaginary input samples */
-    pDst[5] = inI3;
-    pDst[7] = inI4;
-
-    /* increment destination pointer by 8 to process next samples */
-    pDst += 8u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
-    *pDst++ = *pSrc++;
-    in = *pSrc++;
-    *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_conj group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
deleted file mode 100644
index 1a6acb87..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_f32.c    
-*    
-* Description:	Floating-point complex dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @defgroup cmplx_dot_prod Complex Dot Product    
- *    
- * Computes the dot product of two complex vectors.    
- * The vectors are multiplied element-by-element and then summed.    
- *   
- * The pSrcA points to the first complex input vector and    
- * pSrcB points to the second complex input vector.    
- * numSamples specifies the number of complex samples    
- * and the data in each array is stored in an interleaved fashion    
- * (real, imag, real, imag, ...).    
- * Each array has a total of 2*numSamples values.    
- *    
- * The underlying algorithm is used:    
- * 
    
- * realResult=0;    
- * imagResult=0;    
- * for(n=0; n    
- *    
- * There are separate functions for floating-point, Q15, and Q31 data types.    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Floating-point complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- */
-
-void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult)
-{
-  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
-  float32_t a0,b0,c0,d0;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-    
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++; 
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-    
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++; 
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples & 0x3u;
-
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-
-      /* Decrement the loop counter */
-      numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Store the real and imaginary results in the destination buffers */
-  *realResult = real_sum;
-  *imagResult = imag_sum;
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
deleted file mode 100644
index d794e2c3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_q15.c    
-*    
-* Description:	Processing function for the Q15 Complex Dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    
- * These are accumulated in a 64-bit accumulator with 34.30 precision.    
- * As a final step, the accumulators are converted to 8.24 format.    
- * The return results realResult and imagResult are in 8.24 format.    
- */
-
-void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult)
-{
-  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
-  q15_t a0,b0,c0,d0;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += (q31_t)a0 * c0;
-      imag_sum += (q31_t)a0 * d0;
-      real_sum -= (q31_t)b0 * d0;
-      imag_sum += (q31_t)b0 * c0;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += (q31_t)a0 * c0;
-      imag_sum += (q31_t)a0 * d0;
-      real_sum -= (q31_t)b0 * d0;
-      imag_sum += (q31_t)b0 * c0;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += (q31_t)a0 * c0;
-      imag_sum += (q31_t)a0 * d0;
-      real_sum -= (q31_t)b0 * d0;
-      imag_sum += (q31_t)b0 * c0;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += (q31_t)a0 * c0;
-      imag_sum += (q31_t)a0 * d0;
-      real_sum -= (q31_t)b0 * d0;
-      imag_sum += (q31_t)b0 * c0;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += (q31_t)a0 * c0;
-      imag_sum += (q31_t)a0 * d0;
-      real_sum -= (q31_t)b0 * d0;
-      imag_sum += (q31_t)b0 * c0;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += a0 * c0;
-      imag_sum += a0 * d0;
-      real_sum -= b0 * d0;
-      imag_sum += b0 * c0;
-
-
-      /* Decrement the loop counter */
-      numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Store the real and imaginary results in 8.24 format  */
-  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
-  *realResult = (q31_t) (real_sum >> 6);
-  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
-  *imagResult = (q31_t) (imag_sum >> 6);
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
deleted file mode 100644
index 6eeafc10..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_q31.c    
-*    
-* Description:	Q31 complex dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Q31 complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.    
- * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.    
- * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.    
- * The return results realResult and imagResult are in 16.48 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult)
-{
-  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
-  q31_t a0,b0,c0,d0;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-      
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-      a0 = *pSrcA++;
-      b0 = *pSrcA++;
-      c0 = *pSrcB++;
-      d0 = *pSrcB++;  
-  
-      real_sum += ((q63_t)a0 * c0) >> 14;
-      imag_sum += ((q63_t)a0 * d0) >> 14;
-      real_sum -= ((q63_t)b0 * d0) >> 14;
-      imag_sum += ((q63_t)b0 * c0) >> 14;
-
-      /* Decrement the loop counter */
-      numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Store the real and imaginary results in 16.48 format  */
-  *realResult = real_sum;
-  *imagResult = imag_sum;
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
deleted file mode 100644
index 497348b3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_f32.c    
-*    
-* Description:	Floating-point complex magnitude.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @defgroup cmplx_mag Complex Magnitude    
- *    
- * Computes the magnitude of the elements of a complex data vector.    
- *   
- * The pSrc points to the source data and    
- * pDst points to the where the result should be written.    
- * numSamples specifies the number of complex samples    
- * in the input array and the data is stored in an interleaved fashion    
- * (real, imag, real, imag, ...).    
- * The input array has a total of 2*numSamples values;    
- * the output array has a total of numSamples values.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * for(n=0; n    
- *    
- * There are separate functions for floating-point, Q15, and Q31 data types.    
- */
-
-/**    
- * @addtogroup cmplx_mag    
- * @{    
- */
-/**    
- * @brief Floating-point complex magnitude.    
- * @param[in]       *pSrc points to complex input buffer    
- * @param[out]      *pDst points to real output buffer    
- * @param[in]       numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- */
-
-
-void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* out = sqrt((real * real) + (imag * imag)) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of cmplx_mag group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
deleted file mode 100644
index bfe2a5dc..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_q15.c    
-*    
-* Description:	Q15 complex magnitude.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag    
- * @{    
- */
-
-
-/**    
- * @brief  Q15 complex magnitude    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.    
- */
-
-void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t acc2, acc3;
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-    acc0 = __SMUAD(in1, in1);
-    acc1 = __SMUAD(in2, in2);
-    acc2 = __SMUAD(in3, in3);
-    acc3 = __SMUAD(in4, in4);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    acc0 = __SMUAD(in1, in1);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t real, imag;                              /* Temporary variables to hold input values */
-
-  while(numSamples > 0u)
-  {
-    /* out = sqrt(real * real + imag * imag) */
-    real = *pSrc++;
-    imag = *pSrc++;
-
-    acc0 = (real * real);
-    acc1 = (imag * imag);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of cmplx_mag group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
deleted file mode 100644
index 10916739..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_q31.c    
-*    
-* Description:	Q31 complex magnitude    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @addtogroup cmplx_mag        
- * @{        
- */
-
-/**        
- * @brief  Q31 complex magnitude        
- * @param  *pSrc points to the complex input vector        
- * @param  *pDst points to the real output vector        
- * @param  numSamples number of complex samples in the input vector        
- * @return none.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.        
- * Input down scaling is not required.        
- */
-
-void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t real, imag;                              /* Temporary variables to hold input values */
-  q31_t acc0, acc1;                              /* Accumulators */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */
-  q31_t out1, out2, out3, out4;                  /* Accumulators */
-  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* read complex input from source buffer */
-    real1 = pSrc[0];
-    imag1 = pSrc[1];
-    real2 = pSrc[2];
-    imag2 = pSrc[3];
-
-    /* calculate power of input values */
-    mul1 = (q63_t) real1 *real1;
-    mul2 = (q63_t) imag1 *imag1;
-    mul3 = (q63_t) real2 *real2;
-    mul4 = (q63_t) imag2 *imag2;
-
-    /* get the result to 3.29 format */
-    out1 = (q31_t) (mul1 >> 33);
-    out2 = (q31_t) (mul2 >> 33);
-    out3 = (q31_t) (mul3 >> 33);
-    out4 = (q31_t) (mul4 >> 33);
-
-    /* add real and imaginary accumulators */
-    out1 = out1 + out2;
-    out3 = out3 + out4;
-
-    /* read complex input from source buffer */
-    real1 = pSrc[4];
-    imag1 = pSrc[5];
-    real2 = pSrc[6];
-    imag2 = pSrc[7];
-
-    /* calculate square root */
-    arm_sqrt_q31(out1, &pDst[0]);
-
-    /* calculate power of input values */
-    mul1 = (q63_t) real1 *real1;
-
-    /* calculate square root */
-    arm_sqrt_q31(out3, &pDst[1]);
-
-    /* calculate power of input values */
-    mul2 = (q63_t) imag1 *imag1;
-    mul3 = (q63_t) real2 *real2;
-    mul4 = (q63_t) imag2 *imag2;
-
-    /* get the result to 3.29 format */
-    out1 = (q31_t) (mul1 >> 33);
-    out2 = (q31_t) (mul2 >> 33);
-    out3 = (q31_t) (mul3 >> 33);
-    out4 = (q31_t) (mul4 >> 33);
-
-    /* add real and imaginary accumulators */
-    out1 = out1 + out2;
-    out3 = out3 + out4;
-
-    /* calculate square root */
-    arm_sqrt_q31(out1, &pDst[2]);
-
-    /* increment destination by 8 to process next samples */
-    pSrc += 8u;
-
-    /* calculate square root */
-    arm_sqrt_q31(out3, &pDst[3]);
-
-    /* increment destination by 4 to process next samples */
-    pDst += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 2.30 format in the destination buffer. */
-    arm_sqrt_q31(acc0 + acc1, pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_mag group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
deleted file mode 100644
index 5bf3f806..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_f32.c    
-*    
-* Description:	Floating-point complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup cmplx_mag_squared Complex Magnitude Squared        
- *        
- * Computes the magnitude squared of the elements of a complex data vector.        
- *       
- * The pSrc points to the source data and        
- * pDst points to the where the result should be written.        
- * numSamples specifies the number of complex samples        
- * in the input array and the data is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The input array has a total of 2*numSamples values;        
- * the output array has a total of numSamples values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup cmplx_mag_squared        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex magnitude squared        
- * @param[in]  *pSrc points to the complex input vector        
- * @param[out]  *pDst points to the real output vector        
- * @param[in]  numSamples number of complex samples in the input vector        
- * @return none.        
- */
-
-void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */
-  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */
-  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */
-  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */
-  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    /* read real input sample from source buffer */
-    real1 = pSrc[0];
-    /* read imaginary input sample from source buffer */
-    imag1 = pSrc[1];
-
-    /* calculate power of real value */
-    mul1 = real1 * real1;
-
-    /* read real input sample from source buffer */
-    real2 = pSrc[2];
-
-    /* calculate power of imaginary value */
-    mul2 = imag1 * imag1;
-
-    /* read imaginary input sample from source buffer */
-    imag2 = pSrc[3];
-
-    /* calculate power of real value */
-    mul3 = real2 * real2;
-
-    /* read real input sample from source buffer */
-    real3 = pSrc[4];
-
-    /* calculate power of imaginary value */
-    mul4 = imag2 * imag2;
-
-    /* read imaginary input sample from source buffer */
-    imag3 = pSrc[5];
-
-    /* calculate power of real value */
-    mul5 = real3 * real3;
-    /* calculate power of imaginary value */
-    mul6 = imag3 * imag3;
-
-    /* read real input sample from source buffer */
-    real4 = pSrc[6];
-
-    /* accumulate real and imaginary powers */
-    out1 = mul1 + mul2;
-
-    /* read imaginary input sample from source buffer */
-    imag4 = pSrc[7];
-
-    /* accumulate real and imaginary powers */
-    out2 = mul3 + mul4;
-
-    /* calculate power of real value */
-    mul7 = real4 * real4;
-    /* calculate power of imaginary value */
-    mul8 = imag4 * imag4;
-
-    /* store output to destination */
-    pDst[0] = out1;
-
-    /* accumulate real and imaginary powers */
-    out3 = mul5 + mul6;
-
-    /* store output to destination */
-    pDst[1] = out2;
-
-    /* accumulate real and imaginary powers */
-    out4 = mul7 + mul8;
-
-    /* store output to destination */
-    pDst[2] = out3;
-
-    /* increment destination pointer by 8 to process next samples */
-    pSrc += 8u;
-
-    /* store output to destination */
-    pDst[3] = out4;
-
-    /* increment destination pointer by 4 to process next samples */
-    pDst += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-
-    /* out = (real * real) + (imag * imag) */
-    /* store the result in the destination buffer. */
-    *pDst++ = (real * real) + (imag * imag);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_mag_squared group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
deleted file mode 100644
index f5148ba6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_q15.c    
-*    
-* Description:	Q15 complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag_squared    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex magnitude squared    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
- */
-
-void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t acc2, acc3;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-    acc0 = __SMUAD(in1, in1);
-    acc1 = __SMUAD(in2, in2);
-    acc2 = __SMUAD(in3, in3);
-    acc3 = __SMUAD(in4, in4);
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (acc0 >> 17);
-    *pDst++ = (q15_t) (acc1 >> 17);
-    *pDst++ = (q15_t) (acc2 >> 17);
-    *pDst++ = (q15_t) (acc3 >> 17);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    acc0 = __SMUAD(in1, in1);
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (acc0 >> 17);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
-
-  while(numSamples > 0u)
-  {
-    /* out = ((real * real) + (imag * imag)) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (real * real);
-    acc1 = (imag * imag);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of cmplx_mag_squared group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
deleted file mode 100644
index 2cc0b1f3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_q31.c    
-*    
-* Description:	Q31 complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag_squared    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex magnitude squared    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* out = ((real * real) + (imag * imag)) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of cmplx_mag_squared group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
deleted file mode 100644
index bfb7d51c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_f32.c    
-*    
-* Description:	Floating-point complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication        
- *        
- * Multiplies a complex vector by another complex vector and generates a complex result.        
- * The data in the complex arrays is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The parameter numSamples represents the number of complex        
- * samples processed.  The complex arrays have a total of 2*numSamples        
- * real values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup CmplxByCmplxMult        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex-by-complex multiplication        
- * @param[in]  *pSrcA points to the first input vector        
- * @param[in]  *pSrcB points to the second input vector        
- * @param[out]  *pDst  points to the output vector        
- * @param[in]  numSamples number of complex samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counters */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */
-  float32_t acc1, acc2, acc3, acc4;
-
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a1 = *pSrcA;                /* A[2 * i] */
-    c1 = *pSrcB;                /* B[2 * i] */
-
-    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */
-    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */
-
-    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */
-    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */
-
-    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */
-    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */
-    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
-    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */
-    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */
-
-    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */
-    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
-
-    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */
-    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */
-
-    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */
-    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
-    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
-    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */
-    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
-
-    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */
-    acc1 = (a1 * c1);
-
-    d1 = *(pSrcB + 5);
-    acc2 = (b1 * c1);
-
-    *(pDst + 2) = acc3;
-    *(pDst + 3) = acc4;
-
-    a2 = *(pSrcA + 6);
-    acc1 -= (b1 * d1);
-
-    c2 = *(pSrcB + 6);
-    acc2 += (a1 * d1);
-
-    b2 = *(pSrcA + 7);
-    acc3 = (a2 * c2);
-
-    d2 = *(pSrcB + 7);
-    acc4 = (b2 * c2);
-
-    *(pDst + 4) = acc1;
-    pSrcA += 8u;
-
-    acc3 -= (b2 * d2);
-    acc4 += (a2 * d2);
-
-    *(pDst + 5) = acc2;
-    pSrcB += 8u;
-
-    *(pDst + 6) = acc3;
-    *(pDst + 7) = acc4;
-
-    pDst += 8u;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a1 = *pSrcA++;
-    b1 = *pSrcA++;
-    c1 = *pSrcB++;
-    d1 = *pSrcB++;
-
-    /* store the result in the destination buffer. */
-    *pDst++ = (a1 * c1) - (b1 * d1);
-    *pDst++ = (a1 * d1) + (b1 * c1);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of CmplxByCmplxMult group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
deleted file mode 100644
index df6eac05..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_q15.c    
-*    
-* Description:	Q15 complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByCmplxMult    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex-by-complex multiplication    
- * @param[in]  *pSrcA points to the first input vector    
- * @param[in]  *pSrcB points to the second input vector    
- * @param[out]  *pDst  points to the output vector    
- * @param[in]  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
- */
-
-void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of CmplxByCmplxMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
deleted file mode 100644
index ec6b9475..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_q31.c    
-*    
-* Description:	Q31 complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByCmplxMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex-by-complex multiplication    
- * @param[in]  *pSrcA points to the first input vector    
- * @param[in]  *pSrcB points to the second input vector    
- * @param[out]  *pDst  points to the output vector    
- * @param[in]  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t mul1, mul2, mul3, mul4;
-  q31_t out1, out2;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 1u;
-
-  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.     
-   ** a second loop below computes the remaining 1 sample. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.     
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x2u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of CmplxByCmplxMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
deleted file mode 100644
index 04e8ecaa..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_f32.c    
-*    
-* Description:	Floating-point complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup CmplxByRealMult Complex-by-Real Multiplication        
- *        
- * Multiplies a complex vector by a real vector and generates a complex result.        
- * The data in the complex arrays is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The parameter numSamples represents the number of complex        
- * samples processed.  The complex arrays have a total of 2*numSamples        
- * real values while the real array has a total of numSamples        
- * real values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup CmplxByRealMult        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex-by-real multiplication        
- * @param[in]  *pSrcCmplx points to the complex input vector        
- * @param[in]  *pSrcReal points to the real input vector        
- * @param[out]  *pCmplxDst points to the complex output vector        
- * @param[in]  numSamples number of samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  float32_t in;                                  /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counters */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */
-  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */
-  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */
-  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */
-  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read input from complex input buffer */
-    inA1 = pSrcCmplx[0];
-    inA2 = pSrcCmplx[1];
-    /* read input from real input buffer */
-    inB1 = pSrcReal[0];
-
-    /* read input from complex input buffer */
-    inA3 = pSrcCmplx[2];
-
-    /* multiply complex buffer real input with real buffer input */
-    out1 = inA1 * inB1;
-
-    /* read input from complex input buffer */
-    inA4 = pSrcCmplx[3];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out2 = inA2 * inB1;
-
-    /* read input from real input buffer */
-    inB2 = pSrcReal[1];
-    /* read input from complex input buffer */
-    inA5 = pSrcCmplx[4];
-
-    /* multiply complex buffer real input with real buffer input */
-    out3 = inA3 * inB2;
-
-    /* read input from complex input buffer */
-    inA6 = pSrcCmplx[5];
-    /* read input from real input buffer */
-    inB3 = pSrcReal[2];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out4 = inA4 * inB2;
-
-    /* read input from complex input buffer */
-    inA7 = pSrcCmplx[6];
-
-    /* multiply complex buffer real input with real buffer input */
-    out5 = inA5 * inB3;
-
-    /* read input from complex input buffer */
-    inA8 = pSrcCmplx[7];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out6 = inA6 * inB3;
-
-    /* read input from real input buffer */
-    inB4 = pSrcReal[3];
-
-    /* store result to destination bufer */
-    pCmplxDst[0] = out1;
-
-    /* multiply complex buffer real input with real buffer input */
-    out7 = inA7 * inB4;
-
-    /* store result to destination bufer */
-    pCmplxDst[1] = out2;
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out8 = inA8 * inB4;
-
-    /* store result to destination bufer */
-    pCmplxDst[2] = out3;
-    pCmplxDst[3] = out4;
-    pCmplxDst[4] = out5;
-
-    /* incremnet complex input buffer by 8 to process next samples */
-    pSrcCmplx += 8u;
-
-    /* store result to destination bufer */
-    pCmplxDst[5] = out6;
-
-    /* increment real input buffer by 4 to process next samples */
-    pSrcReal += 4u;
-
-    /* store result to destination bufer */
-    pCmplxDst[6] = out7;
-    pCmplxDst[7] = out8;
-
-    /* increment destination buffer by 8 to process next sampels */
-    pCmplxDst += 8u;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ = (*pSrcCmplx++) * (in);
-    *pCmplxDst++ = (*pSrcCmplx++) * (in);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of CmplxByRealMult group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
deleted file mode 100644
index ebf7255d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_q15.c    
-*    
-* Description:	Q15 complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByRealMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q15 complex-by-real multiplication    
- * @param[in]  *pSrcCmplx points to the complex input vector    
- * @param[in]  *pSrcReal points to the real input vector    
- * @param[out]  *pCmplxDst points to the complex output vector    
- * @param[in]  numSamples number of samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  q15_t in;                                      /* Temporary variable to store input value */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t inA1, inA2;                              /* Temporary variables to hold input data */
-  q31_t inB1;                                    /* Temporary variables to hold input data */
-  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
-  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read complex number both real and imaginary from complex input buffer */
-    inA1 = *__SIMD32(pSrcCmplx)++;
-    /* read two real values at a time from real input buffer */
-    inB1 = *__SIMD32(pSrcReal)++;
-    /* read complex number both real and imaginary from complex input buffer */
-    inA2 = *__SIMD32(pSrcCmplx)++;
-
-    /* multiply complex number with real numbers */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
-    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
-    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
-    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* saturate the result */
-    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
-    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
-    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
-    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
-    /* pack real and imaginary outputs and store them to destination */
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
-    inA1 = *__SIMD32(pSrcCmplx)++;
-    inB1 = *__SIMD32(pSrcReal)++;
-    inA2 = *__SIMD32(pSrcCmplx)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
-    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
-    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
-    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
-    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
-    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
-    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut = realA * realB.            */
-    /* imagOut = imagA * realB.                */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
-    /* Decrement the numSamples loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of CmplxByRealMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
deleted file mode 100644
index 73db1077..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_q31.c    
-*    
-* Description:	Q31 complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByRealMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex-by-real multiplication    
- * @param[in]  *pSrcCmplx points to the complex input vector    
- * @param[in]  *pSrcReal points to the real input vector    
- * @param[out]  *pCmplxDst points to the complex output vector    
- * @param[in]  numSamples number of samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
- */
-
-void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  q31_t inA1;                                    /* Temporary variable to store input value */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */
-  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */
-  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-    inB2 = *pSrcReal++;
-    /* read imaginary input from complex input buffer */
-    inA3 = *pSrcCmplx++;
-    inA4 = *pSrcCmplx++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-    out3 = ((q63_t) inA3 * inB2) >> 32;
-    out4 = ((q63_t) inA4 * inB2) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-    out3 = __SSAT(out3, 31);
-    out4 = __SSAT(out4, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-    out3 = out3 << 1;
-    out4 = out4 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-    *pCmplxDst++ = out3;
-    *pCmplxDst++ = out4;
-
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-    inB2 = *pSrcReal++;
-    /* read imaginary input from complex input buffer */
-    inA3 = *pSrcCmplx++;
-    inA4 = *pSrcCmplx++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-    out3 = ((q63_t) inA3 * inB2) >> 32;
-    out4 = ((q63_t) inA4 * inB2) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-    out3 = __SSAT(out3, 31);
-    out4 = __SSAT(out4, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-    out3 = out3 << 1;
-    out4 = out4 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-    *pCmplxDst++ = out3;
-    *pCmplxDst++ = out4;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut = realA * realB.            */
-    /* imagReal = imagA * realB.               */
-    inA1 = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
-    *pCmplxDst++ =
-      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
-
-    /* Decrement the numSamples loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of CmplxByRealMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
deleted file mode 100644
index 2bc1854e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_f32.c    
-*    
-* Description:	Floating-point PID Control initialization function    
-*				   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point PID Control.   
- * @param[in,out] *S points to an instance of the PID structure.   
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.   
- * @return none.   
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag)
-{
-
-  /* Derived coefficient A0 */
-  S->A0 = S->Kp + S->Ki + S->Kd;
-
-  /* Derived coefficient A1 */
-  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
-
-  /* Derived coefficient A2 */
-  S->A2 = S->Kd;
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(float32_t));
-  }
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
deleted file mode 100644
index c163901b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_q15.c    
-*    
-* Description:	Q15 PID Control initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @details    
- * @param[in,out] *S points to an instance of the Q15 PID structure.    
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.    
- * @return none.    
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Derived coefficient A0 */
-  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
-
-  /* Derived coefficients and pack into A1 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
-
-#else
-
-  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q15_t));
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t temp;                                    /*to store the sum */
-
-  /* Derived coefficient A0 */
-  temp = S->Kp + S->Ki + S->Kd;
-  S->A0 = (q15_t) __SSAT(temp, 16);
-
-  /* Derived coefficients and pack into A1 */
-  temp = -(S->Kd + S->Kd + S->Kp);
-  S->A1 = (q15_t) __SSAT(temp, 16);
-  S->A2 = S->Kd;
-
-
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q15_t));
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
deleted file mode 100644
index 012e8732..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_q31.c    
-*    
-* Description:	Q31 PID Control initialization function     
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q31 PID Control.   
- * @param[in,out] *S points to an instance of the Q31 PID structure.   
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
- * @return none.    
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Derived coefficient A0 */
-  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
-
-  /* Derived coefficient A1 */
-  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t temp;
-
-  /* Derived coefficient A0 */
-  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
-  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
-
-  /* Derived coefficient A1 */
-  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
-  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Derived coefficient A2 */
-  S->A2 = S->Kd;
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q31_t));
-  }
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
deleted file mode 100644
index 081cf0cd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_f32.c    
-*    
-* Description:	Floating-point PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the floating-point PID Control.   
-* @param[in] *S	Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S)
-{
-
-  /* Clear the state buffer.  The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(float32_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
deleted file mode 100644
index 4dfe4198..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_q15.c    
-*    
-* Description:	Q15 PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the Q15 PID Control.   
-* @param[in] *S		Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S)
-{
-  /* Reset state to zero, The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(q15_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
deleted file mode 100644
index 540a54a5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_q31.c    
-*    
-* Description:	Q31 PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the Q31 PID Control.   
-* @param[in] *S	Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S)
-{
-
-  /* Clear the state buffer.  The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(q31_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
deleted file mode 100644
index 37d63a8b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_cos_f32.c    
-*    
-* Description:	Sine and Cosine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupController    
- */
-
-/**    
- * @defgroup SinCos Sine Cosine   
- *    
- * Computes the trigonometric sine and cosine values using a combination of table lookup   
- * and linear interpolation.     
- * There are separate functions for Q31 and floating-point data types.   
- * The input to the floating-point version is in degrees while the   
- * fixed-point Q31 have a scaled input with the range   
- * [-1 0.9999] mapping to [-180 +180] degrees.   
- *
- * The floating point function also allows values that are out of the usual range. When this happens, the function will
- * take extra time to adjust the input value to the range of [-180 180].
- *   
- * The implementation is based on table lookup using 360 values together with linear interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index.   
- *  -# Compute the fractional portion (fract) of the input.   
- *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.      
- *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).    
- *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.      
- *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).    
- */
-
- /**    
- * @addtogroup SinCos    
- * @{    
- */
-
-/**    
- * @brief  Floating-point sin_cos function.   
- * @param[in]  theta    input value in degrees    
- * @param[out] *pSinVal points to the processed sine output.    
- * @param[out] *pCosVal points to the processed cos output.    
- * @return none.   
- */
-
-void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal)
-{
-  float32_t fract, in;                             /* Temporary variables for input, output */
-  uint16_t indexS, indexC;                         /* Index variable */
-  float32_t f1, f2, d1, d2;                        /* Two nearest output values */
-  int32_t n;
-  float32_t findex, Dn, Df, temp;
-
-  /* input x is in degrees */
-  /* Scale the input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
-  in = theta * 0.00277777777778f;
-
-  /* Calculation of floor value of input */
-  n = (int32_t) in;
-
-  /* Make negative values towards -infinity */
-  if(in < 0.0f)
-  {
-    n--;
-  }
-  /* Map input value to [0 1] */
-  in = in - (float32_t) n;
-
-  /* Calculation of index of the table */
-  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
-  indexS = ((uint16_t)findex) & 0x1ff;
-  indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
-
-  /* fractional value calculation */
-  fract = findex - (float32_t) indexS;
-
-  /* Read two nearest values of input value from the cos & sin tables */
-  f1 = sinTable_f32[indexC+0];
-  f2 = sinTable_f32[indexC+1];
-  d1 = -sinTable_f32[indexS+0];
-  d2 = -sinTable_f32[indexS+1];
-
-  Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
-  Df = f2 - f1; // delta between the values of the functions
-  temp = Dn*(d1 + d2) - 2*Df;
-  temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
-  temp = fract*temp + d1*Dn;
-
-  /* Calculation of cosine value */
-  *pCosVal = fract*temp + f1;
-  
-  /* Read two nearest values of input value from the cos & sin tables */
-  f1 = sinTable_f32[indexS+0];
-  f2 = sinTable_f32[indexS+1];
-  d1 = sinTable_f32[indexC+0];
-  d2 = sinTable_f32[indexC+1];
-
-  Df = f2 - f1; // delta between the values of the functions
-  temp = Dn*(d1 + d2) - 2*Df;
-  temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn);
-  temp = fract*temp + d1*Dn;
-  
-  /* Calculation of sine value */
-  *pSinVal = fract*temp + f1;
-}
-/**    
- * @} end of SinCos group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
deleted file mode 100644
index 5e11b0f9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_cos_q31.c    
-*    
-* Description:	Cosine & Sine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupController    
- */
-
- /**    
- * @addtogroup SinCos    
- * @{    
- */
-
-/**    
- * @brief  Q31 sin_cos function.   
- * @param[in]  theta    scaled input value in degrees    
- * @param[out] *pSinVal points to the processed sine output.    
- * @param[out] *pCosVal points to the processed cosine output.    
- * @return none.   
- *    
- * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].   
- *    
- */
-
-void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal)
-{
-  q31_t fract;                                 /* Temporary variables for input, output */
-  uint16_t indexS, indexC;                     /* Index variable */
-  q31_t f1, f2, d1, d2;                        /* Two nearest output values */
-  q31_t Dn, Df;
-  q63_t temp;
-  
-  /* Calculate the nearest index */
-  indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
-  indexC = (indexS + 128) & 0x1ff;
-
-  /* Calculation of fractional value */
-  fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
-  
-  /* Read two nearest values of input value from the cos & sin tables */
-  f1 = sinTable_q31[indexC+0];
-  f2 = sinTable_q31[indexC+1];
-  d1 = -sinTable_q31[indexS+0];
-  d2 = -sinTable_q31[indexS+1];
-
-  Dn = 0x1921FB5; // delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE
-  Df = f2 - f1; // delta between the values of the functions
-  temp = Dn*((q63_t)d1 + d2);
-  temp = temp - ((q63_t)Df << 32);
-  temp = (q63_t)fract*(temp >> 31);
-  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
-  temp = (q63_t)fract*(temp >> 31);
-  temp = temp + (q63_t)d1*Dn;
-  temp = (q63_t)fract*(temp >> 31);
-
-  /* Calculation of cosine value */
-  *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
-  
-  /* Read two nearest values of input value from the cos & sin tables */
-  f1 = sinTable_q31[indexS+0];
-  f2 = sinTable_q31[indexS+1];
-  d1 = sinTable_q31[indexC+0];
-  d2 = sinTable_q31[indexC+1];
-
-  Df = f2 - f1; // delta between the values of the functions
-  temp = Dn*((q63_t)d1 + d2);
-  temp = temp - ((q63_t)Df << 32);
-  temp = (q63_t)fract*(temp >> 31);
-  temp = temp + ((3*(q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1))*Dn);
-  temp = (q63_t)fract*(temp >> 31);
-  temp = temp + (q63_t)d1*Dn;
-  temp = (q63_t)fract*(temp >> 31);
-  
-  /* Calculation of sine value */
-  *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
-}
-
-/**    
- * @} end of SinCos group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
deleted file mode 100644
index a6d977bf..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_f32.c    
-*    
-* Description:	Fast cosine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-/**    
- * @ingroup groupFastMath    
- */
-
-/**    
- * @defgroup cos Cosine    
- *    
- * Computes the trigonometric cosine function using a combination of table lookup   
- * and cubic interpolation.  There are separate functions for   
- * Q15, Q31, and floating-point data types.   
- * The input to the floating-point version is in radians while the   
- * fixed-point Q15 and Q31 have a scaled input with the range   
- * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
- * value of 2*pi wraps around to 0.
- *   
- * The implementation is based on table lookup using 256 values together with cubic interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index   
- *  -# Fetch the four table values a, b, c, and d     
- *  -# Compute the fractional portion (fract) of the table index.   
- *  -# Calculation of wa, wb, wc, wd    
- *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
- *   
- * where   
- * 
    
- *    a=Table[index-1];    
- *    b=Table[index+0];    
- *    c=Table[index+1];    
- *    d=Table[index+2];    
- * 
   
- * and   
- * 
    
- *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
- *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
- *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
- *    wd=(1/6)*fract.^3 - (1/6)*fract;    
- * 
    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-/**   
- * @brief  Fast approximation to the trigonometric cosine function for floating-point data.   
- * @param[in] x input value in radians.   
- * @return cos(x).   
- */
-
-float32_t arm_cos_f32(
-  float32_t x)
-{
-  float32_t cosVal, fract, in;                   /* Temporary variables for input, output */
-  uint16_t index;                                /* Index variable */
-  float32_t a, b;                                /* Two nearest output values */
-  int32_t n;
-  float32_t findex;
-
-  /* input x is in radians */
-  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */
-  in = x * 0.159154943092f + 0.25f;
-
-  /* Calculation of floor value of input */
-  n = (int32_t) in;
-
-  /* Make negative values towards -infinity */
-  if(in < 0.0f)
-  {
-    n--;
-  }
-
-  /* Map input value to [0 1] */
-  in = in - (float32_t) n;
-
-  /* Calculation of index of the table */
-  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
-  index = ((uint16_t)findex) & 0x1ff;
-
-  /* fractional value calculation */
-  fract = findex - (float32_t) index;
-
-  /* Read two nearest values of input value from the cos table */
-  a = sinTable_f32[index];
-  b = sinTable_f32[index+1];
-
-  /* Linear interpolation process */
-  cosVal = (1.0f-fract)*a + fract*b;
-
-  /* Return the output value */
-  return (cosVal);
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
deleted file mode 100644
index d46a70a7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_q15.c    
-*    
-* Description:	Fast cosine calculation for Q15 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-/**   
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  cos(x).   
- *   
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
- * value in the range [0 2*pi).
- */
-
-q15_t arm_cos_q15(
-  q15_t x)
-{
-  q15_t sinVal;                                  /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variables */
-  q15_t a, b;                                    /* Four nearest output values */
-  q15_t fract;                                   /* Temporary values for fractional values */
-
-  /* add 0.25 (pi/2) to read sine table */
-  x += 0x2000;
-  if(x < 0)
-  {   /* convert negative numbers to corresponding positive ones */
-      x = x + 0x8000;
-  }
-
-  /* Calculate the nearest index */
-  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
-
-  /* Calculation of fractional value */
-  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
-
-  /* Read two nearest values of input value from the sin table */
-  a = sinTable_q15[index];
-  b = sinTable_q15[index+1];
-
-  /* Linear interpolation process */
-  sinVal = (q31_t)(0x8000-fract)*a >> 16;
-  sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
-
-  return sinVal << 1;
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
deleted file mode 100644
index 6c1f280f..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_q31.c    
-*    
-* Description:	Fast cosine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-/**   
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  cos(x).   
- *   
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
- * value in the range [0 2*pi).
- */
-
-q31_t arm_cos_q31(
-  q31_t x)
-{
-  q31_t cosVal;                                  /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variables */
-  q31_t a, b;                                    /* Four nearest output values */
-  q31_t fract;                                   /* Temporary values for fractional values */
-
-  /* add 0.25 (pi/2) to read sine table */
-  x += 0x20000000;
-  if(x < 0)
-  {   /* convert negative numbers to corresponding positive ones */
-      x = x + 0x80000000;
-  }
-  
-  /* Calculate the nearest index */
-  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
-
-  /* Calculation of fractional value */
-  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
-
-  /* Read two nearest values of input value from the sin table */
-  a = sinTable_q31[index];
-  b = sinTable_q31[index+1];
-
-  /* Linear interpolation process */
-  cosVal = (q63_t)(0x80000000-fract)*a >> 32;
-  cosVal = (q31_t)((((q63_t)cosVal << 32) + ((q63_t)fract*b)) >> 32);
-
-  return cosVal << 1;
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
deleted file mode 100644
index c6a609a4..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_f32.c    
-*    
-* Description:	Fast sine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
-/**    
- * @defgroup sin Sine    
- *    
- * Computes the trigonometric sine function using a combination of table lookup   
- * and cubic interpolation.  There are separate functions for   
- * Q15, Q31, and floating-point data types.   
- * The input to the floating-point version is in radians while the   
- * fixed-point Q15 and Q31 have a scaled input with the range   
- * [0 +0.9999] mapping to [0 2*pi).  The fixed-point range is chosen so that a
- * value of 2*pi wraps around to 0.
- *   
- * The implementation is based on table lookup using 256 values together with cubic interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index   
- *  -# Fetch the four table values a, b, c, and d     
- *  -# Compute the fractional portion (fract) of the table index.   
- *  -# Calculation of wa, wb, wc, wd    
- *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
- *   
- * where   
- * 
    
- *    a=Table[index-1];    
- *    b=Table[index+0];    
- *    c=Table[index+1];    
- *    d=Table[index+2];    
- * 
   
- * and   
- * 
    
- *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
- *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
- *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
- *    wd=(1/6)*fract.^3 - (1/6)*fract;    
- * 
    
- */
-
-/**    
- * @addtogroup sin    
- * @{    
- */
-
-/**   
- * @brief  Fast approximation to the trigonometric sine function for floating-point data.   
- * @param[in] x input value in radians.   
- * @return  sin(x).   
- */
-
-float32_t arm_sin_f32(
-  float32_t x)
-{
-  float32_t sinVal, fract, in;                           /* Temporary variables for input, output */
-  uint16_t index;                                        /* Index variable */
-  float32_t a, b;                                        /* Two nearest output values */
-  int32_t n;
-  float32_t findex;
-
-  /* input x is in radians */
-  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
-  in = x * 0.159154943092f;
-
-  /* Calculation of floor value of input */
-  n = (int32_t) in;
-
-  /* Make negative values towards -infinity */
-  if(x < 0.0f)
-  {
-    n--;
-  }
-
-  /* Map input value to [0 1] */
-  in = in - (float32_t) n;
-
-  /* Calculation of index of the table */
-  findex = (float32_t) FAST_MATH_TABLE_SIZE * in;
-  index = ((uint16_t)findex) & 0x1ff;
-
-  /* fractional value calculation */
-  fract = findex - (float32_t) index;
-
-  /* Read two nearest values of input value from the sin table */
-  a = sinTable_f32[index];
-  b = sinTable_f32[index+1];
-
-  /* Linear interpolation process */
-  sinVal = (1.0f-fract)*a + fract*b;
-
-  /* Return the output value */
-  return (sinVal);
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
deleted file mode 100644
index e2209b39..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_q15.c    
-*    
-* Description:	Fast sine calculation for Q15 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup sin    
- * @{    
- */
-
-/**   
- * @brief Fast approximation to the trigonometric sine function for Q15 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  sin(x).   
- *   
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
- */
-
-q15_t arm_sin_q15(
-  q15_t x)
-{
-  q15_t sinVal;                                  /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variables */
-  q15_t a, b;                                    /* Four nearest output values */
-  q15_t fract;                                   /* Temporary values for fractional values */
-
-  /* Calculate the nearest index */
-  index = (uint32_t)x >> FAST_MATH_Q15_SHIFT;
-
-  /* Calculation of fractional value */
-  fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9;
-
-  /* Read two nearest values of input value from the sin table */
-  a = sinTable_q15[index];
-  b = sinTable_q15[index+1];
-
-  /* Linear interpolation process */
-  sinVal = (q31_t)(0x8000-fract)*a >> 16;
-  sinVal = (q15_t)((((q31_t)sinVal << 16) + ((q31_t)fract*b)) >> 16);
-
-  return sinVal << 1;
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
deleted file mode 100644
index 606ab66d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_q31.c    
-*    
-* Description:	Fast sine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup sin    
- * @{    
- */
-
-/**   
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return  sin(x).
- *
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
-
-q31_t arm_sin_q31(
-  q31_t x)
-{
-  q31_t sinVal;                                  /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variables */
-  q31_t a, b;                                    /* Four nearest output values */
-  q31_t fract;                                   /* Temporary values for fractional values */
-
-  /* Calculate the nearest index */
-  index = (uint32_t)x >> FAST_MATH_Q31_SHIFT;
-
-  /* Calculation of fractional value */
-  fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9;
-
-  /* Read two nearest values of input value from the sin table */
-  a = sinTable_q31[index];
-  b = sinTable_q31[index+1];
-
-  /* Linear interpolation process */
-  sinVal = (q63_t)(0x80000000-fract)*a >> 32;
-  sinVal = (q31_t)((((q63_t)sinVal << 32) + ((q63_t)fract*b)) >> 32);
-
-  return sinVal << 1;
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
deleted file mode 100644
index 28180125..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* ----------------------------------------------------------------------     
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
-*     
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*     
-* Project:      CMSIS DSP Library  
-* Title:		arm_sqrt_q15.c     
-*     
-* Description:	Q15 square root function.    
-*     
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-
-/**     
- * @ingroup groupFastMath     
- */
-
-/**     
- * @addtogroup SQRT     
- * @{     
- */
-
-  /**    
-   * @brief  Q15 square root function.    
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.    
-   * @param[out]  *pOut  square root of input value.    
-   * @return The function returns ARM_MATH_SUCCESS if the input value is positive
-   * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
-   * negative inputs, the function returns *pOut = 0.
-   */
-
-arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut)
-{
-  q15_t number, temp1, var1, signBits1, half;
-  q31_t bits_val1;
-  float32_t temp_float1;
-  union
-  {
-    q31_t fracval;
-    float32_t floatval;
-  } tempconv;
-
-  number = in;
-
-  /* If the input is a positive number then compute the signBits. */
-  if(number > 0)
-  {
-    signBits1 = __CLZ(number) - 17;
-
-    /* Shift by the number of signBits1 */
-    if((signBits1 % 2) == 0)
-    {
-      number = number << signBits1;
-    }
-    else
-    {
-      number = number << (signBits1 - 1);
-    }
-
-    /* Calculate half value of the number */
-    half = number >> 1;
-    /* Store the number for later use */
-    temp1 = number;
-
-    /*Convert to float */
-    temp_float1 = number * 3.051757812500000e-005f;
-    /*Store as integer */
-    tempconv.floatval = temp_float1;
-    bits_val1 = tempconv.fracval;
-    /* Subtract the shifted value from the magic number to give intial guess */
-    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
-    /* Store as float */
-    tempconv.fracval = bits_val1;
-    temp_float1 = tempconv.floatval;
-    /* Convert to integer format */
-    var1 = (q31_t) (temp_float1 * 16384);
-
-    /* 1st iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-    /* 2nd iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-    /* 3rd iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-
-    /* Multiply the inverse square root with the original value */
-    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
-
-    /* Shift the output down accordingly */
-    if((signBits1 % 2) == 0)
-    {
-      var1 = var1 >> (signBits1 / 2);
-    }
-    else
-    {
-      var1 = var1 >> ((signBits1 - 1) / 2);
-    }
-    *pOut = var1;
-
-    return (ARM_MATH_SUCCESS);
-  }
-  /* If the number is a negative number then store zero as its square root value */
-  else
-  {
-    *pOut = 0;
-    return (ARM_MATH_ARGUMENT_ERROR);
-  }
-}
-
-/**     
- * @} end of SQRT group     
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
deleted file mode 100644
index 34b77549..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------     
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
-*     
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*     
-* Project:      CMSIS DSP Library  
-* Title:		arm_sqrt_q31.c     
-*     
-* Description:	Q31 square root function.    
-*     
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**     
- * @ingroup groupFastMath     
- */
-
-/**     
- * @addtogroup SQRT     
- * @{     
- */
-
-/**    
- * @brief Q31 square root function.    
- * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.    
- * @param[out]  *pOut square root of input value.    
- * @return The function returns ARM_MATH_SUCCESS if the input value is positive
- * and ARM_MATH_ARGUMENT_ERROR if the input is negative.  For
- * negative inputs, the function returns *pOut = 0.
- */
-
-arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut)
-{
-  q31_t number, temp1, bits_val1, var1, signBits1, half;
-  float32_t temp_float1;
-  union
-  {
-      q31_t fracval;
-      float32_t floatval;
-  } tempconv;
-
-  number = in;
-
-  /* If the input is a positive number then compute the signBits. */
-  if(number > 0)
-  {
-    signBits1 = __CLZ(number) - 1;
-
-    /* Shift by the number of signBits1 */
-    if((signBits1 % 2) == 0)
-    {
-      number = number << signBits1;
-    }
-    else
-    {
-      number = number << (signBits1 - 1);
-    }
-
-    /* Calculate half value of the number */
-    half = number >> 1;
-    /* Store the number for later use */
-    temp1 = number;
-
-    /*Convert to float */
-    temp_float1 = number * 4.6566128731e-010f;
-    /*Store as integer */
-    tempconv.floatval = temp_float1;
-    bits_val1 = tempconv.fracval;
-    /* Subtract the shifted value from the magic number to give intial guess */
-    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
-    /* Store as float */
-    tempconv.fracval = bits_val1;
-    temp_float1 = tempconv.floatval;
-    /* Convert to integer format */
-    var1 = (q31_t) (temp_float1 * 1073741824);
-
-    /* 1st iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-    /* 2nd iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-    /* 3rd iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-
-    /* Multiply the inverse square root with the original value */
-    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
-
-    /* Shift the output down accordingly */
-    if((signBits1 % 2) == 0)
-    {
-      var1 = var1 >> (signBits1 / 2);
-    }
-    else
-    {
-      var1 = var1 >> ((signBits1 - 1) / 2);
-    }
-    *pOut = var1;
-
-    return (ARM_MATH_SUCCESS);
-  }
-  /* If the number is a negative number then store zero as its square root value */
-  else
-  {
-    *pOut = 0;
-    return (ARM_MATH_ARGUMENT_ERROR);
-  }
-}
-
-/**     
- * @} end of SQRT group     
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
deleted file mode 100644
index 9f4ab2ff..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c    
-*    
-* Description:	High precision Q31 Biquad cascade filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1_32x64    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.    
- * @param[in]     numStages     number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs      points to the filter coefficients.    
- * @param[in]     *pState       points to the state buffer.    
- * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState points to state variables array and size of each state variable is 1.63 format.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the state array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1_32x64 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
deleted file mode 100644
index 886d422c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_32x64_q31.c    
-*    
-* Description:	High precision Q31 Biquad cascade filter processing function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter    
- *    
- * This function implements a high precision Biquad cascade filter which operates on    
- * Q31 data values.  The filter coefficients are in 1.31 format and the state variables    
- * are in 1.63 format.  The double precision state variables reduce quantization noise    
- * in the filter and provide a cleaner output.    
- * These filters are particularly useful when implementing filters in which the    
- * singularities are close to the unit circle.  This is common for low pass or high    
- * pass filters with very low cutoff frequencies.    
- *    
- * The function operates on blocks of input and output data    
- * and each call to the function processes blockSize samples through    
- * the filter. pSrc and pDst points to input and output arrays    
- * containing blockSize Q31 values.    
- *    
- * \par Algorithm    
- * Each Biquad stage implements a second order filter using the difference equation:    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
- * 
    
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
- * \image html Biquad.gif "Single Biquad filter stage"    
- * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
- * Pay careful attention to the sign of the feedback coefficients.    
- * Some design tools use the difference equation    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
- * 
    
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
- *    
- * \par    
- * Higher order filters are realized as a cascade of second order sections.    
- * numStages refers to the number of second order stages used.    
- * For example, an 8th order filter would be realized with numStages=4 second order stages.    
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
- *    
- * \par    
- * The pState points to state variables array .    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.    
- * The state variables are arranged in the array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- *    
- * \par    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values of data in 1.63 format.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- *    
- * \par Init Function    
- * There is also an associated initialization function which performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. 
- *
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * For example, to statically initialize the filter instance structure use    
- * 
    
- *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    
- * 
    
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.    
- * \par Fixed-Point Behavior    
- * Care must be taken while using Biquad Cascade 32x64 filter function.    
- * Following issues must be considered:    
- * - Scaling of coefficients    
- * - Filter gain    
- * - Overflow and saturation    
- *    
- * \par    
- * Filter coefficients are represented as fractional values and    
- * restricted to lie in the range [-1 +1).    
- * The processing function has an additional scaling parameter postShift    
- * which allows the filter coefficients to exceed the range [+1 -1).    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
- * This essentially scales the filter coefficients by 2^postShift.    
- * For example, to realize the coefficients    
- * 
    
- *    {1.5, -0.8, 1.2, 1.6, -0.9}    
- * 
    
- * set the Coefficient array to:    
- * 
    
- *    {0.75, -0.4, 0.6, 0.8, -0.45}    
- * 
    
- * and set postShift=1    
- *    
- * \par    
- * The second thing to keep in mind is the gain through the filter.    
- * The frequency response of a Biquad filter is a function of its coefficients.    
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
- *    
- * \par    
- * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.    
- * This is described in the function specific documentation below.    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1_32x64    
- * @{    
- */
-
-/**    
- * @details    
-    
- * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
- * 1.31 format by discarding the low 32 bits.    
- *    
- * \par    
- * Two related functions are provided in the CMSIS DSP library.    
- * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.    
- * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.    
- */
-
-void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q63_t *pState = S->pState;                     /*  state pointer initialization  */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q63_t acc;                                     /*  accumulator                   */
-  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */
-  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t Xn;                                      /*  temporary input               */
-  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-  q31_t acc_l, acc_h;                            /*  temporary output               */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = (q31_t) (pState[0]);
-    Xn2 = (q31_t) (pState[1]);
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /* The variable acc hold output value that is being computed and    
-     * stored in the destination buffer    
-     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* The result is converted to 1.63 , Yn2 variable is reused */
-      Yn2 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut = acc_h;
-
-      /* Read the second input into Xn2, to reuse the value */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc +=  b1 * x[n-1] */
-      acc = (q63_t) Xn *b1;
-
-      /* acc =  b0 * x[n] */
-      acc += (q63_t) Xn2 *b0;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn1 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn2, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn1, a2);
-
-      /* The result is converted to 1.63, Yn1 variable is reused */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Read the third input into Xn1, to reuse the value */
-      Xn1 = *pIn++;
-
-      /* The result is converted to 1.31 */
-      /* Store the output in the destination buffer. */
-      *(pOut + 1u) = acc_h;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn1 *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn2 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* The result is converted to 1.63, Yn2 variable is reused  */
-      Yn2 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *(pOut + 2u) = acc_h;
-
-      /* Read the fourth input into Xn, to reuse the value */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn2, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn1, a2);
-
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *(pOut + 3u) = acc_h;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* update output pointer */
-      pOut += 4u;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut++ = acc_h;
-      //Yn1 = acc << shift; 
-
-      /* Store the output in the destination buffer in 1.31 format. */
-//      *pOut++ = (q31_t) (acc >> (32 - shift)); 
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage output is given as input to the second stage. */
-    pIn = pDst;
-
-    /* Reset to destination buffer working pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = (q63_t) Xn1;
-    *pState++ = (q63_t) Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* The variable acc hold output value that is being computed and        
-     * stored in the destination buffer            
-     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]            
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut++ = acc_h;
-
-      //Yn1 = acc << shift; 
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      //*pOut++ = (q31_t) (acc >> (32 - shift)); 
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage output is given as input to the second stage. */
-    pIn = pDst;
-
-    /* Reset to destination buffer working pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = (q63_t) Xn1;
-    *pState++ = (q63_t) Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*    #ifndef ARM_MATH_CM0_FAMILY     */
-}
-
-  /**    
-   * @} end of BiquadCascadeDF1_32x64 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
deleted file mode 100644
index 83e9f767..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_f32.c    
-*    
-* Description:	Processing function for the    
-*               floating-point Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure    
- *    
- * This set of functions implements arbitrary order recursive (IIR) filters.    
- * The filters are implemented as a cascade of second order Biquad sections.    
- * The functions support Q15, Q31 and floating-point data types.  
- * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.    
- *    
- * The functions operate on blocks of input and output data and each call to the function    
- * processes blockSize samples through the filter.    
- * pSrc points to the array of input data and    
- * pDst points to the array of output data.    
- * Both arrays contain blockSize values.    
- *    
- * \par Algorithm    
- * Each Biquad stage implements a second order filter using the difference equation:    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
- * 
    
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
- * \image html Biquad.gif "Single Biquad filter stage"    
- * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
- * Pay careful attention to the sign of the feedback coefficients.    
- * Some design tools use the difference equation    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
- * 
    
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
- *    
- * \par    
- * Higher order filters are realized as a cascade of second order sections.    
- * numStages refers to the number of second order stages used.    
- * For example, an 8th order filter would be realized with numStages=4 second order stages.    
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
- *    
- * \par    
- * The pState points to state variables array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- *    
- * \par    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Init Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    
- *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    
- *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    
- * 
    
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.    
- * Following issues must be considered:    
- * - Scaling of coefficients    
- * - Filter gain    
- * - Overflow and saturation    
- *    
- * \par    
- * Scaling of coefficients:     
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift    
- * which allow the filter coefficients to exceed the range [+1 -1).    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
- * This essentially scales the filter coefficients by 2^postShift.    
- * For example, to realize the coefficients    
- * 
    
- *    {1.5, -0.8, 1.2, 1.6, -0.9}    
- * 
    
- * set the pCoeffs array to:    
- * 
    
- *    {0.75, -0.4, 0.6, 0.8, -0.45}    
- * 
    
- * and set postShift=1    
- *    
- * \par    
- * Filter gain:     
- * The frequency response of a Biquad filter is a function of its coefficients.    
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
- *    
- * \par    
- * Overflow and saturation:     
- * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.    
- * @param[in]  *pSrc      points to the block of input data.    
- * @param[out] *pDst      points to the block of output data.    
- * @param[in]  blockSize  number of samples to process per call.    
- * @return     none.    
- *    
- */
-
-void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /*  source pointer            */
-  float32_t *pOut = pDst;                        /*  destination pointer       */
-  float32_t *pState = S->pState;                 /*  pState pointer            */
-  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-  float32_t acc;                                 /*  Simulates the accumulator */
-  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
-  float32_t Xn;                                  /*  temporary input           */
-  uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the pState values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the first input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the second input */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the third input */
-      Xn1 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as: */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the forth input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = blockSize & 0x3u;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:    */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* decrement the loop counter */
-      sample--;
-
-    }
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent numStages  occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the pState values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:        
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]        
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:    */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent numStages  occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY         */
-
-}
-
-
-  /**    
-   * @} end of BiquadCascadeDF1 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
deleted file mode 100644
index a637b037..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_fast_q15.c    
-*    
-* Description:	Fast processing function for the    
-*				Q15 Biquad cascade filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).    
- * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.    
- *    
- */
-
-void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q31_t in;                                      /*  Temporary variable to hold input value       */
-  q31_t out;                                     /*  Temporary variable to hold output value      */
-  q31_t b0;                                      /*  Temporary variable to hold bo value          */
-  q31_t b1, a1;                                  /*  Filter coefficients                          */
-  q31_t state_in, state_out;                     /*  Filter state variables                       */
-  q31_t acc;                                     /*  Accumulator                                  */
-  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
-
-
-
-  do
-  {
-
-    /* Read the b0 and 0 coefficients using SIMD  */
-    b0 = *__SIMD32(pCoeffs)++;
-
-    /* Read the b1 and b2 coefficients using SIMD */
-    b1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the a1 and a2 coefficients using SIMD */
-    a1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
-    state_in = *__SIMD32(pState)++;
-
-    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
-    state_out = *__SIMD32(pState)--;
-
-    /* Apply loop unrolling and compute 2 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:       
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     */
-    sample = blockSize >> 1u;
-
-    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
-     ** a second loop below computes the remaining 1 sample. */
-    while(sample > 0u)
-    {
-
-      /* Read the input */
-      in = *__SIMD32(pIn)++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUAD(b0, in);
-      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
-      state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUADX(b0, in);
-      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-
-      /* Store the output in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in >> 16, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-      /* Decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-
-    if((blockSize & 0x1u) != 0u)
-    {
-      /* Read the input */
-      in = *pIn++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      out = __SMUAD(b0, in);
-
-#else
-
-      out = __SMUADX(b0, in);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) out;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer.  */
-    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the state array */
-    *__SIMD32(pState)++ = state_in;
-    *__SIMD32(pState)++ = state_out;
-
-
-    /* Decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-}
-
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
deleted file mode 100644
index ff3cddf2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_fast_q31.c    
-*    
-* Description:	Processing function for the    
-*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return 	   none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function    
- * arm_biquad_cascade_df1_init_q31() to initialize filter structure.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.    
- */
-
-void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t acc = 0;                                 /*  accumulator                   */
-  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q31_t *pState = S->pState;                     /*  pState pointer initialization */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q31_t Xn;                                      /*  temporary input               */
-  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variables acc ... acc3 hold output values that are being computed:       
-     *       
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
-      mult_32x32_keep32_R(acc, b1, Xn1);
-      /* acc +=  b1 * x[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);   
-      multAcc_32x32_keep32_R(acc, b0, Xn);
-      /* acc +=  b[2] * x[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, b2, Xn2);
-      /* acc +=  a1 * y[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, a1, Yn1);
-      /* acc +=  a2 * y[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, a2, Yn2);
-
-      /* The result is converted to 1.31 , Yn2 variable is reused */
-      Yn2 = acc << shift;
-
-      /* Read the second input */
-      Xn2 = *(pIn + 1u);
-
-      /* Store the output in the destination buffer. */
-      *pOut = Yn2;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
-      mult_32x32_keep32_R(acc, b0, Xn2);
-      /* acc +=  b1 * x[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
-      multAcc_32x32_keep32_R(acc, b1, Xn);
-      /* acc +=  b[2] * x[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, b2, Xn1);
-      /* acc +=  a1 * y[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, a1, Yn2);
-      /* acc +=  a2 * y[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, a2, Yn1);
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Read the third input  */
-      Xn1 = *(pIn + 2u);
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 1u) = Yn1;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
-      mult_32x32_keep32_R(acc, b0, Xn1);
-      /* acc +=  b1 * x[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, b1, Xn2);
-      /* acc +=  b[2] * x[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
-      multAcc_32x32_keep32_R(acc, b2, Xn);
-      /* acc +=  a1 * y[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, a1, Yn1);
-      /* acc +=  a2 * y[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, a2, Yn2);
-
-      /* The result is converted to 1.31, Yn2 variable is reused  */
-      Yn2 = acc << shift;
-
-      /* Read the forth input */
-      Xn = *(pIn + 3u);
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 2u) = Yn2;
-      pIn += 4u;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
-      mult_32x32_keep32_R(acc, b0, Xn);
-      /* acc +=  b1 * x[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, b1, Xn1);
-      /* acc +=  b[2] * x[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, b2, Xn2);
-      /* acc +=  a1 * y[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, a1, Yn2);
-      /* acc +=  a2 * y[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, a2, Yn1);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      Xn2 = Xn1;
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Xn1 = Xn     */
-      Xn1 = Xn;
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 3u) = Yn1;
-      pOut += 4u;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-   while(sample > 0u)
-   {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
-      mult_32x32_keep32_R(acc, b0, Xn);
-      /* acc +=  b1 * x[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, b1, Xn1);
-      /* acc +=  b[2] * x[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, b2, Xn2);
-      /* acc +=  a1 * y[n-1] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      multAcc_32x32_keep32_R(acc, a1, Yn1);
-      /* acc +=  a2 * y[n-2] */
-      //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-      multAcc_32x32_keep32_R(acc, a2, Yn2);
-
-      /* The result is converted to 1.31  */
-      acc = acc << shift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = acc;
-
-      /* decrement the loop counter */
-      sample--;
-   }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-}
-
-/**    
-  * @} end of BiquadCascadeDF1 group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
deleted file mode 100644
index fab57d6d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df1_init_f32.c    
-*    
-* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- * @brief  Initialization function for the floating-point Biquad cascade filter.    
- * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients array.    
- * @param[in]     *pState      points to the state array.    
- * @return        none    
- *    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- *    
- */
-
-void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
deleted file mode 100644
index 0dbb6d1c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df1_init_q15.c    
-*    
-* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients.    
- * @param[in]     *pState      points to the state buffer.    
- * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 6*numStages values.    
- * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.    
- *    
- * \par    
- * The state variables are stored in the array pState.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
deleted file mode 100644
index 96ae6f9f..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_init_q31.c    
-*    
-* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients buffer.    
- * @param[in]     *pState      points to the state buffer.    
- * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState points to state variables array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
deleted file mode 100644
index 8cfc5340..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_q15.c    
-*    
-* Description:	Processing function for the    
-*				Q15 Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 Biquad cascade filter.    
- * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the location where the output result is written.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return none.    
- *    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.    
- * Finally, the result is saturated to 1.15 format.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q31_t in;                                      /*  Temporary variable to hold input value       */
-  q31_t out;                                     /*  Temporary variable to hold output value      */
-  q31_t b0;                                      /*  Temporary variable to hold bo value          */
-  q31_t b1, a1;                                  /*  Filter coefficients                          */
-  q31_t state_in, state_out;                     /*  Filter state variables                       */
-  q31_t acc_l, acc_h;
-  q63_t acc;                                     /*  Accumulator                                  */
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
-  int32_t uShift = (32 - lShift);
-
-  do
-  {
-    /* Read the b0 and 0 coefficients using SIMD  */
-    b0 = *__SIMD32(pCoeffs)++;
-
-    /* Read the b1 and b2 coefficients using SIMD */
-    b1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the a1 and a2 coefficients using SIMD */
-    a1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
-    state_in = *__SIMD32(pState)++;
-
-    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
-    state_out = *__SIMD32(pState)--;
-
-    /* Apply loop unrolling and compute 2 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-    sample = blockSize >> 1u;
-
-    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
-     ** a second loop below computes the remaining 1 sample. */
-    while(sample > 0u)
-    {
-
-      /* Read the input */
-      in = *__SIMD32(pIn)++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUAD(b0, in);
-
-      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
-      state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUADX(b0, in);
-      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Store the output in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in >> 16, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-      /* Decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-
-    if((blockSize & 0x1u) != 0u)
-    {
-      /* Read the input */
-      in = *pIn++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      out = __SMUAD(b0, in);
-
-#else
-
-      out = __SMUADX(b0, in);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) out;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    }
-
-    /*  The first stage goes from the input wire to the output wire.  */
-    /*  Subsequent numStages occur in-place in the output wire  */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the state array */
-    *__SIMD32(pState)++ = state_in;
-    *__SIMD32(pState)++ = state_out;
-
-
-    /* Decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q15_t Xn;                                      /*  temporary input               */
-  q63_t acc;                                     /*  Accumulator                                  */
-  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    pCoeffs++;  // skip the 0 coefficient
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:         
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) b0 *Xn;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q31_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q31_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q31_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q31_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = __SSAT((acc >> shift), 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q15_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*     #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
deleted file mode 100644
index 35f2124b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_q31.c    
-*    
-* Description:	Processing function for the    
-*				Q31 Biquad cascade filter    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 Biquad cascade filter.    
- * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]  *pSrc      points to the block of input data.    
- * @param[out] *pDst      points to the block of output data.    
- * @param[in]  blockSize  number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
- * 1.31 format by discarding the low 32 bits.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q63_t acc;                                     /*  accumulator                   */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q31_t *pState = S->pState;                     /*  pState pointer initialization */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t Xn;                                      /*  temporary input               */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-
-
-#ifndef ARM_MATH_CM0_FAMILY_FAMILY
-
-  q31_t acc_l, acc_h;                            /*  temporary output variables    */
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31 , Yn2 variable is reused */
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Read the second input */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn2;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn1;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn2;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn1;
-
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Read the third input  */
-      Xn1 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn1;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn2;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31, Yn2 variable is reused  */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Read the forth input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn2;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn1;
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = acc >> lShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q31_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q31_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:         
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = acc >> lShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q31_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q31_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*  #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
-}
-
-
-
-
-/**    
-  * @} end of BiquadCascadeDF1 group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
deleted file mode 100644
index fc15e3cc..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+++ /dev/null
@@ -1,603 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df2T_f32.c    
-*    
-* Description:  Processing function for the floating-point transposed    
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
-* @ingroup groupFilters       
-*/
-
-/**       
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
-*       
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
-* The filters are implemented as a cascade of second order Biquad sections.       
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
-* Only floating-point data is supported.       
-*       
-* This function operate on blocks of input and output data and each call to the function       
-* processes blockSize samples through the filter.       
-* pSrc points to the array of input data and       
-* pDst points to the array of output data.       
-* Both arrays contain blockSize values.       
-*       
-* \par Algorithm       
-* Each Biquad stage implements a second order filter using the difference equation:       
-* 
       
-*    y[n] = b0 * x[n] + d1       
-*    d1 = b1 * x[n] + a1 * y[n] + d2       
-*    d2 = b2 * x[n] + a2 * y[n]       
-* 
       
-* where d1 and d2 represent the two state values.       
-*       
-* \par       
-* A Biquad filter using a transposed Direct Form II structure is shown below.       
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
-* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       
-* Pay careful attention to the sign of the feedback coefficients.       
-* Some design tools flip the sign of the feedback coefficients:       
-* 
       
-*    y[n] = b0 * x[n] + d1;       
-*    d1 = b1 * x[n] - a1 * y[n] + d2;       
-*    d2 = b2 * x[n] - a2 * y[n];       
-* 
       
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       
-*       
-* \par       
-* Higher order filters are realized as a cascade of second order sections.       
-* numStages refers to the number of second order stages used.       
-* For example, an 8th order filter would be realized with numStages=4 second order stages.       
-* A 9th order filter would be realized with numStages=5 second order stages with the       
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       
-*       
-* \par       
-* pState points to the state variable array.       
-* Each Biquad stage has 2 state variables d1 and d2.       
-* The state variables are arranged in the pState array as:       
-* 
       
-*     {d11, d12, d21, d22, ...}       
-* 
       
-* where d1x refers to the state variables for the first Biquad and       
-* d2x refers to the state variables for the second Biquad.       
-* The state array has a total length of 2*numStages values.       
-* The state variables are updated after each block of data is processed; the coefficients are untouched.       
-*       
-* \par       
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
-* That is why the Direct Form I structure supports Q15 and Q31 data types.    
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
-*       
-* \par Instance Structure       
-* The coefficients and state variables for a filter are stored together in an instance data structure.       
-* A separate instance structure must be defined for each filter.       
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
-*       
-* \par Init Functions       
-* There is also an associated initialization function.      
-* The initialization function performs following operations:       
-* - Sets the values of the internal structure fields.       
-* - Zeros out the values in the state buffer.       
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
-*       
-* \par       
-* Use of the initialization function is optional.       
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
-* To place an instance structure into a const data section, the instance structure must be manually initialized.       
-* Set the values in the state buffer to zeros before static initialization.       
-* For example, to statically initialize the instance structure use       
-* 
       
-*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
-* 
       
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       
-* pCoeffs is the address of the coefficient buffer;        
-*       
-*/
-
-/**       
-* @addtogroup BiquadCascadeDF2T       
-* @{       
-*/
-
-/**      
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
-* @param[in]  *S        points to an instance of the filter data structure.      
-* @param[in]  *pSrc     points to the block of input data.      
-* @param[out] *pDst     points to the block of output data      
-* @param[in]  blockSize number of samples to process.      
-* @return none.      
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_df2T_f32(
-const arm_biquad_cascade_df2T_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-
-   float32_t *pIn = pSrc;                         /*  source pointer            */
-   float32_t *pOut = pDst;                        /*  destination pointer       */
-   float32_t *pState = S->pState;                 /*  State pointer             */
-   float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-   float32_t acc1;                                /*  accumulator               */
-   float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-   float32_t Xn1;                                 /*  temporary input           */
-   float32_t d1, d2;                              /*  state variables           */
-   uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-#if defined(ARM_MATH_CM7)
-	
-   float32_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
-   float32_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
-   float32_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
-   float32_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
-
-   do
-   {
-      /* Reading the coefficients */ 
-      b0 = pCoeffs[0]; 
-      b1 = pCoeffs[1]; 
-      b2 = pCoeffs[2]; 
-      a1 = pCoeffs[3]; 
-      /* Apply loop unrolling and compute 16 output values simultaneously. */ 
-      sample = blockSize >> 4u; 
-      a2 = pCoeffs[4]; 
-
-      /*Reading the state values */ 
-      d1 = pState[0]; 
-      d2 = pState[1]; 
-
-      pCoeffs += 5u;
-
-      
-      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.       
-       ** a second loop below computes the remaining 1 to 15 samples. */
-      while(sample > 0u) {
-
-         /* y[n] = b0 * x[n] + d1 */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         /* d2 = b2 * x[n] + a2 * y[n] */
-
-         /* Read the first 2 inputs. 2 cycles */
-         Xn1  = pIn[0 ];
-         Xn2  = pIn[1 ];
-
-         /* Sample 1. 5 cycles */
-         Xn3  = pIn[2 ];
-         acc1 = b0 * Xn1 + d1;
-         
-         Xn4  = pIn[3 ];
-         d1 = b1 * Xn1 + d2;
-         
-         Xn5  = pIn[4 ];
-         d2 = b2 * Xn1;
-         
-         Xn6  = pIn[5 ];
-         d1 += a1 * acc1;
-         
-         Xn7  = pIn[6 ];
-         d2 += a2 * acc1;
-
-         /* Sample 2. 5 cycles */
-         Xn8  = pIn[7 ];
-         acc2 = b0 * Xn2 + d1;
-         
-         Xn9  = pIn[8 ];
-         d1 = b1 * Xn2 + d2;
-         
-         Xn10 = pIn[9 ];
-         d2 = b2 * Xn2;
-         
-         Xn11 = pIn[10];
-         d1 += a1 * acc2;
-         
-         Xn12 = pIn[11];
-         d2 += a2 * acc2;
-
-         /* Sample 3. 5 cycles */
-         Xn13 = pIn[12];
-         acc3 = b0 * Xn3 + d1;
-         
-         Xn14 = pIn[13];
-         d1 = b1 * Xn3 + d2;
-         
-         Xn15 = pIn[14];
-         d2 = b2 * Xn3;
-         
-         Xn16 = pIn[15];
-         d1 += a1 * acc3;
-         
-         pIn += 16;
-         d2 += a2 * acc3;
-
-         /* Sample 4. 5 cycles */
-         acc4 = b0 * Xn4 + d1;
-         d1 = b1 * Xn4 + d2;
-         d2 = b2 * Xn4;
-         d1 += a1 * acc4;
-         d2 += a2 * acc4;
-
-         /* Sample 5. 5 cycles */
-         acc5 = b0 * Xn5 + d1;
-         d1 = b1 * Xn5 + d2;
-         d2 = b2 * Xn5;
-         d1 += a1 * acc5;
-         d2 += a2 * acc5;
-
-         /* Sample 6. 5 cycles */
-         acc6 = b0 * Xn6 + d1;
-         d1 = b1 * Xn6 + d2;
-         d2 = b2 * Xn6;
-         d1 += a1 * acc6;
-         d2 += a2 * acc6;
-
-         /* Sample 7. 5 cycles */
-         acc7 = b0 * Xn7 + d1;
-         d1 = b1 * Xn7 + d2;
-         d2 = b2 * Xn7;
-         d1 += a1 * acc7;
-         d2 += a2 * acc7;
-
-         /* Sample 8. 5 cycles */
-         acc8 = b0 * Xn8 + d1;
-         d1 = b1 * Xn8 + d2;
-         d2 = b2 * Xn8;
-         d1 += a1 * acc8;
-         d2 += a2 * acc8;
-
-         /* Sample 9. 5 cycles */
-         acc9 = b0 * Xn9 + d1;
-         d1 = b1 * Xn9 + d2;
-         d2 = b2 * Xn9;
-         d1 += a1 * acc9;
-         d2 += a2 * acc9;
-
-         /* Sample 10. 5 cycles */
-         acc10 = b0 * Xn10 + d1;
-         d1 = b1 * Xn10 + d2;
-         d2 = b2 * Xn10;
-         d1 += a1 * acc10;
-         d2 += a2 * acc10;
-
-         /* Sample 11. 5 cycles */
-         acc11 = b0 * Xn11 + d1;
-         d1 = b1 * Xn11 + d2;
-         d2 = b2 * Xn11;
-         d1 += a1 * acc11;
-         d2 += a2 * acc11;
-
-         /* Sample 12. 5 cycles */
-         acc12 = b0 * Xn12 + d1;
-         d1 = b1 * Xn12 + d2;
-         d2 = b2 * Xn12;
-         d1 += a1 * acc12;
-         d2 += a2 * acc12;
-
-         /* Sample 13. 5 cycles */
-         acc13 = b0 * Xn13 + d1;         
-         d1 = b1 * Xn13 + d2;         
-         d2 = b2 * Xn13;
-         
-         pOut[0 ] = acc1 ;
-         d1 += a1 * acc13;
-         
-         pOut[1 ] = acc2 ;	
-         d2 += a2 * acc13;
-
-         /* Sample 14. 5 cycles */
-         pOut[2 ] = acc3 ;	
-         acc14 = b0 * Xn14 + d1;
-             
-         pOut[3 ] = acc4 ;
-         d1 = b1 * Xn14 + d2;
-          
-         pOut[4 ] = acc5 ; 
-         d2 = b2 * Xn14;
-         
-         pOut[5 ] = acc6 ;	  
-         d1 += a1 * acc14;
-         
-         pOut[6 ] = acc7 ;	
-         d2 += a2 * acc14;
-
-         /* Sample 15. 5 cycles */
-         pOut[7 ] = acc8 ;
-         pOut[8 ] = acc9 ;  
-         acc15 = b0 * Xn15 + d1;
-              
-         pOut[9 ] = acc10;	
-         d1 = b1 * Xn15 + d2;
-         
-         pOut[10] = acc11;	
-         d2 = b2 * Xn15;
-         
-         pOut[11] = acc12;
-         d1 += a1 * acc15;
-         
-         pOut[12] = acc13;
-         d2 += a2 * acc15;
-
-         /* Sample 16. 5 cycles */
-         pOut[13] = acc14;	
-         acc16 = b0 * Xn16 + d1;
-         
-         pOut[14] = acc15;	
-         d1 = b1 * Xn16 + d2;
-         
-         pOut[15] = acc16;
-         d2 = b2 * Xn16;
-         
-         sample--;	 
-         d1 += a1 * acc16;
-         
-         pOut += 16;
-         d2 += a2 * acc16;
-      }
-
-      sample = blockSize & 0xFu;
-      while(sample > 0u) {
-         Xn1 = *pIn;         
-         acc1 = b0 * Xn1 + d1;
-         
-         pIn++;
-         d1 = b1 * Xn1 + d2;
-         
-         *pOut = acc1; 
-         d2 = b2 * Xn1;
-         
-         pOut++;
-         d1 += a1 * acc1;
-         
-         sample--;	
-         d2 += a2 * acc1; 
-      }
-
-      /* Store the updated state variables back into the state array */ 
-      pState[0] = d1; 
-      /* The current stage input is given as the output to the next stage */ 
-      pIn = pDst; 
-      
-      pState[1] = d2; 
-      /* decrement the loop counter */ 
-      stage--; 
-
-      pState += 2u;
-
-      /*Reset the output working pointer */ 
-      pOut = pDst; 
-
-   } while(stage > 0u);
-	
-#elif defined(ARM_MATH_CM0_FAMILY)
-
-   /* Run the below code for Cortex-M0 */
-
-   do
-   {
-      /* Reading the coefficients */
-      b0 = *pCoeffs++;
-      b1 = *pCoeffs++;
-      b2 = *pCoeffs++;
-      a1 = *pCoeffs++;
-      a2 = *pCoeffs++;
-
-      /*Reading the state values */
-      d1 = pState[0];
-      d2 = pState[1];
-
-
-      sample = blockSize;
-
-      while(sample > 0u)
-      {
-         /* Read the input */
-         Xn1 = *pIn++;
-
-         /* y[n] = b0 * x[n] + d1 */
-         acc1 = (b0 * Xn1) + d1;
-
-         /* Store the result in the accumulator in the destination buffer. */
-         *pOut++ = acc1;
-
-         /* Every time after the output is computed state should be updated. */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
-
-         /* d2 = b2 * x[n] + a2 * y[n] */
-         d2 = (b2 * Xn1) + (a2 * acc1);
-
-         /* decrement the loop counter */
-         sample--;
-      }
-
-      /* Store the updated state variables back into the state array */
-      *pState++ = d1;
-      *pState++ = d2;
-
-      /* The current stage input is given as the output to the next stage */
-      pIn = pDst;
-
-      /*Reset the output working pointer */
-      pOut = pDst;
-
-      /* decrement the loop counter */
-      stage--;
-
-   } while(stage > 0u);
-	 
-#else
-
-   float32_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
-   float32_t acc2, acc3, acc4;              		  /*  accumulator               */
-
-
-   float32_t p0, p1, p2, p3, p4, A1;
-
-   /* Run the below code for Cortex-M4 and Cortex-M3 */
-   do
-   {
-      /* Reading the coefficients */     
-      b0 = *pCoeffs++;
-      b1 = *pCoeffs++;
-      b2 = *pCoeffs++;
-      a1 = *pCoeffs++;
-      a2 = *pCoeffs++;
-      
-
-      /*Reading the state values */
-      d1 = pState[0];
-      d2 = pState[1];
-
-      /* Apply loop unrolling and compute 4 output values simultaneously. */
-      sample = blockSize >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-   ** a second loop below computes the remaining 1 to 3 samples. */
-      while(sample > 0u) {
-
-         /* y[n] = b0 * x[n] + d1 */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         /* d2 = b2 * x[n] + a2 * y[n] */
-
-         /* Read the four inputs */
-         Xn1 = pIn[0];
-         Xn2 = pIn[1];
-         Xn3 = pIn[2];
-         Xn4 = pIn[3];
-         pIn += 4;     
-
-         p0 = b0 * Xn1; 
-         p1 = b1 * Xn1;
-         acc1 = p0 + d1;
-         p0 = b0 * Xn2; 
-         p3 = a1 * acc1;
-         p2 = b2 * Xn1;
-         A1 = p1 + p3;
-         p4 = a2 * acc1;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         p1 = b1 * Xn2;
-         acc2 = p0 + d1;
-         p0 = b0 * Xn3;	 
-         p3 = a1 * acc2; 
-         p2 = b2 * Xn2;                                 
-         A1 = p1 + p3;
-         p4 = a2 * acc2;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         p1 = b1 * Xn3;
-         acc3 = p0 + d1;
-         p0 = b0 * Xn4;	
-         p3 = a1 * acc3;
-         p2 = b2 * Xn3;
-         A1 = p1 + p3;
-         p4 = a2 * acc3;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         acc4 = p0 + d1;
-         p1 = b1 * Xn4;
-         p3 = a1 * acc4;
-         p2 = b2 * Xn4;
-         A1 = p1 + p3;
-         p4 = a2 * acc4;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         pOut[0] = acc1;	
-         pOut[1] = acc2;	
-         pOut[2] = acc3;	
-         pOut[3] = acc4;
-		 pOut += 4;
-				 
-         sample--;	       
-      }
-
-      sample = blockSize & 0x3u;
-      while(sample > 0u) {
-         Xn1 = *pIn++;
-
-         p0 = b0 * Xn1; 
-         p1 = b1 * Xn1;
-         acc1 = p0 + d1;
-         p3 = a1 * acc1;
-         p2 = b2 * Xn1;
-         A1 = p1 + p3;
-         p4 = a2 * acc1;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-	
-         *pOut++ = acc1;
-         
-         sample--;	       
-      }
-
-      /* Store the updated state variables back into the state array */
-      *pState++ = d1;
-      *pState++ = d2;
-
-      /* The current stage input is given as the output to the next stage */
-      pIn = pDst;
-
-      /*Reset the output working pointer */
-      pOut = pDst;
-
-      /* decrement the loop counter */
-      stage--;
-
-   } while(stage > 0u);
-
-#endif 
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**       
-   * @} end of BiquadCascadeDF2T group       
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
deleted file mode 100644
index 265bd3a5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
+++ /dev/null
@@ -1,603 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df2T_f64.c    
-*    
-* Description:  Processing function for the floating-point transposed    
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
-* @ingroup groupFilters       
-*/
-
-/**       
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
-*       
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
-* The filters are implemented as a cascade of second order Biquad sections.       
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
-* Only floating-point data is supported.       
-*       
-* This function operate on blocks of input and output data and each call to the function       
-* processes blockSize samples through the filter.       
-* pSrc points to the array of input data and       
-* pDst points to the array of output data.       
-* Both arrays contain blockSize values.       
-*       
-* \par Algorithm       
-* Each Biquad stage implements a second order filter using the difference equation:       
-* 
       
-*    y[n] = b0 * x[n] + d1       
-*    d1 = b1 * x[n] + a1 * y[n] + d2       
-*    d2 = b2 * x[n] + a2 * y[n]       
-* 
       
-* where d1 and d2 represent the two state values.       
-*       
-* \par       
-* A Biquad filter using a transposed Direct Form II structure is shown below.       
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
-* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       
-* Pay careful attention to the sign of the feedback coefficients.       
-* Some design tools flip the sign of the feedback coefficients:       
-* 
       
-*    y[n] = b0 * x[n] + d1;       
-*    d1 = b1 * x[n] - a1 * y[n] + d2;       
-*    d2 = b2 * x[n] - a2 * y[n];       
-* 
       
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       
-*       
-* \par       
-* Higher order filters are realized as a cascade of second order sections.       
-* numStages refers to the number of second order stages used.       
-* For example, an 8th order filter would be realized with numStages=4 second order stages.       
-* A 9th order filter would be realized with numStages=5 second order stages with the       
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       
-*       
-* \par       
-* pState points to the state variable array.       
-* Each Biquad stage has 2 state variables d1 and d2.       
-* The state variables are arranged in the pState array as:       
-* 
       
-*     {d11, d12, d21, d22, ...}       
-* 
       
-* where d1x refers to the state variables for the first Biquad and       
-* d2x refers to the state variables for the second Biquad.       
-* The state array has a total length of 2*numStages values.       
-* The state variables are updated after each block of data is processed; the coefficients are untouched.       
-*       
-* \par       
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
-* That is why the Direct Form I structure supports Q15 and Q31 data types.    
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
-*       
-* \par Instance Structure       
-* The coefficients and state variables for a filter are stored together in an instance data structure.       
-* A separate instance structure must be defined for each filter.       
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
-*       
-* \par Init Functions       
-* There is also an associated initialization function.      
-* The initialization function performs following operations:       
-* - Sets the values of the internal structure fields.       
-* - Zeros out the values in the state buffer.       
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
-*       
-* \par       
-* Use of the initialization function is optional.       
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
-* To place an instance structure into a const data section, the instance structure must be manually initialized.       
-* Set the values in the state buffer to zeros before static initialization.       
-* For example, to statically initialize the instance structure use       
-* 
       
-*     arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};       
-* 
       
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       
-* pCoeffs is the address of the coefficient buffer;        
-*       
-*/
-
-/**       
-* @addtogroup BiquadCascadeDF2T       
-* @{       
-*/
-
-/**      
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
-* @param[in]  *S        points to an instance of the filter data structure.      
-* @param[in]  *pSrc     points to the block of input data.      
-* @param[out] *pDst     points to the block of output data      
-* @param[in]  blockSize number of samples to process.      
-* @return none.      
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_df2T_f64(
-const arm_biquad_cascade_df2T_instance_f64 * S,
-float64_t * pSrc,
-float64_t * pDst,
-uint32_t blockSize)
-{
-
-   float64_t *pIn = pSrc;                         /*  source pointer            */
-   float64_t *pOut = pDst;                        /*  destination pointer       */
-   float64_t *pState = S->pState;                 /*  State pointer             */
-   float64_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-   float64_t acc1;                                /*  accumulator               */
-   float64_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-   float64_t Xn1;                                 /*  temporary input           */
-   float64_t d1, d2;                              /*  state variables           */
-   uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-#if defined(ARM_MATH_CM7)
-	
-   float64_t Xn2, Xn3, Xn4, Xn5, Xn6, Xn7, Xn8;   /*  Input State variables     */
-   float64_t Xn9, Xn10, Xn11, Xn12, Xn13, Xn14, Xn15, Xn16;
-   float64_t acc2, acc3, acc4, acc5, acc6, acc7;  /*  Simulates the accumulator */
-   float64_t acc8, acc9, acc10, acc11, acc12, acc13, acc14, acc15, acc16;
-
-   do
-   {
-      /* Reading the coefficients */ 
-      b0 = pCoeffs[0]; 
-      b1 = pCoeffs[1]; 
-      b2 = pCoeffs[2]; 
-      a1 = pCoeffs[3]; 
-      /* Apply loop unrolling and compute 16 output values simultaneously. */ 
-      sample = blockSize >> 4u; 
-      a2 = pCoeffs[4]; 
-
-      /*Reading the state values */ 
-      d1 = pState[0]; 
-      d2 = pState[1]; 
-
-      pCoeffs += 5u;
-
-      
-      /* First part of the processing with loop unrolling.  Compute 16 outputs at a time.       
-       ** a second loop below computes the remaining 1 to 15 samples. */
-      while(sample > 0u) {
-
-         /* y[n] = b0 * x[n] + d1 */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         /* d2 = b2 * x[n] + a2 * y[n] */
-
-         /* Read the first 2 inputs. 2 cycles */
-         Xn1  = pIn[0 ];
-         Xn2  = pIn[1 ];
-
-         /* Sample 1. 5 cycles */
-         Xn3  = pIn[2 ];
-         acc1 = b0 * Xn1 + d1;
-         
-         Xn4  = pIn[3 ];
-         d1 = b1 * Xn1 + d2;
-         
-         Xn5  = pIn[4 ];
-         d2 = b2 * Xn1;
-         
-         Xn6  = pIn[5 ];
-         d1 += a1 * acc1;
-         
-         Xn7  = pIn[6 ];
-         d2 += a2 * acc1;
-
-         /* Sample 2. 5 cycles */
-         Xn8  = pIn[7 ];
-         acc2 = b0 * Xn2 + d1;
-         
-         Xn9  = pIn[8 ];
-         d1 = b1 * Xn2 + d2;
-         
-         Xn10 = pIn[9 ];
-         d2 = b2 * Xn2;
-         
-         Xn11 = pIn[10];
-         d1 += a1 * acc2;
-         
-         Xn12 = pIn[11];
-         d2 += a2 * acc2;
-
-         /* Sample 3. 5 cycles */
-         Xn13 = pIn[12];
-         acc3 = b0 * Xn3 + d1;
-         
-         Xn14 = pIn[13];
-         d1 = b1 * Xn3 + d2;
-         
-         Xn15 = pIn[14];
-         d2 = b2 * Xn3;
-         
-         Xn16 = pIn[15];
-         d1 += a1 * acc3;
-         
-         pIn += 16;
-         d2 += a2 * acc3;
-
-         /* Sample 4. 5 cycles */
-         acc4 = b0 * Xn4 + d1;
-         d1 = b1 * Xn4 + d2;
-         d2 = b2 * Xn4;
-         d1 += a1 * acc4;
-         d2 += a2 * acc4;
-
-         /* Sample 5. 5 cycles */
-         acc5 = b0 * Xn5 + d1;
-         d1 = b1 * Xn5 + d2;
-         d2 = b2 * Xn5;
-         d1 += a1 * acc5;
-         d2 += a2 * acc5;
-
-         /* Sample 6. 5 cycles */
-         acc6 = b0 * Xn6 + d1;
-         d1 = b1 * Xn6 + d2;
-         d2 = b2 * Xn6;
-         d1 += a1 * acc6;
-         d2 += a2 * acc6;
-
-         /* Sample 7. 5 cycles */
-         acc7 = b0 * Xn7 + d1;
-         d1 = b1 * Xn7 + d2;
-         d2 = b2 * Xn7;
-         d1 += a1 * acc7;
-         d2 += a2 * acc7;
-
-         /* Sample 8. 5 cycles */
-         acc8 = b0 * Xn8 + d1;
-         d1 = b1 * Xn8 + d2;
-         d2 = b2 * Xn8;
-         d1 += a1 * acc8;
-         d2 += a2 * acc8;
-
-         /* Sample 9. 5 cycles */
-         acc9 = b0 * Xn9 + d1;
-         d1 = b1 * Xn9 + d2;
-         d2 = b2 * Xn9;
-         d1 += a1 * acc9;
-         d2 += a2 * acc9;
-
-         /* Sample 10. 5 cycles */
-         acc10 = b0 * Xn10 + d1;
-         d1 = b1 * Xn10 + d2;
-         d2 = b2 * Xn10;
-         d1 += a1 * acc10;
-         d2 += a2 * acc10;
-
-         /* Sample 11. 5 cycles */
-         acc11 = b0 * Xn11 + d1;
-         d1 = b1 * Xn11 + d2;
-         d2 = b2 * Xn11;
-         d1 += a1 * acc11;
-         d2 += a2 * acc11;
-
-         /* Sample 12. 5 cycles */
-         acc12 = b0 * Xn12 + d1;
-         d1 = b1 * Xn12 + d2;
-         d2 = b2 * Xn12;
-         d1 += a1 * acc12;
-         d2 += a2 * acc12;
-
-         /* Sample 13. 5 cycles */
-         acc13 = b0 * Xn13 + d1;         
-         d1 = b1 * Xn13 + d2;         
-         d2 = b2 * Xn13;
-         
-         pOut[0 ] = acc1 ;
-         d1 += a1 * acc13;
-         
-         pOut[1 ] = acc2 ;	
-         d2 += a2 * acc13;
-
-         /* Sample 14. 5 cycles */
-         pOut[2 ] = acc3 ;	
-         acc14 = b0 * Xn14 + d1;
-             
-         pOut[3 ] = acc4 ;
-         d1 = b1 * Xn14 + d2;
-          
-         pOut[4 ] = acc5 ; 
-         d2 = b2 * Xn14;
-         
-         pOut[5 ] = acc6 ;	  
-         d1 += a1 * acc14;
-         
-         pOut[6 ] = acc7 ;	
-         d2 += a2 * acc14;
-
-         /* Sample 15. 5 cycles */
-         pOut[7 ] = acc8 ;
-         pOut[8 ] = acc9 ;  
-         acc15 = b0 * Xn15 + d1;
-              
-         pOut[9 ] = acc10;	
-         d1 = b1 * Xn15 + d2;
-         
-         pOut[10] = acc11;	
-         d2 = b2 * Xn15;
-         
-         pOut[11] = acc12;
-         d1 += a1 * acc15;
-         
-         pOut[12] = acc13;
-         d2 += a2 * acc15;
-
-         /* Sample 16. 5 cycles */
-         pOut[13] = acc14;	
-         acc16 = b0 * Xn16 + d1;
-         
-         pOut[14] = acc15;	
-         d1 = b1 * Xn16 + d2;
-         
-         pOut[15] = acc16;
-         d2 = b2 * Xn16;
-         
-         sample--;	 
-         d1 += a1 * acc16;
-         
-         pOut += 16;
-         d2 += a2 * acc16;
-      }
-
-      sample = blockSize & 0xFu;
-      while(sample > 0u) {
-         Xn1 = *pIn;         
-         acc1 = b0 * Xn1 + d1;
-         
-         pIn++;
-         d1 = b1 * Xn1 + d2;
-         
-         *pOut = acc1; 
-         d2 = b2 * Xn1;
-         
-         pOut++;
-         d1 += a1 * acc1;
-         
-         sample--;	
-         d2 += a2 * acc1; 
-      }
-
-      /* Store the updated state variables back into the state array */ 
-      pState[0] = d1; 
-      /* The current stage input is given as the output to the next stage */ 
-      pIn = pDst; 
-      
-      pState[1] = d2; 
-      /* decrement the loop counter */ 
-      stage--; 
-
-      pState += 2u;
-
-      /*Reset the output working pointer */ 
-      pOut = pDst; 
-
-   } while(stage > 0u);
-	
-#elif defined(ARM_MATH_CM0_FAMILY)
-
-   /* Run the below code for Cortex-M0 */
-
-   do
-   {
-      /* Reading the coefficients */
-      b0 = *pCoeffs++;
-      b1 = *pCoeffs++;
-      b2 = *pCoeffs++;
-      a1 = *pCoeffs++;
-      a2 = *pCoeffs++;
-
-      /*Reading the state values */
-      d1 = pState[0];
-      d2 = pState[1];
-
-
-      sample = blockSize;
-
-      while(sample > 0u)
-      {
-         /* Read the input */
-         Xn1 = *pIn++;
-
-         /* y[n] = b0 * x[n] + d1 */
-         acc1 = (b0 * Xn1) + d1;
-
-         /* Store the result in the accumulator in the destination buffer. */
-         *pOut++ = acc1;
-
-         /* Every time after the output is computed state should be updated. */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
-
-         /* d2 = b2 * x[n] + a2 * y[n] */
-         d2 = (b2 * Xn1) + (a2 * acc1);
-
-         /* decrement the loop counter */
-         sample--;
-      }
-
-      /* Store the updated state variables back into the state array */
-      *pState++ = d1;
-      *pState++ = d2;
-
-      /* The current stage input is given as the output to the next stage */
-      pIn = pDst;
-
-      /*Reset the output working pointer */
-      pOut = pDst;
-
-      /* decrement the loop counter */
-      stage--;
-
-   } while(stage > 0u);
-	 
-#else
-
-   float64_t Xn2, Xn3, Xn4;                  	  /*  Input State variables     */
-   float64_t acc2, acc3, acc4;              		  /*  accumulator               */
-
-
-   float64_t p0, p1, p2, p3, p4, A1;
-
-   /* Run the below code for Cortex-M4 and Cortex-M3 */
-   do
-   {
-      /* Reading the coefficients */     
-      b0 = *pCoeffs++;
-      b1 = *pCoeffs++;
-      b2 = *pCoeffs++;
-      a1 = *pCoeffs++;
-      a2 = *pCoeffs++;
-      
-
-      /*Reading the state values */
-      d1 = pState[0];
-      d2 = pState[1];
-
-      /* Apply loop unrolling and compute 4 output values simultaneously. */
-      sample = blockSize >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-   ** a second loop below computes the remaining 1 to 3 samples. */
-      while(sample > 0u) {
-
-         /* y[n] = b0 * x[n] + d1 */
-         /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-         /* d2 = b2 * x[n] + a2 * y[n] */
-
-         /* Read the four inputs */
-         Xn1 = pIn[0];
-         Xn2 = pIn[1];
-         Xn3 = pIn[2];
-         Xn4 = pIn[3];
-         pIn += 4;     
-
-         p0 = b0 * Xn1; 
-         p1 = b1 * Xn1;
-         acc1 = p0 + d1;
-         p0 = b0 * Xn2; 
-         p3 = a1 * acc1;
-         p2 = b2 * Xn1;
-         A1 = p1 + p3;
-         p4 = a2 * acc1;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         p1 = b1 * Xn2;
-         acc2 = p0 + d1;
-         p0 = b0 * Xn3;	 
-         p3 = a1 * acc2; 
-         p2 = b2 * Xn2;                                 
-         A1 = p1 + p3;
-         p4 = a2 * acc2;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         p1 = b1 * Xn3;
-         acc3 = p0 + d1;
-         p0 = b0 * Xn4;	
-         p3 = a1 * acc3;
-         p2 = b2 * Xn3;
-         A1 = p1 + p3;
-         p4 = a2 * acc3;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         acc4 = p0 + d1;
-         p1 = b1 * Xn4;
-         p3 = a1 * acc4;
-         p2 = b2 * Xn4;
-         A1 = p1 + p3;
-         p4 = a2 * acc4;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-
-         pOut[0] = acc1;	
-         pOut[1] = acc2;	
-         pOut[2] = acc3;	
-         pOut[3] = acc4;
-				 pOut += 4;
-				 
-         sample--;	       
-      }
-
-      sample = blockSize & 0x3u;
-      while(sample > 0u) {
-         Xn1 = *pIn++;
-
-         p0 = b0 * Xn1; 
-         p1 = b1 * Xn1;
-         acc1 = p0 + d1;
-         p3 = a1 * acc1;
-         p2 = b2 * Xn1;
-         A1 = p1 + p3;
-         p4 = a2 * acc1;
-         d1 = A1 + d2;
-         d2 = p2 + p4;
-	
-         *pOut++ = acc1;
-         
-         sample--;	       
-      }
-
-      /* Store the updated state variables back into the state array */
-      *pState++ = d1;
-      *pState++ = d2;
-
-      /* The current stage input is given as the output to the next stage */
-      pIn = pDst;
-
-      /*Reset the output working pointer */
-      pOut = pDst;
-
-      /* decrement the loop counter */
-      stage--;
-
-   } while(stage > 0u);
-
-#endif 
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**       
-   * @} end of BiquadCascadeDF2T group       
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
deleted file mode 100644
index d9011fea..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df2T_init_f32.c    
-*    
-* Description:  Initialization function for the floating-point transposed   
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF2T    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
- * @param[in,out] *S           points to an instance of the filter data structure.   
- * @param[in]     numStages    number of 2nd order stages in the filter.   
- * @param[in]     *pCoeffs     points to the filter coefficients.   
- * @param[in]     *pState      points to the state buffer.   
- * @return        none   
- *    
- * Coefficient and State Ordering:    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 2 state variables d1, and d2.    
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
- * The state array has a total length of 2*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 2 * numStages */
-  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF2T group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
deleted file mode 100644
index c6065e92..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df2T_init_f64.c    
-*    
-* Description:  Initialization function for the floating-point transposed   
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF2T    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
- * @param[in,out] *S           points to an instance of the filter data structure.   
- * @param[in]     numStages    number of 2nd order stages in the filter.   
- * @param[in]     *pCoeffs     points to the filter coefficients.   
- * @param[in]     *pState      points to the state buffer.   
- * @return        none   
- *    
- * Coefficient and State Ordering:    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 2 state variables d1, and d2.    
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
- * The state array has a total length of 2*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 2 * numStages */
-  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float64_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF2T group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
deleted file mode 100644
index 48119736..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_stereo_df2T_f32.c    
-*    
-* Description:  Processing function for the floating-point transposed    
-*               direct form II Biquad cascade filter. 2 channels  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
-* @ingroup groupFilters       
-*/
-
-/**       
-* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
-*       
-* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
-* The filters are implemented as a cascade of second order Biquad sections.       
-* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
-* Only floating-point data is supported.       
-*       
-* This function operate on blocks of input and output data and each call to the function       
-* processes blockSize samples through the filter.       
-* pSrc points to the array of input data and       
-* pDst points to the array of output data.       
-* Both arrays contain blockSize values.       
-*       
-* \par Algorithm       
-* Each Biquad stage implements a second order filter using the difference equation:       
-* 
       
-*    y[n] = b0 * x[n] + d1       
-*    d1 = b1 * x[n] + a1 * y[n] + d2       
-*    d2 = b2 * x[n] + a2 * y[n]       
-* 
       
-* where d1 and d2 represent the two state values.       
-*       
-* \par       
-* A Biquad filter using a transposed Direct Form II structure is shown below.       
-* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
-* Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       
-* Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       
-* Pay careful attention to the sign of the feedback coefficients.       
-* Some design tools flip the sign of the feedback coefficients:       
-* 
       
-*    y[n] = b0 * x[n] + d1;       
-*    d1 = b1 * x[n] - a1 * y[n] + d2;       
-*    d2 = b2 * x[n] - a2 * y[n];       
-* 
       
-* In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       
-*       
-* \par       
-* Higher order filters are realized as a cascade of second order sections.       
-* numStages refers to the number of second order stages used.       
-* For example, an 8th order filter would be realized with numStages=4 second order stages.       
-* A 9th order filter would be realized with numStages=5 second order stages with the       
-* coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       
-*       
-* \par       
-* pState points to the state variable array.       
-* Each Biquad stage has 2 state variables d1 and d2.       
-* The state variables are arranged in the pState array as:       
-* 
       
-*     {d11, d12, d21, d22, ...}       
-* 
       
-* where d1x refers to the state variables for the first Biquad and       
-* d2x refers to the state variables for the second Biquad.       
-* The state array has a total length of 2*numStages values.       
-* The state variables are updated after each block of data is processed; the coefficients are untouched.       
-*       
-* \par       
-* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
-* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
-* That is why the Direct Form I structure supports Q15 and Q31 data types.    
-* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    
-* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
-* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
-*       
-* \par Instance Structure       
-* The coefficients and state variables for a filter are stored together in an instance data structure.       
-* A separate instance structure must be defined for each filter.       
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
-*       
-* \par Init Functions       
-* There is also an associated initialization function.      
-* The initialization function performs following operations:       
-* - Sets the values of the internal structure fields.       
-* - Zeros out the values in the state buffer.       
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
-*       
-* \par       
-* Use of the initialization function is optional.       
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
-* To place an instance structure into a const data section, the instance structure must be manually initialized.       
-* Set the values in the state buffer to zeros before static initialization.       
-* For example, to statically initialize the instance structure use       
-* 
       
-*     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
-* 
       
-* where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       
-* pCoeffs is the address of the coefficient buffer;        
-*       
-*/
-
-/**       
-* @addtogroup BiquadCascadeDF2T       
-* @{       
-*/
-
-/**      
-* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
-* @param[in]  *S        points to an instance of the filter data structure.      
-* @param[in]  *pSrc     points to the block of input data.      
-* @param[out] *pDst     points to the block of output data      
-* @param[in]  blockSize number of samples to process.      
-* @return none.      
-*/
-
-
-LOW_OPTIMIZATION_ENTER
-void arm_biquad_cascade_stereo_df2T_f32(
-const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-
-    float32_t *pIn = pSrc;                         /*  source pointer            */
-    float32_t *pOut = pDst;                        /*  destination pointer       */
-    float32_t *pState = S->pState;                 /*  State pointer             */
-    float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-    float32_t acc1a, acc1b;                        /*  accumulator               */
-    float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-    float32_t Xn1a, Xn1b;                          /*  temporary input           */
-    float32_t d1a, d2a, d1b, d2b;                  /*  state variables           */
-    uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-#if defined(ARM_MATH_CM7)
-	
-    float32_t Xn2a, Xn3a, Xn4a, Xn5a, Xn6a, Xn7a, Xn8a;         /*  Input State variables     */
-    float32_t Xn2b, Xn3b, Xn4b, Xn5b, Xn6b, Xn7b, Xn8b;         /*  Input State variables     */
-    float32_t acc2a, acc3a, acc4a, acc5a, acc6a, acc7a, acc8a;  /*  Simulates the accumulator */
-    float32_t acc2b, acc3b, acc4b, acc5b, acc6b, acc7b, acc8b;  /*  Simulates the accumulator */
-
-    do
-    {
-        /* Reading the coefficients */ 
-        b0 = pCoeffs[0]; 
-        b1 = pCoeffs[1]; 
-        b2 = pCoeffs[2]; 
-        a1 = pCoeffs[3]; 
-        /* Apply loop unrolling and compute 8 output values simultaneously. */ 
-        sample = blockSize >> 3u; 
-        a2 = pCoeffs[4]; 
-
-        /*Reading the state values */ 
-        d1a = pState[0]; 
-        d2a = pState[1]; 
-        d1b = pState[2]; 
-        d2b = pState[3]; 
-
-        pCoeffs += 5u;
-
-        /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.       
-        ** a second loop below computes the remaining 1 to 7 samples. */
-        while(sample > 0u) {
-
-            /* y[n] = b0 * x[n] + d1 */
-            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-            /* d2 = b2 * x[n] + a2 * y[n] */
-
-            /* Read the first 2 inputs. 2 cycles */
-            Xn1a  = pIn[0 ];
-            Xn1b  = pIn[1 ];
-
-            /* Sample 1. 5 cycles */
-            Xn2a  = pIn[2 ];
-            acc1a = b0 * Xn1a + d1a;
-
-            Xn2b  = pIn[3 ];
-            d1a = b1 * Xn1a + d2a;
-
-            Xn3a  = pIn[4 ];
-            d2a = b2 * Xn1a;
-
-            Xn3b  = pIn[5 ];
-            d1a += a1 * acc1a;
-
-            Xn4a  = pIn[6 ];
-            d2a += a2 * acc1a;
-
-            /* Sample 2. 5 cycles */
-            Xn4b  = pIn[7 ];
-            acc1b = b0 * Xn1b + d1b;
-
-            Xn5a  = pIn[8 ];
-            d1b = b1 * Xn1b + d2b;
-
-            Xn5b = pIn[9 ];
-            d2b = b2 * Xn1b;
-
-            Xn6a = pIn[10];
-            d1b += a1 * acc1b;
-
-            Xn6b = pIn[11];
-            d2b += a2 * acc1b;
-
-            /* Sample 3. 5 cycles */
-            Xn7a = pIn[12];
-            acc2a = b0 * Xn2a + d1a;
-
-            Xn7b = pIn[13];
-            d1a = b1 * Xn2a + d2a;
-
-            Xn8a = pIn[14];
-            d2a = b2 * Xn2a;
-
-            Xn8b = pIn[15];
-            d1a += a1 * acc2a;
-
-            pIn += 16;
-            d2a += a2 * acc2a;
-
-            /* Sample 4. 5 cycles */
-            acc2b = b0 * Xn2b + d1b;
-            d1b = b1 * Xn2b + d2b;
-            d2b = b2 * Xn2b;
-            d1b += a1 * acc2b;
-            d2b += a2 * acc2b;
-
-            /* Sample 5. 5 cycles */
-            acc3a = b0 * Xn3a + d1a;
-            d1a = b1 * Xn3a + d2a;
-            d2a = b2 * Xn3a;
-            d1a += a1 * acc3a;
-            d2a += a2 * acc3a;
-
-            /* Sample 6. 5 cycles */
-            acc3b = b0 * Xn3b + d1b;
-            d1b = b1 * Xn3b + d2b;
-            d2b = b2 * Xn3b;
-            d1b += a1 * acc3b;
-            d2b += a2 * acc3b;
-
-            /* Sample 7. 5 cycles */
-            acc4a = b0 * Xn4a + d1a;
-            d1a = b1 * Xn4a + d2a;
-            d2a = b2 * Xn4a;
-            d1a += a1 * acc4a;
-            d2a += a2 * acc4a;
-
-            /* Sample 8. 5 cycles */
-            acc4b = b0 * Xn4b + d1b;
-            d1b = b1 * Xn4b + d2b;
-            d2b = b2 * Xn4b;
-            d1b += a1 * acc4b;
-            d2b += a2 * acc4b;
-
-            /* Sample 9. 5 cycles */
-            acc5a = b0 * Xn5a + d1a;
-            d1a = b1 * Xn5a + d2a;
-            d2a = b2 * Xn5a;
-            d1a += a1 * acc5a;
-            d2a += a2 * acc5a;
-
-            /* Sample 10. 5 cycles */
-            acc5b = b0 * Xn5b + d1b;
-            d1b = b1 * Xn5b + d2b;
-            d2b = b2 * Xn5b;
-            d1b += a1 * acc5b;
-            d2b += a2 * acc5b;
-
-            /* Sample 11. 5 cycles */
-            acc6a = b0 * Xn6a + d1a;
-            d1a = b1 * Xn6a + d2a;
-            d2a = b2 * Xn6a;
-            d1a += a1 * acc6a;
-            d2a += a2 * acc6a;
-
-            /* Sample 12. 5 cycles */
-            acc6b = b0 * Xn6b + d1b;
-            d1b = b1 * Xn6b + d2b;
-            d2b = b2 * Xn6b;
-            d1b += a1 * acc6b;
-            d2b += a2 * acc6b;
-
-            /* Sample 13. 5 cycles */
-            acc7a = b0 * Xn7a + d1a;         
-            d1a = b1 * Xn7a + d2a;   
-            
-            pOut[0 ] = acc1a ;      
-            d2a = b2 * Xn7a;
-
-            pOut[1 ] = acc1b ;	
-            d1a += a1 * acc7a;
-
-            pOut[2 ] = acc2a ;	
-            d2a += a2 * acc7a;
-
-            /* Sample 14. 5 cycles */
-            pOut[3 ] = acc2b ;
-            acc7b = b0 * Xn7b + d1b;
-
-            pOut[4 ] = acc3a ; 
-            d1b = b1 * Xn7b + d2b;
-
-            pOut[5 ] = acc3b ;	
-            d2b = b2 * Xn7b;
-
-            pOut[6 ] = acc4a ;	  
-            d1b += a1 * acc7b;
-
-            pOut[7 ] = acc4b ;
-            d2b += a2 * acc7b;
-
-            /* Sample 15. 5 cycles */
-            pOut[8 ] = acc5a ;  
-            acc8a = b0 * Xn8a + d1a;
-
-            pOut[9 ] = acc5b;	
-            d1a = b1 * Xn8a + d2a;
-
-            pOut[10] = acc6a;	
-            d2a = b2 * Xn8a;
-
-            pOut[11] = acc6b;
-            d1a += a1 * acc8a;
-
-            pOut[12] = acc7a;
-            d2a += a2 * acc8a;
-
-            /* Sample 16. 5 cycles */
-            pOut[13] = acc7b;	
-            acc8b = b0 * Xn8b + d1b;
-
-            pOut[14] = acc8a;	
-            d1b = b1 * Xn8b + d2b;
-
-            pOut[15] = acc8b;
-            d2b = b2 * Xn8b;
-
-            sample--;	 
-            d1b += a1 * acc8b;
-
-            pOut += 16;
-            d2b += a2 * acc8b;
-        }
-
-        sample = blockSize & 0x7u;
-        while(sample > 0u) {
-            /* Read the input */
-            Xn1a = *pIn++; //Channel a
-            Xn1b = *pIn++; //Channel b
-
-            /* y[n] = b0 * x[n] + d1 */
-            acc1a = (b0 * Xn1a) + d1a;
-            acc1b = (b0 * Xn1b) + d1b;
-
-            /* Store the result in the accumulator in the destination buffer. */
-            *pOut++ = acc1a;
-            *pOut++ = acc1b;
-
-            /* Every time after the output is computed state should be updated. */
-            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
-            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
-
-            /* d2 = b2 * x[n] + a2 * y[n] */
-            d2a = (b2 * Xn1a) + (a2 * acc1a);
-            d2b = (b2 * Xn1b) + (a2 * acc1b);
-
-            sample--;	
-        }
-
-        /* Store the updated state variables back into the state array */ 
-        pState[0] = d1a; 
-        pState[1] = d2a;         
-
-        pState[2] = d1b; 
-        pState[3] = d2b; 
-        
-        /* The current stage input is given as the output to the next stage */ 
-        pIn = pDst; 
-        /* decrement the loop counter */ 
-        stage--; 
-
-        pState += 4u;
-        /*Reset the output working pointer */ 
-        pOut = pDst; 
-
-    } while(stage > 0u);
-	
-#elif defined(ARM_MATH_CM0_FAMILY)
-
-    /* Run the below code for Cortex-M0 */
-
-    do
-    {
-        /* Reading the coefficients */
-        b0 = *pCoeffs++;
-        b1 = *pCoeffs++;
-        b2 = *pCoeffs++;
-        a1 = *pCoeffs++;
-        a2 = *pCoeffs++;
-
-        /*Reading the state values */
-        d1a = pState[0];
-        d2a = pState[1];
-        d1b = pState[2];
-        d2b = pState[3];
-
-
-        sample = blockSize;
-
-        while(sample > 0u)
-        {
-            /* Read the input */
-            Xn1a = *pIn++; //Channel a
-            Xn1b = *pIn++; //Channel b
-
-            /* y[n] = b0 * x[n] + d1 */
-            acc1a = (b0 * Xn1a) + d1a;
-            acc1b = (b0 * Xn1b) + d1b;
-
-            /* Store the result in the accumulator in the destination buffer. */
-            *pOut++ = acc1a;
-            *pOut++ = acc1b;
-
-            /* Every time after the output is computed state should be updated. */
-            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-            d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
-            d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
-
-            /* d2 = b2 * x[n] + a2 * y[n] */
-            d2a = (b2 * Xn1a) + (a2 * acc1a);
-            d2b = (b2 * Xn1b) + (a2 * acc1b);
-
-            /* decrement the loop counter */
-            sample--;
-        }
-
-        /* Store the updated state variables back into the state array */
-        *pState++ = d1a;
-        *pState++ = d2a;
-        *pState++ = d1b;
-        *pState++ = d2b;
-
-        /* The current stage input is given as the output to the next stage */
-        pIn = pDst;
-
-        /*Reset the output working pointer */
-        pOut = pDst;
-
-        /* decrement the loop counter */
-        stage--;
-
-    } while(stage > 0u);
-	 
-#else
-
-    float32_t Xn2a, Xn3a, Xn4a;                          /*  Input State variables     */
-    float32_t Xn2b, Xn3b, Xn4b;                          /*  Input State variables     */
-    float32_t acc2a, acc3a, acc4a;                       /*  accumulator               */
-    float32_t acc2b, acc3b, acc4b;                       /*  accumulator               */
-    float32_t p0a, p1a, p2a, p3a, p4a, A1a;
-    float32_t p0b, p1b, p2b, p3b, p4b, A1b;
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-    do
-    {
-        /* Reading the coefficients */     
-        b0 = *pCoeffs++;
-        b1 = *pCoeffs++;
-        b2 = *pCoeffs++;
-        a1 = *pCoeffs++;
-        a2 = *pCoeffs++;      
-
-        /*Reading the state values */
-        d1a = pState[0];
-        d2a = pState[1];
-        d1b = pState[2];
-        d2b = pState[3];
-
-        /* Apply loop unrolling and compute 4 output values simultaneously. */
-        sample = blockSize >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-        ** a second loop below computes the remaining 1 to 3 samples. */
-        while(sample > 0u) {
-
-            /* y[n] = b0 * x[n] + d1 */
-            /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-            /* d2 = b2 * x[n] + a2 * y[n] */
-
-            /* Read the four inputs */
-            Xn1a = pIn[0];
-            Xn1b = pIn[1];
-            Xn2a = pIn[2];
-            Xn2b = pIn[3];
-            Xn3a = pIn[4];
-            Xn3b = pIn[5];
-            Xn4a = pIn[6];
-            Xn4b = pIn[7];
-            pIn += 8;     
-            
-            p0a = b0 * Xn1a; 
-            p0b = b0 * Xn1b; 
-            p1a = b1 * Xn1a;
-            p1b = b1 * Xn1b;
-            acc1a = p0a + d1a;
-            acc1b = p0b + d1b;
-            p0a = b0 * Xn2a; 
-            p0b = b0 * Xn2b; 
-            p3a = a1 * acc1a;
-            p3b = a1 * acc1b;
-            p2a = b2 * Xn1a;
-            p2b = b2 * Xn1b;
-            A1a = p1a + p3a;
-            A1b = p1b + p3b;
-            p4a = a2 * acc1a;
-            p4b = a2 * acc1b;
-            d1a = A1a + d2a;
-            d1b = A1b + d2b;
-            d2a = p2a + p4a;
-            d2b = p2b + p4b;
-            
-            p1a = b1 * Xn2a;
-            p1b = b1 * Xn2b;
-            acc2a = p0a + d1a;
-            acc2b = p0b + d1b;
-            p0a = b0 * Xn3a; 
-            p0b = b0 * Xn3b; 
-            p3a = a1 * acc2a;
-            p3b = a1 * acc2b;
-            p2a = b2 * Xn2a;
-            p2b = b2 * Xn2b;
-            A1a = p1a + p3a;
-            A1b = p1b + p3b;
-            p4a = a2 * acc2a;
-            p4b = a2 * acc2b;
-            d1a = A1a + d2a;
-            d1b = A1b + d2b;
-            d2a = p2a + p4a;
-            d2b = p2b + p4b;
-            
-            p1a = b1 * Xn3a;
-            p1b = b1 * Xn3b;
-            acc3a = p0a + d1a;
-            acc3b = p0b + d1b;
-            p0a = b0 * Xn4a; 
-            p0b = b0 * Xn4b; 
-            p3a = a1 * acc3a;
-            p3b = a1 * acc3b;
-            p2a = b2 * Xn3a;
-            p2b = b2 * Xn3b;
-            A1a = p1a + p3a;
-            A1b = p1b + p3b;
-            p4a = a2 * acc3a;
-            p4b = a2 * acc3b;
-            d1a = A1a + d2a;
-            d1b = A1b + d2b;
-            d2a = p2a + p4a;
-            d2b = p2b + p4b;
-            
-            acc4a = p0a + d1a;
-            acc4b = p0b + d1b;
-            p1a = b1 * Xn4a;
-            p1b = b1 * Xn4b;
-            p3a = a1 * acc4a;
-            p3b = a1 * acc4b;
-            p2a = b2 * Xn4a;
-            p2b = b2 * Xn4b;
-            A1a = p1a + p3a;
-            A1b = p1b + p3b;
-            p4a = a2 * acc4a;
-            p4b = a2 * acc4b;
-            d1a = A1a + d2a;
-            d1b = A1b + d2b;
-            d2a = p2a + p4a;
-            d2b = p2b + p4b;
-
-            pOut[0] = acc1a;	
-            pOut[1] = acc1b;	
-            pOut[2] = acc2a;	
-            pOut[3] = acc2b;
-            pOut[4] = acc3a;	
-            pOut[5] = acc3b;	
-            pOut[6] = acc4a;	
-            pOut[7] = acc4b;
-            pOut += 8;
-             
-            sample--;	       
-        }
-
-        sample = blockSize & 0x3u;
-        while(sample > 0u) {
-            Xn1a = *pIn++;
-            Xn1b = *pIn++;
-
-            p0a = b0 * Xn1a; 
-            p0b = b0 * Xn1b; 
-            p1a = b1 * Xn1a;
-            p1b = b1 * Xn1b;
-            acc1a = p0a + d1a;
-            acc1b = p0b + d1b;
-            p3a = a1 * acc1a;
-            p3b = a1 * acc1b;
-            p2a = b2 * Xn1a;
-            p2b = b2 * Xn1b;
-            A1a = p1a + p3a;
-            A1b = p1b + p3b;
-            p4a = a2 * acc1a;
-            p4b = a2 * acc1b;
-            d1a = A1a + d2a;
-            d1b = A1b + d2b;
-            d2a = p2a + p4a;
-            d2b = p2b + p4b;
-
-            *pOut++ = acc1a;
-            *pOut++ = acc1b;
-
-            sample--;	       
-        }
-
-        /* Store the updated state variables back into the state array */
-        *pState++ = d1a;
-        *pState++ = d2a;
-        *pState++ = d1b;
-        *pState++ = d2b;
-
-        /* The current stage input is given as the output to the next stage */
-        pIn = pDst;
-
-        /*Reset the output working pointer */
-        pOut = pDst;
-
-        /* decrement the loop counter */
-        stage--;
-
-    } while(stage > 0u);
-
-#endif 
-
-}
-LOW_OPTIMIZATION_EXIT
-
-/**       
-   * @} end of BiquadCascadeDF2T group       
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
deleted file mode 100644
index b19587a0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_stereo_df2T_init_f32.c    
-*    
-* Description:  Initialization function for the floating-point transposed   
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF2T    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
- * @param[in,out] *S           points to an instance of the filter data structure.   
- * @param[in]     numStages    number of 2nd order stages in the filter.   
- * @param[in]     *pCoeffs     points to the filter coefficients.   
- * @param[in]     *pState      points to the state buffer.   
- * @return        none   
- *    
- * Coefficient and State Ordering:    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 2 state variables d1, and d2 for each channel.    
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
- * The state array has a total length of 2*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF2T group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
deleted file mode 100644
index 1fdc6a17..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
+++ /dev/null
@@ -1,647 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_f32.c    
-*    
-* Description:	Convolution of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup Conv Convolution    
- *    
- * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.    
- * Convolution is similar to correlation and is frequently used in filtering and data analysis.    
- * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.    
- * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.    
- *    
- * \par Algorithm    
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
- * Then the convolution    
- *    
- * 
    
- *                   c[n] = a[n] * b[n]    
- * 
    
- *    
- * \par    
- * is defined as    
- * \image html ConvolutionEquation.gif    
- * \par    
- * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.    
- * pSrcA points to the first input vector of length srcALen and    
- * pSrcB points to the second input vector of length srcBLen.    
- * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.    
- *    
- * \par    
- * Conceptually, when two signals a[n] and b[n] are convolved,    
- * the signal b[n] slides over a[n].    
- * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.    
- *    
- * \par    
- * Note that convolution is a commutative operation:    
- *    
- * 
    
- *                   a[n] * b[n] = b[n] * a[n].    
- * 
    
- *    
- * \par    
- * This means that switching the A and B arguments to the convolution functions has no effect.    
- *    
- * Fixed-Point Behavior    
- *    
- * \par    
- * Convolution requires summing up a large number of intermediate products.    
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
- * Refer to the function specific documentation below for further details of the particular algorithm used.    
- *
- *
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of floating-point sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- */
-
-void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1;                               /* inputA pointer */
-  float32_t *pIn2;                               /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
-  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum += *px++ * *py--;
-
-      /* x[1] * y[srcBLen - 2] */
-      sum += *px++ * *py--;
-
-      /* x[2] * y[srcBLen - 3] */
-      sum += *px++ * *py--;
-
-      /* x[3] * y[srcBLen - 4] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 += x0 * c0;
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 += x1 * c0;
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 += x2 * c0;
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] */
-        acc3 += x3 * c0;
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py--);
-
-        /* Read x[4] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 += x1 * c0;
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 += x2 * c0;
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 += x3 * c0;
-        /* acc3 +=  x[4] * y[srcBLen - 2] */
-        acc3 += x0 * c0;
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 += x2 * c0;
-        /* acc1 +=  x[3] * y[srcBLen - 2] */
-        acc1 += x3 * c0;
-        /* acc2 +=  x[4] * y[srcBLen - 2] */
-        acc2 += x0 * c0;
-        /* acc3 +=  x[5] * y[srcBLen - 2] */
-        acc3 += x1 * c0;
-
-        /* Read y[srcBLen - 4] sample */
-        c0 = *(py--);
-
-        /* Read x[6] sample */
-        x2 = *(px + 3u);
-        px += 4u;
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[srcBLen - 4] */
-        acc0 += x3 * c0;
-        /* acc1 +=  x[4] * y[srcBLen - 4] */
-        acc1 += x0 * c0;
-        /* acc2 +=  x[5] * y[srcBLen - 4] */
-        acc2 += x1 * c0;
-        /* acc3 +=  x[6] * y[srcBLen - 4] */
-        acc3 += x2 * c0;
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 += x3 * c0;
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-      *pOut++ = acc1;
-      *pOut++ = acc2;
-      *pOut++ = acc3;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
-  {
-    /* Initialize sum with zero to carry out MAC operations */
-    sum = 0.0f;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += pIn1[j] * pIn2[i - j];
-      }
-    }
-    /* Store the output in the destination buffer */
-    pDst[i] = sum;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
deleted file mode 100644
index 70f1bfc1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *     
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results    
- * but provides only a single guard bit. There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
- *    
- * \par    
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
- */
-
-void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  uint32_t tapCnt;                               /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifdef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* Pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2 + srcBLen - 1;
-
-  /* points to smaller length sequence */
-  px = pIn2;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-
-  /* Copy smaller length input sequence in reverse order into second scratch buffer */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Assuming scratch1 buffer is aligned by 32-bit */
-  /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr1, srcALen);
-
-  /* Update pointers */
-  pScr1 += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = py;
-
-  /* First part of the processing with loop unrolling process 4 data points at a time.       
-   ** a second loop below process for the remaining 1 to 3 samples. */
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = _SIMD32_OFFSET(pScr1);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x2, y2, acc0);
-      acc2 = __SMLAD(x1, y2, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-      acc1 = __SMLADX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-	  a = *pScr1;
-	  b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-	  a = *(pScr1 + 2);
-	  b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* update scratch pointers */
-      pIn2 += 4u;
-      pScr1 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2);
-      acc1 += (*pScr1++ * *pIn2);
-      acc2 += (*pScr1++ * *pIn2);
-      acc3 += (*pScr1++ * *pIn2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr1++ * *pIn2++);
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
deleted file mode 100644
index 44f19bb6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
+++ /dev/null
@@ -1,1410 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_fast_q15.c   
-*   
-* Description:	Fast Q15 Convolution.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-* 
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * This fast version uses a 32-bit accumulator with 2.30 format.   
- * The accumulator maintains full precision of the intermediate multiplication results   
- * but provides only a single guard bit. There is no saturation on intermediate additions.   
- * Thus, if the accumulator overflows it wraps around and distorts the result.   
- * The input signals should be scaled down to avoid intermediate overflows.   
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
- *   
- * \par   
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
- */
-
-void arm_conv_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
-      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
-      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-  q15_t a, b;
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;	  
-
-      /* read x[0], x[1] samples */
-	  a = *px++;
-	  b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *px;
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *px;
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x2 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  x2 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  a = *(px + 2);
-	  b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px+1);
-		px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		a = *(px+2);
-		b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-	  *pOut++ = (q15_t)(acc0 >> 15);
-	  *pOut++ = (q15_t)(acc1 >> 15);
-	  *pOut++ = (q15_t)(acc2 >> 15);
-	  *pOut++ = (q15_t)(acc3 >> 15);
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {	
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
deleted file mode 100644
index 4111a1e8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
+++ /dev/null
@@ -1,577 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_fast_q31.c    
-*    
-* Description:	Q31 Convolution (fast version).    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- *    
- * \par    
- * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
- */
-
-void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-  q31_t *pIn1;                                   /* inputA pointer */
-  q31_t *pIn2;                                   /* inputB pointer */
-  q31_t *pOut = pDst;                            /* output pointer */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[1] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[2] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[3] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum << 1;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py--);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc3 +=  x[4] * y[srcBLen - 2] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc1 +=  x[3] * y[srcBLen - 3] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc2 +=  x[4] * y[srcBLen - 3] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc3 +=  x[5] * y[srcBLen - 3] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* Read y[srcBLen - 4] sample */
-        c0 = *(py--);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[srcBLen - 4] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc1 +=  x[4] * y[srcBLen - 4] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc2 +=  x[5] * y[srcBLen - 4] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc3 +=  x[6] * y[srcBLen - 4] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = (q31_t) (acc0 << 1);
-      *pOut++ = (q31_t) (acc1 << 1);
-      *pOut++ = (q31_t) (acc2 << 1);
-      *pOut++ = (q31_t) (acc3 << 1);
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum << 1;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
deleted file mode 100644
index dffa2de7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_opt_q15.c    
-*    
-* Description:	Convolution of Q15 sequences.      
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q15 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).    
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *    
- *       
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * This approach provides 33 guard bits and there is no risk of overflow.    
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
- *  
- *   
- * \par    
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.     
- * 
- *  
- */
-
-void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  uint32_t tapCnt;                               /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2 + srcBLen - 1;
-
-  /* points to smaller length sequence */
-  px = pIn2;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  /* Copy smaller length input sequence in reverse order into second scratch buffer */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Assuming scratch1 buffer is aligned by 32-bit */
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr1, srcALen);
-
-  /* Update pointers */
-  pScr1 += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = py;
-
-  /* First part of the processing with loop unrolling process 4 data points at a time.       
-   ** a second loop below process for the remaining 1 to 3 samples. */
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      /* multiply and accumlate */
-      acc0 = __SMLALD(x1, y1, acc0);
-      acc2 = __SMLALD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = _SIMD32_OFFSET(pScr1);
-
-      /* multiply and accumlate */
-      acc0 = __SMLALD(x2, y2, acc0);
-      acc2 = __SMLALD(x1, y2, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-	  a = *pScr1;
-	  b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-	  a = *(pScr1 + 2);
-	  b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-      pScr1 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2);
-      acc1 += (*pScr1++ * *pIn2);
-      acc2 += (*pScr1++ * *pIn2);
-      acc3 += (*pScr1++ * *pIn2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read next two samples from scratch1 buffer */
-      acc0 += (*pScr1++ * *pIn2++);
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
deleted file mode 100644
index b77afbe4..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_opt_q7.c    
-*    
-* Description:	Convolution of Q7 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q7 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
- *       
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.    
- *
- */
-
-void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t out0, out1, out2, out3;                   /* temporary variables */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2;
-
-  /* points to smaller length sequence */
-  px = pIn2 + srcBLen - 1;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy (srcALen) samples in scratch buffer */
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = (q7_t *) py;
-
-  pScr2 = py;
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-      acc0 = __SMLAD(x2, y1, acc0);
-
-      acc2 = __SMLAD(x1, y1, acc2);
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      pScr2 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2);
-      acc1 += (*pScr1++ * *pScr2);
-      acc2 += (*pScr1++ * *pScr2);
-      acc3 += (*pScr1++ * *pScr2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
-    out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
-    out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
-    out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-      acc0 += (*pScr1++ * *pScr2++);
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
deleted file mode 100644
index 226ffd57..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_f32.c    
-*    
-* Description:	Partial convolution of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup PartialConv Partial Convolution    
- *    
- * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.    
- * Each function has two additional arguments.    
- * firstIndex specifies the starting index of the subset of output samples.    
- * numPoints is the number of output samples to compute.    
- * The function computes the output in the range    
- * [firstIndex, ..., firstIndex+numPoints-1].    
- * The output array pDst contains numPoints values.    
- *    
- * The allowable range of output indices is [0 srcALen+srcBLen-2].    
- * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.    
- * Otherwise the functions return ARM_MATH_SUCCESS.    
- * \note Refer arm_conv_f32() for details on fixed point behavior.   
- *
- * 
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of floating-point sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- */
-
-arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
-  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count = 0u, blkCnt, check;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = ((int32_t) check - blockSize3) -
-      (blockSize1 + (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc1 = pIn2 + firstIndex;
-    py = pSrc1;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first stage starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum += *px++ * *py--;
-
-        /* x[1] * y[srcBLen - 2] */
-        sum += *px++ * *py--;
-
-        /* x[2] * y[srcBLen - 3] */
-        sum += *px++ * *py--;
-
-        /* x[3] * y[srcBLen - 4] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc1;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0.0f;
-        acc1 = 0.0f;
-        acc2 = 0.0f;
-        acc3 = 0.0f;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 += x0 * c0;
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 += x1 * c0;
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 += x2 * c0;
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] */
-          acc3 += x3 * c0;
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py--);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 += x1 * c0;
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 += x2 * c0;
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 += x3 * c0;
-          /* acc3 +=  x[4] * y[srcBLen - 2] */
-          acc3 += x0 * c0;
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 += x2 * c0;
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 += x3 * c0;
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 += x0 * c0;
-          /* acc3 +=  x[5] * y[srcBLen - 2] */
-          acc3 += x1 * c0;
-
-          /* Read y[srcBLen - 4] sample */
-          c0 = *(py--);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[3] * y[srcBLen - 4] */
-          acc0 += x3 * c0;
-          /* acc1 +=  x[4] * y[srcBLen - 4] */
-          acc1 += x0 * c0;
-          /* acc2 +=  x[5] * y[srcBLen - 4] */
-          acc2 += x1 * c0;
-          /* acc3 +=  x[6] * y[srcBLen - 4] */
-          acc3 += x2 * c0;
-
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += x0 * c0;
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += x1 * c0;
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += x2 * c0;
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 += x3 * c0;
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = acc0;
-        *pOut++ = acc1;
-        *pOut++ = acc2;
-        *pOut++ = acc3;
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0.0f;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0.0f;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0.0f;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0u; j <= i; j++)
-      {
-        /* Check the array limitations for inputs */
-        if((((i - j) < srcBLen) && (j < srcALen)))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += pIn1[j] * pIn2[i - j];
-        }
-      }
-      /* Store the output in the destination buffer */
-      pDst[i] = sum;
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
deleted file mode 100644
index 194246f0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+++ /dev/null
@@ -1,768 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Partial convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *     
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;
-
-  uint32_t tapCnt;                               /* loop count */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-
-    /* Copy smaller length input sequence in reverse order into second scratch buffer */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Assuming scratch1 buffer is aligned by 32-bit */
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-    /* Copy (srcALen) samples in scratch buffer */
-    arm_copy_q15(pIn1, pScr1, srcALen);
-
-    /* Update pointers */
-    pScr1 += srcALen;
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* First part of the processing with loop unrolling process 4 data points at a time.       
-     ** a second loop below process for the remaining 1 to 3 samples. */
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pIn2);
-        y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x1, y1, acc0);
-        acc2 = __SMLAD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = _SIMD32_OFFSET(pScr1);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x2, y2, acc0);
-
-        acc2 = __SMLAD(x1, y2, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-        acc1 = __SMLADX(x3, y2, acc1);
-
-        x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y2, acc3);
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pIn2)++;
-
-        acc0 = __SMLAD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-       ** Then store the output in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
-  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2;
-        y11 = *(pIn2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-        acc2 += (q31_t) x20 *y10;
-        acc2 += (q31_t) x21 *y11;
-
-        /* multiply and accumlate */
-        acc1 += (q31_t) x11 *y10;
-        acc1 += (q31_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x21 *y10;
-        acc3 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pIn2 + 2u);
-        y11 = *(pIn2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x20 *y10;
-        acc0 += (q31_t) x21 *y11;
-        acc2 += (q31_t) x10 *y10;
-        acc2 += (q31_t) x11 *y11;
-        acc1 += (q31_t) x21 *y10;
-        acc1 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x11 *y10;
-        acc3 += (q31_t) x20 *y11;
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = __SSAT((acc0 >> 15), 16);
-      *pOut++ = __SSAT((acc1 >> 15), 16);
-      *pOut++ = __SSAT((acc2 >> 15), 16);
-      *pOut++ = __SSAT((acc3 >> 15), 16);
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2++;
-        y11 = *pIn2++;
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
deleted file mode 100644
index 794879e8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
+++ /dev/null
@@ -1,1492 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_fast_q15.c   
-*   
-* Description:	Fast Q15 Partial convolution.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *   
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
- */
-
-
-arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >=srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    while((count < 4u) && (blockSize1 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is the index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-
-    /* --------------------   
-     * Stage2 process   
-     * -------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-      py = py - 1u;
-
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-
-        /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-        /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read the last two inputB samples using SIMD:   
-           * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-          acc0 = __SMLADX(x0, c0, acc0);
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-          acc1 = __SMLADX(x1, c0, acc1);
-
-          /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-          /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-          acc2 = __SMLADX(x2, c0, acc2);
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-          acc3 = __SMLADX(x3, c0, acc3);
-
-          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-          acc0 = __SMLADX(x2, c0, acc0);
-
-          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-          acc1 = __SMLADX(x3, c0, acc1);
-
-          /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-          /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-          acc2 = __SMLADX(x0, c0, acc2);
-
-          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-          acc3 = __SMLADX(x1, c0, acc3);
-
-        } while(--k);
-
-        /* For the next MAC operations, SIMD is not used   
-         * So, the 16 bit pointer if inputB, py is updated */
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        if(k == 1u)
-        {
-          /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-          /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLAD(x0, c0, acc0);
-          acc1 = __SMLAD(x1, c0, acc1);
-          acc2 = __SMLADX(x1, c0, acc2);
-          acc3 = __SMLADX(x3, c0, acc3);
-        }
-
-        if(k == 2u)
-        {
-          /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-          /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x0, c0, acc0);
-          acc1 = __SMLADX(x1, c0, acc1);
-          acc2 = __SMLADX(x3, c0, acc2);
-          acc3 = __SMLADX(x2, c0, acc3);
-        }
-
-        if(k == 3u)
-        {
-          /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-          /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-          /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x0, c0, acc0);
-          acc1 = __SMLADX(x1, c0, acc1);
-          acc2 = __SMLADX(x3, c0, acc2);
-          acc3 = __SMLADX(x2, c0, acc3);
-
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-          /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x1, c0, acc0);
-          acc1 = __SMLAD(x2, c0, acc1);
-          acc2 = __SMLADX(x2, c0, acc2);
-          acc3 = __SMLADX(x3, c0, acc3);
-        }
-
-        /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
-        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
-
-#else
-
-        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
-        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-  q15_t a, b;
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >=srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = ((int32_t) check - blockSize3) -
-      (blockSize1 + (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-  while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is the index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-
-    /* --------------------   
-     * Stage2 process   
-     * -------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-      py = py - 1u;
-
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-      /* read x[0], x[1] samples */
-	  a = *px++;
-	  b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *px;
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *px;
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x2 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  x2 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  a = *(px + 2);
-	  b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px+1);
-		px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		a = *(px+2);
-		b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-	  *pOut++ = (q15_t)(acc0 >> 15);
-	  *pOut++ = (q15_t)(acc1 >> 15);
-	  *pOut++ = (q15_t)(acc2 >> 15);
-	  *pOut++ = (q15_t)(acc3 >> 15);
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {	
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-  while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
deleted file mode 100644
index 46ef94d2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
+++ /dev/null
@@ -1,611 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_fast_q31.c    
-*    
-* Description:	Fast Q31 Partial convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par    
- * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
- */
-
-arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first loop starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[1] * y[srcBLen - 2] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[2] * y[srcBLen - 3] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[3] * y[srcBLen - 4] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py--);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc3 +=  x[4] * y[srcBLen - 2] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc3 +=  x[5] * y[srcBLen - 2] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-          /* Read y[srcBLen - 4] sample */
-          c0 = *(py--);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[3] * y[srcBLen - 4] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc1 +=  x[4] * y[srcBLen - 4] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc2 +=  x[5] * y[srcBLen - 4] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc3 +=  x[6] * y[srcBLen - 4] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (acc0 << 1);
-        *pOut++ = (q31_t) (acc1 << 1);
-        *pOut++ = (q31_t) (acc2 << 1);
-        *pOut++ = (q31_t) (acc3 << 1);
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum << 1;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum << 1;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------    
-     * Stage3 process    
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
deleted file mode 100644
index 0734938e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_opt_q15.c    
-*    
-* Description:	Partial convolution of Q15 sequences.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q15 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, state buffers should be aligned by 32-bit    
- *    
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
- *  
- * 
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-    /* Copy (srcALen) samples in scratch buffer */
-    arm_copy_q15(pIn1, pScr1, srcALen);
-
-    /* Update pointers */
-    pScr1 += srcALen;
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pIn2);
-        y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-        /* multiply and accumlate */
-        acc0 = __SMLALD(x1, y1, acc0);
-        acc2 = __SMLALD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLALDX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = _SIMD32_OFFSET(pScr1);
-
-        /* multiply and accumlate */
-        acc0 = __SMLALD(x2, y2, acc0);
-        acc2 = __SMLALD(x1, y2, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLALDX(x3, y1, acc3);
-        acc1 = __SMLALDX(x3, y2, acc1);
-
-        x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLALDX(x3, y2, acc3);
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pIn2)++;
-
-        acc0 = __SMLALD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
-  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2;
-        y11 = *(pIn2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x10 *y10;
-        acc0 += (q63_t) x11 *y11;
-        acc2 += (q63_t) x20 *y10;
-        acc2 += (q63_t) x21 *y11;
-
-        /* multiply and accumlate */
-        acc1 += (q63_t) x11 *y10;
-        acc1 += (q63_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q63_t) x21 *y10;
-        acc3 += (q63_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pIn2 + 2u);
-        y11 = *(pIn2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x20 *y10;
-        acc0 += (q63_t) x21 *y11;
-        acc2 += (q63_t) x10 *y10;
-        acc2 += (q63_t) x11 *y11;
-        acc1 += (q63_t) x21 *y10;
-        acc1 += (q63_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q63_t) x11 *y10;
-        acc3 += (q63_t) x20 *y11;
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = __SSAT((acc0 >> 15), 16);
-      *pOut++ = __SSAT((acc1 >> 15), 16);
-      *pOut++ = __SSAT((acc2 >> 15), 16);
-      *pOut++ = __SSAT((acc3 >> 15), 16);
-
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2++;
-        y11 = *pIn2++;
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x10 *y10;
-        acc0 += (q63_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
deleted file mode 100644
index e8fcce5b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
+++ /dev/null
@@ -1,803 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_opt_q7.c    
-*    
-* Description:	Partial convolution of Q7 sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q7 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit   
- * 
- *
- * 
- */
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
-  arm_status status;
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t out0, out1, out2, out3;                   /* temporary variables */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2;
-
-    /* points to smaller length sequence */
-    px = pIn2 + srcBLen - 1;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy (srcALen) samples in scratch buffer */
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = (q7_t *) py;
-
-    pScr2 = py;
-
-    pOut = pDst + firstIndex;
-
-    pScratch1 += firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pScr2);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x1, y1, acc0);
-        acc2 = __SMLAD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-        acc0 = __SMLAD(x2, y1, acc0);
-
-        acc2 = __SMLAD(x1, y1, acc2);
-
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-
-        pScr2 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2);
-        acc1 += (*pScr1++ * *pScr2);
-        acc2 += (*pScr1++ * *pScr2);
-        acc3 += (*pScr1++ * *pScr2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-    blkCnt = (numPoints) & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pScr2)++;
-
-        acc0 = __SMLAD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-
-  }
-
-  return (status);
-
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  arm_status status;
-  q7_t *pOut = pDst;                             /* output pointer */
-  q15_t x10, x11, x20, x21;                      /* Temporary input variables */
-  q15_t y10, y11;                                /* Temporary input variables */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2;
-
-    /* points to smaller length sequence */
-    px = pIn2 + srcBLen - 1;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy (srcALen) samples in scratch buffer */
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = (q7_t *) py;
-
-    pScr2 = py;
-
-    pOut = pDst + firstIndex;
-
-    pScratch1 += firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y10 = *pScr2;
-        y11 = *(pScr2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-        acc2 += (q31_t) x20 *y10;
-        acc2 += (q31_t) x21 *y11;
-
-
-        acc1 += (q31_t) x11 *y10;
-        acc1 += (q31_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x21 *y10;
-        acc3 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pScr2 + 2u);
-        y11 = *(pScr2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x20 *y10;
-        acc0 += (q31_t) x21 *y11;
-        acc2 += (q31_t) x10 *y10;
-        acc2 += (q31_t) x11 *y11;
-        acc1 += (q31_t) x21 *y10;
-        acc1 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x11 *y10;
-        acc3 += (q31_t) x20 *y11;
-
-        /* update scratch pointers */
-
-        pScr1 += 4u;
-        pScr2 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2);
-        acc1 += (*pScr1++ * *pScr2);
-        acc2 += (*pScr1++ * *pScr2);
-        acc3 += (*pScr1++ * *pScr2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-    blkCnt = (numPoints) & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pScr2++;
-        y11 = *pScr2++;
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  return (status);
-
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
deleted file mode 100644
index c2979891..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_q15.c   
-*   
-* Description:	Partial convolution of Q15 sequences.  
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-* 
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q15 sequences.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *   
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.  
- * 
- * \par    
- * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
- * 
- */
-
-
-arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    while((count < 4u) && (blockSize1 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLALDX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLALDX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLALDX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLALDX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLALDX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLALDX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLALDX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLALDX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-
-		c0 = *(py-1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-  	  
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-  
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
-  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)  */
-
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
deleted file mode 100644
index 98fc654b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_q31.c    
-*    
-* Description:	Partial convolution of Q31 sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q31 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */
-  q31_t x0, x1, x2, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first loop starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[1] * y[srcBLen - 2] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[2] * y[srcBLen - 3] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[3] * y[srcBLen - 4] */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blkCnt */
-
-      blkCnt = blockSize2 / 3;
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-
-        /* read x[0], x[1] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-
-        /* Apply loop unrolling and compute 3 MACs simultaneously. */
-        k = srcBLen / 3;
-
-        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-         ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py);
-
-          /* Read x[2] sample */
-          x2 = *(px);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 += (q63_t) x0 *c0;
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 += (q63_t) x1 *c0;
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 += (q63_t) x2 *c0;
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py - 1u);
-
-          /* Read x[3] sample */
-          x0 = *(px + 1u);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 += (q63_t) x1 *c0;
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 += (q63_t) x2 *c0;
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 += (q63_t) x0 *c0;
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py - 2u);
-
-          /* Read x[4] sample */
-          x1 = *(px + 2u);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 += (q63_t) x2 *c0;
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 += (q63_t) x0 *c0;
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 += (q63_t) x1 *c0;
-
-
-          px += 3u;
-
-          py -= 3u;
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-         ** No loop unrolling is used. */
-        k = srcBLen - (3 * (srcBLen / 3));
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += (q63_t) x0 *c0;
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += (q63_t) x1 *c0;
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += (q63_t) x2 *c0;
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (acc0 >> 31);
-        *pOut++ = (q31_t) (acc1 >> 31);
-        *pOut++ = (q31_t) (acc2 >> 31);
-
-        /* Increment the pointer pIn1 index, count by 3 */
-        count += 3u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (sum >> 31);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (sum >> 31);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The blockSize3 variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------    
-     * Stage3 process    
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
-  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q31_t) (sum >> 31u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*    #ifndef ARM_MATH_CM0_FAMILY      */
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
deleted file mode 100644
index 65eaceaa..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
+++ /dev/null
@@ -1,741 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_q7.c   
-*   
-* Description:	Partial convolution of Q7 sequences.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q7 sequences.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *  
- * \par    
- * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
- *  
- */
-
-arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer */
-  q7_t *pIn2;                                    /* inputB pointer */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t *px;                                      /* Intermediate inputA pointer */
-  q7_t *py;                                      /* Intermediate inputB pointer */
-  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t input1, input2;
-  q15_t in1, in2;
-  q7_t x0, x1, x2, x3, c0, c1;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
-  arm_status status;
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
-    blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* The first stage starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] , x[1] */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[srcBLen - 1] , y[srcBLen - 2] */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* x[0] * y[srcBLen - 1] */
-        /* x[1] * y[srcBLen - 2] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* x[2] , x[3] */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[srcBLen - 3] , y[srcBLen - 4] */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* x[2] * y[srcBLen - 3] */
-        /* x[3] * y[srcBLen - 4] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    if((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
-    {
-      px = pIn1 + firstIndex - srcBLen + 1;
-    }
-    else
-    {
-      px = pIn1;
-    }
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------   
-     * Stage2 process   
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-          /* Read y[srcBLen - 2] sample */
-          c1 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* x[0] and x[1] are packed */
-          in1 = (q15_t) x0;
-          in2 = (q15_t) x1;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
-          in1 = (q15_t) c0;
-          in2 = (q15_t) c1;
-
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
-          acc0 = __SMLAD(input1, input2, acc0);
-
-          /* x[1] and x[2] are packed */
-          in1 = (q15_t) x1;
-          in2 = (q15_t) x2;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
-          acc1 = __SMLAD(input1, input2, acc1);
-
-          /* x[2] and x[3] are packed */
-          in1 = (q15_t) x2;
-          in2 = (q15_t) x3;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
-          acc2 = __SMLAD(input1, input2, acc2);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* x[3] and x[4] are packed */
-          in1 = (q15_t) x3;
-          in2 = (q15_t) x0;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
-          acc3 = __SMLAD(input1, input2, acc3);
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-          /* Read y[srcBLen - 4] sample */
-          c1 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* x[2] and x[3] are packed */
-          in1 = (q15_t) x2;
-          in2 = (q15_t) x3;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
-          in1 = (q15_t) c0;
-          in2 = (q15_t) c1;
-
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
-          acc0 = __SMLAD(input1, input2, acc0);
-
-          /* x[3] and x[4] are packed */
-          in1 = (q15_t) x3;
-          in2 = (q15_t) x0;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
-          acc1 = __SMLAD(input1, input2, acc1);
-
-          /* x[4] and x[5] are packed */
-          in1 = (q15_t) x0;
-          in2 = (q15_t) x1;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
-          acc2 = __SMLAD(input1, input2, acc2);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* x[5] and x[6] are packed */
-          in1 = (q15_t) x1;
-          in2 = (q15_t) x2;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
-          acc3 = __SMLAD(input1, input2, acc3);
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += ((q31_t) x0 * c0);
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += ((q31_t) x1 * c0);
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += ((q31_t) x2 * c0);
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 += ((q31_t) x3 * c0);
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-
-          /* Reading two inputs of SrcA buffer and packing */
-          in1 = (q15_t) * px++;
-          in2 = (q15_t) * px++;
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Reading two inputs of SrcB buffer and packing */
-          in1 = (q15_t) * py--;
-          in2 = (q15_t) * py--;
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Perform the multiply-accumulates */
-          sum = __SMLAD(input1, input2, sum);
-
-          /* Reading two inputs of SrcA buffer and packing */
-          in1 = (q15_t) * px++;
-          in2 = (q15_t) * px++;
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Reading two inputs of SrcB buffer and packing */
-          in1 = (q15_t) * py--;
-          in2 = (q15_t) * py--;
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Perform the multiply-accumulates */
-          sum = __SMLAD(input1, input2, sum);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-        /* Increment the pointer pIn1 index, count by 1 */
- 	    count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-      	px = pIn1 + count;
-        py = pSrc2;	
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
-  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
deleted file mode 100644
index a3c37746..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
+++ /dev/null
@@ -1,734 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_q15.c   
-*   
-* Description:	Convolution of Q15 sequences.     
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q15 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 64-bit internal accumulator.   
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
- * This approach provides 33 guard bits and there is no risk of overflow.   
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
- *   
- * \par   
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
- *
- * \par    
- * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
- *  
- */
-
-void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLALDX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLALDX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLALDX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLALDX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLALDX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLALDX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLALDX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLALDX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-
-		c0 = *(py-1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-       /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  blockSize3 = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* input pointer */
-  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
-  }
-
-#endif /*  #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
-
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
deleted file mode 100644
index c108bed1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_q31.c    
-*    
-* Description:	Convolution of Q31 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q31 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer */
-  q31_t *pIn2;                                   /* inputB pointer */
-  q31_t *pOut = pDst;                            /* output pointer */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q63_t sum;                                     /* Accumulator */
-  q63_t acc0, acc1, acc2;                        /* Accumulator */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (q31_t *) pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = (q31_t *) pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[1] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[2] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[3] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q31_t) (sum >> 31);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll by 3 */
-    blkCnt = blockSize2 / 3;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-
-      /* Apply loop unrolling and compute 3 MACs simultaneously. */
-      k = srcBLen / 3;
-
-      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py);
-
-        /* Read x[3] sample */
-        x2 = *(px);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py - 1u);
-
-        /* Read x[4] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 += ((q63_t) x1 * c0);
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 += ((q63_t) x2 * c0);
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 += ((q63_t) x0 * c0);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py - 2u);
-
-        /* Read x[5] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 += ((q63_t) x2 * c0);
-        /* acc1 +=  x[3] * y[srcBLen - 2] */
-        acc1 += ((q63_t) x0 * c0);
-        /* acc2 +=  x[4] * y[srcBLen - 2] */
-        acc2 += ((q63_t) x1 * c0);
-
-        /* update scratch pointers */
-        px += 3u;
-        py -= 3u;
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-       ** No loop unrolling is used. */
-      k = srcBLen - (3 * (srcBLen / 3));
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = (q31_t) (acc0 >> 31);
-      *pOut++ = (q31_t) (acc1 >> 31);
-      *pOut++ = (q31_t) (acc2 >> 31);
-
-      /* Increment the pointer pIn1 index, count by 3 */
-      count += 3u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q31_t) (sum >> 31);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* input pointer */
-  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q31_t) (sum >> 31u);
-  }
-
-#endif /*     #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
deleted file mode 100644
index 12a00554..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
+++ /dev/null
@@ -1,690 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_q7.c   
-*   
-* Description:	Convolution of Q7 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q7 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 32-bit internal accumulator.   
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
- *
- * \par    
- * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
- * 
- */
-
-void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer */
-  q7_t *pIn2;                                    /* inputB pointer */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t *px;                                      /* Intermediate inputA pointer */
-  q7_t *py;                                      /* Intermediate inputB pointer */
-  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
-  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t input1, input2;                          /* Temporary input variables */
-  q15_t in1, in2;                                /* Temporary input variables */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = (srcALen - srcBLen) + 1u;
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] , x[1] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* y[srcBLen - 1] , y[srcBLen - 2] */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* x[0] * y[srcBLen - 1] */
-      /* x[1] * y[srcBLen - 2] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[2] , x[3] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* y[srcBLen - 3] , y[srcBLen - 4] */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* x[2] * y[srcBLen - 3] */
-      /* x[3] * y[srcBLen - 4] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-        /* Read y[srcBLen - 2] sample */
-        c1 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* x[0] and x[1] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[1] and x[2] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-        /* Read y[srcBLen - 4] sample */
-        c1 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[4] and x[5] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* x[5] and x[6] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += ((q15_t) x0 * c0);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += ((q15_t) x1 * c0);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += ((q15_t) x2 * c0);
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 += ((q15_t) x3 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q15_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q15_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* input pointer */
-  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
-
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
deleted file mode 100644
index 6a8127b8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_f32.c    
-*    
-* Description:	 Correlation of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup Corr Correlation    
- *    
- * Correlation is a mathematical operation that is similar to convolution.    
- * As with convolution, correlation uses two signals to produce a third signal.    
- * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.    
- * Correlation is commonly used to measure the similarity between two signals.    
- * It has applications in pattern recognition, cryptanalysis, and searching.    
- * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.    
- * Fast versions of the Q15 and Q31 functions are also provided.    
- *    
- * \par Algorithm    
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
- * The convolution of the two signals is denoted by    
- * 
    
- *                   c[n] = a[n] * b[n]    
- * 
    
- * In correlation, one of the signals is flipped in time    
- * 
    
- *                   c[n] = a[n] * b[-n]    
- * 
    
- *    
- * \par    
- * and this is mathematically defined as    
- * \image html CorrelateEquation.gif    
- * \par    
- * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.    
- * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).    
- * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.    
- *    
- * Note   
- * \par  
- * The pDst should be initialized to all zeros before being used.  
- *  
- * Fixed-Point Behavior    
- * \par    
- * Correlation requires summing up a large number of intermediate products.    
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
- * Refer to the function specific documentation below for further details of the particular algorithm used.    
- *
- *
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-/**    
- * @brief Correlation of floating-point sequences.    
- * @param[in]  *pSrcA points to the first input sequence.    
- * @param[in]  srcALen length of the first input sequence.    
- * @param[in]  *pSrcB points to the second input sequence.    
- * @param[in]  srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- */
-
-void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1;                               /* inputA pointer */
-  float32_t *pIn2;                               /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1;                              /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
-  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,    
-   * we assume zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding has to be done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-    //while(j > 0u)   
-    //{   
-    //  /* Zero is stored in the destination buffer */   
-    //  *pOut++ = 0.0f;   
-
-    //  /* Decrement the loop counter */   
-    //  j--;   
-    //}   
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum += *px++ * *py++;
-      /* x[1] * y[srcBLen - 3] */
-      sum += *px++ * *py++;
-      /* x[2] * y[srcBLen - 2] */
-      sum += *px++ * *py++;
-      /* x[3] * y[srcBLen - 1] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* x[0] * y[srcBLen - 1] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py++);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[1] * y[0] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[2] * y[0] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[3] * y[0] */
-        acc3 += x3 * c0;
-
-        /* Read y[1] sample */
-        c0 = *(py++);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 += x1 * c0;
-        /* acc1 +=  x[2] * y[1] */
-        acc1 += x2 * c0;
-        /* acc2 +=  x[3] * y[1] */
-        acc2 += x3 * c0;
-        /* acc3 +=  x[4] * y[1] */
-        acc3 += x0 * c0;
-
-        /* Read y[2] sample */
-        c0 = *(py++);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 += x2 * c0;
-        /* acc1 +=  x[3] * y[2] */
-        acc1 += x3 * c0;
-        /* acc2 +=  x[4] * y[2] */
-        acc2 += x0 * c0;
-        /* acc3 +=  x[5] * y[2] */
-        acc3 += x1 * c0;
-
-        /* Read y[3] sample */
-        c0 = *(py++);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[3] */
-        acc0 += x3 * c0;
-        /* acc1 +=  x[4] * y[3] */
-        acc1 += x0 * c0;
-        /* acc2 +=  x[5] * y[3] */
-        acc2 += x1 * c0;
-        /* acc3 +=  x[6] * y[3] */
-        acc3 += x2 * c0;
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[7] * y[4] */
-        acc3 += x3 * c0;
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = acc0;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = acc1;
-      pOut += inc;
-
-      *pOut = acc2;
-      pOut += inc;
-
-      *pOut = acc3;
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two    
-   * inputs of same length. But to improve the performance, we assume zeroes    
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted   
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0.0f;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = sum;
-    else
-      *pDst++ = sum;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
deleted file mode 100644
index 7aa289fd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
+++ /dev/null
@@ -1,512 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Correlation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @return none.    
- *    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch buffers should be aligned by 32-bit    
- *    
- *     
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
- *    
- * \par    
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
- */
-
-void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch)
-{
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */
-  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-  uint32_t tapCnt;
-  q31_t y1, y2;
-  q15_t *pScr;                                   /* Intermediate pointers        */
-  q15_t *pOut = pDst;                            /* output pointer               */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  pScr = pScratch;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr, srcALen);
-
-  /* Update pointers */
-  pScr += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = srcALen % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = (srcBLen - 1u) % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pIn2;
-
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read four samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr)++;
-
-    /* Read next four samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x1 = _SIMD32_OFFSET(pScr);
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-	  a = *pScr;
-	  b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-	  a = *(pScr + 2);
-	  b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-
-      pScr += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2);
-      acc1 += (*pScr++ * *pIn2);
-      acc2 += (*pScr++ * *pIn2);
-      acc3 += (*pScr++ * *pIn2++);
-
-      pScr -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-    *pOut = (__SSAT(acc0 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc1 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc2 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc3 >> 15u, 16));
-    pOut += inc;
-
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr++ * *pIn2++);
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-
-    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 1u;
-
-  }
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
deleted file mode 100644
index d15bb1dc..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
+++ /dev/null
@@ -1,1319 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_fast_q15.c   
-*   
-* Description:	Fast Q15 Correlation.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * This fast version uses a 32-bit accumulator with 2.30 format.   
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
- * There is no saturation on intermediate additions.   
- * Thus, if the accumulator overflows it wraps around and distorts the result.   
- * The input signals should be scaled down to avoid intermediate overflows.   
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
- *   
- * \par   
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
- */
-
-void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = __SMLAD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px + 1);
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLAD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px + 1);
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLAD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLAD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLAD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLAD(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px + 2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px + 3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLAD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLAD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py)++;
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-
-        c0 = (*py);
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 = _SIMD32_OFFSET(px + 2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (acc0 >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (acc1 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc2 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc3 >> 15);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-  q15_t a, b;
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLAD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(x1, c0, acc1);
-
-        /* Read x[2], x[3], x[4] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x2 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x2 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLAD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLAD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-		  a = *(py + 2);
-		  b = *(py + 3);
-
-		  py += 4u;
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLAD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLAD(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  	a = *(px + 2);
-	  	b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x0 = __PKHBT(a, b, 16);
-	  	a = *(px + 4);
-	  	x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x0 = __PKHBT(b, a, 16);
-	  	a = *(px + 4);
-	  	x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLAD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLAD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px + 1);
-
-		px++;;
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		x3 = __PKHBT(a, b, 16);
-	
-#else
-	
-		x3 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x3 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x3 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		py += 2u;
-
-        /* Read x[7], x[8], x[9] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x3 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x3 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-
-        c0 = (*py);
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		b = *(px + 3);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		x3 = __PKHBT(a, b, 16);
-	
-#else
-	
-		x3 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (acc0 >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (acc1 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc2 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc3 >> 15);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
deleted file mode 100644
index ed8efb72..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
+++ /dev/null
@@ -1,612 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_fast_q31.c    
-*    
-* Description:	Fast Q31 Correlation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- *    
- * \par    
- * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
- */
-
-void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[1] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[2] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[3] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum << 1;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py++);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[1] * y[0] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[2] * y[0] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[3] * y[0] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Read y[1] sample */
-        c0 = *(py++);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc1 +=  x[2] * y[1] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc2 +=  x[3] * y[1] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc3 +=  x[4] * y[1] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* Read y[2] sample */
-        c0 = *(py++);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc1 +=  x[3] * y[2] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc2 +=  x[4] * y[2] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc3 +=  x[5] * y[2] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* Read y[3] sample */
-        c0 = *(py++);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[3] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc1 +=  x[4] * y[3] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc2 +=  x[5] * y[3] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc3 +=  x[6] * y[3] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[7] * y[4] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (acc0 << 1);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q31_t) (acc1 << 1);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc2 << 1);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc3 << 1);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum << 1;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum << 1;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum << 1;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
deleted file mode 100644
index ccb8652a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_opt_q15.c    
-*    
-* Description:	Correlation of Q15 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch buffers should be aligned by 32-bit    
- *     
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * This approach provides 33 guard bits and there is no risk of overflow.    
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
- *    
- * \par    
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
- *  
- * 
- */
-
-
-void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch)
-{
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */
-  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
-  int32_t inc = 1;                               /* output pointer increment     */
-  uint32_t tapCnt;
-  q31_t y1, y2;
-  q15_t *pScr;                                   /* Intermediate pointers        */
-  q15_t *pOut = pDst;                            /* output pointer               */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  pScr = pScratch;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr, srcALen);
-
-  /* Update pointers */
-  //pIn1 += srcALen;    
-  pScr += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = srcALen % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = (srcBLen - 1u) % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pIn2;
-
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read four samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr)++;
-
-    /* Read next four samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-      x1 = _SIMD32_OFFSET(pScr);
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-	  a = *pScr;
-	  b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-	  a = *(pScr + 2);
-	  b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-
-      pScr += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2);
-      acc1 += (*pScr++ * *pIn2);
-      acc2 += (*pScr++ * *pIn2);
-      acc3 += (*pScr++ * *pIn2++);
-
-      pScr -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-    *pOut = (__SSAT(acc0 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc1 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc2 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc3 >> 15u, 16));
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr++ * *pIn2++);
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 1u;
-
-  }
-
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
deleted file mode 100644
index 2f62f606..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_opt_q7.c    
-*    
-* Description:	Correlation of Q7 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q7 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
- * @return none.    
- *    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
- *        
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.  
- *  
- * 
- */
-
-
-
-void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q7_t *pOut = pDst;                             /* output pointer                */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */
-  q7_t *pIn1;                                    /* inputA pointer                */
-  q7_t *pIn2;                                    /* inputB pointer                */
-  q15_t *py;                                     /* Intermediate inputB pointer   */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  uint32_t j, k = 0u, blkCnt;                    /* loop counter                  */
-  int32_t inc = 1;                               /* output pointer increment          */
-  uint32_t outBlockSize;                         /* loop counter                  */
-  q15_t x4;                                      /* Temporary input variable      */
-  uint32_t tapCnt;                               /* loop counter                  */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-
-  /* Copy (srcBLen) samples in scratch buffer */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy (srcALen) samples in scratch buffer */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for second sequence */
-  py = pScratch2;
-
-  /* Initialization of pScr2 pointer */
-  pScr2 = pScratch2;
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-      acc0 = __SMLAD(x2, y1, acc0);
-
-      acc2 = __SMLAD(x1, y1, acc2);
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      pScr2 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2);
-      acc1 += (*pScr1++ * *pScr2);
-      acc2 += (*pScr1++ * *pScr2);
-      acc3 += (*pScr1++ * *pScr2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-      acc0 += (*pScr1++ * *pScr2++);
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
deleted file mode 100644
index 3003f751..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
+++ /dev/null
@@ -1,719 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_q15.c   
-*   
-* Description:	Correlation of Q15 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q15 sequences. 
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 64-bit internal accumulator.   
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
- * This approach provides 33 guard bits and there is no risk of overflow.   
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
- *   
- * \par   
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
- *
- * \par    
- * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
- * 
- */
-
-void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = __SMLALD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px + 1);
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLALD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLALD(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px + 1);
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLALD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLALD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLALD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLALD(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px + 2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px + 3);
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLALD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLALD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALD(x3, c0, acc2);
-        acc3 = __SMLALD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py)++;
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALD(x3, c0, acc2);
-        acc3 = __SMLALD(x2, c0, acc3);
-
-        c0 = (*py);
-
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[10] */
-        x3 = _SIMD32_OFFSET(px + 2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
-      pOut += inc;
-
-      /* Increment the count by 4 as 4 output values are computed */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment count by 1, as one output value is computed */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
-  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
-  q63_t sum;                                     /* Accumulators                  */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two   
-   * inputs of same length. But to improve the performance, we include zeroes   
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted  
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
-    else
-      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
-  }
-
-#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
deleted file mode 100644
index eaab75f7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
+++ /dev/null
@@ -1,665 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_q31.c    
-*    
-* Description:	Correlation of Q31 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q31 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1;                                  /* Intermediate pointers        */
-  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */
-  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,    
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[1] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[2] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[3] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q31_t) (sum >> 31);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll by 3 */
-    blkCnt = blockSize2 / 3;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-
-      /* Apply loop unrolling and compute 3 MACs simultaneously. */
-      k = srcBLen / 3;
-
-      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py);
-
-        /* Read x[2] sample */
-        x2 = *(px);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[1] * y[0] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[2] * y[0] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Read y[1] sample */
-        c0 = *(py + 1u);
-
-        /* Read x[3] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 += ((q63_t) x1 * c0);
-        /* acc1 +=  x[2] * y[1] */
-        acc1 += ((q63_t) x2 * c0);
-        /* acc2 +=  x[3] * y[1] */
-        acc2 += ((q63_t) x0 * c0);
-
-        /* Read y[2] sample */
-        c0 = *(py + 2u);
-
-        /* Read x[4] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 += ((q63_t) x2 * c0);
-        /* acc1 +=  x[3] * y[2] */
-        acc1 += ((q63_t) x0 * c0);
-        /* acc2 +=  x[4] * y[2] */
-        acc2 += ((q63_t) x1 * c0);
-
-        /* update scratch pointers */
-        px += 3u;
-        py += 3u;
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-       ** No loop unrolling is used. */
-      k = srcBLen - (3 * (srcBLen / 3));
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (acc0 >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q31_t) (acc1 >> 31);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc2 >> 31);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 3 */
-      count += 3u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (sum >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (sum >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q31_t) (sum >> 31);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
-  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
-  q63_t sum;                                     /* Accumulators                  */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two    
-   * inputs of same length. But to improve the performance, we include zeroes    
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted   
-   * using correlation but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate correlation for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to correlation equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q31_t) (sum >> 31u);
-    else
-      *pDst++ = (q31_t) (sum >> 31u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
deleted file mode 100644
index 6adef05e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
+++ /dev/null
@@ -1,790 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_q7.c   
-*   
-* Description:	Correlation of Q7 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q7 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 32-bit internal accumulator.   
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
- *
- * \par    
- * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
- * 
- */
-
-void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer               */
-  q7_t *pIn2;                                    /* inputB pointer               */
-  q7_t *pOut = pDst;                             /* output pointer               */
-  q7_t *px;                                      /* Intermediate inputA pointer  */
-  q7_t *py;                                      /* Intermediate inputB pointer  */
-  q7_t *pSrc1;                                   /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t input1, input2;                          /* temporary variables */
-  q15_t in1, in2;                                /* temporary variables */
-  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] , x[1] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[srcBLen - 4] , y[srcBLen - 3] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* x[0] * y[srcBLen - 4] */
-      /* x[1] * y[srcBLen - 3] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[2] , x[3] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[srcBLen - 2] , y[srcBLen - 1] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* x[2] * y[srcBLen - 2] */
-      /* x[3] * y[srcBLen - 1] */
-      sum = __SMLAD(input1, input2, sum);
-
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q31_t) ((q15_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *px++;
-      x1 = *px++;
-      x2 = *px++;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *py++;
-        /* Read y[1] sample */
-        c1 = *py++;
-
-        /* Read x[3] sample */
-        x3 = *px++;
-
-        /* x[0] and x[1] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[0] and y[1] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[1] and x[2] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc1 += x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-        /* Read y[2] sample */
-        c0 = *py++;
-        /* Read y[3] sample */
-        c1 = *py++;
-
-        /* Read x[5] sample */
-        x1 = *px++;
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[2] and y[3] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[4] and x[5] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[6] sample */
-        x2 = *px++;
-
-        /* x[5] and x[6] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *py++;
-
-        /* Read x[7] sample */
-        x3 = *px++;
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += ((q15_t) x0 * c0);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += ((q15_t) x1 * c0);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += ((q15_t) x2 * c0);
-        /* acc3 +=  x[7] * y[4] */
-        acc3 += ((q15_t) x3 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
-      pOut += inc;
-
-	  count += 4u;
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py++;
-        in2 = (q15_t) * py++;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py++;
-        in2 = (q15_t) * py++;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q15_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-	  count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q15_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[0] , y[1] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[2] , y[3] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
-  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two   
-   * inputs of same length. But to improve the performance, we include zeroes   
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted  
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
-    else
-      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
deleted file mode 100644
index 15929739..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_f32.c    
-*    
-* Description:	FIR decimation for floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator    
- *    
- * These functions combine an FIR filter together with a decimator.    
- * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.    
- * Conceptually, the functions are equivalent to the block diagram below:    
- * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"    
- * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized    
- * cutoff frequency of 1/M in order to prevent aliasing distortion.    
- * The user of the function is responsible for providing the filter coefficients.    
- *    
- * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.    
- * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the    
- * samples output by the decimator are computed.    
- * The functions operate on blocks of input and output data.    
- * pSrc points to an array of blockSize input values and    
- * pDst points to an array of blockSize/M output values.    
- * In order to have an integer number of output samples blockSize    
- * must always be a multiple of the decimation factor M.    
- *    
- * The library provides separate functions for Q15, Q31 and floating-point data types.    
- *    
- * \par Algorithm:    
- * The FIR portion of the algorithm uses the standard form filter:    
- * 
    
- *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- * where, b[n] are the filter coefficients.    
- * \par   
- * The pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * - Checks to make sure that the size of the input is a multiple of the decimation factor.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    
- *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    
- *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    
- * 
    
- * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;    
- * pCoeffs is the address of the coefficient buffer;    
- * pState is the address of the state buffer.    
- * Be sure to set the values in the state buffer to zeros when doing static initialization.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-  /**    
-   * @brief Processing function for the floating-point FIR decimator.    
-   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.    
-   * @param[in] *pSrc     points to the block of input data.    
-   * @param[out] *pDst    points to the block of output data.    
-   * @param[in] blockSize number of input samples to process per call.    
-   * @return none.    
-   */
-
-void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t sum0;                                /* Accumulator */
-  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  uint32_t blkCntN4;
-  float32_t *px0, *px1, *px2, *px3;
-  float32_t acc0, acc1, acc2, acc3;
-  float32_t x1, x2, x3;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 4;
-  blkCntN4 = outBlockSize - (4 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy 4 * decimation factor number of new input samples into the state buffer */
-    i = 4 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulators to zero */
-    acc0 = 0.0f;
-    acc1 = 0.0f;
-    acc2 = 0.0f;
-    acc3 = 0.0f;
-
-    /* Initialize state pointer for all the samples */
-    px0 = pState;
-    px1 = pState + S->M;
-    px2 = pState + 2 * S->M;
-    px3 = pState + 3 * S->M;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample for acc0 */
-      x0 = *(px0++);
-      /* Read x[n-numTaps-1] sample for acc1 */
-      x1 = *(px1++);
-      /* Read x[n-numTaps-1] sample for acc2 */
-      x2 = *(px2++);
-      /* Read x[n-numTaps-1] sample for acc3 */
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch  state variables for acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + 4 * S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = acc0;
-    *pDst++ = acc1;
-    *pDst++ = acc2;
-    *pDst++ = acc3;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN4 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = sum0;
-
-    /* Decrement the loop counter */
-    blkCntN4--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = sum0;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  i = (numTaps - 1u);
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
deleted file mode 100644
index 8ae0d2e0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
+++ /dev/null
@@ -1,598 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_fast_q15.c    
-*    
-* Description:	Fast Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * \par Restrictions   
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
- *	In this case input, output, state buffers should be aligned by 32-bit   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).    
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
- * Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.    
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
-  q31_t sum0;                                    /* Accumulators */
-  q31_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c1 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c0, sum0);
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c1, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c0, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-
-void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
-  q31_t sum0;                                    /* Accumulators */
-  q31_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] and sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] and  sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
deleted file mode 100644
index 4f012696..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_fast_q31.c    
-*    
-* Description:	Fast Q31 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
- * Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.    
- */
-
-void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q31_t *px;                                     /* Temporary pointers for state buffer */
-  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
-  q31_t sum0;                                    /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-  uint32_t blkCntN2;
-  q31_t x1;
-  q31_t acc0, acc1;
-  q31_t *px0, *px1;
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-
-  blkCnt = outBlockSize / 2;
-  blkCntN2 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-    px1 = pState + S->M;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb);
-
-      /* Read x[n-numTaps-1] for sample 0 sample 1 */
-      x0 = *(px0);
-      x1 = *(px1);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb + 1u);
-
-      /* Read x[n-numTaps-2]  for sample 0 sample 1  */
-      x0 = *(px0 + 1u);
-      x1 = *(px1 + 1u);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb + 2u);
-
-      /* Read x[n-numTaps-3]  for sample 0 sample 1 */
-      x0 = *(px0 + 2u);
-      x1 = *(px1 + 2u);
-      pb += 4u;
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb - 1u);
-
-      /* Read x[n-numTaps-4] for sample 0 sample 1 */
-      x0 = *(px0 + 3u);
-      x1 = *(px1 + 3u);
-
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* update state pointers */
-      px0 += 4u;
-      px1 += 4u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px0++);
-      x1 = *(px1++);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-    *pDst++ = (q31_t) (acc1 << 1);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN2 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 << 1);
-
-    /* Decrement the loop counter */
-    blkCntN2--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
deleted file mode 100644
index 78965103..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_f32.c    
-*    
-* Description:  Floating-point FIR Decimator initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point FIR decimator.    
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation Factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
deleted file mode 100644
index a3fad6b8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_q15.c    
-*    
-* Description:  Initialization function for the Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q15 FIR decimator.    
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples    
- * to the call arm_fir_decimate_q15().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
deleted file mode 100644
index 9d332f31..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_q31.c    
-*    
-* Description:  Initialization function for Q31 FIR Decimation filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q31 FIR decimator.    
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
deleted file mode 100644
index f3a6a4a2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
+++ /dev/null
@@ -1,696 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_q15.c    
-*    
-* Description:	Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR decimator.    
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the location where the output result is written.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  q63_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c1 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c0, sum0);
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c1, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c0, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  q63_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] and sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] and  sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#else
-
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q31_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /*Store filter output , smlad will return the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = numTaps - 1u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-}
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
deleted file mode 100644
index 5696b231..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
+++ /dev/null
@@ -1,311 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_q31.c    
-*    
-* Description:	Q31 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR decimator.    
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q31_t *px;                                     /* Temporary pointers for state buffer */
-  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
-  q63_t sum0;                                    /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor    
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 >> 31);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 >> 31);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = numTaps - 1u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
deleted file mode 100644
index a827e68d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
+++ /dev/null
@@ -1,997 +0,0 @@
-/* ----------------------------------------------------------------------  
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.  
-*  
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*  
-* Project: 	    CMSIS DSP Library  
-* Title:	    arm_fir_f32.c  
-*  
-* Description:	Floating-point FIR filter processing function.  
-*  
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**  
-* @ingroup groupFilters  
-*/
-
-/**  
-* @defgroup FIR Finite Impulse Response (FIR) Filters  
-*  
-* This set of functions implements Finite Impulse Response (FIR) filters  
-* for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.  
-* The functions operate on blocks of input and output data and each call to the function processes  
-* blockSize samples through the filter.  pSrc and  
-* pDst points to input and output arrays containing blockSize values.  
-*  
-* \par Algorithm:  
-* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.  
-* Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].  
-* 
  
-*    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  
-* 
  
-* \par  
-* \image html FIR.gif "Finite Impulse Response filter"  
-* \par  
-* pCoeffs points to a coefficient array of size numTaps.  
-* Coefficients are stored in time reversed order.  
-* \par  
-* 
  
-*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  
-* 
  
-* \par  
-* pState points to a state array of size numTaps + blockSize - 1.  
-* Samples in the state buffer are stored in the following order.  
-* \par  
-* 
  
-*    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  
-* 
  
-* \par  
-* Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.  
-* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,  
-* to be avoided and yields a significant speed improvement.  
-* The state variables are updated after each block of data is processed; the coefficients are untouched.  
-* \par Instance Structure  
-* The coefficients and state variables for a filter are stored together in an instance data structure.  
-* A separate instance structure must be defined for each filter.  
-* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.  
-* There are separate instance structure declarations for each of the 4 supported data types.  
-*  
-* \par Initialization Functions  
-* There is also an associated initialization function for each data type.  
-* The initialization function performs the following operations:  
-* - Sets the values of the internal structure fields.  
-* - Zeros out the values in the state buffer.  
-* To do this manually without calling the init function, assign the follow subfields of the instance structure:
-* numTaps, pCoeffs, pState. Also set all of the values in pState to zero. 
-*  
-* \par  
-* Use of the initialization function is optional.  
-* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.  
-* To place an instance structure into a const data section, the instance structure must be manually initialized.  
-* Set the values in the state buffer to zeros before static initialization.  
-* The code below statically initializes each of the 4 different data type filter instance structures  
-* 
  
-*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  
-*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  
-*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  
-*arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  
-* 
  
-*  
-* where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;  
-* pCoeffs is the address of the coefficient buffer.  
-*  
-* \par Fixed-Point Behavior  
-* Care must be taken when using the fixed-point versions of the FIR filter functions.  
-* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.  
-* Refer to the function specific documentation below for usage guidelines.  
-*/
-
-/**  
-* @addtogroup FIR  
-* @{  
-*/
-
-/**  
-*  
-* @param[in]  *S points to an instance of the floating-point FIR filter structure.  
-* @param[in]  *pSrc points to the block of input data.  
-* @param[out] *pDst points to the block of output data.  
-* @param[in]  blockSize number of samples to process per call.  
-* @return     none.  
-*  
-*/
-
-#if defined(ARM_MATH_CM7)
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-   float32_t *pState = S->pState;                 /* State pointer */
-   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
-   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
-   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-   /* pStateCurnt points to the location where the new input data should be written */
-   pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-   /* Apply loop unrolling and compute 8 output values simultaneously.  
-    * The variables acc0 ... acc7 hold output values that are being computed:  
-    *  
-    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
-    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
-    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
-    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
-    */
-   blkCnt = blockSize >> 3;
-
-   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.  
-   ** a second loop below computes the remaining 1 to 7 samples. */
-   while(blkCnt > 0u)
-   {
-      /* Copy four new input samples into the state buffer */
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-      acc4 = 0.0f;
-      acc5 = 0.0f;
-      acc6 = 0.0f;
-      acc7 = 0.0f;		
-
-      /* Initialize state pointer */
-      px = pState;
-
-      /* Initialize coeff pointer */
-      pb = (pCoeffs);		
-   
-      /* This is separated from the others to avoid 
-       * a call to __aeabi_memmove which would be slower
-       */
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-
-      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-      x0 = *px++;
-      x1 = *px++;
-      x2 = *px++;
-      x3 = *px++;
-      x4 = *px++;
-      x5 = *px++;
-      x6 = *px++;
-
-      /* Loop unrolling.  Process 8 taps at a time. */
-      tapCnt = numTaps >> 3u;
-      
-      /* Loop over the number of taps.  Unroll by a factor of 8.  
-       ** Repeat until we've computed numTaps-8 coefficients. */
-      while(tapCnt > 0u)
-      {
-         /* Read the b[numTaps-1] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-3] sample */
-         x7 = *(px++);
-
-         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
-         acc0 += x0 * c0;
-
-         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
-         acc1 += x1 * c0;
-
-         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
-         acc2 += x2 * c0;
-
-         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
-         acc3 += x3 * c0;
-
-         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
-         acc4 += x4 * c0;
-
-         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
-         acc5 += x5 * c0;
-
-         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
-         acc6 += x6 * c0;
-
-         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
-         acc7 += x7 * c0;
-         
-         /* Read the b[numTaps-2] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-4] sample */
-         x0 = *(px++);
-
-         /* Perform the multiply-accumulate */
-         acc0 += x1 * c0;
-         acc1 += x2 * c0;   
-         acc2 += x3 * c0;   
-         acc3 += x4 * c0;   
-         acc4 += x5 * c0;   
-         acc5 += x6 * c0;   
-         acc6 += x7 * c0;   
-         acc7 += x0 * c0;   
-         
-         /* Read the b[numTaps-3] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-5] sample */
-         x1 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x2 * c0;
-         acc1 += x3 * c0;   
-         acc2 += x4 * c0;   
-         acc3 += x5 * c0;   
-         acc4 += x6 * c0;   
-         acc5 += x7 * c0;   
-         acc6 += x0 * c0;   
-         acc7 += x1 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x2 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x3 * c0;
-         acc1 += x4 * c0;   
-         acc2 += x5 * c0;   
-         acc3 += x6 * c0;   
-         acc4 += x7 * c0;   
-         acc5 += x0 * c0;   
-         acc6 += x1 * c0;   
-         acc7 += x2 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x3 = *(px++);
-         /* Perform the multiply-accumulates */      
-         acc0 += x4 * c0;
-         acc1 += x5 * c0;   
-         acc2 += x6 * c0;   
-         acc3 += x7 * c0;   
-         acc4 += x0 * c0;   
-         acc5 += x1 * c0;   
-         acc6 += x2 * c0;   
-         acc7 += x3 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x4 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x5 * c0;
-         acc1 += x6 * c0;   
-         acc2 += x7 * c0;   
-         acc3 += x0 * c0;   
-         acc4 += x1 * c0;   
-         acc5 += x2 * c0;   
-         acc6 += x3 * c0;   
-         acc7 += x4 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x5 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x6 * c0;
-         acc1 += x7 * c0;   
-         acc2 += x0 * c0;   
-         acc3 += x1 * c0;   
-         acc4 += x2 * c0;   
-         acc5 += x3 * c0;   
-         acc6 += x4 * c0;   
-         acc7 += x5 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x6 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x7 * c0;
-         acc1 += x0 * c0;   
-         acc2 += x1 * c0;   
-         acc3 += x2 * c0;   
-         acc4 += x3 * c0;   
-         acc5 += x4 * c0;   
-         acc6 += x5 * c0;   
-         acc7 += x6 * c0;   
-
-         tapCnt--;
-      }
-
-      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
-      tapCnt = numTaps % 0x8u;
-
-      while(tapCnt > 0u)
-      {
-         /* Read coefficients */
-         c0 = *(pb++);
-
-         /* Fetch 1 state variable */
-         x7 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         acc0 += x0 * c0;
-         acc1 += x1 * c0;   
-         acc2 += x2 * c0;   
-         acc3 += x3 * c0;   
-         acc4 += x4 * c0;   
-         acc5 += x5 * c0;   
-         acc6 += x6 * c0;   
-         acc7 += x7 * c0;   
-
-         /* Reuse the present sample states for next sample */
-         x0 = x1;
-         x1 = x2;
-         x2 = x3;
-         x3 = x4;
-         x4 = x5;
-         x5 = x6;
-         x6 = x7;
-
-         /* Decrement the loop counter */
-         tapCnt--;
-      }
-
-      /* Advance the state pointer by 8 to process the next group of 8 samples */
-      pState = pState + 8;
-
-      /* The results in the 8 accumulators, store in the destination buffer. */
-      *pDst++ = acc0;
-      *pDst++ = acc1;
-      *pDst++ = acc2;
-      *pDst++ = acc3;
-      *pDst++ = acc4;
-      *pDst++ = acc5;
-      *pDst++ = acc6;
-      *pDst++ = acc7;
-
-      blkCnt--;
-   }
-
-   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.  
-   ** No loop unrolling is used. */
-   blkCnt = blockSize % 0x8u;
-
-   while(blkCnt > 0u)
-   {
-      /* Copy one sample at a time into state buffer */
-      *pStateCurnt++ = *pSrc++;
-
-      /* Set the accumulator to zero */
-      acc0 = 0.0f;
-
-      /* Initialize state pointer */
-      px = pState;
-
-      /* Initialize Coefficient pointer */
-      pb = (pCoeffs);
-
-      i = numTaps;
-
-      /* Perform the multiply-accumulates */
-      do
-      {
-         acc0 += *px++ * *pb++;
-         i--;
-
-      } while(i > 0u);
-
-      /* The result is store in the destination buffer. */
-      *pDst++ = acc0;
-
-      /* Advance state pointer by 1 for the next sample */
-      pState = pState + 1;
-
-      blkCnt--;
-   }
-
-   /* Processing is complete.  
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.  
-   ** This prepares the state buffer for the next function call. */
-
-   /* Points to the start of the state buffer */
-   pStateCurnt = S->pState;
-
-   tapCnt = (numTaps - 1u) >> 2u;
-
-   /* copy data */
-   while(tapCnt > 0u)
-   {
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-   }
-
-   /* Calculate remaining number of copies */
-   tapCnt = (numTaps - 1u) % 0x4u;
-
-   /* Copy the remaining q31_t data */
-   while(tapCnt > 0u)
-   {
-      *pStateCurnt++ = *pState++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-   }
-}
-
-#elif defined(ARM_MATH_CM0_FAMILY)
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-   float32_t *pState = S->pState;                 /* State pointer */
-   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-   /* Run the below code for Cortex-M0 */
-
-   float32_t acc;
-
-   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-   /* pStateCurnt points to the location where the new input data should be written */
-   pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-   /* Initialize blkCnt with blockSize */
-   blkCnt = blockSize;
-
-   while(blkCnt > 0u)
-   {
-      /* Copy one sample at a time into state buffer */
-      *pStateCurnt++ = *pSrc++;
-
-      /* Set the accumulator to zero */
-      acc = 0.0f;
-
-      /* Initialize state pointer */
-      px = pState;
-
-      /* Initialize Coefficient pointer */
-      pb = pCoeffs;
-
-      i = numTaps;
-
-      /* Perform the multiply-accumulates */
-      do
-      {
-         /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-         acc += *px++ * *pb++;
-         i--;
-
-      } while(i > 0u);
-
-      /* The result is store in the destination buffer. */
-      *pDst++ = acc;
-
-      /* Advance state pointer by 1 for the next sample */
-      pState = pState + 1;
-
-      blkCnt--;
-   }
-
-   /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-   /* Points to the start of the state buffer */
-   pStateCurnt = S->pState;
-
-   /* Copy numTaps number of values */
-   tapCnt = numTaps - 1u;
-
-   /* Copy data */
-   while(tapCnt > 0u)
-   {
-      *pStateCurnt++ = *pState++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-   }
-
-}
-
-#else
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_f32(
-const arm_fir_instance_f32 * S,
-float32_t * pSrc,
-float32_t * pDst,
-uint32_t blockSize)
-{
-   float32_t *pState = S->pState;                 /* State pointer */
-   float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-   float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-   float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-   float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
-   float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
-   uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-   uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-   float32_t p0,p1,p2,p3,p4,p5,p6,p7;             /* Temporary product values */
-
-   /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-   /* pStateCurnt points to the location where the new input data should be written */
-   pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-   /* Apply loop unrolling and compute 8 output values simultaneously.  
-    * The variables acc0 ... acc7 hold output values that are being computed:  
-    *  
-    *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
-    *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
-    *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
-    *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
-    */
-   blkCnt = blockSize >> 3;
-
-   /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.  
-   ** a second loop below computes the remaining 1 to 7 samples. */
-   while(blkCnt > 0u)
-   {
-      /* Copy four new input samples into the state buffer */
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-      acc4 = 0.0f;
-      acc5 = 0.0f;
-      acc6 = 0.0f;
-      acc7 = 0.0f;		
-
-      /* Initialize state pointer */
-      px = pState;
-
-      /* Initialize coeff pointer */
-      pb = (pCoeffs);		
-   
-      /* This is separated from the others to avoid 
-       * a call to __aeabi_memmove which would be slower
-       */
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-      *pStateCurnt++ = *pSrc++;
-
-      /* Read the first seven samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-      x0 = *px++;
-      x1 = *px++;
-      x2 = *px++;
-      x3 = *px++;
-      x4 = *px++;
-      x5 = *px++;
-      x6 = *px++;
-
-      /* Loop unrolling.  Process 8 taps at a time. */
-      tapCnt = numTaps >> 3u;
-      
-      /* Loop over the number of taps.  Unroll by a factor of 8.  
-       ** Repeat until we've computed numTaps-8 coefficients. */
-      while(tapCnt > 0u)
-      {
-         /* Read the b[numTaps-1] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-3] sample */
-         x7 = *(px++);
-
-         /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
-         p0 = x0 * c0;
-
-         /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
-         p1 = x1 * c0;
-
-         /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
-         p2 = x2 * c0;
-
-         /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
-         p3 = x3 * c0;
-
-         /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
-         p4 = x4 * c0;
-
-         /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
-         p5 = x5 * c0;
-
-         /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
-         p6 = x6 * c0;
-
-         /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
-         p7 = x7 * c0;
-         
-         /* Read the b[numTaps-2] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-4] sample */
-         x0 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-
-         /* Perform the multiply-accumulate */
-         p0 = x1 * c0;
-         p1 = x2 * c0;   
-         p2 = x3 * c0;   
-         p3 = x4 * c0;   
-         p4 = x5 * c0;   
-         p5 = x6 * c0;   
-         p6 = x7 * c0;   
-         p7 = x0 * c0;   
-         
-         /* Read the b[numTaps-3] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-5] sample */
-         x1 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x2 * c0;
-         p1 = x3 * c0;   
-         p2 = x4 * c0;   
-         p3 = x5 * c0;   
-         p4 = x6 * c0;   
-         p5 = x7 * c0;   
-         p6 = x0 * c0;   
-         p7 = x1 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x2 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x3 * c0;
-         p1 = x4 * c0;   
-         p2 = x5 * c0;   
-         p3 = x6 * c0;   
-         p4 = x7 * c0;   
-         p5 = x0 * c0;   
-         p6 = x1 * c0;   
-         p7 = x2 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x3 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x4 * c0;
-         p1 = x5 * c0;   
-         p2 = x6 * c0;   
-         p3 = x7 * c0;   
-         p4 = x0 * c0;   
-         p5 = x1 * c0;   
-         p6 = x2 * c0;   
-         p7 = x3 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x4 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x5 * c0;
-         p1 = x6 * c0;   
-         p2 = x7 * c0;   
-         p3 = x0 * c0;   
-         p4 = x1 * c0;   
-         p5 = x2 * c0;   
-         p6 = x3 * c0;   
-         p7 = x4 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x5 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x6 * c0;
-         p1 = x7 * c0;   
-         p2 = x0 * c0;   
-         p3 = x1 * c0;   
-         p4 = x2 * c0;   
-         p5 = x3 * c0;   
-         p6 = x4 * c0;   
-         p7 = x5 * c0;   
-
-         /* Read the b[numTaps-4] coefficient */
-         c0 = *(pb++);
-
-         /* Read x[n-numTaps-6] sample */
-         x6 = *(px++);
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Perform the multiply-accumulates */      
-         p0 = x7 * c0;
-         p1 = x0 * c0;   
-         p2 = x1 * c0;   
-         p3 = x2 * c0;   
-         p4 = x3 * c0;   
-         p5 = x4 * c0;   
-         p6 = x5 * c0;   
-         p7 = x6 * c0;   
-
-         tapCnt--;
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-      }
-
-      /* If the filter length is not a multiple of 8, compute the remaining filter taps */
-      tapCnt = numTaps % 0x8u;
-
-      while(tapCnt > 0u)
-      {
-         /* Read coefficients */
-         c0 = *(pb++);
-
-         /* Fetch 1 state variable */
-         x7 = *(px++);
-
-         /* Perform the multiply-accumulates */      
-         p0 = x0 * c0;
-         p1 = x1 * c0;   
-         p2 = x2 * c0;   
-         p3 = x3 * c0;   
-         p4 = x4 * c0;   
-         p5 = x5 * c0;   
-         p6 = x6 * c0;   
-         p7 = x7 * c0;   
-
-         /* Reuse the present sample states for next sample */
-         x0 = x1;
-         x1 = x2;
-         x2 = x3;
-         x3 = x4;
-         x4 = x5;
-         x5 = x6;
-         x6 = x7;
-         
-         acc0 += p0;
-         acc1 += p1;
-         acc2 += p2;
-         acc3 += p3;
-         acc4 += p4;
-         acc5 += p5;
-         acc6 += p6;
-         acc7 += p7;
-
-         /* Decrement the loop counter */
-         tapCnt--;
-      }
-
-      /* Advance the state pointer by 8 to process the next group of 8 samples */
-      pState = pState + 8;
-
-      /* The results in the 8 accumulators, store in the destination buffer. */
-      *pDst++ = acc0;
-      *pDst++ = acc1;
-      *pDst++ = acc2;
-      *pDst++ = acc3;
-      *pDst++ = acc4;
-      *pDst++ = acc5;
-      *pDst++ = acc6;
-      *pDst++ = acc7;
-
-      blkCnt--;
-   }
-
-   /* If the blockSize is not a multiple of 8, compute any remaining output samples here.  
-   ** No loop unrolling is used. */
-   blkCnt = blockSize % 0x8u;
-
-   while(blkCnt > 0u)
-   {
-      /* Copy one sample at a time into state buffer */
-      *pStateCurnt++ = *pSrc++;
-
-      /* Set the accumulator to zero */
-      acc0 = 0.0f;
-
-      /* Initialize state pointer */
-      px = pState;
-
-      /* Initialize Coefficient pointer */
-      pb = (pCoeffs);
-
-      i = numTaps;
-
-      /* Perform the multiply-accumulates */
-      do
-      {
-         acc0 += *px++ * *pb++;
-         i--;
-
-      } while(i > 0u);
-
-      /* The result is store in the destination buffer. */
-      *pDst++ = acc0;
-
-      /* Advance state pointer by 1 for the next sample */
-      pState = pState + 1;
-
-      blkCnt--;
-   }
-
-   /* Processing is complete.  
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.  
-   ** This prepares the state buffer for the next function call. */
-
-   /* Points to the start of the state buffer */
-   pStateCurnt = S->pState;
-
-   tapCnt = (numTaps - 1u) >> 2u;
-
-   /* copy data */
-   while(tapCnt > 0u)
-   {
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-      *pStateCurnt++ = *pState++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-   }
-
-   /* Calculate remaining number of copies */
-   tapCnt = (numTaps - 1u) % 0x4u;
-
-   /* Copy the remaining q31_t data */
-   while(tapCnt > 0u)
-   {
-      *pStateCurnt++ = *pState++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-   }
-}
-
-#endif 
-
-/**  
-* @} end of FIR group  
-*/
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
deleted file mode 100644
index 72b50635..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_fast_q15.c    
-*    
-* Description:  Q15 Fast FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q15 FIR filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
- *    
- * \par    
- * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_init_q15() to initialize the filter structure.    
- */
-
-void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.      
-   * The variables acc0 ... acc3 hold output values that are being computed:      
-   *      
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.      
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
-    px = pState;
-
-    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = *__SIMD32(px)++;
-
-    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
-    x2 = *__SIMD32(px)++;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.      
-     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLAD(x2, c0, acc2);
-
-      /* pack  x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack  x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLADX(x1, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLAD(x2, c0, acc0);
-
-      /* Read state x[n-N-6], x[n-N-7] with offset */
-      x2 = _SIMD32_OFFSET(px + 2u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLAD(x0, c0, acc2);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack  x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLADX(x1, c0, acc3);
-
-      /* Update state pointer for next state reading */
-      px += 4u;
-
-      /* Decrement tap count */
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-
-      /* Read last two coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLAD(x0, c0, acc0);
-      acc2 = __SMLAD(x2, c0, acc2);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read last state variables */
-      x0 = *__SIMD32(px);
-
-      /* Perform the multiply-accumulates */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* Perform the multiply-accumulates */
-      acc3 = __SMLADX(x1, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Use SIMD to hold states and coefficients */
-    px = pState;
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1u;
-
-    do
-    {
-
-      acc0 += (q31_t) * px++ * *pb++;
-	  acc0 += (q31_t) * px++ * *pb++;
-
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.      
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
deleted file mode 100644
index 13073c43..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
+++ /dev/null
@@ -1,305 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_fast_q31.c    
-*    
-* Description:	Processing function for the Q31 Fast FIR filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q31 structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- *    
- * \par    
- * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_init_q31() to initialize the filter structure.    
- */
-
-IAR_ONLY_LOW_OPTIMIZATION_ENTER
-void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
-  q31_t c0;                                      /* Temporary variable to hold coefficient value */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first three samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-    x0 = *(px++);
-    x1 = *(px++);
-    x2 = *(px++);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *pb;
-
-      /* Read x[n-numTaps-3] sample */
-      x3 = *px;
-
-      /* acc0 +=  b[numTaps] * x[n-numTaps] */
-      multAcc_32x32_keep32_R(acc0, x0, c0);
-
-      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
-      multAcc_32x32_keep32_R(acc1, x1, c0);
-
-      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
-      multAcc_32x32_keep32_R(acc2, x2, c0);
-
-      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
-      multAcc_32x32_keep32_R(acc3, x3, c0);
-
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb + 1u);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px + 1u);
-
-      /* Perform the multiply-accumulates */      
-      multAcc_32x32_keep32_R(acc0, x1, c0);
-      multAcc_32x32_keep32_R(acc1, x2, c0);
-      multAcc_32x32_keep32_R(acc2, x3, c0);
-      multAcc_32x32_keep32_R(acc3, x0, c0);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb + 2u);
-
-      /* Read x[n-numTaps-5] sample */
-      x1 = *(px + 2u);
-
-      /* Perform the multiply-accumulates */      
-      multAcc_32x32_keep32_R(acc0, x2, c0);
-      multAcc_32x32_keep32_R(acc1, x3, c0);
-      multAcc_32x32_keep32_R(acc2, x0, c0);
-      multAcc_32x32_keep32_R(acc3, x1, c0);
-
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *(pb + 3u);
-
-      /* Read x[n-numTaps-6] sample */
-      x2 = *(px + 3u);
-
-      /* Perform the multiply-accumulates */      
-      multAcc_32x32_keep32_R(acc0, x3, c0);
-      multAcc_32x32_keep32_R(acc1, x0, c0);
-      multAcc_32x32_keep32_R(acc2, x1, c0);
-      multAcc_32x32_keep32_R(acc3, x2, c0);
-
-      /* update coefficient pointer */
-      pb += 4u;
-      px += 4u;
-      
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
-    i = numTaps - (tapCnt * 4u);
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x3 = *(px++);
-
-      /* Perform the multiply-accumulates */      
-      multAcc_32x32_keep32_R(acc0, x0, c0);
-      multAcc_32x32_keep32_R(acc1, x1, c0);
-      multAcc_32x32_keep32_R(acc2, x2, c0);
-      multAcc_32x32_keep32_R(acc3, x3, c0);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-      x2 = x3;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31    
-     ** Then store the 4 outputs in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-    *pDst++ = (q31_t) (acc1 << 1);
-    *pDst++ = (q31_t) (acc2 << 1);
-    *pDst++ = (q31_t) (acc3 << 1);
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.31    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-
-}
-IAR_ONLY_LOW_OPTIMIZATION_EXIT
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
deleted file mode 100644
index 34cf7ea0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_f32.c    
-*    
-* Description:  Floating-point FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs points to the filter coefficients buffer.    
- * @param[in]     *pState points to the state buffer.    
- * @param[in] 	  blockSize number of samples that are processed per call.    
- * @return 		  none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().    
- */
-
-void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
deleted file mode 100644
index 7eaab235..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_q15.c    
-*    
-* Description:  Q15 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.    
- * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.    
- * @param[in]      *pCoeffs points to the filter coefficients buffer.    
- * @param[in]      *pState points to the state buffer.    
- * @param[in]      blockSize is number of samples processed per call.    
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if    
- * numTaps is not greater than or equal to 4 and even.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * Note that numTaps must be even and greater than or equal to 4.    
- * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.    
- * For example, to implement a filter with numTaps=3 and coefficients    
- * 
    
- *     {0.3, -0.8, 0.3}    
- * 
    
- * set numTaps=4 and use the coefficients:    
- * 
    
- *     {0.3, -0.8, 0.3, 0}.    
- * 
    
- * Similarly, to implement a two point filter    
- * 
    
- *     {0.3, -0.3}    
- * 
    
- * set numTaps=4 and use the coefficients:    
- * 
    
- *     {0.3, -0.3, 0, 0}.    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3  and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().    
- */
-
-arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* The Number of filter coefficients in the filter must be even and at least 4 */
-  if(numTaps & 0x1u)
-  {
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */
-    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  status = ARM_MATH_SUCCESS;
-
-  return (status);
-
-#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
deleted file mode 100644
index c2092e02..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_init_q31.c    
-*    
-* Description:	Q31 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S points to an instance of the Q31 FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
- * @param[in] 	  *pState points to the state buffer.    
- * @param[in] 	  blockSize number of samples that are processed per call.    
- * @return        none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().    
- */
-
-void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
-  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
deleted file mode 100644
index ccbc7d73..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_q7.c    
-*    
-* Description:  Q7 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-/**    
- * @param[in,out] *S points to an instance of the Q7 FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
- * @param[in]     *pState points to the state buffer.    
- * @param[in]     blockSize number of samples that are processed per call.    
- * @return     	  none    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().    
- */
-
-void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize)
-{
-
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
deleted file mode 100644
index 5ad249e3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_interpolate_f32.c    
-*    
-* Description:	FIR interpolation for floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator    
- *    
- * These functions combine an upsampler (zero stuffer) and an FIR filter.    
- * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.    
- * Conceptually, the functions are equivalent to the block diagram below:    
- * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"    
- * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized    
- * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.    
- * The user of the function is responsible for providing the filter coefficients.    
- *    
- * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.    
- * The upsampler inserts L-1 zeros between each sample.    
- * Instead of multiplying by these zero values, the FIR filter is designed to skip them.    
- * This leads to an efficient implementation without any wasted effort.    
- * The functions operate on blocks of input and output data.    
- * pSrc points to an array of blockSize input values and    
- * pDst points to an array of blockSize*L output values.    
- *    
- * The library provides separate functions for Q15, Q31, and floating-point data types.    
- *    
- * \par Algorithm:    
- * The functions use a polyphase filter structure:    
- * 
    
- *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    
- *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    
- *    ...    
- *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    
- * 
    
- * This approach is more efficient than straightforward upsample-then-filter algorithms.    
- * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.    
- * \par    
- * pCoeffs points to a coefficient array of size numTaps.    
- * numTaps must be a multiple of the interpolation factor L and this is checked by the    
- * initialization functions.    
- * Internally, the function divides the FIR filter's impulse response into shorter filters of length    
- * phaseLength=numTaps/L.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size blockSize + phaseLength - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    
- * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    
- * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    
- * 
    
- * where L is the interpolation factor; phaseLength=numTaps/L is the    
- * length of each of the shorter FIR filters used internally,    
- * pCoeffs is the address of the coefficient buffer;    
- * pState is the address of the state buffer.    
- * Be sure to set the values in the state buffer to zeros when doing static initialization.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point FIR interpolator.    
- * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- */
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
-  float32_t sum0;                                /* Accumulators */
-  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j;                         /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-  float32_t acc0, acc1, acc2, acc3;
-  float32_t x1, x2, x3;
-  uint32_t blkCntN4;
-  float32_t c1, c2, c3;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 4;
-  blkCntN4 = blockSize - (4 * blkCnt);
-
-  /* Samples loop unrolled by 4 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-      x1 = *(ptr1++);
-      x2 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x3 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x0 * c0;
-        acc1 += x1 * c0;
-        acc2 += x2 * c0;
-        acc3 += x3 * c0;
-
-        /* Read the coefficient */
-        c1 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x1 * c1;
-        acc1 += x2 * c1;
-        acc2 += x3 * c1;
-        acc3 += x0 * c1;
-
-        /* Read the coefficient */
-        c2 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x2 * c2;
-        acc1 += x3 * c2;
-        acc2 += x0 * c2;
-        acc3 += x1 * c2;
-
-        /* Read the coefficient */
-        c3 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x2 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x3 * c3;
-        acc1 += x0 * c3;
-        acc2 += x1 * c3;
-        acc3 += x2 * c3;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x3 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x0 * c0;
-        acc1 += x1 * c0;
-        acc2 += x2 * c0;
-        acc3 += x3 * c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = acc0;
-      *(pDst + S->L) = acc1;
-      *(pDst + 2 * S->L) = acc2;
-      *(pDst + 3 * S->L) = acc3;
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 4;
-
-    pDst += S->L * 3;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-
-  while(blkCntN4 > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum0 += *(ptr1++) * (*ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = sum0;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCntN4--;
-  }
-
-  /* Processing is complete.        
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  tapCnt = (phaseLen - 1u) % 0x04u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
-
-
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      /* Loop over the polyPhase length */
-      tapCnt = phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *ptr1++ * *ptr2;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = sum;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = phaseLen - 1u;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
deleted file mode 100644
index 085cb578..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_f32.c    
-*    
-* Description:  Floating-point FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point FIR interpolator.    
- * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().    
- */
-
-arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize +
-            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
deleted file mode 100644
index 99895226..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_q15.c    
-*    
-* Description:  Q15 FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q15 FIR interpolator.    
- * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().    
- */
-
-arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
deleted file mode 100644
index 1887524d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_q31.c    
-*    
-* Description:  Q31 FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-
-/**    
- * @brief  Initialization function for the Q31 FIR interpolator.    
- * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().    
- */
-
-arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
deleted file mode 100644
index 34c085ae..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fir_interpolate_q15.c    
-*    
-* Description:	Q15 FIR interpolation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR interpolator.    
- * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer                                            */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
-  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
-  q63_t sum0;                                    /* Accumulators                                             */
-  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
-  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
-  uint32_t blkCntN2;
-  q63_t acc0, acc1;
-  q15_t x1;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 2;
-  blkCntN2 = blockSize - (2 * blkCnt);
-
-  /* Samples loop unrolled by 2 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0;
-      acc1 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
-      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 2;
-
-    pDst += S->L;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blkCntN2;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen & 0x3u;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete.    
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = ((uint32_t) phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-	
-	/* Decrement the loop counter */
-    i--;
-  }
-
-  i = ((uint32_t) phaseLen - 1u) % 0x04u;
-
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer                                            */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
-  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
-  q63_t sum;                                     /* Accumulator */
-  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
-  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      /* Loop over the polyPhase length */
-      tapCnt = (uint32_t) phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *ptr2;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *ptr1++;
-
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) x0 * c0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Store the result after converting to 1.15 format in the destination buffer */
-      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (uint32_t) phaseLen - 1u;
-
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
deleted file mode 100644
index a4e91b06..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fir_interpolate_q31.c    
-*    
-* Description:	Q31 FIR interpolation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR interpolator.    
- * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).    
- * since numTaps/L additions occur per output sample.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
-  q63_t sum0;                                    /* Accumulators */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j;                         /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-  uint32_t blkCntN2;
-  q63_t acc0, acc1;
-  q31_t x1;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 2;
-  blkCntN2 = blockSize - (2 * blkCnt);
-
-  /* Samples loop unrolled by 2 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0;
-      acc1 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = (q31_t) (acc0 >> 31);
-      *(pDst + S->L) = (q31_t) (acc1 >> 31);
-
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 2;
-
-    pDst += S->L;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blkCntN2;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen & 0x3u;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q31_t) (sum0 >> 31);
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.        
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  tapCnt = (phaseLen - 1u) % 0x04u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-
-#else
-
-void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
-
-  /* Run the below code for Cortex-M0 */
-
-  q63_t sum;                                     /* Accumulator */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      tapCnt = phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *ptr1++;
-
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q31_t) (sum >> 31);
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = phaseLen - 1u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
deleted file mode 100644
index 4be468c7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_f32.c    
-*    
-* Description:	Processing function for the floating-point FIR Lattice filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters    
- *    
- * This set of functions implements Finite Impulse Response (FIR) lattice filters    
- * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
- * variety of adaptive filter applications.  The filter structure is feedforward and    
- * the net impulse response is finite length.    
- * The functions operate on blocks    
- * of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst point to input and output arrays containing blockSize values.    
- *    
- * \par Algorithm:    
- * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"    
- * The following difference equation is implemented:    
- * 
    
- *    f0[n] = g0[n] = x[n]    
- *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    
- *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    
- *    y[n] = fM[n]    
- * 
    
- * \par    
- * pCoeffs points to tha array of reflection coefficients of size numStages.    
- * Reflection Coefficients are stored in the following order.    
- * \par    
- * 
    
- *    {k1, k2, ..., kM}    
- * 
    
- * where M is number of stages    
- * \par    
- * pState points to a state array of size numStages.    
- * The state variables (g values) hold previous inputs and are stored in the following order.    
- * 
    
- *    {g0[n], g1[n], g2[n] ...gM-1[n]}    
- * 
    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pCoeffs, pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
- * 
    
- *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    
- *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    
- *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    
- * 
    
- * \par    
- * where numStages is the number of stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer.    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-  /**    
-   * @brief Processing function for the floating-point FIR lattice filter.    
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.    
-   * @param[in]  *pSrc     points to the block of input data.    
-   * @param[out] *pDst     points to the block of output data    
-   * @param[in]  blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState;                             /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *px;                                 /* temporary state pointer */
-  float32_t *pk;                                 /* temporary coefficient pointer */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
-  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
-  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
-  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  gcurr1 = 0.0f;
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* Read two samples from input buffer */
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-    fcurr2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Read g0(n-1) from state */
-    gcurr1 = *px;
-
-    /* Process first sample for first tap */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = fcurr1 + ((*pk) * gcurr1);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (fcurr1 * (*pk)) + gcurr1;
-
-    /* Process second sample for first tap */
-    /* for sample 2 processing */
-    fnext2 = fcurr2 + ((*pk) * fcurr1);
-    gnext2 = (fcurr2 * (*pk)) + fcurr1;
-
-    /* Read next two samples from input buffer */
-    /* f0(n+2) = x(n+2) */
-    fcurr3 = *pSrc++;
-    fcurr4 = *pSrc++;
-
-    /* Copy only last input samples into the state buffer    
-       which will be used for next four samples processing */
-    *px++ = fcurr4;
-
-    /* Process third sample for first tap */
-    fnext3 = fcurr3 + ((*pk) * fcurr2);
-    gnext3 = (fcurr3 * (*pk)) + fcurr2;
-
-    /* Process fourth sample for first tap */
-    fnext4 = fcurr4 + ((*pk) * fcurr3);
-    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
-
-    /* Update of f values for next coefficient set processing */
-    fcurr1 = fnext1;
-    fcurr2 = fnext2;
-    fcurr3 = fnext3;
-    fcurr4 = fnext4;
-
-    /* Loop unrolling.  Process 4 taps at a time . */
-    stageCnt = (numStages - 1u) >> 2u;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numStages-3 coefficients. */
-
-    /* Process 2nd, 3rd, 4th and 5th taps ... here */
-    while(stageCnt > 0u)
-    {
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Process first sample for 2nd, 6th .. tap */
-      /* Sample processing for K2, K6.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* Process second sample for 2nd, 6th .. tap */
-      /* for sample 2 processing */
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      /* Process third sample for 2nd, 6th .. tap */
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      /* Process fourth sample for 2nd, 6th .. tap */
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g2(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K3, K7.... */
-      /* Process first sample for 3rd, 7th .. tap */
-      /* f3(n) = f2(n) +  K3 * g2(n-1) */
-      fcurr1 = fnext1 + ((*pk) * gcurr1);
-      /* Process second sample for 3rd, 7th .. tap */
-      fcurr2 = fnext2 + ((*pk) * gnext1);
-      /* Process third sample for 3rd, 7th .. tap */
-      fcurr3 = fnext3 + ((*pk) * gnext2);
-      /* Process fourth sample for 3rd, 7th .. tap */
-      fcurr4 = fnext4 + ((*pk) * gnext3);
-
-      /* Calculation of state values for next stage */
-      /* g3(n) = f2(n) * K3  +  g2(n-1) */
-      gnext4 = (fnext4 * (*pk)) + gnext3;
-      gnext3 = (fnext3 * (*pk)) + gnext2;
-      gnext2 = (fnext2 * (*pk)) + gnext1;
-      gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
-
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g3(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K4, K8.... */
-      /* Process first sample for 4th, 8th .. tap */
-      /* f4(n) = f3(n) +  K4 * g3(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* Process second sample for 4th, 8th .. tap */
-      /* for sample 2 processing */
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      /* Process third sample for 4th, 8th .. tap */
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      /* Process fourth sample for 4th, 8th .. tap */
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g4(n) = f3(n) * K4  +  g3(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g4(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K5, K9.... */
-      /* Process first sample for 5th, 9th .. tap */
-      /* f5(n) = f4(n) +  K5 * g4(n-1) */
-      fcurr1 = fnext1 + ((*pk) * gcurr1);
-      /* Process second sample for 5th, 9th .. tap */
-      fcurr2 = fnext2 + ((*pk) * gnext1);
-      /* Process third sample for 5th, 9th .. tap */
-      fcurr3 = fnext3 + ((*pk) * gnext2);
-      /* Process fourth sample for 5th, 9th .. tap */
-      fcurr4 = fnext4 + ((*pk) * gnext3);
-
-      /* Calculation of state values for next stage */
-      /* g5(n) = f4(n) * K5  +  g4(n-1) */
-      gnext4 = (fnext4 * (*pk)) + gnext3;
-      gnext3 = (fnext3 * (*pk)) + gnext2;
-      gnext2 = (fnext2 * (*pk)) + gnext1;
-      gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
-      stageCnt--;
-    }
-
-    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
-    stageCnt = (numStages - 1u) % 0x4u;
-
-    while(stageCnt > 0u)
-    {
-      gcurr1 = *px;
-
-      /* save g value in state buffer */
-      *px++ = gnext4;
-
-      /* Process four samples for last three taps here */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* Update of f values for next coefficient set processing */
-      fcurr1 = fnext1;
-      fcurr2 = fnext2;
-      fcurr3 = fnext3;
-      fcurr4 = fnext4;
-
-      stageCnt--;
-
-    }
-
-    /* The results in the 4 accumulators, store in the destination buffer. */
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-    *pDst++ = fcurr2;
-    *pDst++ = fcurr3;
-    *pDst++ = fcurr4;
-
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g2(n) from state buffer */
-    gcurr1 = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = fcurr1 + ((*pk) * gcurr1);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr1;
-
-    /* f1(n) is saved in fcurr1    
-       for next stage processing */
-    fcurr1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* f1(n) is saved in fcurr1    
-         for next stage processing */
-      fcurr1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-
-    blkCnt--;
-
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = pCoeffs;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurr = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = fcurr + ((*pk) * gcurr);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = (fcurr * (*pk++)) + gcurr;
-
-    /* save f0(n) in state buffer */
-    *px++ = fcurr;
-
-    /* f1(n) is saved in fcurr            
-       for next stage processing */
-    fcurr = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = fcurr + ((*pk) * gcurr);
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = (fcurr * (*pk++)) + gcurr;
-
-      /* f1(n) is saved in fcurr1            
-         for next stage processing */
-      fcurr = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr;
-
-    blkCnt--;
-
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
deleted file mode 100644
index c6aa00d9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_f32.c    
-*    
-* Description:  Floating-point FIR Lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Initialization function for the floating-point FIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.    
- * @param[in] numStages  number of filter stages.    
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
- * @param[in] *pState points to the state buffer.  The array is of length numStages.    
- * @return none.    
- */
-
-void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
deleted file mode 100644
index 34f33336..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_q15.c    
-*    
-* Description:  Q15 FIR Lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q15 FIR lattice filter.    
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.    
-   * @param[in] numStages  number of filter stages.    
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.     
-   * @param[in] *pState points to the state buffer.  The array is of length numStages.     
-   * @return none.    
-   */
-
-void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
deleted file mode 100644
index 786152f9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_q31.c    
-*    
-* Description:  Q31 FIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q31 FIR lattice filter.    
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.    
-   * @param[in] numStages  number of filter stages.    
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.    
-   * @return none.    
-   */
-
-void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
deleted file mode 100644
index 044a500d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_q15.c    
-*    
-* Description:	Q15 FIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-/**    
- * @brief Processing function for the Q15 FIR lattice filter.    
- * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- */
-
-void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *px;                                     /* temporary state pointer */
-  q15_t *pk;                                     /* temporary coefficient pointer */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
-  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
-  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
-  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* Read two samples from input buffer */
-    /* f0(n) = x(n) */
-    fcurnt1 = *pSrc++;
-    fcurnt2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Read g0(n-1) from state */
-    gcurnt1 = *px;
-
-    /* Process first sample for first tap */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-    fnext1 = __SSAT(fnext1, 16);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
-    gnext1 = __SSAT(gnext1, 16);
-
-    /* Process second sample for first tap */
-    /* for sample 2 processing */
-    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
-    fnext2 = __SSAT(fnext2, 16);
-
-    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
-    gnext2 = __SSAT(gnext2, 16);
-
-
-    /* Read next two samples from input buffer */
-    /* f0(n+2) = x(n+2) */
-    fcurnt3 = *pSrc++;
-    fcurnt4 = *pSrc++;
-
-    /* Copy only last input samples into the state buffer    
-       which is used for next four samples processing */
-    *px++ = (q15_t) fcurnt4;
-
-    /* Process third sample for first tap */
-    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
-    fnext3 = __SSAT(fnext3, 16);
-    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
-    gnext3 = __SSAT(gnext3, 16);
-
-    /* Process fourth sample for first tap */
-    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
-    fnext4 = __SSAT(fnext4, 16);
-    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
-    gnext4 = __SSAT(gnext4, 16);
-
-    /* Update of f values for next coefficient set processing */
-    fcurnt1 = fnext1;
-    fcurnt2 = fnext2;
-    fcurnt3 = fnext3;
-    fcurnt4 = fnext4;
-
-
-    /* Loop unrolling.  Process 4 taps at a time . */
-    stageCnt = (numStages - 1u) >> 2;
-
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numStages-3 coefficients. */
-
-    /* Process 2nd, 3rd, 4th and 5th taps ... here */
-    while(stageCnt > 0u)
-    {
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Process first sample for 2nd, 6th .. tap */
-      /* Sample processing for K2, K6.... */
-      /* f1(n) = f0(n) +  K1 * g0(n-1) */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-
-      /* Process second sample for 2nd, 6th .. tap */
-      /* for sample 2 processing */
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-      /* Process third sample for 2nd, 6th .. tap */
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-      /* Process fourth sample for 2nd, 6th .. tap */
-      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K3, K7.... */
-      /* Process first sample for 3rd, 7th .. tap */
-      /* f3(n) = f2(n) +  K3 * g2(n-1) */
-      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
-      fcurnt1 = __SSAT(fcurnt1, 16);
-
-      /* Process second sample for 3rd, 7th .. tap */
-      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
-      fcurnt2 = __SSAT(fcurnt2, 16);
-
-      /* Process third sample for 3rd, 7th .. tap */
-      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
-      fcurnt3 = __SSAT(fcurnt3, 16);
-
-      /* Process fourth sample for 3rd, 7th .. tap */
-      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
-      fcurnt4 = __SSAT(fcurnt4, 16);
-
-      /* Calculation of state values for next stage */
-      /* g3(n) = f2(n) * K3  +  g2(n-1) */
-      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-
-      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-
-      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K4, K8.... */
-      /* Process first sample for 4th, 8th .. tap */
-      /* f4(n) = f3(n) +  K4 * g3(n-1) */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-      /* Process second sample for 4th, 8th .. tap */
-      /* for sample 2 processing */
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-
-      /* Process third sample for 4th, 8th .. tap */
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-
-      /* Process fourth sample for 4th, 8th .. tap */
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g4(n) = f3(n) * K4  +  g3(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g4(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K5, K9.... */
-      /* Process first sample for 5th, 9th .. tap */
-      /* f5(n) = f4(n) +  K5 * g4(n-1) */
-      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
-      fcurnt1 = __SSAT(fcurnt1, 16);
-
-      /* Process second sample for 5th, 9th .. tap */
-      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
-      fcurnt2 = __SSAT(fcurnt2, 16);
-
-      /* Process third sample for 5th, 9th .. tap */
-      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
-      fcurnt3 = __SSAT(fcurnt3, 16);
-
-      /* Process fourth sample for 5th, 9th .. tap */
-      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
-      fcurnt4 = __SSAT(fcurnt4, 16);
-
-      /* Calculation of state values for next stage */
-      /* g5(n) = f4(n) * K5  +  g4(n-1) */
-      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      stageCnt--;
-    }
-
-    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
-    stageCnt = (numStages - 1u) % 0x4u;
-
-    while(stageCnt > 0u)
-    {
-      gcurnt1 = *px;
-
-      /* save g value in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Process four samples for last three taps here */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      /* Update of f values for next coefficient set processing */
-      fcurnt1 = fnext1;
-      fcurnt2 = fnext2;
-      fcurnt3 = fnext3;
-      fcurnt4 = fnext4;
-
-      stageCnt--;
-
-    }
-
-    /* The results in the 4 accumulators, store in the destination buffer. */
-    /* y(n) = fN(n) */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
-
-#else
-
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurnt1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g2(n) from state buffer */
-    gcurnt1 = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-    fnext1 = __SSAT(fnext1, 16);
-
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-    gnext1 = __SSAT(gnext1, 16);
-
-    /* save g1(n) in state buffer */
-    *px++ = (q15_t) fcurnt1;
-
-    /* f1(n) is saved in fcurnt1    
-       for next stage processing */
-    fcurnt1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* f1(n) is saved in fcurnt1    
-         for next stage processing */
-      fcurnt1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = __SSAT(fcurnt1, 16);
-
-
-    blkCnt--;
-
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurnt = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurnt = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
-    fnext = __SSAT(fnext, 16);
-
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
-    gnext = __SSAT(gnext, 16);
-
-    /* save f0(n) in state buffer */
-    *px++ = (q15_t) fcurnt;
-
-    /* f1(n) is saved in fcurnt            
-       for next stage processing */
-    fcurnt = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g1(n-1) from state buffer */
-      gcurnt = *px;
-
-      /* save g0(n-1) in state buffer */
-      *px++ = (q15_t) gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
-      fnext = __SSAT(fnext, 16);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
-      gnext = __SSAT(gnext, 16);
-
-
-      /* f1(n) is saved in fcurnt            
-         for next stage processing */
-      fcurnt = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = __SSAT(fcurnt, 16);
-
-
-    blkCnt--;
-
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
deleted file mode 100644
index 4a64538b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_q31.c    
-*    
-* Description:	Q31 FIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-/**    
- * @brief Processing function for the Q31 FIR lattice filter.    
- * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.    
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* temporary state pointer */
-  q31_t *pk;                                     /* temporary coefficient pointer */
-  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
-  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-  q31_t k;
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 1u;
-
-  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.        
-     a second loop below computes the remaining 1 sample. */
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* f0(n) = x(n) */
-    fcurr2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n - 1) from state buffer */
-    gcurr1 = *px;
-
-    /* Read the reflection coefficient */
-    k = *pk++;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-    fnext1 = fcurr1 + (fnext1 << 1u);
-    gnext1 = gcurr1 + (gnext1 << 1u);
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
-    fnext2 = fcurr2 + (fnext2 << 1u);
-    gnext2 = fcurr1 + (gnext2 << 1u);
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr2;
-
-    /* f1(n) is saved in fcurr1        
-       for next stage processing */
-    fcurr1 = fnext1;
-    fcurr2 = fnext2;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-
-      /* Read the reflection coefficient */
-      k = *pk++;
-
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext2;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
-
-      fnext1 = fcurr1 + (fnext1 << 1u);
-      fnext2 = fcurr2 + (fnext2 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
-      gnext2 = gnext1 + (gnext2 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-      gnext1 = gcurr1 + (gnext1 << 1u);
-
-      /* f1(n) is saved in fcurr1        
-         for next stage processing */
-      fcurr1 = fnext1;
-      fcurr2 = fnext2;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-    *pDst++ = fcurr2;
-
-    blkCnt--;
-
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x2u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n - 1) from state buffer */
-    gcurr1 = *px;
-
-    /* Read the reflection coefficient */
-    k = *pk++;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-    fnext1 = fcurr1 + (fnext1 << 1u);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-    gnext1 = gcurr1 + (gnext1 << 1u);
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr1;
-
-    /* f1(n) is saved in fcurr1        
-       for next stage processing */
-    fcurr1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* Read the reflection coefficient */
-      k = *pk++;
-
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-      fnext1 = fcurr1 + (fnext1 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-      gnext1 = gcurr1 + (gnext1 << 1u);
-
-      /* f1(n) is saved in fcurr1        
-         for next stage processing */
-      fcurr1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-
-    blkCnt--;
-
-  }
-
-
-}
-
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* temporary state pointer */
-  q31_t *pk;                                     /* temporary coefficient pointer */
-  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurr = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
-    /* save g1(n) in state buffer */
-    *px++ = fcurr;
-
-    /* f1(n) is saved in fcurr1            
-       for next stage processing */
-    fcurr = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
-
-      /* f1(n) is saved in fcurr1            
-         for next stage processing */
-      fcurr = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr;
-
-    blkCnt--;
-
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
deleted file mode 100644
index b0d3d09b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_q15.c    
-*    
-* Description:  Q15 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
- * @ingroup groupFilters       
- */
-
-/**       
- * @addtogroup FIR       
- * @{       
- */
-
-/**       
- * @brief Processing function for the Q15 FIR filter.       
- * @param[in] *S points to an instance of the Q15 FIR structure.       
- * @param[in] *pSrc points to the block of input data.       
- * @param[out] *pDst points to the block of output data.       
- * @param[in]  blockSize number of samples to process per call.       
- * @return none.       
- *   
- *   
- * \par Restrictions   
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
- *	In this case input, output, state buffers should be aligned by 32-bit   
- *   
- * Scaling and Overflow Behavior:       
- * \par       
- * The function is implemented using a 64-bit internal accumulator.       
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.       
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.       
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.       
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.       
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.       
- *       
- * \par       
- * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.       
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.       
-   * The variables acc0 ... acc3 hold output values that are being computed:       
-   *       
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]       
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]       
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]       
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]       
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.       
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer of type q15 */
-    px1 = pState;
-
-    /* Initialize coeff pointer of type q31 */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = _SIMD32_OFFSET(px1);
-
-    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
-    x1 = _SIMD32_OFFSET(px1 + 1u);
-
-    px1 += 2u;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Read state x[n-N-2], x[n-N-3] */
-      x2 = _SIMD32_OFFSET(px1);
-
-      /* Read state x[n-N-3], x[n-N-4] */
-      x3 = _SIMD32_OFFSET(px1 + 1u);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLALD(x3, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLALD(x2, c0, acc0);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLALD(x3, c0, acc1);
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px1 + 2u);
-
-      /* Read state x[n-N-5], x[n-N-6] */
-      x1 = _SIMD32_OFFSET(px1 + 3u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLALD(x0, c0, acc2);
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLALD(x1, c0, acc3);
-
-      px1 += 4u;
-
-      tapCnt--;
-
-    }
-
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-      /* Read 2 coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Fetch 4 state variables */
-      x2 = _SIMD32_OFFSET(px1);
-
-      x3 = _SIMD32_OFFSET(px1 + 1u);
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      px1 += 2u;
-
-      acc1 = __SMLALD(x1, c0, acc1);
-      acc2 = __SMLALD(x2, c0, acc2);
-      acc3 = __SMLALD(x3, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer of type q15 */
-    px1 = pState;
-
-    /* Initialize coeff pointer of type q31 */
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1;
-
-    do
-    {
-
-      c0 = *__SIMD32(pb)++;
-      x0 = *__SIMD32(px1)++;
-
-      acc0 = __SMLALD(x0, c0, acc0);
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Copy state values to start of state buffer */
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else /* UNALIGNED_SUPPORT_DISABLE */
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.      
-   * The variables acc0 ... acc3 hold output values that are being computed:      
-   *      
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.      
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
-    px = pState;
-
-    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = *__SIMD32(px)++;
-
-    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
-    x2 = *__SIMD32(px)++;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.      
-     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* pack  x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack  x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLALDX(x1, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLALD(x2, c0, acc0);
-
-      /* Read state x[n-N-6], x[n-N-7] with offset */
-      x2 = _SIMD32_OFFSET(px + 2u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLALD(x0, c0, acc2);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack  x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLALDX(x1, c0, acc3);
-
-      /* Update state pointer for next state reading */
-      px += 4u;
-
-      /* Decrement tap count */
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-
-      /* Read last two coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLALD(x0, c0, acc0);
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read last state variables */
-      x0 = *__SIMD32(px);
-
-      /* Perform the multiply-accumulates */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* Perform the multiply-accumulates */
-      acc3 = __SMLALDX(x1, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Use SIMD to hold states and coefficients */
-    px = pState;
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1u;
-
-    do
-    {
-      acc0 += (q31_t) * px++ * *pb++;
-	  acc0 += (q31_t) * px++ * *pb++;
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.      
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#else /* ARM_MATH_CM0_FAMILY */
-
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-
-
-
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc;                                     /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q31_t) * px++ * *pb++;
-      tapCnt--;
-    } while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15         
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  tapCnt = (numTaps - 1u);
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-
-
-
-/**       
- * @} end of FIR group       
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
deleted file mode 100644
index 35360595..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_q31.c    
-*    
-* Description:	Q31 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q31 FIR filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.  
- *    
- * \par    
- * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t x0, x1, x2;                              /* Temporary variables to hold state */
-  q31_t c0;                                      /* Temporary variable to hold coefficient value */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc0, acc1, acc2;                        /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize / 3;
-  blockSize = blockSize - (3 * blkCnt);
-
-  tapCnt = numTaps / 3;
-  tapCntN3 = numTaps - (3 * tapCnt);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy three new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1] */
-    x0 = *(px++);
-    x1 = *(px++);
-
-    /* Loop unrolling.  Process 3 taps at a time. */
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *pb;
-
-      /* Read x[n-numTaps-2] sample */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x0 * c0);
-      acc1 += ((q63_t) x1 * c0);
-      acc2 += ((q63_t) x2 * c0);
-
-      /* Read the coefficient and state */
-      c0 = *(pb + 1u);
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x1 * c0);
-      acc1 += ((q63_t) x2 * c0);
-      acc2 += ((q63_t) x0 * c0);
-
-      /* Read the coefficient and state */
-      c0 = *(pb + 2u);
-      x1 = *(px++);
-
-      /* update coefficient pointer */
-      pb += 3u;
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x2 * c0);
-      acc1 += ((q63_t) x0 * c0);
-      acc2 += ((q63_t) x1 * c0);
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 3, compute the remaining filter taps */
-
-    i = tapCntN3;
-
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x0 * c0);
-      acc1 += ((q63_t) x1 * c0);
-      acc2 += ((q63_t) x2 * c0);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 3 to process the next group of 3 samples */
-    pState = pState + 3;
-
-    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31    
-     ** Then store the 3 outputs in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 >> 31u);
-    *pDst++ = (q31_t) (acc1 >> 31u);
-    *pDst++ = (q31_t) (acc2 >> 31u);
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-
-  while(blockSize > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 += (q63_t) * (px++) * (*(pb++));
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.62 format.  Convert to 1.31    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 >> 31u);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blockSize--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc;                                     /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = pCoeffs;
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q63_t) * px++ * *pb++;
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.62 format.  Convert to 1.31         
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  tapCnt = numTaps - 1u;
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-
-#endif /*  #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
deleted file mode 100644
index 24a50dcd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_q7.c    
-*    
-* Description:  Q7 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in]   *S points to an instance of the Q7 FIR filter structure.    
- * @param[in]   *pSrc points to the block of input data.    
- * @param[out]  *pDst points to the block of output data.    
- * @param[in]   blockSize number of samples to process per call.    
- * @return 	none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is converted to 18.7 format by discarding the low 7 bits.    
- * Finally, the result is truncated to 1.7 format.    
- */
-
-void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
-  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
-  q7_t c0;                                       /* Temporary variable to hold coefficient value */
-  q7_t *px;                                      /* Temporary pointer for state */
-  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first three samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-    x0 = *(px++);
-    x1 = *(px++);
-    x2 = *(px++);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *pb;
-
-      /* Read x[n-numTaps-3] sample */
-      x3 = *px;
-      
-      /* acc0 +=  b[numTaps] * x[n-numTaps] */
-      acc0 += ((q15_t) x0 * c0);
-
-      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
-      acc1 += ((q15_t) x1 * c0);
-
-      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
-      acc2 += ((q15_t) x2 * c0);
-
-      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
-      acc3 += ((q15_t) x3 * c0);
-
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb + 1u);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px + 1u);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x1 * c0);
-      acc1 += ((q15_t) x2 * c0);
-      acc2 += ((q15_t) x3 * c0);
-      acc3 += ((q15_t) x0 * c0);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb + 2u);
-
-      /* Read x[n-numTaps-5] sample */
-      x1 = *(px + 2u);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x2 * c0);
-      acc1 += ((q15_t) x3 * c0);
-      acc2 += ((q15_t) x0 * c0);
-      acc3 += ((q15_t) x1 * c0);
-
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *(pb + 3u);
-
-      /* Read x[n-numTaps-6] sample */
-      x2 = *(px + 3u);
-      
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x3 * c0);
-      acc1 += ((q15_t) x0 * c0);
-      acc2 += ((q15_t) x1 * c0);
-      acc3 += ((q15_t) x2 * c0);
-
-      /* update coefficient pointer */
-      pb += 4u;
-      px += 4u;
-      
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
-    i = numTaps - (tapCnt * 4u);
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x3 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x0 * c0);
-      acc1 += ((q15_t) x1 * c0);
-      acc2 += ((q15_t) x2 * c0);
-      acc3 += ((q15_t) x3 * c0);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-      x2 = x3;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31    
-     ** Then store the 4 outputs in the destination buffer. */
-    acc0 = __SSAT((acc0 >> 7u), 8);
-    *pDst++ = acc0;
-    acc1 = __SSAT((acc1 >> 7u), 8);
-    *pDst++ = acc1;
-    acc2 = __SSAT((acc2 >> 7u), 8);
-    *pDst++ = acc2;
-    acc3 = __SSAT((acc3 >> 7u), 8);
-    *pDst++ = acc3;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 += (q15_t) * (px++) * (*(pb++));
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.14 format.  Convert to 1.7    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = __SSAT((acc0 >> 7u), 8);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
-  q31_t acc = 0;                                 /* Accumlator */
-  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  /* Perform filtering upto BlockSize - BlockSize%4  */
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer of type q7 */
-    px = pState;
-
-    /* Initialize coeff pointer of type q7 */
-    pb = pCoeffs;
-
-
-    i = numTaps;
-
-    while(i > 0u)
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q15_t) * px++ * *pb++;
-      i--;
-    }
-
-    /* Store the 1.7 format filter output in destination buffer */
-    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
-
-    /* Advance the state pointer by 1 to process the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-
-  /* Copy numTaps number of values */
-  i = (numTaps - 1u);
-
-  /* Copy q7_t data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
deleted file mode 100644
index 9ef8edf9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_f32.c    
-*    
-* Description:	Floating-point sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters    
- *    
- * This group of functions implements sparse FIR filters.     
- * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.   
- * Sparse filters are used for simulating reflections in communications and audio applications.   
- *   
- * There are separate functions for Q7, Q15, Q31, and floating-point data types.    
- * The functions operate on blocks  of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst points to input and output arrays respectively containing blockSize values.    
- *    
- * \par Algorithm:    
- * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.   
- * This is in addition to the coefficient array b.   
- * The implementation essentially skips the multiplications by zero and leads to an efficient realization.   
- * 
   
- *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    
- * 
    
- * \par    
- * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"   
- * \par    
- * pCoeffs points to a coefficient array of size numTaps;    
- * pTapDelay points to an array of nonzero indices and is also of size numTaps;   
- * pState points to a state array of size maxDelay + blockSize, where   
- * maxDelay is the largest offset value that is ever used in the pTapDelay array.   
- * Some of the processing functions also require temporary working buffers.   
- *   
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 4 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 4 different data type filter instance structures    
- * 
    
- *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- * 
    
- * \par    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the floating-point sparse FIR filter.   
- * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.   
- * @param[in]  *pSrc       points to the block of input data.   
- * @param[out] *pDst       points to the block of output data   
- * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize   number of input samples to process per call.   
- * @return none.   
- */
-
-void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize)
-{
-
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *px;                                 /* Scratch buffer pointer */
-  float32_t *py = pState;                        /* Temporary pointers for state buffer */
-  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
-  float32_t *pOut;                               /* Destination pointer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
-
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
-                        (int32_t *) pSrc, 1, blockSize);
-
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                       blockSize);
-
-  /* Working pointer for the scratch buffer */
-  px = pb;
-
-  /* Working pointer for destination buffer */
-  pOut = pDst;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 Multiplications at a time. */
-  blkCnt = blockSize >> 2u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer */
-    px = pb;
-
-    /* Working pointer for destination buffer */
-    pOut = pDst;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = ((int32_t) S->stateIndex -
-                 (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */
-
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-											 blockSize);
-
-	/* Working pointer for the scratch buffer */
-	px = pb;
-
-	/* Working pointer for destination buffer */
-	pOut = pDst;
-
-	/* Loop over the blockSize. Unroll by a factor of 4.    
-	 * Compute 4 MACS at a time. */
-	blkCnt = blockSize >> 2u;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pOut++ += *px++ * coeff;
-		*pOut++ += *px++ * coeff;
-		*pOut++ += *px++ * coeff;
-		*pOut++ += *px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-	/* If the blockSize is not a multiple of 4,    
-	 * compute the remaining samples */
-	blkCnt = blockSize % 0x4u;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pOut++ += *px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer */
-    px = pb;
-
-    /* Working pointer for destination buffer */
-    pOut = pDst;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex =
-      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */	
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-											 blockSize);
-
-	/* Working pointer for the scratch buffer */
-	px = pb;
-
-	/* Working pointer for destination buffer */
-	pOut = pDst;
-
-	blkCnt = blockSize;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pOut++ += *px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY        */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
deleted file mode 100644
index a0fa81cc..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_f32.c    
-*    
-* Description:	Floating-point sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of samples processed by the arm_fir_sparse_f32() function.    
- */
-
-void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
deleted file mode 100644
index 41bbd7e5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q15.c    
-*    
-* Description:	Q15 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q15 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of words processed by arm_fir_sparse_q15() function.    
- */
-
-void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
deleted file mode 100644
index 82505504..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q31.c    
-*    
-* Description:	Q31 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q31 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the number of words processed by arm_fir_sparse_q31() function.    
- */
-
-void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
deleted file mode 100644
index 6c495a49..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q7.c    
-*    
-* Description:	Q7 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE. 
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q7 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of samples processed by the arm_fir_sparse_q7() function.    
- */
-
-void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
deleted file mode 100644
index 23666853..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q15.c    
-*    
-* Description:	Q15 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the Q15 sparse FIR filter.   
- * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.   
- * @param[in]  *pSrc        points to the block of input data.   
- * @param[out] *pDst        points to the block of output data   
- * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
- * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize    number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 32-bit accumulator.   
- * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.   
- * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.   
- * If the accumulator result overflows it will wrap around rather than saturate.   
- * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.    
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
- */
-
-
-void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize)
-{
-
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pIn = pSrc;                             /* Working pointer for input */
-  q15_t *pOut = pDst;                            /* Working pointer for output */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *px;                                     /* Temporary pointers for scratch buffer */
-  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
-  q15_t *py = pState;                            /* Temporary pointers for state buffer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
-  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in1, in2;                                /* Temporary variables */
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                       pb, pb, blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                         pb, pb, blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */		
-
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_q15(py, delaySize, &readIndex, 1,
-											 pb, pb, blockSize, 1, blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pScratchOut = pScr2;
-
-	/* Loop over the blockSize. Unroll by a factor of 4.    
-	 * Compute 4 MACS at a time. */
-	blkCnt = blockSize >> 2;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-	/* If the blockSize is not a multiple of 4,    
-	 * compute the remaining samples */
-	blkCnt = blockSize % 0x4u;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-  /* All the output values are in pScratchOut buffer.    
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in1 = *pScr2++;
-    in2 = *pScr2++;
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
-              16);
-
-#else
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
-              16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    in1 = *pScr2++;
-
-    in2 = *pScr2++;
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
-              16);
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
-              16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-    blkCnt--;
-
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-     remaining samples are processed in the below loop */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                       pb, pb, blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                         pb, pb, blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */	
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_q15(py, delaySize, &readIndex, 1,
-											 pb, pb, blockSize, 1, blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pScratchOut = pScr2;
-
-	blkCnt = blockSize;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		*pScratchOut++ += (q31_t) * px++ * coeff;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-  /* All the output values are in pScratchOut buffer.       
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
deleted file mode 100644
index 2183cd3a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q31.c    
-*    
-* Description:	Q31 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the Q31 sparse FIR filter.   
- * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.   
- * @param[in]  *pSrc       points to the block of input data.   
- * @param[out] *pDst       points to the block of output data   
- * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize   number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 32-bit accumulator.   
- * The 1.31 x 1.31 multiplications are truncated to 2.30 format.   
- * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.    
- * If the accumulator result overflows, it wraps around rather than saturate.   
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
- */
-
-void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize)
-{
-
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* Scratch buffer pointer */
-  q31_t *py = pState;                            /* Temporary pointers for state buffer */
-  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
-  q31_t *pOut;                                   /* Destination pointer */
-  q63_t out;                                     /* Temporary output variable */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
-  q31_t in;
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
-                        (int32_t *) pSrc, 1, blockSize);
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                       blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pOut = pDst;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 Multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pOut = pDst;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-											 blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pOut = pDst;
-
-	/* Loop over the blockSize. Unroll by a factor of 4.    
-	 * Compute 4 MACS at a time. */
-	blkCnt = blockSize >> 2;
-
-	while(blkCnt > 0u)
-	{
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-	/* If the blockSize is not a multiple of 4,    
-	 * compute the remaining samples */
-	blkCnt = blockSize % 0x4u;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}	
-
-  /* Working output pointer is updated */
-  pOut = pDst;
-
-  /* Output is converted into 1.31 format. */
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * process 4 output samples at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * process the remaining output samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pOut = pDst;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */	
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-											 (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-											 blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pOut = pDst;
-
-	blkCnt = blockSize;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		out = *pOut;
-		out += ((q63_t) * px++ * coeff) >> 32;
-		*pOut++ = (q31_t) (out);
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-  /* Working output pointer is updated */
-  pOut = pDst;
-
-  /* Output is converted into 1.31 format. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
deleted file mode 100644
index 9f43580b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q7.c    
-*    
-* Description:	Q7 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-
-/**   
- * @brief Processing function for the Q7 sparse FIR filter.   
- * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.   
- * @param[in]  *pSrc        points to the block of input data.   
- * @param[out] *pDst        points to the block of output data   
- * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
- * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize    number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is then converted to 18.7 format by discarding the low 7 bits.   
- * Finally, the result is truncated to 1.7 format.   
- */
-
-void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize)
-{
-
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *px;                                      /* Scratch buffer pointer */
-  q7_t *py = pState;                             /* Temporary pointers for state buffer */
-  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
-  q7_t *pOut = pDst;                             /* Destination pointer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
-  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
-  q31_t in;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t in1, in2, in3, in4;
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
-                       blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                      (int32_t) blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                        (int32_t) blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = ((int32_t) S->stateIndex -
-                 (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */	
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-											(int32_t) blockSize, 1, blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pScratchOut = pScr2;
-
-	/* Loop over the blockSize. Unroll by a factor of 4.    
-	 * Compute 4 MACS at a time. */
-	blkCnt = blockSize >> 2;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-	/* If the blockSize is not a multiple of 4,    
-	 * compute the remaining samples */
-	blkCnt = blockSize % 0x4u;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-  /* All the output values are in pScratchOut buffer.    
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-     remaining samples are processed in the below loop */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
-                       blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                      (int32_t) blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 2u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                        (int32_t) blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize */
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex =
-      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-	
-	/* Compute last tap without the final read of pTapDelay */	
-	
-	/* Working pointer for state buffer is updated */
-	py = pState;
-
-	/* blockSize samples are read from the state buffer */
-	arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-											(int32_t) blockSize, 1, blockSize);
-
-	/* Working pointer for the scratch buffer of state values */
-	px = pb;
-
-	/* Working pointer for scratch buffer of output values */
-	pScratchOut = pScr2;
-
-	/* Loop over the blockSize */
-	blkCnt = blockSize;
-
-	while(blkCnt > 0u)
-	{
-		/* Perform Multiply-Accumulate */
-		in = *pScratchOut + ((q31_t) * px++ * coeff);
-		*pScratchOut++ = in;
-
-		/* Decrement the loop counter */
-		blkCnt--;
-	}
-
-  /* All the output values are in pScratchOut buffer.       
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
deleted file mode 100644
index f3056f4d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
+++ /dev/null
@@ -1,447 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_f32.c    
-*    
-* Description:	Floating-point IIR Lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters    
- *    
- * This set of functions implements lattice filters    
- * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
- * variety of adaptive filter applications.  The filter structure has feedforward and    
- * feedback components and the net impulse response is infinite length.    
- * The functions operate on blocks    
- * of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst point to input and output arrays containing blockSize values.    
-    
- * \par Algorithm:    
- * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"    
- * 
    
- *    fN(n)   =  x(n)    
- *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    
- *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    
- *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    
- * 
    
- * \par    
- * pkCoeffs points to array of reflection coefficients of size numStages.     
- * Reflection coefficients are stored in time-reversed order.    
- * \par    
- * 
    
- *    {kN, kN-1, ....k1}    
- * 
    
- * pvCoeffs points to the array of ladder coefficients of size (numStages+1).     
- * Ladder coefficients are stored in time-reversed order.    
- * \par    
- * 
    
- *    {vN, vN-1, ...v0}    
- * 
    
- * pState points to a state array of size numStages + blockSize.    
- * The state variables shown in the figure above (the g values) are stored in the pState array.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
-  *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.   
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. 
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
- * 
    
- *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- * 
    
- * \par    
- * where numStages is the number of stages in the filter; pState points to the state buffer array;    
- * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point IIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */
-  float32_t acc;                                 /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
-  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  float32_t *pState;                             /* State pointer */
-  float32_t *pStateCurnt;                        /* State current pointer */
-  float32_t k1, k2;
-  float32_t v1, v2, v3, v4;
-  float32_t gcurr2;
-  float32_t fnext2;
-
-  /* initialise loop count */
-  blkCnt = blockSize;
-
-  /* initialise state pointer */
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fnext2 = *pSrc++;
-
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-
-    /* Set accumulator to zero */
-    acc = 0.0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages) >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Read gN-1(n-1) from state buffer */
-      gcurr1 = *px1;
-
-      /* read reflection coefficient kN */
-      k1 = *pk;
-
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext1 = fnext2 - (k1 * gcurr1);
-
-      /* read ladder coefficient vN */
-      v1 = *pv;
-
-      /* read next reflection coefficient kN-1 */
-      k2 = *(pk + 1u);
-
-      /* Read gN-2(n-1) from state buffer */
-      gcurr2 = *(px1 + 1u);
-
-      /* read next ladder coefficient vN-1 */
-      v2 = *(pv + 1u);
-
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext2 = fnext1 - (k2 * gcurr2);
-
-      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */
-      gnext = gcurr1 + (k1 * fnext1);
-
-      /* read reflection coefficient kN-2 */
-      k1 = *(pk + 2u);
-
-      /* write gN(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* Read gN-3(n-1) from state buffer */
-      gcurr1 = *(px1 + 2u);
-
-      /* y(n) += gN(n) * vN  */
-      acc += (gnext * v1);
-
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fnext1 = fnext2 - (k1 * gcurr1);
-
-      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = gcurr2 + (k2 * fnext2);
-
-      /* Read gN-4(n-1) from state buffer */
-      gcurr2 = *(px1 + 3u);
-
-      /* y(n) += gN-1(n) * vN-1  */
-      acc += (gnext * v2);
-
-      /* read reflection coefficient kN-3 */
-      k2 = *(pk + 3u);
-
-      /* write gN-1(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext2 = fnext1 - (k2 * gcurr2);
-
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = gcurr1 + (k1 * fnext1);
-
-      /* read ladder coefficient vN-2 */
-      v3 = *(pv + 2u);
-
-      /* y(n) += gN-2(n) * vN-2  */
-      acc += (gnext * v3);
-
-      /* write gN-2(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* update pointer */
-      pk += 4u;
-
-      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
-      gnext = (fnext2 * k2) + gcurr2;
-
-      /* read next ladder coefficient vN-3 */
-      v4 = *(pv + 3u);
-
-      /* y(n) += gN-4(n) * vN-4  */
-      acc += (gnext * v4);
-
-      /* write gN-3(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* update pointers */
-      px1 += 4u;
-      pv += 4u;
-
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr1 = *px1++;
-      /* Process sample for last taps */
-      fnext1 = fnext2 - ((*pk) * gcurr1);
-      gnext = (fnext1 * (*pk++)) + gcurr1;
-      /* Output samples for last taps */
-      acc += (gnext * (*pv++));
-      *px2++ = gnext;
-      fnext2 = fnext1;
-
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (fnext2 * (*pv));
-
-    *px2++ = fnext2;
-
-    /* write out into pDst */
-    *pDst++ = acc;
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer        
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numStages) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else
-
-void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
-  float32_t acc;                                 /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
-  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  float32_t *pState;                             /* State pointer */
-  float32_t *pStateCurnt;                        /* State current pointer */
-
-
-  /* Run the below code for Cortex-M0 */
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0.0f;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for numStages */
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = fcurr - ((*pk) * gcurr);
-      gnext = (fnext * (*pk++)) + gcurr;
-
-      /* Output samples for last taps */
-      acc += (gnext * (*pv++));
-      *px2++ = gnext;
-      fcurr = fnext;
-
-      /* Decrementing loop counter */
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (fnext * (*pv));
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = acc;
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages;
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
deleted file mode 100644
index 89bfb686..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_f32.c    
-*    
-* Description:  Floating-point IIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Initialization function for the floating-point IIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
- * @param[in] numStages number of stages in the filter.    
- * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
- * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
- * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- */
-
-void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-  /**    
-   * @} end of IIR_Lattice group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
deleted file mode 100644
index bc5c0af8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_q15.c    
-*    
-* Description:  Q15 IIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q15 IIR lattice filter.    
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
-   * @param[in] numStages  number of stages in the filter.    
-   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.    
-   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.    
-   * @param[in] blockSize number of samples to process per call.    
-   * @return none.    
-   */
-
-void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
deleted file mode 100644
index d8e26a37..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_q31.c    
-*    
-* Description:  Initialization function for the Q31 IIR lattice filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q31 IIR lattice filter.    
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
-   * @param[in] numStages number of stages in the filter.    
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
deleted file mode 100644
index 5bee62d3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_q15.c    
-*    
-* Description:	Q15 IIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 IIR lattice filter.    
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- */
-
-void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
-  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
-  uint32_t stgCnt;                               /* Temporary variables for counts */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pStateCurnt;                            /* State current pointer */
-  q15_t out;                                     /* Temporary variable for output */
-  q31_t v;                                       /* Temporary variable for ladder coefficient */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-	q15_t v1, v2;
-#endif
-
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for first tap */
-    gcurr = *px1++;
-    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-    fnext = __SSAT(fnext, 16);
-    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-    gnext = __SSAT(gnext, 16);
-    /* write gN(n) into state for next sample processing */
-    *px2++ = (q15_t) gnext;
-    /* y(n) += gN(n) * vN  */
-    acc += (q31_t) ((gnext * (*pv++)));
-
-
-    /* Update f values for next coefficient processing */
-    fcurr = fnext;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages - 1u) >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Process sample for 2nd, 6th ...taps */
-      /* Read gN-2(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 2nd, 6th .. taps */
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext1 = (q15_t) __SSAT(gnext, 16);
-      /* write gN-1(n) into state */
-      *px2++ = (q15_t) gnext1;
-
-
-      /* Process sample for 3nd, 7th ...taps */
-      /* Read gN-3(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 3rd, 7th .. taps */
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
-      fcurr = __SSAT(fcurr, 16);
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
-      gnext2 = (q15_t) __SSAT(gnext, 16);
-      /* write gN-2(n) into state */
-      *px2++ = (q15_t) gnext2;
-
-      /* Read vN-1 and vN-2 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      v = *__SIMD32(pv)++;
-
-#else
-
-	  v1 = *pv++;
-	  v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  v = __PKHBT(v1, v2, 16);
-
-#else
-
-	  v = __PKHBT(v2, v1, 16);
-
-#endif	/* 	#ifndef ARM_MATH_BIG_ENDIAN		*/
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-      /* Pack gN-1(n) and gN-2(n) */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
-      gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* y(n) += gN-1(n) * vN-1  */
-      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
-      /* y(n) += gN-2(n) * vN-2  */
-      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
-      acc = __SMLALD(gnext, v, acc);
-
-
-      /* Process sample for 4th, 8th ...taps */
-      /* Read gN-4(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 4th, 8th .. taps */
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext1 = (q15_t) __SSAT(gnext, 16);
-      /* write  gN-3(n) for the next sample process */
-      *px2++ = (q15_t) gnext1;
-
-
-      /* Process sample for 5th, 9th ...taps */
-      /* Read gN-5(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 5th, 9th .. taps */
-      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
-      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
-      fcurr = __SSAT(fcurr, 16);
-      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
-      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
-      gnext2 = (q15_t) __SSAT(gnext, 16);
-      /* write      gN-4(n) for the next sample process */
-      *px2++ = (q15_t) gnext2;
-
-      /* Read vN-3 and vN-4 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      v = *__SIMD32(pv)++;
-
-#else
-
-	  v1 = *pv++;
-	  v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  v = __PKHBT(v1, v2, 16);
-
-#else
-
-	  v = __PKHBT(v2, v1, 16);
-
-#endif	/* #ifndef ARM_MATH_BIG_ENDIAN	 */
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-      /* Pack gN-3(n) and gN-4(n) */
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
-      gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* y(n) += gN-4(n) * vN-4  */
-      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
-      /* y(n) += gN-3(n) * vN-3  */
-      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
-      acc = __SMLALD(gnext, v, acc);
-
-      tapCnt--;
-
-    }
-
-    fnext = fcurr;
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages - 1u) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext = __SSAT(gnext, 16);
-      /* Output samples for last taps */
-      acc += (q31_t) (((q31_t) gnext * (*pv++)));
-      *px2++ = (q15_t) gnext;
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q31_t) (((q31_t) fnext * (*pv++)));
-
-    out = (q15_t) __SSAT(acc >> 15, 16);
-    *px2++ = (q15_t) fnext;
-
-    /* write out into pDst */
-    *pDst++ = out;
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
-     for the preperation of next frame process */
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  stgCnt = (numStages >> 2u);
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-#endif /*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-    /* Decrement the loop counter */
-    stgCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  stgCnt = (numStages) % 0x4u;
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    stgCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
-  uint32_t stgCnt;                               /* Temporary variables for counts */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pStateCurnt;                            /* State current pointer */
-  q15_t out;                                     /* Temporary variable for output */
-
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample */
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext = fcurr - ((gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
-      gnext = __SSAT(gnext, 16);
-      /* Output samples */
-      /* y(n) += gN(n) * vN */
-      acc += (q31_t) ((gnext * (*pv++)));
-      /* write gN(n) into state for next sample processing */
-      *px2++ = (q15_t) gnext;
-      /* Update f values for next coefficient processing */
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q31_t) ((fnext * (*pv++)));
-
-    out = (q15_t) __SSAT(acc >> 15, 16);
-    *px2++ = (q15_t) fnext;
-
-    /* write out into pDst */
-    *pDst++ = out;
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  stgCnt = numStages;
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    stgCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
deleted file mode 100644
index 347c857b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_q31.c    
-*    
-* Description:	Q31 IIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 IIR lattice filter.    
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.    
- */
-
-void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pStateCurnt;                            /* State current pointer */
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for first tap */
-    gcurr = *px1++;
-    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-    /* write gN-1(n-1) into state for next sample processing */
-    *px2++ = gnext;
-    /* y(n) += gN(n) * vN  */
-    acc += ((q63_t) gnext * *pv++);
-
-    /* Update f values for next coefficient processing */
-    fcurr = fnext;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages - 1u) >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Process sample for 2nd, 6th .. taps */
-      /* Read gN-2(n-1) from state buffer */
-      gcurr = *px1++;
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* y(n) += gN-1(n) * vN-1  */
-      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-1(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* Process sample for 3nd, 7th ...taps */
-      /* Read gN-3(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 3rd, 7th .. taps */
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
-      /* y(n) += gN-2(n) * vN-2  */
-      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-2(n) into state for next sample processing */
-      *px2++ = gnext;
-
-
-      /* Process sample for 4th, 8th ...taps */
-      /* Read gN-4(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 4th, 8th .. taps */
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* y(n) += gN-3(n) * vN-3  */
-      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-3(n) into state for next sample processing */
-      *px2++ = gnext;
-
-
-      /* Process sample for 5th, 9th ...taps */
-      /* Read gN-5(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 5th, 9th .. taps */
-      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
-      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
-      /* y(n) += gN-4(n) * vN-4  */
-      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-4(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      tapCnt--;
-
-    }
-
-    fnext = fcurr;
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages - 1u) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* Output samples for last taps */
-      acc += ((q63_t) gnext * *pv++);
-      *px2++ = gnext;
-      fcurr = fnext;
-
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q63_t) fnext *(
-  *pv++);
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numStages) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  };
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample */
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext =
-        clip_q63_to_q31(((q63_t) fcurr -
-                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
-      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-      gnext =
-        clip_q63_to_q31(((q63_t) gcurr +
-                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
-      /* Output samples */
-      /* y(n) += gN(n) * vN  */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-1(n-1) into state for next sample processing */
-      *px2++ = gnext;
-      /* Update f values for next coefficient processing */
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q63_t) fnext *(
-  *pv++);
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
deleted file mode 100644
index 269330ca..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
+++ /dev/null
@@ -1,442 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_f32.c    
-*    
-* Description:	Processing function for the floating-point LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup LMS Least Mean Square (LMS) Filters    
- *    
- * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.    
- * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.    
- * Adaptive filters are often used in communication systems, equalizers, and noise removal.    
- * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.    
- * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.    
- *    
- * An LMS filter consists of two components as shown below.    
- * The first component is a standard transversal or FIR filter.    
- * The second component is a coefficient update mechanism.    
- * The LMS filter has two input signals.    
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
- * This "error signal" tends towards zero as the filter adapts.    
- * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
- * \image html LMS.gif "Internal structure of the Least Mean Square filter"    
- *    
- * The functions operate on blocks of data and each call to the function processes    
- * blockSize samples through the filter.    
- * pSrc points to input signal, pRef points to reference signal,    
- * pOut points to output signal and pErr points to error signal.    
- * All arrays contain blockSize values.    
- *    
- * The functions operate on a block-by-block basis.    
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
- *    
- * \par Algorithm:    
- * The output signal y[n] is computed by a standard FIR filter:    
- * 
    
- *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- *    
- * \par    
- * The error signal equals the difference between the reference signal d[n] and the filter output:    
- * 
    
- *     e[n] = d[n] - y[n].    
- * 
    
- *    
- * \par    
- * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:    
- * 
    
- *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    
- * 
    
- * where mu is the step size and controls the rate of coefficient convergence.    
- *\par    
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * \par    
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
- * to be avoided and yields a significant speed improvement.    
- * The state variables are updated after each block of data is processed.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter and    
- * coefficient and state arrays cannot be shared among instances.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. 
- *
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    
- *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    
- *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    
- * 
    
- * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.    
- *    
- * \par Fixed-Point Behavior:    
- * Care must be taken when using the Q15 and Q31 versions of the LMS filter.    
- * The following issues must be considered:    
- * - Scaling of coefficients    
- * - Overflow and saturation    
- *    
- * \par Scaling of Coefficients:    
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift.    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * This essentially scales the filter coefficients by 2^postShift and    
- * allows the filter coefficients to exceed the range [+1 -1).    
- * The value of postShift is set by the user based on the expected gain through the system being modeled.    
- *    
- * \par Overflow and Saturation:    
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
- * described separately as part of the function specific documentation below.    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-/**           
- * @details           
- * This function operates on floating-point data types.       
- *    
- * @brief Processing function for floating-point LMS filter.    
- * @param[in]  *S points to an instance of the floating-point LMS filter structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[in]  *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in]  blockSize number of samples to process.    
- * @return     none.    
- */
-
-void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t mu = S->mu;                          /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
-  float32_t w = 0.0f;                            /* weight factor */
-
-  e = 0.0f;
-  d = 0.0f;
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator, store in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for the updating filter coefficients */
-    w = e * mu;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result is stored in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Weighting factor for the LMS version */
-    w = e * mu;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-   * start of the state buffer. This prepares the state buffer for the        
-   * next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
deleted file mode 100644
index a347ddb7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_f32.c    
-*    
-* Description:  Floating-point LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for floating-point LMS filter.    
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to the coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-/**    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().    
- */
-
-void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps */
-  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
deleted file mode 100644
index cac7dfc5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_q15.c    
-*    
-* Description:  Q15 LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-/**    
-* @brief Initialization function for the Q15 LMS filter.    
-* @param[in] *S points to an instance of the Q15 LMS filter structure.    
-* @param[in] numTaps  number of filter coefficients.    
-* @param[in] *pCoeffs points to the coefficient buffer.    
-* @param[in] *pState points to the state buffer.    
-* @param[in] mu step size that controls filter coefficient updates.    
-* @param[in] blockSize number of samples to process.    
-* @param[in] postShift bit shift applied to coefficients.    
-* @return    none.    
-*    
-* \par Description:    
-* pCoeffs points to the array of filter coefficients stored in time reversed order:    
-* 
    
-*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
-* 
    
-* The initial filter coefficients serve as a starting point for the adaptive filter.    
-* pState points to the array of state variables and size of array is    
-* numTaps+blockSize-1 samples, where blockSize is the number of    
-* input samples processed by each call to arm_lms_q15().    
-*/
-
-void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Assign postShift value to be applied */
-  S->postShift = postShift;
-
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
deleted file mode 100644
index d425557b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_q31.c    
-*    
-* Description:  Q31 LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q31 LMS filter.    
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to    
- * arm_lms_q31().    
- */
-
-void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Assign postShift value to be applied */
-  S->postShift = postShift;
-
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
deleted file mode 100644
index 6e3117fe..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_f32.c    
-*    
-* Description:	Processing function for the floating-point Normalised LMS.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup LMS_NORM Normalized LMS Filters    
- *    
- * This set of functions implements a commonly used adaptive filter.    
- * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization    
- * factor which increases the adaptation rate of the filter.    
- * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.    
- *    
- * A normalized least mean square (NLMS) filter consists of two components as shown below.    
- * The first component is a standard transversal or FIR filter.    
- * The second component is a coefficient update mechanism.    
- * The NLMS filter has two input signals.    
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
- * This "error signal" tends towards zero as the filter adapts.    
- * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
- * \image html LMS.gif "Internal structure of the NLMS adaptive filter"    
- *    
- * The functions operate on blocks of data and each call to the function processes    
- * blockSize samples through the filter.    
- * pSrc points to input signal, pRef points to reference signal,    
- * pOut points to output signal and pErr points to error signal.    
- * All arrays contain blockSize values.    
- *    
- * The functions operate on a block-by-block basis.    
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
- *    
- * \par Algorithm:    
- * The output signal y[n] is computed by a standard FIR filter:    
- * 
    
- *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- *    
- * \par    
- * The error signal equals the difference between the reference signal d[n] and the filter output:    
- * 
    
- *     e[n] = d[n] - y[n].    
- * 
    
- *    
- * \par    
- * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:    
- * 
    
- *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    
- * 
    
- * The filter coefficients b[k] are then updated on a sample-by-sample basis:    
- * 
    
- *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    
- * 
    
- * where mu is the step size and controls the rate of coefficient convergence.    
- *\par    
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * \par    
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
- * to be avoided and yields a significant speed improvement.    
- * The state variables are updated after each block of data is processed.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter and    
- * coefficient and state arrays cannot be shared among instances.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * To do this manually without calling the init function, assign the follow subfields of the instance structure:
- * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. 
- * For Q7, Q15, and Q31 the following fields must also be initialized;
- * recipTable, postShift
- *
- * \par    
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.    
- * \par Fixed-Point Behavior:    
- * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.    
- * The following issues must be considered:    
- * - Scaling of coefficients    
- * - Overflow and saturation    
- *    
- * \par Scaling of Coefficients:    
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift.    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * This essentially scales the filter coefficients by 2^postShift and    
- * allows the filter coefficients to exceed the range [+1 -1).    
- * The value of postShift is set by the user based on the expected gain through the system being modeled.    
- *    
- * \par Overflow and Saturation:    
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
- * described separately as part of the function specific documentation below.    
- */
-
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-
-  /**    
-   * @brief Processing function for floating-point normalized LMS filter.    
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.    
-   * @param[in] *pSrc points to the block of input data.    
-   * @param[in] *pRef points to the block of reference data.    
-   * @param[out] *pOut points to the block of output data.    
-   * @param[out] *pErr points to the block of error data.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t mu = S->mu;                          /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  float32_t energy;                              /* Energy of the input */
-  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
-  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
-
-  /* Initializations of error,  difference, Coefficient update */
-  e = 0.0f;
-  d = 0.0f;
-  w = 0.0f;
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= x0 * x0;
-    energy += in * in;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator, store in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for updating filter coefficients */
-    /* epsilon value 0.000000119209289f */
-    w = (e * mu) / (energy + 0.000000119209289f);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  S->energy = energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= x0 * x0;
-    energy += in * in;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator is stored in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for updating filter coefficients */
-    /* epsilon value 0.000000119209289f */
-    w = (e * mu) / (energy + 0.000000119209289f);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCcoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  S->energy = energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     satrt of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of LMS_NORM group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
deleted file mode 100644
index 2c23315e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_f32.c    
-*    
-* Description:  Floating-point NLMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for floating-point normalized LMS filter.    
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   *    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().    
- */
-
-void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialise Energy to zero */
-  S->energy = 0.0f;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0.0f;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
deleted file mode 100644
index be3e31f6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_q15.c    
-*    
-* Description:  Q15 NLMS initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q15 normalized LMS filter.    
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to the array of state variables and size of array is    
- * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed    
- * by each call to arm_lms_norm_q15().    
- */
-
-void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign post Shift value applied to coefficients */
-  S->postShift = postShift;
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialize reciprocal pointer table */
-  S->recipTable = (q15_t *) armRecipTableQ15;
-
-  /* Initialise Energy to zero */
-  S->energy = 0;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
deleted file mode 100644
index 9ada3a00..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_q31.c    
-*    
-* Description:  Q31 NLMS initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q31 normalized LMS filter.    
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().    
- */
-
-void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1  */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
-  /* Assign post Shift value applied to coefficients */
-  S->postShift = postShift;
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialize reciprocal pointer table */
-  S->recipTable = (q31_t *) armRecipTableQ31;
-
-  /* Initialise Energy to zero */
-  S->energy = 0;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
deleted file mode 100644
index 208a9d88..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_q15.c    
-*    
-* Description:	Q15 NLMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-/**    
-* @brief Processing function for Q15 normalized LMS filter.    
-* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
-* @param[in] *pSrc points to the block of input data.    
-* @param[in] *pRef points to the block of reference data.    
-* @param[out] *pOut points to the block of output data.    
-* @param[out] *pErr points to the block of error data.    
-* @param[in] blockSize number of samples to process.    
-* @return none.    
-*    
-* Scaling and Overflow Behavior:     
-* \par     
-* The function is implemented using a 64-bit internal accumulator.     
-* Both coefficients and state variables are represented in 1.15 format and    
-* multiplications yield a 2.30 result. The 2.30 intermediate results are    
-* accumulated in a 64-bit accumulator in 34.30 format.     
-* There is no risk of internal overflow with this approach and the full    
-* precision of intermediate multiplications is preserved. After all additions    
-* have been performed, the accumulator is truncated to 34.15 format by    
-* discarding low 15 bits. Lastly, the accumulator is saturated to yield a    
-* result in 1.15 format.    
-*    
-* \par   
-* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
-*    
- */
-
-void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
-  q15_t mu = S->mu;                              /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q31_t energy;                                  /* Energy of the input */
-  q63_t acc;                                     /* Accumulator */
-  q15_t e = 0, d = 0;                            /* error, reference data sample */
-  q15_t w = 0, in;                               /* weight factor and state */
-  q15_t x0;                                      /* temporary variable to hold input sample */
-  //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */ 
-  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
-  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
-  q31_t coef;                                    /* Teporary variable for coefficient */
-  q31_t acc_l, acc_h;
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
-  int32_t uShift = (32 - lShift);
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= (((q31_t) x0 * (x0)) >> 15);
-    energy += (((q31_t) in * (in)) >> 15);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (((q31_t) * px++ * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16u);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q15_t) acc;
-    *pErr++ = e;
-
-    /* Calculation of 1/energy */
-    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
-                              &oneByEnergy, S->recipTable);
-
-    /* Calculation of e * mu value */
-    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
-    /* Calculation of (e * mu) * (1/energy) value */
-    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
-    /* Weighting factor for the normalized version */
-    w = (q15_t) __SSAT((q31_t) acc, 16);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q15_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-#endif
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= (((q31_t) x0 * (x0)) >> 15);
-    energy += (((q31_t) in * (in)) >> 15);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (((q31_t) * px++ * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16u);
-
-    /* Converting the result to 1.15 format */
-    //acc = __SSAT((acc >> (16u - shift)), 16u); 
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q15_t) acc;
-    *pErr++ = e;
-
-    /* Calculation of 1/energy */
-    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
-                              &oneByEnergy, S->recipTable);
-
-    /* Calculation of e * mu value */
-    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
-    /* Calculation of (e * mu) * (1/energy) value */
-    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
-    /* Weighting factor for the normalized version */
-    w = (q15_t) __SSAT((q31_t) acc, 16);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q15_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     satrt of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* copy (numTaps - 1u) data */
-  tapCnt = (numTaps - 1u);
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-
-/**    
-   * @} end of LMS_NORM group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
deleted file mode 100644
index 3d990e3f..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_q31.c    
-*    
-* Description:	Processing function for the Q31 NLMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-/**    
-* @brief Processing function for Q31 normalized LMS filter.    
-* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
-* @param[in] *pSrc points to the block of input data.    
-* @param[in] *pRef points to the block of reference data.    
-* @param[out] *pOut points to the block of output data.    
-* @param[out] *pErr points to the block of error data.    
-* @param[in] blockSize number of samples to process.    
-* @return none.    
-*    
-* Scaling and Overflow Behavior:     
-* \par     
-* The function is implemented using an internal 64-bit accumulator.     
-* The accumulator has a 2.62 format and maintains full precision of the intermediate   
-* multiplication results but provides only a single guard bit.     
-* Thus, if the accumulator result overflows it wraps around rather than clip.     
-* In order to avoid overflows completely the input signal must be scaled down by    
-* log2(numTaps) bits. The reference signal should not be scaled down.     
-* After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
-* and saturated to 1.31 format to yield the final result.     
-* The output signal and error signal are in 1.31 format.     
-*    
-* \par    
-* 	In this filter, filter coefficients are updated for each sample and the    
-* updation of filter cofficients are saturted.    
-*     
-*/
-
-void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
-  q31_t mu = S->mu;                              /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t energy;                                  /* Energy of the input */
-  q63_t acc;                                     /* Accumulator */
-  q31_t e = 0, d = 0;                            /* error, reference data sample */
-  q31_t w = 0, in;                               /* weight factor and state */
-  q31_t x0;                                      /* temporary variable to hold input sample */
-//  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */      
-  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
-  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
-  q31_t coef;                                    /* Temporary variable for coef */
-  q31_t acc_l, acc_h;                            /*  temporary input */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy = (q31_t) ((((q63_t) energy << 32) -
-                       (((q63_t) x0 * x0) << 1)) >> 32);
-    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q31_t) acc;
-    *pErr++ = e;
-
-    /* Calculates the reciprocal of energy */
-    postShift = arm_recip_q31(energy + DELTA_Q31,
-                              &oneByEnergy, &S->recipTable[0]);
-
-    /* Calculation of product of (e * mu) */
-    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Weighting factor for the normalized version */
-    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q31_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy =
-      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
-    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-
-    //acc = (q31_t) (acc >> shift); 
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q31_t) acc;
-    *pErr++ = e;
-
-    /* Calculates the reciprocal of energy */
-    postShift =
-      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
-
-    /* Calculation of product of (e * mu) */
-    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Weighting factor for the normalized version */
-    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q31_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
-     start of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
deleted file mode 100644
index c0d465a8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_q15.c    
-*    
-* Description:	Processing function for the Q15 LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
- /**    
- * @brief Processing function for Q15 LMS filter.    
- * @param[in] *S points to an instance of the Q15 LMS filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[in] *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * \par Scaling and Overflow Behavior:    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- *   
- * \par   
- * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
- *    
- */
-
-void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t mu = S->mu;                              /* Adaptive factor */
-  q15_t *px;                                     /* Temporary pointer for state */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t acc;                                     /* Accumulator */
-  q15_t e = 0;                                   /* error of data sample */
-  q15_t alpha;                                   /* Intermediate constant for taps update */
-  q31_t coef;                                    /* Teporary variable for coefficient */
-  q31_t acc_l, acc_h;
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
-  int32_t uShift = (32 - lShift);
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initializing blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2u;
-
-    while(tapCnt > 0u)
-    {
-      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q15_t) acc;
-
-    *pErr++ = (q15_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
-    /* Initialize state pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2u;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-#else
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-#endif
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q15_t) acc;
-
-    *pErr++ = (q15_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
-    /* Initialize pState pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     start of the state buffer. This prepares the state buffer for the   
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
deleted file mode 100644
index 53c57f02..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_q31.c    
-*    
-* Description:	Processing function for the Q31 LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
- /**    
- * @brief Processing function for Q31 LMS filter.    
- * @param[in]  *S points to an instance of the Q15 LMS filter structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[in]  *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in]  blockSize number of samples to process.    
- * @return     none.    
- *    
- * \par Scaling and Overflow Behavior:     
- * The function is implemented using an internal 64-bit accumulator.     
- * The accumulator has a 2.62 format and maintains full precision of the intermediate    
- * multiplication results but provides only a single guard bit.     
- * Thus, if the accumulator result overflows it wraps around rather than clips.     
- * In order to avoid overflows completely the input signal must be scaled down by    
- * log2(numTaps) bits.     
- * The reference signal should not be scaled down.     
- * After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
- * and saturated to 1.31 format to yield the final result.     
- * The output signal and error signal are in 1.31 format.     
- *    
- * \par    
- * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
- */
-
-void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t mu = S->mu;                              /* Adaptive factor */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t acc;                                     /* Accumulator */
-  q31_t e = 0;                                   /* error of data sample */
-  q31_t alpha;                                   /* Intermediate constant for taps update */
-  q31_t coef;                                    /* Temporary variable for coef */
-  q31_t acc_l, acc_h;                            /*  temporary input */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initializing blkCnt with blockSize */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* acc +=  b[N] * x[n-N] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-1] * x[n-N-1] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-2] * x[n-N-2] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-3] * x[n-N-3] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q31_t) acc;
-
-    *pErr++ = (q31_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Initialize state pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Store the result from accumulator into the destination buffer. */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q31_t) acc;
-
-    *pErr++ = (q31_t) e;
-
-    /* Weighting factor for the LMS version */
-    alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Initialize pState pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
-     start of the state buffer. This prepares the state buffer for the   
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
deleted file mode 100644
index 123f9e9a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_add_f32.c    
-*    
-* Description:	Floating-point matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixAdd Matrix Addition        
- *        
- * Adds two matrices.        
- * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"        
- *        
- * The functions check to make sure that        
- * pSrcA, pSrcB, and pDst have the same        
- * number of rows and columns.        
- */
-
-/**        
- * @addtogroup MatrixAdd        
- * @{        
- */
-
-
-/**        
- * @brief Floating-point matrix addition.        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- */
-
-arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Loop unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* out = sourceA + sourceB */
-      out1 = inA1 + inB1;
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* out = sourceA + sourceB */
-      out2 = inA2 + inB2;
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* out = sourceA + sourceB */
-      out1 = inA1 + inB1;
-
-      /* out = sourceA + sourceB */
-      out2 = inA2 + inB2;
-
-      /* Store result in destination */
-      pOut[2] = out1;
-
-      /* Store result in destination */
-      pOut[3] = out2;
-
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add and then store the results in the destination buffer. */
-      *pOut++ = (*pIn1++) + (*pIn2++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixAdd group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
deleted file mode 100644
index ef7f8697..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_add_q15.c    
-*    
-* Description:	Q15 matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixAdd    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix addition.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint16_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix addition  */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop unrolling */
-    blkCnt = (uint32_t) numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = (uint32_t) numSamples % 0x4u;
-
-    /* q15 pointers of input and output are initialized */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = (uint32_t) numSamples;
-
-
-    /* q15 pointers of input and output are initialized */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixAdd group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
deleted file mode 100644
index de02d707..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_add_q31.c    
-*    
-* Description:	Q31 matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**      
- * @ingroup groupMatrix      
- */
-
-/**      
- * @addtogroup MatrixAdd      
- * @{      
- */
-
-/**      
- * @brief Q31 matrix addition.      
- * @param[in]       *pSrcA points to the first input matrix structure      
- * @param[in]       *pSrcB points to the second input matrix structure      
- * @param[out]      *pDst points to output matrix structure      
- * @return     		The function returns either      
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      
- *      
- * Scaling and Overflow Behavior:      
- * \par      
- * The function uses saturating arithmetic.      
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.      
- */
-
-arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t inA1, inB1;                              /* temporary variables */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  q31_t inA2, inB2;                              /* temporary variables */
-  q31_t out1, out2;                              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, saturate and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* Add and saturate */
-      out1 = __QADD(inA1, inB1);
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* Add and saturate */
-      out2 = __QADD(inA2, inB2);
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* Add and saturate */
-      out1 = __QADD(inA1, inB1);
-      out2 = __QADD(inA2, inB2);
-
-      /* Store result in destination */
-      pOut[2] = out1;
-      pOut[3] = out2;
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.      
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, saturate and then store the results in the destination buffer. */
-      inA1 = *pIn1++;
-      inB1 = *pIn2++;
-
-      inA1 = __QADD(inA1, inB1);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-
-      *pOut++ = inA1;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**      
- * @} end of MatrixAdd group      
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
deleted file mode 100644
index dd41e7c4..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* ----------------------------------------------------------------------      
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
-*      
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*      
-* Project:      CMSIS DSP Library 
-* Title:	    arm_mat_cmplx_mult_f32.c      
-*      
-* Description:  Floating-point matrix multiplication.      
-*      
-* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**      
- * @ingroup groupMatrix      
- */
-
-/**      
- * @defgroup CmplxMatrixMult  Complex Matrix Multiplication     
- *     
- * Complex Matrix multiplication is only defined if the number of columns of the      
- * first matrix equals the number of rows of the second matrix.      
- * Multiplying an M x N matrix with an N x P matrix results      
- * in an M x P matrix.      
- * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of      
- * pSrcA and pSrcB are equal; and (2) that the size of the output      
- * matrix equals the outer dimensions of pSrcA and pSrcB.      
- */
-
-
-/**      
- * @addtogroup CmplxMatrixMult      
- * @{      
- */
-
-/**      
- * @brief Floating-point Complex matrix multiplication.      
- * @param[in]       *pSrcA points to the first input complex matrix structure      
- * @param[in]       *pSrcB points to the second input complex matrix structure      
- * @param[out]      *pDst points to output complex matrix structure      
- * @return     		The function returns either      
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      
- */
-
-arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
-  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *px;                                 /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  float32_t sumReal1, sumImag1;                  /* accumulator */
-  float32_t a0, b0, c0, d0;
-  float32_t a1, b1, c1, d1;
-  float32_t sumReal2, sumImag2;                  /* accumulator */
-
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + 2 * i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set      
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sumReal1 = 0.0f;
-        sumImag1 = 0.0f;
-
-        sumReal2 = 0.0f;
-        sumImag2 = 0.0f;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* matrix multiplication        */
-        while(colCnt > 0u)
-        {
-
-          /* Reading real part of complex matrix A */
-          a0 = *pIn1;
-
-          /* Reading real part of complex matrix B */
-          c0 = *pIn2;
-
-          /* Reading imaginary part of complex matrix A */
-          b0 = *(pIn1 + 1u);
-
-          /* Reading imaginary part of complex matrix B */
-          d0 = *(pIn2 + 1u);
-
-          sumReal1 += a0 * c0;
-          sumImag1 += b0 * c0;
-
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          sumReal2 -= b0 * d0;
-          sumImag2 += a0 * d0;
-
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-          a1 = *pIn1;
-          c1 = *pIn2;
-
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          sumReal1 += a1 * c1;
-          sumImag1 += b1 * c1;
-
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          sumReal2 -= b1 * d1;
-          sumImag2 += a1 * d1;
-
-          a0 = *pIn1;
-          c0 = *pIn2;
-
-          b0 = *(pIn1 + 1u);
-          d0 = *(pIn2 + 1u);
-
-          sumReal1 += a0 * c0;
-          sumImag1 += b0 * c0;
-
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          sumReal2 -= b0 * d0;
-          sumImag2 += a0 * d0;
-
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-          a1 = *pIn1;
-          c1 = *pIn2;
-
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          sumReal1 += a1 * c1;
-          sumImag1 += b1 * c1;
-
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          sumReal2 -= b1 * d1;
-          sumImag2 += a1 * d1;
-
-          /* Decrement the loop count */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.      
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          a1 = *pIn1;
-          c1 = *pIn2;
-
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          sumReal1 += a1 * c1;
-          sumImag1 += b1 * c1;
-
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          sumReal2 -= b1 * d1;
-          sumImag2 += a1 * d1;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        sumReal1 += sumReal2;
-        sumImag1 += sumImag2;
-
-        /* Store the result in the destination buffer */
-        *px++ = sumReal1;
-        *px++ = sumImag1;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + 2u * j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + 2 * numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**      
- * @} end of MatrixMult group      
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
deleted file mode 100644
index 8e3fc06c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* ----------------------------------------------------------------------      
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
-*      
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*      
-* Project:      CMSIS DSP Library 
-* Title:	    arm_cmplx_mat_mult_q15.c      
-*      
-* Description:	 Q15 complex matrix multiplication.      
-*      
-* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**      
- * @ingroup groupMatrix      
- */
-
-/**      
- * @addtogroup CmplxMatrixMult      
- * @{      
- */
-
-
-/**      
- * @brief Q15 Complex matrix multiplication      
- * @param[in]       *pSrcA points to the first input complex matrix structure      
- * @param[in]       *pSrcB points to the second input complex matrix structure      
- * @param[out]      *pDst points to output complex matrix structure      
- * @param[in]		*pScratch points to the array for storing intermediate results     
- * @return     		The function returns either      
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.         
- *  
- * \par Conditions for optimum performance  
- *  Input, output and state buffers should be aligned by 32-bit  
- *  
- * \par Restrictions  
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE  
- *	In this case input, output, scratch buffers should be aligned by 32-bit  
- *  
- * @details      
- * Scaling and Overflow Behavior:      
- *      
- * \par      
- * The function is implemented using a 64-bit internal accumulator. The inputs to the      
- * multiplications are in 1.15 format and multiplications yield a 2.30 result.      
- * The 2.30 intermediate      
- * results are accumulated in a 64-bit accumulator in 34.30 format. This approach      
- * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then      
- * truncated to 34.15 format by discarding the low 15 bits and then saturated to      
- * 1.15 format.      
- *      
- * \par      
- * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function.      
- *      
- */
-
-
-
-
-arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch)
-{
-  /* accumulator */
-  q15_t *pSrcBT = pScratch;                      /* input data matrix pointer for transpose */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-  q63_t sumReal, sumImag;
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  q15_t in;                                      /* Temporary variable to hold the input value */
-  q15_t a, b, c, d;
-#else
-  q31_t in;                                      /* Temporary variable to hold the input value */
-  q31_t prod1, prod2;
-  q31_t pSourceA, pSourceB;
-#endif
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Matrix transpose */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = numColsB >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pSrcBT + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifdef UNALIGNED_SUPPORT_DISABLE
-        /* Read two elements from the row */
-        in = *pInB++;
-        *px = in;
-        in = *pInB++;
-        px[1] = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Read two elements from the row */
-        in = *pInB++;
-        *px = in;
-        in = *pInB++;
-        px[1] = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Read two elements from the row */
-        in = *pInB++;
-        *px = in;
-        in = *pInB++;
-        px[1] = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Read two elements from the row */
-        in = *pInB++;
-        *px = in;
-        in = *pInB++;
-        px[1] = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.      
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read two elements from the row */
-        in = *pInB++;
-        *px = in;
-        in = *pInB++;
-        px[1] = in;
-#else
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        *__SIMD32(px) = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        *__SIMD32(px) = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        *__SIMD32(px) = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        *__SIMD32(px) = in;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.      
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        *__SIMD32(px) = in;
-#endif
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB * 2;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i = i + 2u;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Reset the variables for the usage in the following multiplication process */
-    row = numRowsA;
-    i = 0u;
-    px = pDst->pData;
-
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set      
-       ** to the starting address of the transposed pSrcB data */
-      pInB = pSrcBT;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sumReal = 0;
-        sumImag = 0;
-
-        /* Apply loop unrolling and compute 2 MACs simultaneously. */
-        colCnt = numColsA >> 1;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pInA = pSrcA->pData + i * 2;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-          /* read real and imag values from pSrcA buffer */
-          a = *pInA;
-          b = *(pInA + 1u);
-          /* read real and imag values from pSrcB buffer */
-          c = *pInB;
-          d = *(pInB + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal += (q31_t) a *c;
-          sumImag += (q31_t) a *d;
-          sumReal -= (q31_t) b *d;
-          sumImag += (q31_t) b *c;
-
-          /* read next real and imag values from pSrcA buffer */
-          a = *(pInA + 2u);
-          b = *(pInA + 3u);
-          /* read next real and imag values from pSrcB buffer */
-          c = *(pInB + 2u);
-          d = *(pInB + 3u);
-
-          /* update pointer */
-          pInA += 4u;
-
-          /* Multiply and Accumlates */
-          sumReal += (q31_t) a *c;
-          sumImag += (q31_t) a *d;
-          sumReal -= (q31_t) b *d;
-          sumImag += (q31_t) b *c;
-          /* update pointer */
-          pInB += 4u;
-#else
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          pSourceA = *__SIMD32(pInA)++;
-          pSourceB = *__SIMD32(pInB)++;
-
-          /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
-          prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
-          prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
-          prod2 = __SMUADX(pSourceA, pSourceB);
-          sumReal += (q63_t) prod1;
-          sumImag += (q63_t) prod2;
-
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          pSourceA = *__SIMD32(pInA)++;
-          pSourceB = *__SIMD32(pInB)++;
-
-          /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
-          prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
-          prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
-          prod2 = __SMUADX(pSourceA, pSourceB);
-          sumReal += (q63_t) prod1;
-          sumImag += (q63_t) prod2;
-
-#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* process odd column samples */
-        if((numColsA & 0x1u) > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          a = *pInA++;
-          b = *pInA++;
-          c = *pInB++;
-          d = *pInB++;
-
-          /* Multiply and Accumlates */
-          sumReal += (q31_t) a *c;
-          sumImag += (q31_t) a *d;
-          sumReal -= (q31_t) b *d;
-          sumImag += (q31_t) b *c;
-
-#else
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          pSourceA = *__SIMD32(pInA)++;
-          pSourceB = *__SIMD32(pInB)++;
-
-          /* Multiply and Accumlates */
-#ifdef ARM_MATH_BIG_ENDIAN
-          prod1 = -__SMUSD(pSourceA, pSourceB);
-#else
-          prod1 = __SMUSD(pSourceA, pSourceB);
-#endif
-          prod2 = __SMUADX(pSourceA, pSourceB);
-          sumReal += (q63_t) prod1;
-          sumImag += (q63_t) prod2;
-
-#endif /*      #ifdef UNALIGNED_SUPPORT_DISABLE */
-
-        }
-
-        /* Saturate and store the result in the destination buffer */
-
-        *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
-        *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      i = i + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**      
- * @} end of MatrixMult group      
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
deleted file mode 100644
index 4dfe1fd5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* ----------------------------------------------------------------------      
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved. 
-*      
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*      
-* Project:      CMSIS DSP Library 
-* Title:	    arm_mat_cmplx_mult_q31.c      
-*      
-* Description:  Floating-point matrix multiplication.      
-*      
-* Target Processor:          Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**     
- * @ingroup groupMatrix     
- */
-
-/**      
- * @addtogroup CmplxMatrixMult      
- * @{      
- */
-
-/**      
- * @brief Q31 Complex matrix multiplication      
- * @param[in]       *pSrcA points to the first input complex matrix structure      
- * @param[in]       *pSrcB points to the second input complex matrix structure      
- * @param[out]      *pDst points to output complex matrix structure      
- * @return     		The function returns either      
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      
- *      
- * @details      
- * Scaling and Overflow Behavior:      
- *      
- * \par      
- * The function is implemented using an internal 64-bit accumulator.      
- * The accumulator has a 2.62 format and maintains full precision of the intermediate      
- * multiplication results but provides only a single guard bit. There is no saturation      
- * on intermediate additions. Thus, if the accumulator overflows it wraps around and      
- * distorts the result. The input signals should be scaled down to avoid intermediate      
- * overflows. The input is thus scaled down by log2(numColsA) bits      
- * to avoid overflows, as a total of numColsA additions are performed internally.      
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.      
- *      
- *      
- */
-
-arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  q63_t sumReal1, sumImag1;                      /* accumulator */
-  q31_t a0, b0, c0, d0;
-  q31_t a1, b1, c1, d1;
-
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + 2 * i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set     
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sumReal1 = 0.0;
-        sumImag1 = 0.0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* matrix multiplication        */
-        while(colCnt > 0u)
-        {
-
-          /* Reading real part of complex matrix A */
-          a0 = *pIn1;
-
-          /* Reading real part of complex matrix B */
-          c0 = *pIn2;
-
-          /* Reading imaginary part of complex matrix A */
-          b0 = *(pIn1 + 1u);
-
-          /* Reading imaginary part of complex matrix B */
-          d0 = *(pIn2 + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal1 += (q63_t) a0 *c0;
-          sumImag1 += (q63_t) b0 *c0;
-
-          /* update pointers */
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          /* Multiply and Accumlates */
-          sumReal1 -= (q63_t) b0 *d0;
-          sumImag1 += (q63_t) a0 *d0;
-
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          a1 = *pIn1;
-          c1 = *pIn2;
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal1 += (q63_t) a1 *c1;
-          sumImag1 += (q63_t) b1 *c1;
-
-          /* update pointers */
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          /* Multiply and Accumlates */
-          sumReal1 -= (q63_t) b1 *d1;
-          sumImag1 += (q63_t) a1 *d1;
-
-          a0 = *pIn1;
-          c0 = *pIn2;
-
-          b0 = *(pIn1 + 1u);
-          d0 = *(pIn2 + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal1 += (q63_t) a0 *c0;
-          sumImag1 += (q63_t) b0 *c0;
-
-          /* update pointers */
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          /* Multiply and Accumlates */
-          sumReal1 -= (q63_t) b0 *d0;
-          sumImag1 += (q63_t) a0 *d0;
-
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-
-          a1 = *pIn1;
-          c1 = *pIn2;
-
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal1 += (q63_t) a1 *c1;
-          sumImag1 += (q63_t) b1 *c1;
-
-          /* update pointers */
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          /* Multiply and Accumlates */
-          sumReal1 -= (q63_t) b1 *d1;
-          sumImag1 += (q63_t) a1 *d1;
-
-          /* Decrement the loop count */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.     
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          a1 = *pIn1;
-          c1 = *pIn2;
-
-          b1 = *(pIn1 + 1u);
-          d1 = *(pIn2 + 1u);
-
-          /* Multiply and Accumlates */
-          sumReal1 += (q63_t) a1 *c1;
-          sumImag1 += (q63_t) b1 *c1;
-
-          /* update pointers */
-          pIn1 += 2u;
-          pIn2 += 2 * numColsB;
-
-          /* Multiply and Accumlates */
-          sumReal1 -= (q63_t) b1 *d1;
-          sumImag1 += (q63_t) a1 *d1;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Store the result in the destination buffer */
-        *px++ = (q31_t) clip_q63_to_q31(sumReal1 >> 31);
-        *px++ = (q31_t) clip_q63_to_q31(sumImag1 >> 31);
-        
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + 2u * j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + 2 * numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**     
- * @} end of MatrixMult group     
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
deleted file mode 100644
index 1a0e5e86..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_f32.c    
-*    
-* Description:	Floating-point matrix initialization.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInit Matrix Initialization    
- *    
- * Initializes the underlying matrix data structure.    
- * The functions set the numRows,    
- * numCols, and pData fields    
- * of the matrix data structure.    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-/**    
-   * @brief  Floating-point matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
deleted file mode 100644
index 33f2f785..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_q15.c    
-*    
-* Description:	Q15 matrix initialization.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-  /**    
-   * @brief  Q15 matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
deleted file mode 100644
index 27c451a2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_q31.c    
-*    
-* Description:	Q31 matrix initialization.    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInit Matrix Initialization    
- *    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-  /**    
-   * @brief  Q31 matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
deleted file mode 100644
index 40b67ad8..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
+++ /dev/null
@@ -1,703 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_inverse_f32.c    
-*    
-* Description:	Floating-point matrix inverse.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInv Matrix Inverse    
- *    
- * Computes the inverse of a matrix.    
- *    
- * The inverse is defined only if the input matrix is square and non-singular (the determinant    
- * is non-zero). The function checks that the input and output matrices are square and of the    
- * same size.    
- *    
- * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
- * inversion of floating-point matrices.    
- *    
- * \par Algorithm    
- * The Gauss-Jordan method is used to find the inverse.    
- * The algorithm performs a sequence of elementary row-operations until it    
- * reduces the input matrix to an identity matrix. Applying the same sequence    
- * of elementary row-operations to an identity matrix yields the inverse matrix.    
- * If the input matrix is singular, then the algorithm terminates and returns error status    
- * ARM_MATH_SINGULAR.    
- * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
- */
-
-/**    
- * @addtogroup MatrixInv    
- * @{    
- */
-
-/**    
- * @brief Floating-point matrix inverse.    
- * @param[in]       *pSrc points to input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns    
- * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size    
- * of the output matrix does not match the size of the input matrix.    
- * If the input matrix is found to be singular (non-invertible), then the function returns    
- * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.    
- */
-
-arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
-  float32_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
-  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
-  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
-  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
-
-#ifndef ARM_MATH_CM0_FAMILY
-  float32_t maxC;                                /* maximum value in the column */
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------    
-	 * Matrix Inverse can be solved using elementary row operations.    
-	 *    
-	 *	Gauss-Jordan Method:    
-	 *    
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
-	 *        augmented matrix as follows:    
-	 *				        _ 	      	       _         _	       _    
-	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
-	 *					   |           |        |   =   |           |    
-	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
-	 *    
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *    
-	 *		3. Begin with the first row. Let i = 1.    
-	 *    
-	 *	    4. Check to see if the pivot for column i is the greatest of the column.    
-	 *		   The pivot is the element of the main diagonal that is on the current row.    
-	 *		   For instance, if working with row i, then the pivot element is aii.    
-	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
-	 *		   below it that does contain the most significant value in column i. If the most
-	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
-	 *		   The most significant value of the column is the absolute maximum.
-	 *    
-	 *	    5. Divide every element of row i by the pivot.    
-	 *    
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
-	 *		   a multiple of row i so that each new element in column i below row i is zero.    
-	 *    
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
-	 *		   for every element below and above the main diagonal.    
-	 *    
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
-	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pOutT1 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pOutT1++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.    
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.    
-       * If there is no non zero element to replace in the rows below,    
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points    
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points    
-       * to the pivot element of the particular row  */
-      pOutT1 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Grab the most significant value from column l */
-      maxC = 0;
-      for (i = l; i < numRows; i++)
-      {
-        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
-        pInT1 += numCols;
-      }
-
-      /* Update the status if the matrix is singular */
-      if(maxC == 0.0f)
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Restore pInT1  */
-      pInT1 = pIn;
-
-      /* Destination pointer modifier */
-      k = 1u;
-      
-      /* Check if the pivot element is the most significant of the column */
-      if( (in > 0.0f ? in : -in) != maxC)
-      {
-        /* Loop over the number rows present below */
-        i = numRows - (l + 1u);
-
-        while(i > 0u)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pOutT2 = pOutT1 + (numCols * k);
-
-          /* Look for the most significant element to    
-           * replace in the rows below */
-          if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
-          {
-            /* Loop over number of columns    
-             * to the right of the pilot element */
-            j = numCols - l;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Loop over number of columns of the destination matrix */
-            j = numCols;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the destination matrix */
-              Xchg = *pOutT2;
-              *pOutT2++ = *pOutT1;
-              *pOutT1++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-
-          /* Decrement the loop counter */
-          i--;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pInT2 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *pPivotRowIn;
-
-      /* Loop over number of columns    
-       * to the right of the pilot element */
-      j = (numCols - l);
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the input matrix    
-         * by the pivot element */
-        in1 = *pInT1;
-        *pInT1++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Loop over number of columns of the destination matrix */
-      j = numCols;
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the destination matrix    
-         * by the pivot element */
-        in1 = *pInT2;
-        *pInT2++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i    
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pInT2 = pOut;
-
-      /* index used to check for pivot element */
-      i = 0u;
-
-      /* Loop over number of rows */
-      /*  to be replaced by the sum of that row and a multiple of row i */
-      k = numRows;
-
-      while(k > 0u)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,    
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-
-          pInT2 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,    
-             to replace the elements in the input matrix */
-          j = (numCols - l);
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT1;
-            *pInT1++ = in1 - (in * *pPRT_in++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-          /* Loop over the number of columns to    
-             replace the elements in the destination matrix */
-          j = numCols;
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT2;
-            *pInT2++ = in1 - (in * *pPRT_pDst++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-        }
-
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-
-        /* Decrement the loop counter */
-        k--;
-
-        /* Increment the pivot index */
-        i++;
-      }
-
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------       
-	 * Matrix Inverse can be solved using elementary row operations.        
-	 *        
-	 *	Gauss-Jordan Method:       
-	 *	 	       
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
-	 *        augmented matrix as follows:        
-	 *				        _  _	      _	    _	   _   _         _	       _       
-	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
-	 *					   |  |            | | |        |   |   =   |           |        
-	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
-	 *					          
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *       
-	 *		3. Begin with the first row. Let i = 1.       
-	 *       
-	 *	    4. Check to see if the pivot for row i is zero.       
-	 *		   The pivot is the element of the main diagonal that is on the current row.       
-	 *		   For instance, if working with row i, then the pivot element is aii.       
-	 *		   If the pivot is zero, exchange that row with a row below it that does not        
-	 *		   contain a zero in column i. If this is not possible, then an inverse        
-	 *		   to that matrix does not exist.       
-	 *	       
-	 *	    5. Divide every element of row i by the pivot.       
-	 *	       
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
-	 *		   a multiple of row i so that each new element in column i below row i is zero.       
-	 *	       
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
-	 *		   for every element below and above the main diagonal.        
-	 *		   		          
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
-	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pOutT1 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pOutT1++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.     
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.   
-       * If there is no non zero element to replace in the rows below,   
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points     
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points     
-       * to the pivot element of the particular row  */
-      pOutT1 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Destination pointer modifier */
-      k = 1u;
-
-      /* Check if the pivot element is zero */
-      if(*pInT1 == 0.0f)
-      {
-        /* Loop over the number rows present below */
-        for (i = (l + 1u); i < numRows; i++)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pOutT2 = pOutT1 + (numCols * k);
-
-          /* Check if there is a non zero pivot element to     
-           * replace in the rows below */
-          if(*pInT2 != 0.0f)
-          {
-            /* Loop over number of columns     
-             * to the right of the pilot element */
-            for (j = 0u; j < (numCols - l); j++)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-            }
-
-            for (j = 0u; j < numCols; j++)
-            {
-              Xchg = *pOutT2;
-              *pOutT2++ = *pOutT1;
-              *pOutT1++ = Xchg;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pOutT1 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *(pIn + (l * numCols));
-
-      /* Loop over number of columns     
-       * to the right of the pilot element */
-      for (j = 0u; j < (numCols - l); j++)
-      {
-        /* Divide each element of the row of the input matrix     
-         * by the pivot element */
-        *pInT1 = *pInT1 / in;
-        pInT1++;
-      }
-      for (j = 0u; j < numCols; j++)
-      {
-        /* Divide each element of the row of the destination matrix     
-         * by the pivot element */
-        *pOutT1 = *pOutT1 / in;
-        pOutT1++;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i     
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pOutT1 = pOut;
-
-      for (i = 0u; i < numRows; i++)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,     
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-          pOutT1 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,     
-             to replace the elements in the input matrix */
-          for (j = 0u; j < (numCols - l); j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pInT1 = *pInT1 - (in * *pPRT_in++);
-            pInT1++;
-          }
-          /* Loop over the number of columns to     
-             replace the elements in the destination matrix */
-          for (j = 0u; j < numCols; j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
-            pOutT1++;
-          }
-
-        }
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-      }
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-    if((flag != 1u) && (in == 0.0f))
-    {
-      pIn = pSrc->pData;
-      for (i = 0; i < numRows * numCols; i++)
-      {
-        if (pIn[i] != 0.0f)
-            break;
-      }
-      
-      if (i == numRows * numCols)
-        status = ARM_MATH_SINGULAR;
-    }
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixInv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
deleted file mode 100644
index a6c4980e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c
+++ /dev/null
@@ -1,703 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_inverse_f64.c    
-*    
-* Description:	Floating-point matrix inverse.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInv Matrix Inverse    
- *    
- * Computes the inverse of a matrix.    
- *    
- * The inverse is defined only if the input matrix is square and non-singular (the determinant    
- * is non-zero). The function checks that the input and output matrices are square and of the    
- * same size.    
- *    
- * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
- * inversion of floating-point matrices.    
- *    
- * \par Algorithm    
- * The Gauss-Jordan method is used to find the inverse.    
- * The algorithm performs a sequence of elementary row-operations until it    
- * reduces the input matrix to an identity matrix. Applying the same sequence    
- * of elementary row-operations to an identity matrix yields the inverse matrix.    
- * If the input matrix is singular, then the algorithm terminates and returns error status    
- * ARM_MATH_SINGULAR.    
- * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
- */
-
-/**    
- * @addtogroup MatrixInv    
- * @{    
- */
-
-/**    
- * @brief Floating-point matrix inverse.    
- * @param[in]       *pSrc points to input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns    
- * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size    
- * of the output matrix does not match the size of the input matrix.    
- * If the input matrix is found to be singular (non-invertible), then the function returns    
- * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.    
- */
-
-arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * pSrc,
-  arm_matrix_instance_f64 * pDst)
-{
-  float64_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float64_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float64_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
-  float64_t *pOutT1, *pOutT2;                    /* Temporary output data matrix pointer */
-  float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
-  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
-  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
-
-#ifndef ARM_MATH_CM0_FAMILY
-  float64_t maxC;                                /* maximum value in the column */
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float64_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------    
-	 * Matrix Inverse can be solved using elementary row operations.    
-	 *    
-	 *	Gauss-Jordan Method:    
-	 *    
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
-	 *        augmented matrix as follows:    
-	 *				        _ 	      	       _         _	       _    
-	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
-	 *					   |           |        |   =   |           |    
-	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
-	 *    
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *    
-	 *		3. Begin with the first row. Let i = 1.    
-	 *    
-	 *	    4. Check to see if the pivot for column i is the greatest of the column.    
-	 *		   The pivot is the element of the main diagonal that is on the current row.    
-	 *		   For instance, if working with row i, then the pivot element is aii.    
-	 *		   If the pivot is not the most significant of the columns, exchange that row with a row
-	 *		   below it that does contain the most significant value in column i. If the most
-	 *         significant value of the column is zero, then an inverse to that matrix does not exist.
-	 *		   The most significant value of the column is the absolute maximum.
-	 *    
-	 *	    5. Divide every element of row i by the pivot.    
-	 *    
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
-	 *		   a multiple of row i so that each new element in column i below row i is zero.    
-	 *    
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
-	 *		   for every element below and above the main diagonal.    
-	 *    
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
-	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pOutT1 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pOutT1++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.    
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.    
-       * If there is no non zero element to replace in the rows below,    
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points    
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points    
-       * to the pivot element of the particular row  */
-      pOutT1 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Grab the most significant value from column l */
-      maxC = 0;
-      for (i = l; i < numRows; i++)
-      {
-        maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
-        pInT1 += numCols;
-      }
-
-      /* Update the status if the matrix is singular */
-      if(maxC == 0.0f)
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Restore pInT1  */
-      pInT1 = pIn;
-
-      /* Destination pointer modifier */
-      k = 1u;
-      
-      /* Check if the pivot element is the most significant of the column */
-      if( (in > 0.0f ? in : -in) != maxC)
-      {
-        /* Loop over the number rows present below */
-        i = numRows - (l + 1u);
-
-        while(i > 0u)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pOutT2 = pOutT1 + (numCols * k);
-
-          /* Look for the most significant element to    
-           * replace in the rows below */
-          if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
-          {
-            /* Loop over number of columns    
-             * to the right of the pilot element */
-            j = numCols - l;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Loop over number of columns of the destination matrix */
-            j = numCols;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the destination matrix */
-              Xchg = *pOutT2;
-              *pOutT2++ = *pOutT1;
-              *pOutT1++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-
-          /* Decrement the loop counter */
-          i--;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pInT2 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *pPivotRowIn;
-
-      /* Loop over number of columns    
-       * to the right of the pilot element */
-      j = (numCols - l);
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the input matrix    
-         * by the pivot element */
-        in1 = *pInT1;
-        *pInT1++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Loop over number of columns of the destination matrix */
-      j = numCols;
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the destination matrix    
-         * by the pivot element */
-        in1 = *pInT2;
-        *pInT2++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i    
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pInT2 = pOut;
-
-      /* index used to check for pivot element */
-      i = 0u;
-
-      /* Loop over number of rows */
-      /*  to be replaced by the sum of that row and a multiple of row i */
-      k = numRows;
-
-      while(k > 0u)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,    
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-
-          pInT2 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,    
-             to replace the elements in the input matrix */
-          j = (numCols - l);
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT1;
-            *pInT1++ = in1 - (in * *pPRT_in++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-          /* Loop over the number of columns to    
-             replace the elements in the destination matrix */
-          j = numCols;
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT2;
-            *pInT2++ = in1 - (in * *pPRT_pDst++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-        }
-
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-
-        /* Decrement the loop counter */
-        k--;
-
-        /* Increment the pivot index */
-        i++;
-      }
-
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float64_t Xchg, in = 0.0f;                     /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------       
-	 * Matrix Inverse can be solved using elementary row operations.        
-	 *        
-	 *	Gauss-Jordan Method:       
-	 *	 	       
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
-	 *        augmented matrix as follows:        
-	 *				        _  _	      _	    _	   _   _         _	       _       
-	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
-	 *					   |  |            | | |        |   |   =   |           |        
-	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
-	 *					          
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *       
-	 *		3. Begin with the first row. Let i = 1.       
-	 *       
-	 *	    4. Check to see if the pivot for row i is zero.       
-	 *		   The pivot is the element of the main diagonal that is on the current row.       
-	 *		   For instance, if working with row i, then the pivot element is aii.       
-	 *		   If the pivot is zero, exchange that row with a row below it that does not        
-	 *		   contain a zero in column i. If this is not possible, then an inverse        
-	 *		   to that matrix does not exist.       
-	 *	       
-	 *	    5. Divide every element of row i by the pivot.       
-	 *	       
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
-	 *		   a multiple of row i so that each new element in column i below row i is zero.       
-	 *	       
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
-	 *		   for every element below and above the main diagonal.        
-	 *		   		          
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
-	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pOutT1 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pOutT1++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pOutT1++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.     
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.   
-       * If there is no non zero element to replace in the rows below,   
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points     
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points     
-       * to the pivot element of the particular row  */
-      pOutT1 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Destination pointer modifier */
-      k = 1u;
-
-      /* Check if the pivot element is zero */
-      if(*pInT1 == 0.0f)
-      {
-        /* Loop over the number rows present below */
-        for (i = (l + 1u); i < numRows; i++)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pOutT2 = pOutT1 + (numCols * k);
-
-          /* Check if there is a non zero pivot element to     
-           * replace in the rows below */
-          if(*pInT2 != 0.0f)
-          {
-            /* Loop over number of columns     
-             * to the right of the pilot element */
-            for (j = 0u; j < (numCols - l); j++)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-            }
-
-            for (j = 0u; j < numCols; j++)
-            {
-              Xchg = *pOutT2;
-              *pOutT2++ = *pOutT1;
-              *pOutT1++ = Xchg;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        return ARM_MATH_SINGULAR;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pOutT1 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *(pIn + (l * numCols));
-
-      /* Loop over number of columns     
-       * to the right of the pilot element */
-      for (j = 0u; j < (numCols - l); j++)
-      {
-        /* Divide each element of the row of the input matrix     
-         * by the pivot element */
-        *pInT1 = *pInT1 / in;
-        pInT1++;
-      }
-      for (j = 0u; j < numCols; j++)
-      {
-        /* Divide each element of the row of the destination matrix     
-         * by the pivot element */
-        *pOutT1 = *pOutT1 / in;
-        pOutT1++;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i     
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pOutT1 = pOut;
-
-      for (i = 0u; i < numRows; i++)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,     
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-          pOutT1 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,     
-             to replace the elements in the input matrix */
-          for (j = 0u; j < (numCols - l); j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pInT1 = *pInT1 - (in * *pPRT_in++);
-            pInT1++;
-          }
-          /* Loop over the number of columns to     
-             replace the elements in the destination matrix */
-          for (j = 0u; j < numCols; j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
-            pOutT1++;
-          }
-
-        }
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-      }
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-    if((flag != 1u) && (in == 0.0f))
-    {
-      pIn = pSrc->pData;
-      for (i = 0; i < numRows * numCols; i++)
-      {
-        if (pIn[i] != 0.0f)
-            break;
-      }
-      
-      if (i == numRows * numCols)
-        status = ARM_MATH_SINGULAR;
-    }
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixInv group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
deleted file mode 100644
index 55349de7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_f32.c    
-*    
-* Description:  Floating-point matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixMult Matrix Multiplication    
- *    
- * Multiplies two matrices.    
- *    
- * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"    
-    
- * Matrix multiplication is only defined if the number of columns of the    
- * first matrix equals the number of rows of the second matrix.    
- * Multiplying an M x N matrix with an N x P matrix results    
- * in an M x P matrix.    
- * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of    
- * pSrcA and pSrcB are equal; and (2) that the size of the output    
- * matrix equals the outer dimensions of pSrcA and pSrcB.    
- */
-
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Floating-point matrix multiplication.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
-  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *px;                                 /* Temporary output data matrix pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t in1, in2, in3, in4;
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0.0f;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2u;
-
-        /* matrix multiplication        */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          in3 = *pIn2;
-          pIn2 += numColsB;
-          in1 = pIn1[0];
-          in2 = pIn1[1];
-          sum += in1 * in3;
-          in4 = *pIn2;
-          pIn2 += numColsB;
-          sum += in2 * in4;
-
-          in3 = *pIn2;
-          pIn2 += numColsB;
-          in1 = pIn1[2];
-          in2 = pIn1[3];
-          sum += in1 * in3;
-          in4 = *pIn2;
-          pIn2 += numColsB;
-          sum += in2 * in4;
-          pIn1 += 4u;
-
-          /* Decrement the loop count */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pIn1++ * (*pIn2);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Store the result in the destination buffer */
-        *px++ = sum;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set     
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0.0f;
-
-        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pIn1++ * (*pIn2);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Store the result in the destination buffer */
-        *px++ = sum;
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
deleted file mode 100644
index 11139b8a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_fast_q15.c    
-*    
-* Description:	 Q15 matrix multiplication (fast variant)    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-
-/**    
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @param[in]		*pState points to the array for storing intermediate results    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The difference between the function arm_mat_mult_q15() and this fast variant is that    
- * the fast variant use a 32-bit rather than a 64-bit accumulator.    
- * The result of each 1.15 x 1.15 multiplication is truncated to        
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30        
- * format. Finally, the accumulator is saturated and converted to a 1.15 result.        
- *        
- * \par        
- * The fast version has the same overflow behavior as the standard version but provides        
- * less precision since it discards the low 16 bits of each multiplication result.        
- * In order to avoid overflows completely the input signals must be scaled down.        
- * Scale down one of the input matrices by log2(numColsA) bits to        
- * avoid overflows, as a total of numColsA additions are computed internally for each        
- * output element.        
- *        
- * \par    
- * See arm_mat_mult_q15() for a slower implementation of this function    
- * which uses 64-bit accumulation to provide higher precision.    
- */
-
-arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState)
-{
-  q31_t sum;                                     /* accumulator */
-  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* Temporary variable to hold the input value */
-  q31_t inA1, inA2, inB1, inB2;
-
-#else
-
-  q15_t in;                                      /* Temporary variable to hold the input value */
-  q15_t inA1, inA2, inB1, inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Matrix transpose */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = numColsB >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pSrcBT + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-#else
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-        
-		/* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pInB++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Reset the variables for the usage in the following multiplication process */
-    row = numRowsA;
-    i = 0u;
-    px = pDst->pData;
-
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set        
-       ** to the starting address of the transposed pSrcB data */
-      pInB = pSrcBT;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 2 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pInA = pSrcA->pData + i;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-          inA1 = *__SIMD32(pInA)++;
-          inB1 = *__SIMD32(pInB)++;
-          inA2 = *__SIMD32(pInA)++;
-          inB2 = *__SIMD32(pInB)++;
-
-          sum = __SMLAD(inA1, inB1, sum);
-          sum = __SMLAD(inA2, inB2, sum);
-
-#else
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          inA2 = *pInA++;
-          sum += inA1 * inB1;
-          inB2 = *pInB++;
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          sum += inA2 * inB2;
-          inA2 = *pInA++;
-          inB2 = *pInB++;
-
-          sum += inA1 * inB1;
-          sum += inA2 * inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* process odd column samples */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += (q31_t) (*pInA++) * (*pInB++);
-
-          colCnt--;
-        }
-
-        /* Saturate and store the result in the destination buffer */
-        *px = (q15_t) (sum >> 15);
-        px++;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      i = i + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixMult group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
deleted file mode 100644
index dbc31410..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_fast_q31.c    
-*    
-* Description:	 Q31 matrix multiplication (fast variant).    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The difference between the function arm_mat_mult_q31() and this fast variant is that    
- * the fast variant use a 32-bit rather than a 64-bit accumulator.    
- * The result of each 1.31 x 1.31 multiplication is truncated to    
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30    
- * format. Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides    
- * less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * Scale down one of the input matrices by log2(numColsA) bits to    
- * avoid overflows, as a total of numColsA additions are computed internally for each    
- * output element.    
- *    
- * \par    
- * See arm_mat_mult_q31() for a slower implementation of this function    
- * which uses 64-bit accumulation to provide higher precision.    
- */
-
-arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */    
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-  q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          inB1 = *pIn2;
-          pIn2 += numColsB;
-
-          inA1 = pIn1[0];
-          inA2 = pIn1[1];
-
-          inB2 = *pIn2;
-          pIn2 += numColsB;
-
-          inB3 = *pIn2;
-          pIn2 += numColsB;
-
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
-
-          inA3 = pIn1[2];
-          inA4 = pIn1[3];
-
-          inB4 = *pIn2;
-          pIn2 += numColsB;
-
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
-
-          pIn1 += 4u;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
-        *px++ = sum << 1;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
deleted file mode 100644
index 9e8d26dd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_q15.c    
-*    
-* Description:	 Q15 matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-
-/**    
- * @brief Q15 matrix multiplication    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @param[in]		*pState points to the array for storing intermediate results (Unused)  
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator. The inputs to the    
- * multiplications are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate    
- * results are accumulated in a 64-bit accumulator in 34.30 format. This approach    
- * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then    
- * truncated to 34.15 format by discarding the low 15 bits and then saturated to    
- * 1.15 format.    
- *    
- * \par    
- * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.    
- *    
- */
-
-arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState CMSIS_UNUSED)
-{
-  q63_t sum;                                     /* accumulator */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* Temporary variable to hold the input value */
-  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
-
-#else
-
-  q15_t in;                                      /* Temporary variable to hold the input value */
-  q15_t inA1, inB1, inA2, inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Matrix transpose */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = numColsB >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pSrcBT + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-#else
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-       /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pInB++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Reset the variables for the usage in the following multiplication process */
-    row = numRowsA;
-    i = 0u;
-    px = pDst->pData;
-
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set        
-       ** to the starting address of the transposed pSrcB data */
-      pInB = pSrcBT;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 2 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pInA = pSrcA->pData + i;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          pSourceA1 = *__SIMD32(pInA)++;
-          pSourceB1 = *__SIMD32(pInB)++;
-
-          pSourceA2 = *__SIMD32(pInA)++;
-          pSourceB2 = *__SIMD32(pInB)++;
-
-          /* Multiply and Accumlates */
-          sum = __SMLALD(pSourceA1, pSourceB1, sum);
-          sum = __SMLALD(pSourceA2, pSourceB2, sum);
-
-#else
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          inA2 = *pInA++;
-          /* Multiply and Accumlates */
-          sum += inA1 * inB1;
-          inB2 = *pInB++;
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          /* Multiply and Accumlates */
-          sum += inA2 * inB2;
-          inA2 = *pInA++;
-          inB2 = *pInB++;
-
-          /* Multiply and Accumlates */
-          sum += inA1 * inB1;
-          sum += inA2 * inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* process remaining column samples */
-        colCnt = numColsA & 3u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pInA++ * *pInB++;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Saturate and store the result in the destination buffer */
-        *px = (q15_t) (__SSAT((sum >> 15), 16));
-        px++;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      i = i + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set          
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q31_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
-        /* Saturate and store the result in the destination buffer */
-        *px++ = (q15_t) __SSAT((sum >> 15), 16);
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-      /* Update the pointer pSrcA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixMult group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
deleted file mode 100644
index 6c97eef1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_q31.c    
-*    
-* Description:	 Q31 matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Q31 matrix multiplication    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate    
- * multiplication results but provides only a single guard bit. There is no saturation    
- * on intermediate additions. Thus, if the accumulator overflows it wraps around and    
- * distorts the result. The input signals should be scaled down to avoid intermediate    
- * overflows. The input is thus scaled down by log2(numColsA) bits    
- * to avoid overflows, as a total of numColsA additions are performed internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- *    
- */
-
-arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-  q31_t a0, a1, a2, a3, b0, b1, b2, b3;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          b0 = *pIn2;
-          pIn2 += numColsB;
-
-          a0 = *pIn1++;
-          a1 = *pIn1++;
-
-          b1 = *pIn2;
-          pIn2 += numColsB;
-          b2 = *pIn2;
-          pIn2 += numColsB;
-
-          sum += (q63_t) a0 *b0;
-          sum += (q63_t) a1 *b1;
-
-          a2 = *pIn1++;
-          a3 = *pIn1++;
-
-          b3 = *pIn2;
-          pIn2 += numColsB;
-
-          sum += (q63_t) a2 *b2;
-          sum += (q63_t) a3 *b3;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
-        *px++ = (q31_t) (sum >> 31);
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = (pSrcB->pData) + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set          
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
-        *px++ = (q31_t) clip_q63_to_q31(sum >> 31);
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-#endif
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
deleted file mode 100644
index b7be4cea..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_scale_f32.c    
-*    
-* Description:	Multiplies a floating-point matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixScale Matrix Scale        
- *        
- * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the        
- * matrix by the scalar.  For example:        
- * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"        
- *        
- * The function checks to make sure that the input and output matrices are of the same size.        
- *        
- * In the fixed-point Q15 and Q31 functions, scale is represented by        
- * a fractional multiplication scaleFract and an arithmetic shift shift.        
- * The shift allows the gain of the scaling operation to exceed 1.0.        
- * The overall scale factor applied to the fixed-point data is        
- * 
        
- *     scale = scaleFract * 2^shift.        
- * 
        
- */
-
-/**        
- * @addtogroup MatrixScale        
- * @{        
- */
-
-/**        
- * @brief Floating-point matrix scaling.        
- * @param[in]       *pSrc points to input matrix structure        
- * @param[in]       scale scale factor to be applied         
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either ARM_MATH_SIZE_MISMATCH         
- * or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- */
-
-arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix scaling     */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  float32_t in1, in2, in3, in4;                  /* temporary variables */
-  float32_t out1, out2, out3, out4;              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * scale */
-      /* Scaling and results are stored in the destination buffer. */
-      in1 = pIn[0];
-      in2 = pIn[1];
-      in3 = pIn[2];
-      in4 = pIn[3];
-
-      out1 = in1 * scale;
-      out2 = in2 * scale;
-      out3 = in3 * scale;
-      out4 = in4 * scale;
-
-
-      pOut[0] = out1;
-      pOut[1] = out2;
-      pOut[2] = out3;
-      pOut[3] = out4;
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * scale */
-      /* The results are stored in the destination buffer. */
-      *pOut++ = (*pIn++) * scale;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
deleted file mode 100644
index 4e67cf92..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_scale_q15.c    
-*    
-* Description:	Multiplies a Q15 matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixScale    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix scaling.    
- * @param[in]       *pSrc points to input matrix    
- * @param[in]       scaleFract fractional portion of the scale factor    
- * @param[in]       shift number of bits to shift the result by    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The input data *pSrc and scaleFract are in 1.15 format.    
- * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    
- */
-
-arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix scaling     */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  q15_t in1, in2, in3, in4;
-  q31_t out1, out2, out3, out4;
-  q31_t inA1, inA2;
-
-#endif //     #ifndef ARM_MATH_CM0_FAMILY
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif //    #ifdef ARM_MATH_MATRIX_CHECK
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      /* Reading 2 inputs from memory */
-      inA1 = _SIMD32_OFFSET(pIn);
-      inA2 = _SIMD32_OFFSET(pIn + 2);
-
-      /* C = A * scale */
-      /* Scale the inputs and then store the 2 results in the destination buffer        
-       * in single cycle by packing the outputs */
-      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
-      out2 = (q31_t) ((q15_t) inA1 * scaleFract);
-      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
-      out4 = (q31_t) ((q15_t) inA2 * scaleFract);
-
-      out1 = out1 >> totShift;
-      inA1 = _SIMD32_OFFSET(pIn + 4);
-      out2 = out2 >> totShift;
-      inA2 = _SIMD32_OFFSET(pIn + 6);
-      out3 = out3 >> totShift;
-      out4 = out4 >> totShift;
-
-      in1 = (q15_t) (__SSAT(out1, 16));
-      in2 = (q15_t) (__SSAT(out2, 16));
-      in3 = (q15_t) (__SSAT(out3, 16));
-      in4 = (q15_t) (__SSAT(out4, 16));
-
-      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
-      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      *pOut++ =
-        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
deleted file mode 100644
index 845f3061..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_scale_q31.c    
-*    
-* Description:	Multiplies a Q31 matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  ------------------------------------------------ */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @addtogroup MatrixScale        
- * @{        
- */
-
-/**        
- * @brief Q31 matrix scaling.        
- * @param[in]       *pSrc points to input matrix        
- * @param[in]       scaleFract fractional portion of the scale factor        
- * @param[in]       shift number of bits to shift the result by        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- * \par        
- * The input data *pSrc and scaleFract are in 1.31 format.        
- * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.        
- */
-
-arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  int32_t totShift = shift + 1;                  /* shift to apply after scaling */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix scaling      */
-  q31_t in1, in2, out1;                          /* temporary variabels */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  q31_t in3, in4, out2, out3, out4;              /* temporary variables */
-
-#endif //      #ifndef ARM_MAT_CM0
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch  */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif //    #ifdef ARM_MATH_MATRIX_CHECK
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Read values from input */
-      in1 = *pIn;
-      in2 = *(pIn + 1);
-      in3 = *(pIn + 2);
-      in4 = *(pIn + 3);
-
-      /* multiply input with scaler value */
-      in1 = ((q63_t) in1 * scaleFract) >> 32;
-      in2 = ((q63_t) in2 * scaleFract) >> 32;
-      in3 = ((q63_t) in3 * scaleFract) >> 32;
-      in4 = ((q63_t) in4 * scaleFract) >> 32;
-
-      /* apply shifting */
-      out1 = in1 << totShift;
-      out2 = in2 << totShift;
-
-      /* saturate the results. */
-      if(in1 != (out1 >> totShift))
-        out1 = 0x7FFFFFFF ^ (in1 >> 31);
-
-      if(in2 != (out2 >> totShift))
-        out2 = 0x7FFFFFFF ^ (in2 >> 31);
-
-      out3 = in3 << totShift;
-      out4 = in4 << totShift;
-
-      *pOut = out1;
-      *(pOut + 1) = out2;
-
-      if(in3 != (out3 >> totShift))
-        out3 = 0x7FFFFFFF ^ (in3 >> 31);
-
-      if(in4 != (out4 >> totShift))
-        out4 = 0x7FFFFFFF ^ (in4 >> 31);
-
-
-      *(pOut + 2) = out3;
-      *(pOut + 3) = out4;
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      in1 = *pIn++;
-
-      in2 = ((q63_t) in1 * scaleFract) >> 32;
-
-      out1 = in2 << totShift;
-
-      if(in2 != (out1 >> totShift))
-        out1 = 0x7FFFFFFF ^ (in2 >> 31);
-
-      *pOut++ = out1;
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
deleted file mode 100644
index 5451a3a5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_f32.c    
-*    
-* Description:	Floating-point matrix subtraction.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixSub Matrix Subtraction        
- *        
- * Subtract two matrices.        
- * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"        
- *        
- * The functions check to make sure that        
- * pSrcA, pSrcB, and pDst have the same        
- * number of rows and columns.        
- */
-
-/**        
- * @addtogroup MatrixSub        
- * @{        
- */
-
-/**        
- * @brief Floating-point matrix subtraction        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- */
-
-arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix subtraction */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* out = sourceA - sourceB */
-      out1 = inA1 - inB1;
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* out = sourceA - sourceB */
-      out2 = inA2 - inB2;
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* out = sourceA - sourceB */
-      out1 = inA1 - inB1;
-
-
-      /* out = sourceA - sourceB */
-      out2 = inA2 - inB2;
-
-      /* Store result in destination */
-      pOut[2] = out1;
-
-      /* Store result in destination */
-      pOut[3] = out2;
-
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (*pIn1++) - (*pIn2++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixSub group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
deleted file mode 100644
index cc5a7b9a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_q15.c    
-*    
-* Description:	Q15 Matrix subtraction    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixSub    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix subtraction.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix subtraction  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Apply loop unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, Saturate and then store the results in the destination buffer. */
-      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixSub group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
deleted file mode 100644
index d5ac2064..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_q31.c    
-*    
-* Description:	Q31 matrix subtraction    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @addtogroup MatrixSub        
- * @{        
- */
-
-/**        
- * @brief Q31 matrix subtraction.        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function uses saturating arithmetic.        
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        
- */
-
-
-arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t inA1, inB1;                              /* temporary variables */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  q31_t inA2, inB2;                              /* temporary variables */
-  q31_t out1, out2;                              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix subtraction */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition  */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, saturate and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* Subtract and saturate */
-      out1 = __QSUB(inA1, inB1);
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* Subtract and saturate */
-      out2 = __QSUB(inA2, inB2);
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* Subtract and saturate */
-      out1 = __QSUB(inA1, inB1);
-
-      /* Subtract and saturate */
-      out2 = __QSUB(inA2, inB2);
-
-      /* Store result in destination */
-      pOut[2] = out1;
-      pOut[3] = out2;
-
-      /* update pointers to process next samples */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, saturate and then store the results in the destination buffer. */
-      inA1 = *pIn1++;
-      inB1 = *pIn2++;
-
-      inA1 = __QSUB(inA1, inB1);
-
-      *pOut++ = inA1;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixSub group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
deleted file mode 100644
index f5cd4565..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_f32.c    
-*    
-* Description:	Floating-point matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-/**    
- * @defgroup MatrixTrans Matrix Transpose    
- *    
- * Tranposes a matrix.    
- * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.    
- * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"    
- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/**    
-  * @brief Floating-point matrix transpose.    
-  * @param[in]  *pSrc points to the input matrix    
-  * @param[out] *pDst points to the output matrix    
-  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
-  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
-  */
-
-
-arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *px;                                 /* Temporary output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of rows */
-  uint16_t nColumns = pSrc->numCols;             /* number of columns */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
-  arm_status status;                             /* status of matrix transpose  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* Loop Unrolling */
-      blkCnt = nColumns >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(blkCnt > 0u)        /* column loop */
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      blkCnt = nColumns % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  uint16_t col, i = 0u, row = nRows;             /* loop counters */
-  arm_status status;                             /* status of matrix transpose  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);          /* row loop end  */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
deleted file mode 100644
index c4656bbd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_q15.c    
-*    
-* Description:	Q15 matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/*    
- * @brief Q15 matrix transpose.    
- * @param[in]  *pSrc points to the input matrix    
- * @param[out] *pDst points to the output matrix    
- * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
- * or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of nRows */
-  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
-  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* variable to hold temporary output  */
-
-#else
-
-  q15_t in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = nColumns >> 2u;
-
-      /* The pointer pOut is set to starting address of the column being processed */
-      pOut = pDst->pData + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pSrcA)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) in;
-
-#else
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *pOut = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read two elements from the row */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        in = *__SIMD32(pSrcA)++;
-
-#else
-
-        in = *__SIMD32(pSrcA)++;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) in;
-
-#else
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *pOut = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-#else	 
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      col = nColumns % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer pOut is set to starting address of the column being processed */
-      pOut = pDst->pData + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *pOut = *pSrcA++;
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
deleted file mode 100644
index 459700a0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_q31.c    
-*    
-* Description:	Q31 matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/*    
-  * @brief Q31 matrix transpose.    
-  * @param[in]  *pSrc points to the input matrix    
-  * @param[out] *pDst points to the output matrix    
-  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
-  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of nRows */
-  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      blkCnt = nColumns >> 2u;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      blkCnt = nColumns % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  uint16_t col, i = 0u, row = nRows;             /* loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    }
-    while(row > 0u);            /* row loop end */
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
deleted file mode 100644
index 6a1ad396..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_f32.c    
-*    
-* Description:	Maximum value of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup Max Maximum    
- *    
- * Computes the maximum value of an array of data.     
- * The function returns both the maximum value and its position within the array.     
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and it's index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
deleted file mode 100644
index 9a59726e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q15.c    
-*    
-* Description:	Maximum value of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
deleted file mode 100644
index 8a95cf19..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q31.c    
-*    
-* Description:	Maximum value of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
deleted file mode 100644
index 07150d62..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q7.c    
-*    
-* Description:	Maximum value of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
-  * @return none.    
- */
-
-void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
deleted file mode 100644
index 3e699d3c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_f32.c    
-*    
-* Description:	Mean value of a floating-point vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup mean Mean    
- *    
- * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    
- * 
    
- *    
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-
-/**    
- * @brief Mean value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- */
-
-
-void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    sum += in1;
-    sum += in2;
-    sum += in3;
-    sum += in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = sum / (float32_t) blockSize;
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
deleted file mode 100644
index 22ea8dc5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q15.c    
-*    
-* Description:	Mean value of a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * The input is represented in 1.15 format and is accumulated in a 32-bit     
- * accumulator in 17.15 format.     
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.    
- *    
- */
-
-
-void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q15_t) (sum / (q31_t)blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
deleted file mode 100644
index 9f80d842..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q31.c    
-*    
-* Description:	Mean value of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *\par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.31 format and is accumulated in a 64-bit    
- * accumulator in 33.31 format.    
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is truncated to yield a result of 1.31 format.    
- *    
- */
-
-
-void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    sum += in1;
-    sum += in2;
-    sum += in3;
-    sum += in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q31_t) (sum / (int32_t) blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
deleted file mode 100644
index 31a35167..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q7.c    
-*    
-* Description:	Mean value of a Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.     
- * The input is represented in 1.7 format and is accumulated in a 32-bit    
- * accumulator in 25.7 format.    
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is truncated to yield a result of 1.7 format.    
- *    
- */
-
-
-void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in = *__SIMD32(pSrc)++;
-
-    sum += ((in << 24) >> 24);
-    sum += ((in << 16) >> 24);
-    sum += ((in << 8) >> 24);
-    sum += (in >> 24);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q7_t) (sum / (int32_t) blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
deleted file mode 100644
index 7b6504c1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_f32.c    
-*    
-* Description:	Minimum value of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup Min Minimum    
- *    
- * Computes the minimum value of an array of data.     
- * The function returns both the minimum value and its position within the array.     
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
-  * @return none.    
- *    
- */
-
-void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t minVal1, out;                        /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and it's index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
deleted file mode 100644
index 88401b7c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q15.c    
-*    
-* Description:	Minimum value of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t minVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
deleted file mode 100644
index 01746b62..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q31.c    
-*    
-* Description:	Minimum value of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q31_t minVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
deleted file mode 100644
index 587afac1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q7.c    
-*    
-* Description:	Minimum value of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t minVal1, out;                             /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-
-
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
deleted file mode 100644
index 564d84ea..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_f32.c    
-*    
-* Description:	Sum of the squares of the elements of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup power Power    
- *    
- * Calculates the sum of the squares of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-
-/**    
- * @brief Sum of the squares of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* accumulator */
-  float32_t in;                                  /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* compute power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the result to the destination */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
deleted file mode 100644
index 02c41093..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q15.c    
-*    
-* Description:	Sum of the squares of the elements of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.     
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 34.30 format.     
- *    
- */
-
-void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in32;                                    /* Temporary variable to store input value */
-  q15_t in16;                                    /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in32 = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in32, in32, sum);
-    in32 = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in32, in32, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in16 = *pSrc++;
-    sum = __SMLALD(in16, in16, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t in;                                      /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q31_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Store the results in 34.30 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
deleted file mode 100644
index 75c63141..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q31.c    
-*    
-* Description:	Sum of the squares of the elements of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.31 format.    
- * Intermediate multiplication yields a 2.62 format, and this    
- * result is truncated to 2.48 format by discarding the lower 14 bits.    
- * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
- * With 15 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 16.48 format.     
- *    
- */
-
-void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-  q31_t in;
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the results in 16.48 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
deleted file mode 100644
index 4f381566..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q7.c    
-*    
-* Description:	Sum of the squares of the elements of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.     
- * The input is represented in 1.7 format.   
- * Intermediate multiplication yields a 2.14 format, and this    
- * result is added without saturation to an accumulator in 18.14 format.    
- * With 17 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 18.14 format.     
- *    
- */
-
-void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  q7_t in;                                       /* Temporary variable to store input */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t input1;                                  /* Temporary variable to store packed input */
-  q31_t in1, in2;                                /* Temporary variables to store input */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Reading two inputs of pSrc vector and packing */
-    input1 = *__SIMD32(pSrc)++;
-
-    in1 = __SXTB16(__ROR(input1, 8));
-    in2 = __SXTB16(input1);
-
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* calculate power and accumulate to accumulator */
-    sum = __SMLAD(in1, in1, sum);
-    sum = __SMLAD(in2, in2, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q15_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the result in 18.14 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
deleted file mode 100644
index 5f935379..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_f32.c    
-*    
-* Description:	Root mean square value of an array of F32 type    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup RMS Root mean square (RMS)    
- *    
- *     
- * Calculates the Root Mean Sqaure of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    
- * 
    
- *   
- * There are separate functions for floating point, Q31, and Q15 data types.     
- */
-
-/**    
- * @addtogroup RMS    
- * @{    
- */
-
-
-/**    
- * @brief Root Mean Square of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult rms value returned here    
- * @return none.    
- *    
- */
-
-void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Accumulator */
-  float32_t in;                                  /* Tempoprary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Rms and store the result in the destination */
-  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
-}
-
-/**    
- * @} end of RMS group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
deleted file mode 100644
index 3f335a23..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_q15.c    
-*    
-* Description:	Root Mean Square of the elements of a Q15 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup RMS    
- * @{    
- */
-
-/**    
- * @brief Root Mean Square of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult rms value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.    
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- *    
- */
-
-void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q63_t sum = 0;                                 /* accumulator */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* temporary variable to store the input value */
-  q15_t in1;                                     /* temporary variable to store the input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in, in, sum);
-    in = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in, in, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in1 = *pSrc++;
-    sum = __SMLALD(in1, in1, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Truncating and saturating the accumulator to 1.15 format */
-  /* Store the result in the destination */
-  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t in;                                      /* temporary variable to store the input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *pSrc++;
-    sum += ((q31_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Truncating and saturating the accumulator to 1.15 format */
-  /* Store the result in the destination */
-  arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of RMS group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
deleted file mode 100644
index eaca28d7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_q31.c    
-*    
-* Description:	Root Mean Square of the elements of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @addtogroup RMS        
- * @{        
- */
-
-
-/**        
- * @brief Root Mean Square of the elements of a Q31 vector.        
- * @param[in]       *pSrc points to the input vector        
- * @param[in]       blockSize length of the input vector        
- * @param[out]      *pResult rms value returned here        
- * @return none.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- *        
- *\par        
- * The function is implemented using an internal 64-bit accumulator.        
- * The input is represented in 1.31 format, and intermediate multiplication        
- * yields a 2.62 format.        
- * The accumulator maintains full precision of the intermediate multiplication results,         
- * but provides only a single guard bit.        
- * There is no saturation on intermediate additions.        
- * If the accumulator overflows, it wraps around and distorts the result.         
- * In order to avoid overflows completely, the input signal must be scaled down by         
- * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
- * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
- *        
- */
-
-void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* accumulator */
-  q31_t in;                                      /* Temporary variable to store the input */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 7 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the result in a temporary variable, sum */
-    /* read two samples from source buffer */
-    in1 = pSrc[0];
-    in2 = pSrc[1];
-
-    /* calculate power and accumulate to accumulator */
-    sum += (q63_t) in1 *in1;
-    sum += (q63_t) in2 *in2;
-
-    /* read two samples from source buffer */
-    in3 = pSrc[2];
-    in4 = pSrc[3];
-
-    /* calculate power and accumulate to accumulator */
-    sum += (q63_t) in3 *in3;
-    sum += (q63_t) in4 *in4;
-
-
-    /* update source buffer to process next samples */
-    pSrc += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *pSrc++;
-    sum += (q63_t) in *in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
-  /* Compute Rms and store the result in the destination vector */
-  arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
-}
-
-/**        
- * @} end of RMS group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
deleted file mode 100644
index c73c707f..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_f32.c    
-*    
-* Description:	Standard deviation of the elements of a floating-point vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup STD Standard deviation    
- *    
- * Calculates the standard deviation of the elements in the input vector.     
- * The underlying algorithm is used:    
- *   
- * 
    
- * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))   
- *   
- *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
- *   
- *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
- * 
   
- *    
- * There are separate functions for floating point, Q31, and Q15 data types.    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-
-/**    
- * @brief Standard deviation of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
-  float32_t in;                                  /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-   
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t meanOfSquares, mean, squareOfMean;
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
-
-  /* Compute mean of all input values */
-  mean = sum / (float32_t) blockSize;
-
-  /* Compute square of mean */
-  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
-                                  ((float32_t) blockSize - 1.0f));
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t squareOfSum;                         /* Square of Sum */
-  float32_t var;                                 /* Temporary varaince storage */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += in * in;
-
-    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
-    /* Compute Sum of the input samples     
-     * and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute the square of sum */
-  squareOfSum = ((sum * sum) / (float32_t) blockSize);
-
-  /* Compute the variance */
-  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_f32(var, pResult);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
deleted file mode 100644
index 24054d34..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_q15.c    
-*    
-* Description:	Standard deviation of an array of Q15 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-/**    
- * @brief Standard deviation of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- */
-
-void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q31_t sum = 0;                                 /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  uint32_t blkCnt;                               /* loop counter */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-   
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* input value */
-  q15_t in1;                                     /* input value */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in1 = *pSrc++;
-    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
-    sum += in1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
-
-  /* mean of the squares minus the square of the mean. */
-  /* Compute standard deviation and store the result to the destination */
-  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t in;                                      /* input value */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += (in * in);
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = (q31_t)(sumOfSquares / (q63_t)(blockSize - 1));
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t) ((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
-
-  /* mean of the squares minus the square of the mean. */
-  /* Compute standard deviation and store the result to the destination */
-  arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15, 16u), pResult);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
deleted file mode 100644
index f324273a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_q31.c    
-*    
-* Description:	Standard deviation of an array of Q31 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-
-/**    
- * @brief Standard deviation of the elements of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- *\par    
- * The function is implemented using an internal 64-bit accumulator.        
- * The input is represented in 1.31 format, which is then downshifted by 8 bits
- * which yields 1.23, and intermediate multiplication yields a 2.46 format.        
- * The accumulator maintains full precision of the intermediate multiplication results,         
- * but provides only a 16 guard bits.        
- * There is no saturation on intermediate additions.        
- * If the accumulator overflows it wraps around and distorts the result.        
- * In order to avoid overflows completely the input signal must be scaled down by         
- * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.  
- * After division, internal variables should be Q18.46 
- * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. 
- *    
- */
-
-
-void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* Accumulator */
-  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  q31_t in;                                      /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-   
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++ >> 8;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Compute square of mean */
-  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15, pResult);
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
deleted file mode 100644
index 5f0ea7d7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_f32.c    
-*    
-* Description:	Variance of the elements of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup variance  Variance    
- *    
- * Calculates the variance of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)   
- *   
- *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
- *   
- *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
- * 
   
- *    
- * There are separate functions for floating point, Q31, and Q15 data types.    
- */
-
-/**    
- * @addtogroup variance    
- * @{    
- */
-
-
-/**    
- * @brief Variance of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult variance value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
-  float32_t in;                                  /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-  
-#ifndef ARM_MATH_CM0_FAMILY
-   
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
-
-  /* Compute mean of all input values */
-  mean = sum / (float32_t) blockSize;
-
-  /* Compute square of mean */
-  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
-                                  ((float32_t) blockSize - 1.0f));
-
-  /* Compute variance and then store the result to the destination */
-  *pResult = meanOfSquares - squareOfMean;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t squareOfSum;                         /* Square of Sum */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += in * in;
-
-    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
-    /* Compute Sum of the input samples     
-     * and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute the square of sum */
-  squareOfSum = ((sum * sum) / (float32_t) blockSize);
-
-  /* Compute the variance */
-  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of variance group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
deleted file mode 100644
index 94fcef9a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_q15.c    
-*    
-* Description:	Variance of an array of Q15 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup variance    
- * @{    
- */
-
-/**    
- * @brief Variance of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult variance value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- *    
- */
-
-
-void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-
-  q31_t sum = 0;                                 /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  uint32_t blkCnt;                               /* loop counter */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-   
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* input value */
-  q15_t in1;                                     /* input value */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in1 = *pSrc++;
-    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
-    sum += in1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
-
-  /* mean of the squares minus the square of the mean. */
-  *pResult = (meanOfSquares - squareOfMean) >> 15;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t in;                                      /* input value */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += (in * in);
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1));
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t)((q63_t)sum * sum / (q63_t)(blockSize * (blockSize - 1)));
-
-  /* mean of the squares minus the square of the mean. */
-  *pResult = (meanOfSquares - squareOfMean) >> 15;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of variance group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
deleted file mode 100644
index 6b9e2287..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_q31.c    
-*    
-* Description:	Variance of an array of Q31 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupStats        
- */
-
-/**        
- * @addtogroup variance        
- * @{        
- */
-
-/**        
- * @brief Variance of the elements of a Q31 vector.        
- * @param[in]       *pSrc points to the input vector        
- * @param[in]       blockSize length of the input vector        
- * @param[out]      *pResult variance value returned here        
- * @return none.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- *        
- *\par        
- * The function is implemented using an internal 64-bit accumulator.        
- * The input is represented in 1.31 format, which is then downshifted by 8 bits
- * which yields 1.23, and intermediate multiplication yields a 2.46 format.        
- * The accumulator maintains full precision of the intermediate multiplication results,         
- * but provides only a 16 guard bits.        
- * There is no saturation on intermediate additions.        
- * If the accumulator overflows it wraps around and distorts the result.        
- * In order to avoid overflows completely the input signal must be scaled down by         
- * log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.  
- * After division, internal variables should be Q18.46 
- * Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.        
- *        
- */
-
-
-void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* Accumulator */
-  q63_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  q31_t in;                                      /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-
-	if(blockSize == 1)
-	{
-		*pResult = 0;
-		return;
-	}
-   
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++ >> 8;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++ >> 8;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / (q63_t)(blockSize - 1);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  /* Compute square of mean */
-  squareOfMean = sum * sum / (q63_t)(blockSize * (blockSize - 1u));
-
-
-  /* Compute standard deviation and then store the result to the destination */
-  *pResult = (meanOfSquares - squareOfMean) >> 15;
-
-}
-
-/**        
- * @} end of variance group        
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
deleted file mode 100644
index d6c846b6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_f32.c    
-*    
-* Description:	Copies the elements of a floating-point vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup copy Vector Copy    
- *    
- * Copies sample by sample from source vector to destination vector.    
- *    
- * 
    
- * 	pDst[n] = pSrc[n];   0 <= n < blockSize.    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a floating-point vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-
-void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
deleted file mode 100644
index 5c6a391e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q15.c    
-*    
-* Description:	Copies the elements of a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-/**    
- * @brief Copies the elements of a Q15 vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Read two inputs */
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the value in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
deleted file mode 100644
index 0308cb84..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q31.c    
-*    
-* Description:	Copies the elements of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a Q31 vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the values in the destination buffer */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the value in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
deleted file mode 100644
index e2731440..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q7.c    
-*    
-* Description:	Copies the elements of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a Q7 vector.    
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    /* 4 samples are copied and stored at a time using SIMD */
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
deleted file mode 100644
index c8ea2dcd..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_f32.c    
-*    
-* Description:	Fills a constant value into a floating-point vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup Fill Vector Fill    
- *    
- * Fills the destination vector with a constant value.    
- *    
- * 
    
- * 	pDst[n] = value;   0 <= n < blockSize.    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a floating-point vector.     
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-
-void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1 = value;
-  float32_t in2 = value;
-  float32_t in3 = value;
-  float32_t in4 = value;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
deleted file mode 100644
index 5b306a9b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q15.c    
-*    
-* Description:	Fills a constant value into a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q15 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t packedValue;                             /* value packed to 32 bits */
-
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
-  packedValue = __PKHBT(value, value, 16u);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *__SIMD32(pDst)++ = packedValue;
-    *__SIMD32(pDst)++ = packedValue;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
deleted file mode 100644
index 84068b2e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q31.c    
-*    
-* Description:	Fills a constant value into a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q31 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1 = value;
-  q31_t in2 = value;
-  q31_t in3 = value;
-  q31_t in4 = value;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
deleted file mode 100644
index 88ced505..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q7.c    
-*    
-* Description:	Fills a constant value into a Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q7 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t packedValue;                             /* value packed to 32 bits */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
-  packedValue = __PACKq7(value, value, value, value);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *__SIMD32(pDst)++ = packedValue;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
deleted file mode 100644
index a2c486f4..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q15.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q15 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- * \par   
- * The equation used for the conversion process is:    
- * 
    
- * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    
- * 
    
- * \par Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- * \note   
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- *    
- */
-
-
-void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
deleted file mode 100644
index d64609e7..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q31.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup float_to_x  Convert 32-bit floating point value    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q31 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- *\par Description:    
- * \par   
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    
- * 
    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
- *   
- * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- */
-
-
-void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 32768 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
deleted file mode 100644
index 7ecebdfa..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q7.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q7 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- *\par Description:    
- * \par   
- * The equation used for the conversion process is:    
- * 
    
- * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    
- * 
    
- * \par Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
- * \note   
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- */
-
-
-void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0.0f ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
deleted file mode 100644
index bbaf38c1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_float.c    
-*    
-* Description:	Converts the elements of the Q15 vector to floating-point vector.     
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q15_to_x  Convert 16-bit Integer value    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-
-
-
-/**    
- * @brief  Converts the elements of the Q15 vector to floating-point vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 32768 */
-    /* convert from q15 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 32768 */
-    /* convert from q15 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
deleted file mode 100644
index f046427d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_q31.c    
-*    
-* Description:	Converts the elements of the Q15 vector to Q31 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q15 vector to Q31 vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:   
- *   
- * 
    
- * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2;
-  q31_t out1, out2, out3, out4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t)A << 16 */
-    /* convert from q15 to q31 and then store the results in the destination buffer */
-    in1 = *__SIMD32(pIn)++;
-    in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* extract lower 16 bits to 32 bit result */
-    out1 = in1 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out2 = in1 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out3 = in2 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out4 = in2 & 0xFFFF0000;
-
-#else
-
-    /* extract upper 16 bits to 32 bit result */
-    out1 = in1 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out2 = in1 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out3 = in2 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out4 = in2 << 16u;
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    *pDst++ = out1;
-    *pDst++ = out2;
-    *pDst++ = out3;
-    *pDst++ = out4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t)A << 16 */
-    /* convert from q15 to q31 and then store the results in the destination buffer */
-    *pDst++ = (q31_t) * pIn++ << 16;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
deleted file mode 100644
index 9b91c362..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_q7.c    
-*    
-* Description:	Converts the elements of the Q15 vector to Q7 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-
-/**    
- * @brief Converts the elements of the Q15 vector to Q7 vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    
- * 
   
- *   
- */
-
-
-void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2;
-  q31_t out1, out2;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 8 */
-    /* convert from q15 to q7 and then store the results in the destination buffer */
-    in1 = *__SIMD32(pIn)++;
-    in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __PKHTB(in2, in1, 16);
-    out2 = __PKHBT(in2, in1, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHBT(in1, in2, 16);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* rotate packed value by 24 */
-    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
-
-    /* anding with 0xff00ff00 to get two 8 bit values */
-    out1 = out1 & 0xFF00FF00;
-    /* anding with 0x00ff00ff to get two 8 bit values */
-    out2 = out2 & 0x00FF00FF;
-
-    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
-    out1 = out1 | out2;
-
-    /* store 4 samples at a time to destiantion buffer */
-    *__SIMD32(pDst)++ = out1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 8 */
-    /* convert from q15 to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) (*pIn++ >> 8);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
deleted file mode 100644
index 59494741..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_float.c    
-*    
-* Description:	Converts the elements of the Q31 vector to floating-point vector.      
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q31_to_x  Convert 32-bit Integer value    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to floating-point vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 2147483648 */
-    /* convert from q31 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 2147483648 */
-    /* convert from q31 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
deleted file mode 100644
index 33222bc2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_q15.c    
-*    
-* Description:	Converts the elements of the Q31 vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to Q15 vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *     
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-  q31_t out1, out2;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A >> 16 */
-    /* convert from q31 to q15 and then store the results in the destination buffer */
-    in1 = *pIn++;
-    in2 = *pIn++;
-    in3 = *pIn++;
-    in4 = *pIn++;
-
-    /* pack two higher 16-bit values from two 32-bit values */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __PKHTB(in2, in1, 16);
-    out2 = __PKHTB(in4, in3, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHTB(in3, in4, 16);
-
-#endif //      #ifdef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ = out1;
-    *__SIMD32(pDst)++ = out2;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A >> 16 */
-    /* convert from q31 to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) (*pIn++ >> 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
deleted file mode 100644
index d90898a3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_q7.c    
-*    
-* Description:	Converts the elements of the Q31 vector to Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to Q7 vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     
- * 
    
- *   
- */
-
-
-void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-  q7_t out1, out2, out3, out4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 24 */
-    /* convert from q31 to q7 and then store the results in the destination buffer */
-    in1 = *pIn++;
-    in2 = *pIn++;
-    in3 = *pIn++;
-    in4 = *pIn++;
-
-    out1 = (q7_t) (in1 >> 24);
-    out2 = (q7_t) (in2 >> 24);
-    out3 = (q7_t) (in3 >> 24);
-    out4 = (q7_t) (in4 >> 24);
-
-    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 24 */
-    /* convert from q31 to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) (*pIn++ >> 24);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
deleted file mode 100644
index f984cf00..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_float.c    
-*    
-* Description:	Converts the elements of the Q7 vector to floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q7_to_x  Convert 8-bit Integer value    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q7 vector to floating-point vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *		     
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 128 */
-    /* convert from q7 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 128 */
-    /* convert from q7 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
deleted file mode 100644
index bba084c1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_q15.c    
-*    
-* Description:	Converts the elements of the Q7 vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-
-
-
-/**    
- * @brief Converts the elements of the Q7 vector to Q15 vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-  q31_t in;
-  q31_t in1, in2;
-  q31_t out1, out2;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A << 8 */
-    /* convert from q7 to q15 and then store the results in the destination buffer */
-    in = *__SIMD32(pIn)++;
-
-    /* rotatate in by 8 and extend two q7_t values to q15_t values */
-    in1 = __SXTB16(__ROR(in, 8));
-
-    /* extend remainig two q7_t values to q15_t values */
-    in2 = __SXTB16(in);
-
-    in1 = in1 << 8u;
-    in2 = in2 << 8u;
-
-    in1 = in1 & 0xFF00FF00;
-    in2 = in2 & 0xFF00FF00;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out2 = __PKHTB(in1, in2, 16);
-    out1 = __PKHBT(in2, in1, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHBT(in2, in1, 16);
-
-#endif
-
-    *__SIMD32(pDst)++ = out1;
-    *__SIMD32(pDst)++ = out2;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A << 8 */
-    /* convert from q7 to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) * pIn++ << 8;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
deleted file mode 100644
index 0519d92d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_q31.c    
-*    
-* Description:	Converts the elements of the Q7 vector to Q31 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q7 vector to Q31 vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   
- * 
     
- *   
- */
-
-
-void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  q31_t in;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t) A << 24 */
-    /* convert from q7 to q31 and then store the results in the destination buffer */
-    in = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
-    *pDst++ = (in & 0xFF000000);
-
-#else
-
-    *pDst++ = (in & 0xFF000000);
-    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
-
-#endif //              #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t) A << 24 */
-    /* convert from q7 to q31 and then store the results in the destination buffer */
-    *pDst++ = (q31_t) * pIn++ << 24;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
deleted file mode 100644
index 0404ea84..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_bitreversal.c    
-*    
-* Description:	This file has common tables like Bitreverse, reciprocal etc which are used across different functions    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/*    
-* @brief  In-place bit reversal function.   
-* @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.   
-* @param[in]      fftSize      length of the FFT.   
-* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.   
-* @param[in]      *pBitRevTab  points to the bit reversal table.   
-* @return none.   
-*/
-
-void arm_bitreversal_f32(
-float32_t * pSrc,
-uint16_t fftSize,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab)
-{
-   uint16_t fftLenBy2, fftLenBy2p1;
-   uint16_t i, j;
-   float32_t in;
-
-   /*  Initializations */
-   j = 0u;
-   fftLenBy2 = fftSize >> 1u;
-   fftLenBy2p1 = (fftSize >> 1u) + 1u;
-
-   /* Bit Reversal Implementation */
-   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-   {
-      if(i < j)
-      {
-         /*  pSrc[i] <-> pSrc[j]; */
-         in = pSrc[2u * i];
-         pSrc[2u * i] = pSrc[2u * j];
-         pSrc[2u * j] = in;
-
-         /*  pSrc[i+1u] <-> pSrc[j+1u] */
-         in = pSrc[(2u * i) + 1u];
-         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
-         pSrc[(2u * j) + 1u] = in;
-
-         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
-         in = pSrc[2u * (i + fftLenBy2p1)];
-         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
-         pSrc[2u * (j + fftLenBy2p1)] = in;
-
-         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
-         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
-         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
-         pSrc[(2u * (j + fftLenBy2p1)) + 1u];
-         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
-      }
-
-      /*  pSrc[i+1u] <-> pSrc[j+1u] */
-      in = pSrc[2u * (i + 1u)];
-      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
-      pSrc[2u * (j + fftLenBy2)] = in;
-
-      /*  pSrc[i+2u] <-> pSrc[j+2u] */
-      in = pSrc[(2u * (i + 1u)) + 1u];
-      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
-      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
-      /*  Reading the index for the bit reversal */
-      j = *pBitRevTab;
-
-      /*  Updating the bit reversal index depending on the fft length  */
-      pBitRevTab += bitRevFactor;
-   }
-}
-
-
-
-/*    
-* @brief  In-place bit reversal function.   
-* @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.   
-* @param[in]      fftLen       length of the FFT.   
-* @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
-* @param[in]      *pBitRevTab  points to bit reversal table.   
-* @return none.   
-*/
-
-void arm_bitreversal_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTable)
-{
-   uint32_t fftLenBy2, fftLenBy2p1, i, j;
-   q31_t in;
-
-   /*  Initializations      */
-   j = 0u;
-   fftLenBy2 = fftLen / 2u;
-   fftLenBy2p1 = (fftLen / 2u) + 1u;
-
-   /* Bit Reversal Implementation */
-   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-   {
-      if(i < j)
-      {
-         /*  pSrc[i] <-> pSrc[j]; */
-         in = pSrc[2u * i];
-         pSrc[2u * i] = pSrc[2u * j];
-         pSrc[2u * j] = in;
-
-         /*  pSrc[i+1u] <-> pSrc[j+1u] */
-         in = pSrc[(2u * i) + 1u];
-         pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
-         pSrc[(2u * j) + 1u] = in;
-
-         /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
-         in = pSrc[2u * (i + fftLenBy2p1)];
-         pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
-         pSrc[2u * (j + fftLenBy2p1)] = in;
-
-         /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
-         in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
-         pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
-         pSrc[(2u * (j + fftLenBy2p1)) + 1u];
-         pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
-      }
-
-      /*  pSrc[i+1u] <-> pSrc[j+1u] */
-      in = pSrc[2u * (i + 1u)];
-      pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
-      pSrc[2u * (j + fftLenBy2)] = in;
-
-      /*  pSrc[i+2u] <-> pSrc[j+2u] */
-      in = pSrc[(2u * (i + 1u)) + 1u];
-      pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
-      pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
-      /*  Reading the index for the bit reversal */
-      j = *pBitRevTable;
-
-      /*  Updating the bit reversal index depending on the fft length */
-      pBitRevTable += bitRevFactor;
-   }
-}
-
-
-
-/*    
-   * @brief  In-place bit reversal function.   
-   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.   
-   * @param[in]      fftLen       length of the FFT.   
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
-   * @param[in]      *pBitRevTab  points to bit reversal table.   
-   * @return none.   
-*/
-
-void arm_bitreversal_q15(
-q15_t * pSrc16,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab)
-{
-   q31_t *pSrc = (q31_t *) pSrc16;
-   q31_t in;
-   uint32_t fftLenBy2, fftLenBy2p1;
-   uint32_t i, j;
-
-   /*  Initializations */
-   j = 0u;
-   fftLenBy2 = fftLen / 2u;
-   fftLenBy2p1 = (fftLen / 2u) + 1u;
-
-   /* Bit Reversal Implementation */
-   for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-   {
-      if(i < j)
-      {
-         /*  pSrc[i] <-> pSrc[j]; */
-         /*  pSrc[i+1u] <-> pSrc[j+1u] */
-         in = pSrc[i];
-         pSrc[i] = pSrc[j];
-         pSrc[j] = in;
-
-         /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
-         /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
-         in = pSrc[i + fftLenBy2p1];
-         pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
-         pSrc[j + fftLenBy2p1] = in;
-      }
-
-      /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
-      /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
-      in = pSrc[i + 1u];
-      pSrc[i + 1u] = pSrc[j + fftLenBy2];
-      pSrc[j + fftLenBy2] = in;
-
-      /*  Reading the index for the bit reversal */
-      j = *pBitRevTab;
-
-      /*  Updating the bit reversal index depending on the fft length  */
-      pBitRevTab += bitRevFactor;
-   }
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S
deleted file mode 100644
index 08c5d759..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal2.S
+++ /dev/null
@@ -1,211 +0,0 @@
-;/* ----------------------------------------------------------------------
-;* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-;*
-;* $Date:       19. March 2015 
-;* $Revision: 	V.1.4.5
-;*
-;* Project: 	CMSIS DSP Library
-;* Title:	    arm_bitreversal2.S
-;*
-;* Description:	This is the arm_bitreversal_32 function done in
-;*              assembly for maximum speed.  This function is called
-;*              after doing an fft to reorder the output.  The function
-;*              is loop unrolled by 2. arm_bitreversal_16 as well.
-;*
-;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-;*
-;* Redistribution and use in source and binary forms, with or without
-;* modification, are permitted provided that the following conditions
-;* are met:
-;*   - Redistributions of source code must retain the above copyright
-;*     notice, this list of conditions and the following disclaimer.
-;*   - Redistributions in binary form must reproduce the above copyright
-;*     notice, this list of conditions and the following disclaimer in
-;*     the documentation and/or other materials provided with the
-;*     distribution.
-;*   - Neither the name of ARM LIMITED nor the names of its contributors
-;*     may be used to endorse or promote products derived from this
-;*     software without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-;* POSSIBILITY OF SUCH DAMAGE.
-;* -------------------------------------------------------------------- */
-#if defined(__CC_ARM)       // Keil
-    #define CODESECT AREA     ||.text||, CODE, READONLY, ALIGN=2
-    #define LABEL
-#elif defined(__IASMARM__)  // IAR
-    #define CODESECT SECTION `.text`:CODE
-    #define PROC
-    #define LABEL
-    #define ENDP
-    #define EXPORT PUBLIC
-#elif defined(__CSMC__)		/* Cosmic */
-	#define	CODESECT	switch .text
-	#define THUMB
-	#define EXPORT	xdef
-	#define PROC	:
-	#define LABEL	:
-	#define ENDP
-	#define arm_bitreversal_32 _arm_bitreversal_32
-#elif defined (__GNUC__)    // GCC
-    #define THUMB .thumb
-    #define CODESECT .section .text
-    #define EXPORT .global
-    #define PROC :
-    #define LABEL :
-    #define ENDP
-    #define END
-
-    .syntax unified
-#endif
-
-	CODESECT
-	THUMB
-
-;/*
-;* @brief  In-place bit reversal function.
-;* @param[in, out] *pSrc        points to the in-place buffer of unknown 32-bit data type.
-;* @param[in]      bitRevLen    bit reversal table length
-;* @param[in]      *pBitRevTab  points to bit reversal table.
-;* @return none.
-;*/
-	EXPORT arm_bitreversal_32
-	EXPORT arm_bitreversal_16
-
-#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)
-
-arm_bitreversal_32 PROC
-	ADDS     r3,r1,#1
-	PUSH     {r4-r6}
-	ADDS     r1,r2,#0
-	LSRS     r3,r3,#1
-arm_bitreversal_32_0 LABEL
-	LDRH     r2,[r1,#2]
-	LDRH     r6,[r1,#0]
-	ADD      r2,r0,r2
-	ADD      r6,r0,r6
-	LDR      r5,[r2,#0]
-	LDR      r4,[r6,#0]
-	STR      r5,[r6,#0]
-	STR      r4,[r2,#0]
-	LDR      r5,[r2,#4]
-	LDR      r4,[r6,#4]
-	STR      r5,[r6,#4]
-	STR      r4,[r2,#4]
-	ADDS     r1,r1,#4
-	SUBS     r3,r3,#1
-	BNE      arm_bitreversal_32_0
-	POP      {r4-r6}
-	BX       lr
-	ENDP
-
-arm_bitreversal_16 PROC
-	ADDS     r3,r1,#1
-	PUSH     {r4-r6}
-	ADDS     r1,r2,#0
-	LSRS     r3,r3,#1
-arm_bitreversal_16_0 LABEL
-	LDRH     r2,[r1,#2]
-	LDRH     r6,[r1,#0]
-    LSRS     r2,r2,#1
-    LSRS     r6,r6,#1
-	ADD      r2,r0,r2
-	ADD      r6,r0,r6
-	LDR      r5,[r2,#0]
-	LDR      r4,[r6,#0]
-	STR      r5,[r6,#0]
-	STR      r4,[r2,#0]
-	ADDS     r1,r1,#4
-	SUBS     r3,r3,#1
-	BNE      arm_bitreversal_16_0
-	POP      {r4-r6}
-	BX       lr
-	ENDP
-
-#else
-
-arm_bitreversal_32 PROC
-	ADDS     r3,r1,#1
-	CMP      r3,#1
-	IT       LS
-	BXLS     lr
-	PUSH     {r4-r9}
-	ADDS     r1,r2,#2
-	LSRS     r3,r3,#2
-arm_bitreversal_32_0 LABEL       ;/* loop unrolled by 2 */
-	LDRH     r8,[r1,#4]
-	LDRH     r9,[r1,#2]
-	LDRH     r2,[r1,#0]
-	LDRH     r12,[r1,#-2]
-	ADD      r8,r0,r8
-	ADD      r9,r0,r9
-	ADD      r2,r0,r2
-	ADD      r12,r0,r12
-	LDR      r7,[r9,#0]
-	LDR      r6,[r8,#0]
-	LDR      r5,[r2,#0]
-	LDR      r4,[r12,#0]
-	STR      r6,[r9,#0]
-	STR      r7,[r8,#0]
-	STR      r5,[r12,#0]
-	STR      r4,[r2,#0]
-	LDR      r7,[r9,#4]
-	LDR      r6,[r8,#4]
-	LDR      r5,[r2,#4]
-	LDR      r4,[r12,#4]
-	STR      r6,[r9,#4]
-	STR      r7,[r8,#4]
-	STR      r5,[r12,#4]
-	STR      r4,[r2,#4]
-	ADDS     r1,r1,#8
-	SUBS     r3,r3,#1
-	BNE      arm_bitreversal_32_0
-	POP      {r4-r9}
-	BX       lr
-	ENDP
-
-arm_bitreversal_16 PROC
-	ADDS     r3,r1,#1
-	CMP      r3,#1
-	IT       LS
-	BXLS     lr
-	PUSH     {r4-r9}
-	ADDS     r1,r2,#2
-	LSRS     r3,r3,#2
-arm_bitreversal_16_0 LABEL       ;/* loop unrolled by 2 */
-	LDRH     r8,[r1,#4]
-	LDRH     r9,[r1,#2]
-	LDRH     r2,[r1,#0]
-	LDRH     r12,[r1,#-2]
-	ADD      r8,r0,r8,LSR #1
-	ADD      r9,r0,r9,LSR #1
-	ADD      r2,r0,r2,LSR #1
-	ADD      r12,r0,r12,LSR #1
-	LDR      r7,[r9,#0]
-	LDR      r6,[r8,#0]
-	LDR      r5,[r2,#0]
-	LDR      r4,[r12,#0]
-	STR      r6,[r9,#0]
-	STR      r7,[r8,#0]
-	STR      r5,[r12,#0]
-	STR      r4,[r2,#0]
-	ADDS     r1,r1,#8
-	SUBS     r3,r3,#1
-	BNE      arm_bitreversal_16_0
-	POP      {r4-r9}
-	BX       lr
-	ENDP
-
-#endif
-
-	END
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
deleted file mode 100644
index 5fb21b5e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_f32.c   
-*    
-* Description:	Combined Radix Decimation in Frequency CFFT Floating point processing function
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-extern void arm_radix8_butterfly_f32(
-    float32_t * pSrc,
-    uint16_t fftLen,
-    const float32_t * pCoef,
-    uint16_t twidCoefModifier);
-
-extern void arm_bitreversal_32(
-    uint32_t * pSrc,
-    const uint16_t bitRevLen,
-    const uint16_t * pBitRevTable);
-
-/**   
-* @ingroup groupTransforms   
-*/
-
-/**   
-* @defgroup ComplexFFT Complex FFT Functions   
-*   
-* \par
-* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
-* Discrete Fourier Transform (DFT).  The FFT can be orders of magnitude faster
-* than the DFT, especially for long lengths.
-* The algorithms described in this section
-* operate on complex data.  A separate set of functions is devoted to handling
-* of real sequences.
-* \par
-* There are separate algorithms for handling floating-point, Q15, and Q31 data
-* types.  The algorithms available for each data type are described next.
-* \par
-* The FFT functions operate in-place.  That is, the array holding the input data
-* will also be used to hold the corresponding result.  The input data is complex
-* and contains 2*fftLen interleaved values as shown below.
-* 
 {real[0], imag[0], real[1], imag[1],..} 

-* The FFT result will be contained in the same array and the frequency domain
-* values will have the same interleaving.
-*
-* \par Floating-point
-* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-8
-* stages are performed along with a single radix-2 or radix-4 stage, as needed.
-* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
-* a different twiddle factor table.  
-* \par
-* The function uses the standard FFT definition and output values may grow by a
-* factor of fftLen when computing the forward transform.  The
-* inverse transform includes a scale of 1/fftLen as part of the
-* calculation and this matches the textbook definition of the inverse FFT.
-* \par
-* Pre-initialized data structures containing twiddle factors and bit reversal
-* tables are provided and defined in arm_const_structs.h.  Include 
-* this header in your function and then pass one of the constant structures as 
-* an argument to arm_cfft_f32.  For example:
-* \par
-* arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)
-* \par
-* computes a 64-point inverse complex FFT including bit reversal.
-* The data structures are treated as constant data and not modified during the
-* calculation.  The same data structure can be reused for multiple transforms
-* including mixing forward and inverse transforms.
-* \par
-* Earlier releases of the library provided separate radix-2 and radix-4
-* algorithms that operated on floating-point data.  These functions are still
-* provided but are deprecated.  The older functions are slower and less general
-* than the new functions.
-* \par
-* An example of initialization of the constants for the arm_cfft_f32 function follows:
-* \code
-* const static arm_cfft_instance_f32 *S;
-* ...
-*   switch (length) {
-*     case 16:
-*       S = &arm_cfft_sR_f32_len16;
-*       break;
-*     case 32:
-*       S = &arm_cfft_sR_f32_len32;
-*       break;
-*     case 64:
-*       S = &arm_cfft_sR_f32_len64;
-*       break;
-*     case 128:
-*       S = &arm_cfft_sR_f32_len128;
-*       break;
-*     case 256:
-*       S = &arm_cfft_sR_f32_len256;
-*       break;
-*     case 512:
-*       S = &arm_cfft_sR_f32_len512;
-*       break;
-*     case 1024:
-*       S = &arm_cfft_sR_f32_len1024;
-*       break;
-*     case 2048:
-*       S = &arm_cfft_sR_f32_len2048;
-*       break;
-*     case 4096:
-*       S = &arm_cfft_sR_f32_len4096;
-*       break;
-*   }
-* \endcode
-* \par Q15 and Q31
-* The floating-point complex FFT uses a mixed-radix algorithm.  Multiple radix-4
-* stages are performed along with a single radix-2 stage, as needed.
-* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
-* a different twiddle factor table.  
-* \par
-* The function uses the standard FFT definition and output values may grow by a
-* factor of fftLen when computing the forward transform.  The
-* inverse transform includes a scale of 1/fftLen as part of the
-* calculation and this matches the textbook definition of the inverse FFT.
-* \par
-* Pre-initialized data structures containing twiddle factors and bit reversal
-* tables are provided and defined in arm_const_structs.h.  Include 
-* this header in your function and then pass one of the constant structures as 
-* an argument to arm_cfft_q31.  For example:
-* \par
-* arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)
-* \par
-* computes a 64-point inverse complex FFT including bit reversal.
-* The data structures are treated as constant data and not modified during the
-* calculation.  The same data structure can be reused for multiple transforms
-* including mixing forward and inverse transforms.
-* \par
-* Earlier releases of the library provided separate radix-2 and radix-4
-* algorithms that operated on floating-point data.  These functions are still
-* provided but are deprecated.  The older functions are slower and less general
-* than the new functions.
-* \par
-* An example of initialization of the constants for the arm_cfft_q31 function follows:
-* \code
-* const static arm_cfft_instance_q31 *S;
-* ...
-*   switch (length) {
-*     case 16:
-*       S = &arm_cfft_sR_q31_len16;
-*       break;
-*     case 32:
-*       S = &arm_cfft_sR_q31_len32;
-*       break;
-*     case 64:
-*       S = &arm_cfft_sR_q31_len64;
-*       break;
-*     case 128:
-*       S = &arm_cfft_sR_q31_len128;
-*       break;
-*     case 256:
-*       S = &arm_cfft_sR_q31_len256;
-*       break;
-*     case 512:
-*       S = &arm_cfft_sR_q31_len512;
-*       break;
-*     case 1024:
-*       S = &arm_cfft_sR_q31_len1024;
-*       break;
-*     case 2048:
-*       S = &arm_cfft_sR_q31_len2048;
-*       break;
-*     case 4096:
-*       S = &arm_cfft_sR_q31_len4096;
-*       break;
-*   }
-* \endcode
-* 
-*/
-
-void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1) 
-{
-    uint32_t    L  = S->fftLen;
-    float32_t * pCol1, * pCol2, * pMid1, * pMid2;
-    float32_t * p2 = p1 + L;
-    const float32_t * tw = (float32_t *) S->pTwiddle;
-    float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
-    float32_t m0, m1, m2, m3;
-    uint32_t l;
-
-    pCol1 = p1;
-    pCol2 = p2;
-
-    //    Define new length
-    L >>= 1;
-    //    Initialize mid pointers
-    pMid1 = p1 + L;
-    pMid2 = p2 + L;
-
-    // do two dot Fourier transform
-    for ( l = L >> 2; l > 0; l-- ) 
-    {
-        t1[0] = p1[0];
-        t1[1] = p1[1];
-        t1[2] = p1[2];
-        t1[3] = p1[3];
-
-        t2[0] = p2[0];
-        t2[1] = p2[1];
-        t2[2] = p2[2];
-        t2[3] = p2[3];
-
-        t3[0] = pMid1[0];
-        t3[1] = pMid1[1];
-        t3[2] = pMid1[2];
-        t3[3] = pMid1[3];
-
-        t4[0] = pMid2[0];
-        t4[1] = pMid2[1];
-        t4[2] = pMid2[2];
-        t4[3] = pMid2[3];
-
-        *p1++ = t1[0] + t2[0];
-        *p1++ = t1[1] + t2[1];
-        *p1++ = t1[2] + t2[2];
-        *p1++ = t1[3] + t2[3];    // col 1
-
-        t2[0] = t1[0] - t2[0];
-        t2[1] = t1[1] - t2[1];
-        t2[2] = t1[2] - t2[2];
-        t2[3] = t1[3] - t2[3];    // for col 2
-
-        *pMid1++ = t3[0] + t4[0];
-        *pMid1++ = t3[1] + t4[1];
-        *pMid1++ = t3[2] + t4[2];
-        *pMid1++ = t3[3] + t4[3]; // col 1
-
-        t4[0] = t4[0] - t3[0];
-        t4[1] = t4[1] - t3[1];
-        t4[2] = t4[2] - t3[2];
-        t4[3] = t4[3] - t3[3];    // for col 2
-
-        twR = *tw++;
-        twI = *tw++;
-
-        // multiply by twiddle factors
-        m0 = t2[0] * twR;
-        m1 = t2[1] * twI;
-        m2 = t2[1] * twR;
-        m3 = t2[0] * twI;
-        
-        // R  =  R  *  Tr - I * Ti
-        *p2++ = m0 + m1;
-        // I  =  I  *  Tr + R * Ti
-        *p2++ = m2 - m3;
-        
-        // use vertical symmetry
-        //  0.9988 - 0.0491i <==> -0.0491 - 0.9988i
-        m0 = t4[0] * twI;
-        m1 = t4[1] * twR;
-        m2 = t4[1] * twI;
-        m3 = t4[0] * twR;
-        
-        *pMid2++ = m0 - m1;
-        *pMid2++ = m2 + m3;
-
-        twR = *tw++;
-        twI = *tw++;
-        
-        m0 = t2[2] * twR;
-        m1 = t2[3] * twI;
-        m2 = t2[3] * twR;
-        m3 = t2[2] * twI;
-        
-        *p2++ = m0 + m1;
-        *p2++ = m2 - m3;
-        
-        m0 = t4[2] * twI;
-        m1 = t4[3] * twR;
-        m2 = t4[3] * twI;
-        m3 = t4[2] * twR;
-        
-        *pMid2++ = m0 - m1;
-        *pMid2++ = m2 + m3;
-    }
-
-    // first col
-    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
-    // second col
-    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
-}
-
-void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1) 
-{
-    uint32_t    L  = S->fftLen >> 1;
-    float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
-    const float32_t *tw2, *tw3, *tw4;
-    float32_t * p2 = p1 + L;
-    float32_t * p3 = p2 + L;
-    float32_t * p4 = p3 + L;
-    float32_t t2[4], t3[4], t4[4], twR, twI;
-    float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
-    float32_t m0, m1, m2, m3;
-    uint32_t l, twMod2, twMod3, twMod4;
-
-    pCol1 = p1;         // points to real values by default
-    pCol2 = p2;
-    pCol3 = p3;
-    pCol4 = p4;
-    pEnd1 = p2 - 1;     // points to imaginary values by default
-    pEnd2 = p3 - 1;
-    pEnd3 = p4 - 1;
-    pEnd4 = pEnd3 + L;
-
-    tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
-
-    L >>= 1;
-
-    // do four dot Fourier transform
-
-    twMod2 = 2;
-    twMod3 = 4;
-    twMod4 = 6;
-
-    // TOP
-    p1ap3_0 = p1[0] + p3[0];
-    p1sp3_0 = p1[0] - p3[0];
-    p1ap3_1 = p1[1] + p3[1];
-    p1sp3_1 = p1[1] - p3[1];
-
-    // col 2
-    t2[0] = p1sp3_0 + p2[1] - p4[1];
-    t2[1] = p1sp3_1 - p2[0] + p4[0];
-    // col 3
-    t3[0] = p1ap3_0 - p2[0] - p4[0];
-    t3[1] = p1ap3_1 - p2[1] - p4[1];
-    // col 4
-    t4[0] = p1sp3_0 - p2[1] + p4[1];
-    t4[1] = p1sp3_1 + p2[0] - p4[0];
-    // col 1
-    *p1++ = p1ap3_0 + p2[0] + p4[0];
-    *p1++ = p1ap3_1 + p2[1] + p4[1];
-
-    // Twiddle factors are ones
-    *p2++ = t2[0];
-    *p2++ = t2[1];
-    *p3++ = t3[0];
-    *p3++ = t3[1];
-    *p4++ = t4[0];
-    *p4++ = t4[1];
-
-    tw2 += twMod2;
-    tw3 += twMod3;
-    tw4 += twMod4;
-
-    for (l = (L - 2) >> 1; l > 0; l-- ) 
-    {
-        // TOP
-        p1ap3_0 = p1[0] + p3[0];
-        p1sp3_0 = p1[0] - p3[0];
-        p1ap3_1 = p1[1] + p3[1];
-        p1sp3_1 = p1[1] - p3[1];
-        // col 2
-        t2[0] = p1sp3_0 + p2[1] - p4[1];
-        t2[1] = p1sp3_1 - p2[0] + p4[0];
-        // col 3
-        t3[0] = p1ap3_0 - p2[0] - p4[0];
-        t3[1] = p1ap3_1 - p2[1] - p4[1];
-        // col 4
-        t4[0] = p1sp3_0 - p2[1] + p4[1];
-        t4[1] = p1sp3_1 + p2[0] - p4[0];
-        // col 1 - top
-        *p1++ = p1ap3_0 + p2[0] + p4[0];
-        *p1++ = p1ap3_1 + p2[1] + p4[1];
-
-        // BOTTOM
-        p1ap3_1 = pEnd1[-1] + pEnd3[-1];
-        p1sp3_1 = pEnd1[-1] - pEnd3[-1];
-        p1ap3_0 = pEnd1[0] + pEnd3[0];
-        p1sp3_0 = pEnd1[0] - pEnd3[0];
-        // col 2
-        t2[2] = pEnd2[0]  - pEnd4[0] + p1sp3_1;
-        t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
-        // col 3
-        t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
-        t3[3] = p1ap3_0 - pEnd2[0]  - pEnd4[0];
-        // col 4
-        t4[2] = pEnd2[0]  - pEnd4[0]  - p1sp3_1;
-        t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
-        // col 1 - Bottom
-        *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
-        *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
-
-        // COL 2
-        // read twiddle factors
-        twR = *tw2++;
-        twI = *tw2++;
-        // multiply by twiddle factors
-        //  let    Z1 = a + i(b),   Z2 = c + i(d)
-        //   =>  Z1 * Z2  =  (a*c - b*d) + i(b*c + a*d)
-        
-        // Top
-        m0 = t2[0] * twR;
-        m1 = t2[1] * twI;
-        m2 = t2[1] * twR;
-        m3 = t2[0] * twI;
-        
-        *p2++ = m0 + m1;
-        *p2++ = m2 - m3;
-        // use vertical symmetry col 2
-        // 0.9997 - 0.0245i  <==>  0.0245 - 0.9997i
-        // Bottom
-        m0 = t2[3] * twI;
-        m1 = t2[2] * twR;
-        m2 = t2[2] * twI;
-        m3 = t2[3] * twR;
-        
-        *pEnd2-- = m0 - m1;
-        *pEnd2-- = m2 + m3;
-
-        // COL 3
-        twR = tw3[0];
-        twI = tw3[1];
-        tw3 += twMod3;
-        // Top
-        m0 = t3[0] * twR;
-        m1 = t3[1] * twI;
-        m2 = t3[1] * twR;
-        m3 = t3[0] * twI;
-        
-        *p3++ = m0 + m1;
-        *p3++ = m2 - m3;
-        // use vertical symmetry col 3
-        // 0.9988 - 0.0491i  <==>  -0.9988 - 0.0491i
-        // Bottom
-        m0 = -t3[3] * twR;
-        m1 = t3[2] * twI;
-        m2 = t3[2] * twR;
-        m3 = t3[3] * twI;
-        
-        *pEnd3-- = m0 - m1;
-        *pEnd3-- = m3 - m2;
-        
-        // COL 4
-        twR = tw4[0];
-        twI = tw4[1];
-        tw4 += twMod4;
-        // Top
-        m0 = t4[0] * twR;
-        m1 = t4[1] * twI;
-        m2 = t4[1] * twR;
-        m3 = t4[0] * twI;
-        
-        *p4++ = m0 + m1;
-        *p4++ = m2 - m3;
-        // use vertical symmetry col 4
-        // 0.9973 - 0.0736i  <==>  -0.0736 + 0.9973i
-        // Bottom
-        m0 = t4[3] * twI;
-        m1 = t4[2] * twR;
-        m2 = t4[2] * twI;
-        m3 = t4[3] * twR;
-        
-        *pEnd4-- = m0 - m1;
-        *pEnd4-- = m2 + m3;
-    }
-
-    //MIDDLE
-    // Twiddle factors are 
-    //  1.0000  0.7071-0.7071i  -1.0000i  -0.7071-0.7071i
-    p1ap3_0 = p1[0] + p3[0];
-    p1sp3_0 = p1[0] - p3[0];
-    p1ap3_1 = p1[1] + p3[1];
-    p1sp3_1 = p1[1] - p3[1];
-
-    // col 2
-    t2[0] = p1sp3_0 + p2[1] - p4[1];
-    t2[1] = p1sp3_1 - p2[0] + p4[0];
-    // col 3
-    t3[0] = p1ap3_0 - p2[0] - p4[0];
-    t3[1] = p1ap3_1 - p2[1] - p4[1];
-    // col 4
-    t4[0] = p1sp3_0 - p2[1] + p4[1];
-    t4[1] = p1sp3_1 + p2[0] - p4[0];
-    // col 1 - Top
-    *p1++ = p1ap3_0 + p2[0] + p4[0];
-    *p1++ = p1ap3_1 + p2[1] + p4[1];
-
-    // COL 2
-    twR = tw2[0];
-    twI = tw2[1];
-
-    m0 = t2[0] * twR;
-    m1 = t2[1] * twI;
-    m2 = t2[1] * twR;
-    m3 = t2[0] * twI;
-
-    *p2++ = m0 + m1;
-    *p2++ = m2 - m3;
-    // COL 3
-    twR = tw3[0];
-    twI = tw3[1];
-
-    m0 = t3[0] * twR;
-    m1 = t3[1] * twI;
-    m2 = t3[1] * twR;
-    m3 = t3[0] * twI;
-
-    *p3++ = m0 + m1;
-    *p3++ = m2 - m3;
-    // COL 4
-    twR = tw4[0];
-    twI = tw4[1];
-
-    m0 = t4[0] * twR;
-    m1 = t4[1] * twI;
-    m2 = t4[1] * twR;
-    m3 = t4[0] * twI;
-
-    *p4++ = m0 + m1;
-    *p4++ = m2 - m3;
-
-    // first col
-    arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
-    // second col
-    arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
-    // third col
-    arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
-    // fourth col
-    arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
-}
-
-/**
-* @addtogroup ComplexFFT   
-* @{   
-*/
-
-/**   
-* @details   
-* @brief       Processing function for the floating-point complex FFT.
-* @param[in]      *S    points to an instance of the floating-point CFFT structure.  
-* @param[in, out] *p1   points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return none.  
-*/
-
-void arm_cfft_f32( 
-    const arm_cfft_instance_f32 * S, 
-    float32_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag)
-{
-    uint32_t  L = S->fftLen, l;
-    float32_t invL, * pSrc;
-
-    if(ifftFlag == 1u)
-    {
-        /*  Conjugate input data  */
-        pSrc = p1 + 1;
-        for(l=0; lpTwiddle, 1);
-        break;
-    }  
-
-    if( bitReverseFlag )
-        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
-
-    if(ifftFlag == 1u)
-    {
-        invL = 1.0f/(float32_t)L;
-        /*  Conjugate and scale output data */
-        pSrc = p1;
-        for(l=0; l2*fftLen. Processing occurs in-place.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return none.  
-*/
-
-void arm_cfft_q15( 
-    const arm_cfft_instance_q15 * S, 
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag)
-{
-    uint32_t L = S->fftLen;
-
-    if(ifftFlag == 1u)
-    {
-        switch (L) 
-        {
-        case 16: 
-        case 64:
-        case 256:
-        case 1024:
-        case 4096:
-            arm_radix4_butterfly_inverse_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
-            break;
-            
-        case 32:
-        case 128:
-        case 512:
-        case 2048:
-            arm_cfft_radix4by2_inverse_q15  ( p1, L, S->pTwiddle );
-            break;
-        }  
-    }
-    else
-    {
-        switch (L) 
-        {
-        case 16: 
-        case 64:
-        case 256:
-        case 1024:
-        case 4096:
-            arm_radix4_butterfly_q15  ( p1, L, (q15_t*)S->pTwiddle, 1 );
-            break;
-            
-        case 32:
-        case 128:
-        case 512:
-        case 2048:
-            arm_cfft_radix4by2_q15  ( p1, L, S->pTwiddle );
-            break;
-        }  
-    }
-    
-    if( bitReverseFlag )
-        arm_bitreversal_16((uint16_t*)p1,S->bitRevLength,S->pBitRevTable);    
-}
-
-/**    
-* @} end of ComplexFFT group    
-*/
-
-void arm_cfft_radix4by2_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    const q15_t * pCoef) 
-{    
-    uint32_t i;
-    uint32_t n2;
-    q15_t p0, p1, p2, p3;
-#ifndef ARM_MATH_CM0_FAMILY
-    q31_t T, S, R;
-    q31_t coeff, out1, out2;
-    const q15_t *pC = pCoef;
-    q15_t *pSi = pSrc;
-    q15_t *pSl = pSrc + fftLen;
-#else
-    uint32_t ia, l;
-    q15_t xt, yt, cosVal, sinVal;
-#endif
-    
-    n2 = fftLen >> 1; 
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    for (i = n2; i > 0; i--)
-    {
-        coeff = _SIMD32_OFFSET(pC);
-        pC += 2;
-
-        T = _SIMD32_OFFSET(pSi);
-        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
-
-        S = _SIMD32_OFFSET(pSl);
-        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
-        pSi += 2;
-
-    #ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(coeff, R) >> 16;
-        out2 = __SMUSDX(coeff, R);
-
-    #else
-
-        out1 = __SMUSDX(R, coeff) >> 16u;
-        out2 = __SMUAD(coeff, R);
-
-    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSl) =
-        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSl += 2;
-    } 
-    
-#else //    #ifndef ARM_MATH_CM0_FAMILY
-    
-    ia = 0;
-    for (i = 0; i < n2; i++)
-    {
-        cosVal = pCoef[ia * 2];
-        sinVal = pCoef[(ia * 2) + 1];
-        ia++;
-        
-        l = i + n2;        
-        
-        xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-        pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-        
-        yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-        pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
-                  ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
-                       ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-    } 
-    
-#endif //    #ifndef ARM_MATH_CM0_FAMILY
-    
-    // first col
-    arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2u);
-    // second col
-    arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
-			
-    for (i = 0; i < fftLen >> 1; i++)
-    {
-        p0 = pSrc[4*i+0];
-        p1 = pSrc[4*i+1];
-        p2 = pSrc[4*i+2];
-        p3 = pSrc[4*i+3];
-        
-        p0 <<= 1;
-        p1 <<= 1;
-        p2 <<= 1;
-        p3 <<= 1;
-        
-        pSrc[4*i+0] = p0;
-        pSrc[4*i+1] = p1;
-        pSrc[4*i+2] = p2;
-        pSrc[4*i+3] = p3;
-    }
-}
-
-void arm_cfft_radix4by2_inverse_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    const q15_t * pCoef) 
-{    
-    uint32_t i;
-    uint32_t n2;
-    q15_t p0, p1, p2, p3;
-#ifndef ARM_MATH_CM0_FAMILY
-    q31_t T, S, R;
-    q31_t coeff, out1, out2;
-    const q15_t *pC = pCoef;
-    q15_t *pSi = pSrc;
-    q15_t *pSl = pSrc + fftLen;
-#else
-    uint32_t ia, l;
-    q15_t xt, yt, cosVal, sinVal;
-#endif
-    
-    n2 = fftLen >> 1; 
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    for (i = n2; i > 0; i--)
-    {
-        coeff = _SIMD32_OFFSET(pC);
-        pC += 2;
-
-        T = _SIMD32_OFFSET(pSi);
-        T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
-
-        S = _SIMD32_OFFSET(pSl);
-        S = __SHADD16(S, 0); // this is just a SIMD arithmetic shift right by 1
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSi) = __SHADD16(T, S);
-        pSi += 2;
-
-    #ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(coeff, R) >> 16;
-        out2 = __SMUADX(coeff, R);
-    #else
-
-        out1 = __SMUADX(R, coeff) >> 16u;
-        out2 = __SMUSD(__QSUB(0, coeff), R);
-
-    #endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSl) =
-        (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);        
-        pSl += 2;
-    } 
-    
-#else //    #ifndef ARM_MATH_CM0_FAMILY
-
-    ia = 0;
-    for (i = 0; i < n2; i++)
-    {
-        cosVal = pCoef[ia * 2];
-        sinVal = pCoef[(ia * 2) + 1];
-        ia++;
-        
-        l = i + n2;
-        xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-        pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-        
-        yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-        pSrc[2 * i + 1] =
-          ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-        
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
-                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-        
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
-                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-    } 
-    
-#endif //    #ifndef ARM_MATH_CM0_FAMILY
-
-    // first col
-    arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2u);
-    // second col
-    arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2u);
-			
-    for (i = 0; i < fftLen >> 1; i++)
-    {
-        p0 = pSrc[4*i+0];
-        p1 = pSrc[4*i+1];
-        p2 = pSrc[4*i+2];
-        p3 = pSrc[4*i+3];
-        
-        p0 <<= 1;
-        p1 <<= 1;
-        p2 <<= 1;
-        p3 <<= 1;
-        
-        pSrc[4*i+0] = p0;
-        pSrc[4*i+1] = p1;
-        pSrc[4*i+2] = p2;
-        pSrc[4*i+3] = p3;
-    }
-}
-
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
deleted file mode 100644
index 20ad7e78..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_q31.c   
-*    
-* Description:	Combined Radix Decimation in Frequency CFFT fixed point processing function
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-extern void arm_radix4_butterfly_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pCoef,
-    uint32_t twidCoefModifier);
-
-extern void arm_radix4_butterfly_inverse_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pCoef,
-    uint32_t twidCoefModifier);
-
-extern void arm_bitreversal_32(
-    uint32_t * pSrc,
-    const uint16_t bitRevLen,
-    const uint16_t * pBitRevTable);
-    
-void arm_cfft_radix4by2_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    const q31_t * pCoef);
-    
-void arm_cfft_radix4by2_inverse_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    const q31_t * pCoef);
-
-/**   
-* @ingroup groupTransforms   
-*/
-
-/**
-* @addtogroup ComplexFFT   
-* @{   
-*/
-
-/**   
-* @details   
-* @brief       Processing function for the fixed-point complex FFT in Q31 format.
-* @param[in]      *S    points to an instance of the fixed-point CFFT structure.  
-* @param[in, out] *p1   points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return none.  
-*/
-
-void arm_cfft_q31( 
-    const arm_cfft_instance_q31 * S, 
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag)
-{
-    uint32_t L = S->fftLen;
-
-    if(ifftFlag == 1u)
-    {
-        switch (L) 
-        {
-        case 16: 
-        case 64:
-        case 256:
-        case 1024:
-        case 4096:
-            arm_radix4_butterfly_inverse_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
-            break;
-            
-        case 32:
-        case 128:
-        case 512:
-        case 2048:
-            arm_cfft_radix4by2_inverse_q31  ( p1, L, S->pTwiddle );
-            break;
-        }  
-    }
-    else
-    {
-        switch (L) 
-        {
-        case 16: 
-        case 64:
-        case 256:
-        case 1024:
-        case 4096:
-            arm_radix4_butterfly_q31  ( p1, L, (q31_t*)S->pTwiddle, 1 );
-            break;
-            
-        case 32:
-        case 128:
-        case 512:
-        case 2048:
-            arm_cfft_radix4by2_q31  ( p1, L, S->pTwiddle );
-            break;
-        }  
-    }
-    
-    if( bitReverseFlag )
-        arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);    
-}
-
-/**    
-* @} end of ComplexFFT group    
-*/
-
-void arm_cfft_radix4by2_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    const q31_t * pCoef) 
-{    
-    uint32_t i, l;
-    uint32_t n2, ia;
-    q31_t xt, yt, cosVal, sinVal;
-    q31_t p0, p1;
-    
-    n2 = fftLen >> 1;    
-    ia = 0;
-    for (i = 0; i < n2; i++)
-    {
-        cosVal = pCoef[2*ia];
-        sinVal = pCoef[2*ia + 1];
-        ia++;
-        
-        l = i + n2;
-        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
-        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
-        
-        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
-        
-        mult_32x32_keep32_R(p0, xt, cosVal);
-        mult_32x32_keep32_R(p1, yt, cosVal);
-        multAcc_32x32_keep32_R(p0, yt, sinVal); 
-        multSub_32x32_keep32_R(p1, xt, sinVal);
-        
-        pSrc[2u * l] = p0 << 1;
-        pSrc[2u * l + 1u] = p1 << 1;
-    
-    }
-
-    // first col
-    arm_radix4_butterfly_q31( pSrc, n2, (q31_t*)pCoef, 2u);
-    // second col
-    arm_radix4_butterfly_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
-			
-    for (i = 0; i < fftLen >> 1; i++)
-    {
-        p0 = pSrc[4*i+0];
-        p1 = pSrc[4*i+1];
-        xt = pSrc[4*i+2];
-        yt = pSrc[4*i+3];
-        
-        p0 <<= 1;
-        p1 <<= 1;
-        xt <<= 1;
-        yt <<= 1;
-        
-        pSrc[4*i+0] = p0;
-        pSrc[4*i+1] = p1;
-        pSrc[4*i+2] = xt;
-        pSrc[4*i+3] = yt;
-    }
-
-}
-
-void arm_cfft_radix4by2_inverse_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    const q31_t * pCoef) 
-{    
-    uint32_t i, l;
-    uint32_t n2, ia;
-    q31_t xt, yt, cosVal, sinVal;
-    q31_t p0, p1;
-    
-    n2 = fftLen >> 1;    
-    ia = 0;
-    for (i = 0; i < n2; i++)
-    {
-        cosVal = pCoef[2*ia];
-        sinVal = pCoef[2*ia + 1];
-        ia++;
-        
-        l = i + n2;
-        xt = (pSrc[2 * i] >> 2) - (pSrc[2 * l] >> 2);
-        pSrc[2 * i] = (pSrc[2 * i] >> 2) + (pSrc[2 * l] >> 2);
-        
-        yt = (pSrc[2 * i + 1] >> 2) - (pSrc[2 * l + 1] >> 2);
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2) + (pSrc[2 * i + 1] >> 2);
-        
-        mult_32x32_keep32_R(p0, xt, cosVal);
-        mult_32x32_keep32_R(p1, yt, cosVal);
-        multSub_32x32_keep32_R(p0, yt, sinVal); 
-        multAcc_32x32_keep32_R(p1, xt, sinVal);
-        
-        pSrc[2u * l] = p0 << 1;
-        pSrc[2u * l + 1u] = p1 << 1;
-    
-    }
-
-    // first col
-    arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2u);
-    // second col
-    arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2u);
-			
-    for (i = 0; i < fftLen >> 1; i++)
-    {
-        p0 = pSrc[4*i+0];
-        p1 = pSrc[4*i+1];
-        xt = pSrc[4*i+2];
-        yt = pSrc[4*i+3];
-        
-        p0 <<= 1;
-        p1 <<= 1;
-        xt <<= 1;
-        yt <<= 1;
-        
-        pSrc[4*i+0] = p0;
-        pSrc[4*i+1] = p1;
-        pSrc[4*i+2] = xt;
-        pSrc[4*i+3] = yt;
-    }
-}
-
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
deleted file mode 100644
index 8e3b77ca..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_f32.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier,
-  float32_t onebyfftLen);
-
-extern void arm_bitreversal_f32(
-    float32_t * pSrc,
-    uint16_t fftSize,
-    uint16_t bitRevFactor,
-    uint16_t * pBitRevTab);
-
-/**   
-* @ingroup groupTransforms   
-*/
-
-/**   
-* @addtogroup ComplexFFT   
-* @{   
-*/
-
-/**   
-* @details
-* @brief Radix-2 CFFT/CIFFT.
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in]      *S    points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.  
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
-* @return none.
-*/
-
-void arm_cfft_radix2_f32(
-const arm_cfft_radix2_instance_f32 * S,
-float32_t * pSrc)
-{
-
-   if(S->ifftFlag == 1u)
-   {
-      /*  Complex IFFT radix-2  */
-      arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
-      S->twidCoefModifier, S->onebyfftLen);
-   }
-   else
-   {
-      /*  Complex FFT radix-2  */
-      arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
-      S->twidCoefModifier);
-   }
-
-   if(S->bitReverseFlag == 1u)
-   {
-      /*  Bit Reversal */
-      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-   }
-
-}
-
-
-/**    
-* @} end of ComplexFFT group    
-*/
-
-
-
-/* ----------------------------------------------------------------------    
-** Internal helper function used by the FFTs    
-** ------------------------------------------------------------------- */
-
-/*    
-* @brief  Core function for the floating-point CFFT butterfly process.   
-* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
-* @param[in]      fftLen           length of the FFT.   
-* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
-* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.   
-*/
-
-void arm_radix2_butterfly_f32(
-float32_t * pSrc,
-uint32_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
-   uint32_t i, j, k, l;
-   uint32_t n1, n2, ia;
-   float32_t xt, yt, cosVal, sinVal;
-   float32_t p0, p1, p2, p3;
-   float32_t a0, a1;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-   /*  Initializations for the first stage */
-   n2 = fftLen >> 1;
-   ia = 0;
-   i = 0;
-
-   // loop for groups 
-   for (k = n2; k > 0; k--)
-   {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-
-      /*  Twiddle coefficients index modifier */
-      ia += twidCoefModifier;
-
-      /*  index calculation for the input as, */
-      /*  pSrc[i + 0], pSrc[i + fftLen/1] */
-      l = i + n2;
-
-      /*  Butterfly implementation */
-      a0 = pSrc[2 * i] + pSrc[2 * l];
-      xt = pSrc[2 * i] - pSrc[2 * l];
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-      
-      p0 = xt * cosVal;
-      p1 = yt * sinVal;
-      p2 = yt * cosVal;
-      p3 = xt * sinVal;  
-      
-      pSrc[2 * i]     = a0;   
-      pSrc[2 * i + 1] = a1;       
-      
-      pSrc[2 * l]     = p0 + p1;
-      pSrc[2 * l + 1] = p2 - p3;
-      
-      i++;
-   }                             // groups loop end 
-
-   twidCoefModifier <<= 1u;
-
-   // loop for stage 
-   for (k = n2; k > 2; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      j = 0;
-      do
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia += twidCoefModifier;
-
-         // loop for butterfly 
-         i = j;
-         do
-         {
-            l = i + n2;
-            a0 = pSrc[2 * i] + pSrc[2 * l];
-            xt = pSrc[2 * i] - pSrc[2 * l];
-
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-            
-            p0 = xt * cosVal;
-            p1 = yt * sinVal;
-            p2 = yt * cosVal;
-            p3 = xt * sinVal;  
-            
-            pSrc[2 * i] = a0;   
-            pSrc[2 * i + 1] = a1;       
-            
-            pSrc[2 * l]     = p0 + p1;
-            pSrc[2 * l + 1] = p2 - p3;
-            
-            i += n1;
-         } while( i < fftLen );                        // butterfly loop end 
-         j++;
-      } while( j < n2);                          // groups loop end 
-      twidCoefModifier <<= 1u;
-   }                             // stages loop end 
-
-   // loop for butterfly 
-   for (i = 0; i < fftLen; i += 2)
-   {
-      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
-      xt = pSrc[2 * i] - pSrc[2 * i + 2];
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
-      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
-      
-      pSrc[2 * i] = a0;   
-      pSrc[2 * i + 1] = a1;
-      pSrc[2 * i + 2] = xt;
-      pSrc[2 * i + 3] = yt;
-   }                             // groups loop end 
-
-#else
- 
-   n2 = fftLen;
-
-   // loop for stage 
-   for (k = fftLen; k > 1; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      j = 0;
-      do
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia += twidCoefModifier;
-
-         // loop for butterfly 
-         i = j;
-         do
-         {
-            l = i + n2;
-            a0 = pSrc[2 * i] + pSrc[2 * l];
-            xt = pSrc[2 * i] - pSrc[2 * l];
-
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-            
-            p0 = xt * cosVal;
-            p1 = yt * sinVal;
-            p2 = yt * cosVal;
-            p3 = xt * sinVal;  
-            
-            pSrc[2 * i] = a0;   
-            pSrc[2 * i + 1] = a1;       
-            
-            pSrc[2 * l]     = p0 + p1;
-            pSrc[2 * l + 1] = p2 - p3;
-            
-            i += n1;
-         } while(i < fftLen);
-         j++;
-      } while(j < n2);
-      twidCoefModifier <<= 1u;
-   }
-
-#endif //    #ifndef ARM_MATH_CM0_FAMILY
-
-}
-
-
-void arm_radix2_butterfly_inverse_f32(
-float32_t * pSrc,
-uint32_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier,
-float32_t onebyfftLen)
-{
-
-   uint32_t i, j, k, l;
-   uint32_t n1, n2, ia;
-   float32_t xt, yt, cosVal, sinVal;
-   float32_t p0, p1, p2, p3;
-   float32_t a0, a1;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-   n2 = fftLen >> 1;
-   ia = 0;
-
-   // loop for groups 
-   for (i = 0; i < n2; i++)
-   {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia += twidCoefModifier;
-
-      l = i + n2;
-      a0 = pSrc[2 * i] + pSrc[2 * l];
-      xt = pSrc[2 * i] - pSrc[2 * l];
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-      
-      p0 = xt * cosVal;
-      p1 = yt * sinVal;
-      p2 = yt * cosVal;
-      p3 = xt * sinVal;  
-      
-      pSrc[2 * i] = a0;   
-      pSrc[2 * i + 1] = a1;       
-      
-      pSrc[2 * l]     = p0 - p1;
-      pSrc[2 * l + 1] = p2 + p3;  
-   }                             // groups loop end 
-
-   twidCoefModifier <<= 1u;
-
-   // loop for stage 
-   for (k = fftLen / 2; k > 2; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      j = 0;
-      do
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia += twidCoefModifier;
-
-         // loop for butterfly 
-         i = j;
-         do
-         {
-            l = i + n2;
-            a0 = pSrc[2 * i] + pSrc[2 * l];
-            xt = pSrc[2 * i] - pSrc[2 * l];
-
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-            
-            p0 = xt * cosVal;
-            p1 = yt * sinVal;
-            p2 = yt * cosVal;
-            p3 = xt * sinVal;  
-            
-            pSrc[2 * i] = a0;   
-            pSrc[2 * i + 1] = a1;       
-            
-            pSrc[2 * l]     = p0 - p1;
-            pSrc[2 * l + 1] = p2 + p3; 
-
-            i += n1;
-         } while( i < fftLen );                 // butterfly loop end 
-         j++;
-      } while(j < n2);                      // groups loop end 
-
-      twidCoefModifier <<= 1u;
-   }                             // stages loop end 
-
-   // loop for butterfly 
-   for (i = 0; i < fftLen; i += 2)
-   {   
-      a0 = pSrc[2 * i] + pSrc[2 * i + 2];
-      xt = pSrc[2 * i] - pSrc[2 * i + 2];
-      
-      a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
-      yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
-      
-      p0 = a0 * onebyfftLen;
-      p2 = xt * onebyfftLen;
-      p1 = a1 * onebyfftLen;
-      p3 = yt * onebyfftLen; 
-      
-      pSrc[2 * i] = p0;
-      pSrc[2 * i + 1] = p1;  
-      pSrc[2 * i + 2] = p2;       
-      pSrc[2 * i + 3] = p3;
-   }                             // butterfly loop end 
-
-#else
-
-   n2 = fftLen;
-
-   // loop for stage 
-   for (k = fftLen; k > 2; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      j = 0;
-      do
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia = ia + twidCoefModifier;
-
-         // loop for butterfly 
-         i = j;
-         do
-         {
-            l = i + n2;
-            a0 = pSrc[2 * i] + pSrc[2 * l];
-            xt = pSrc[2 * i] - pSrc[2 * l];
-
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-            
-            p0 = xt * cosVal;
-            p1 = yt * sinVal;
-            p2 = yt * cosVal;
-            p3 = xt * sinVal;  
-            
-            pSrc[2 * i] = a0;   
-            pSrc[2 * i + 1] = a1;       
-            
-            pSrc[2 * l]     = p0 - p1;
-            pSrc[2 * l + 1] = p2 + p3;  
-            
-            i += n1;
-         } while( i < fftLen );                    // butterfly loop end 
-         j++;
-      } while( j < n2 );                      // groups loop end 
-
-      twidCoefModifier = twidCoefModifier << 1u;
-   }                             // stages loop end 
-
-   n1 = n2;
-   n2 = n2 >> 1;
-
-   // loop for butterfly 
-   for (i = 0; i < fftLen; i += n1)
-   {
-      l = i + n2;
-      
-      a0 = pSrc[2 * i] + pSrc[2 * l];
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      
-      a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      
-      p0 = a0 * onebyfftLen;
-      p2 = xt * onebyfftLen;
-      p1 = a1 * onebyfftLen;
-      p3 = yt * onebyfftLen; 
-      
-      pSrc[2 * i] = p0;
-      pSrc[2u * l] = p2;
-     
-      pSrc[2 * i + 1] = p1;    
-      pSrc[2u * l + 1u] = p3;
-   }                             // butterfly loop end 
-
-#endif //      #ifndef ARM_MATH_CM0_FAMILY
-
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
deleted file mode 100644
index 55d2a71c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix4_init_f32.c   
-*   
-* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup ComplexFFT   
- * @{   
- */
-
-/**   
-* @brief  Initialization function for the floating-point CFFT/CIFFT.  
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
-* @param[in]     fftLen         length of the FFT.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (float32_t *) twiddleCoef;
-
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.000244140625;
-    break;
-
-  case 2048u:
-    /*  Initializations of structure parameters for 2048 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.00048828125;
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.0009765625f;
-    break;
-
-  case 512u:
-    /*  Initializations of structure parameters for 512 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 8u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 8u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.001953125;
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    S->onebyfftLen = 0.00390625f;
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-    S->onebyfftLen = 0.0078125;
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    S->onebyfftLen = 0.015625f;
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-    S->onebyfftLen = 0.03125;
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    S->onebyfftLen = 0.0625f;
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**   
- * @} end of ComplexFFT group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
deleted file mode 100644
index 3949140e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5   
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix2_init_q15.c    
-*    
-* Description:	Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-/**   
-* @brief Initialization function for the Q15 CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
-* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-
-arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-
-    break;
-
-  case 2048u:
-    /*  Initializations of structure parameters for 2048 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-    S->twidCoefModifier = 4u;
-    S->bitRevFactor = 4u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
-    break;
-
-  case 512u:
-    /*  Initializations of structure parameters for 512 point FFT */
-    S->twidCoefModifier = 8u;
-    S->bitRevFactor = 8u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 32 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
deleted file mode 100644
index 3ce6e5d3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_init_q31.c   
-*   
-* Description:	Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup ComplexFFT   
- * @{   
- */
-
-
-/**    
-*    
-* @brief  Initialization function for the Q31 CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-
-arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of Instance structure depending on the FFT length */
-  switch (S->fftLen)
-  {
-    /*  Initializations of structure parameters for 4096 point FFT */
-  case 4096u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    break;
-
-    /*  Initializations of structure parameters for 2048 point FFT */
-  case 2048u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-    break;
-
-    /*  Initializations of structure parameters for 1024 point FFT */
-  case 1024u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    break;
-
-    /*  Initializations of structure parameters for 512 point FFT */
-  case 512u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 8u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 8u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 32 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**   
- * @} end of ComplexFFT group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
deleted file mode 100644
index 74d821a9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_q15.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier);
-	
-void arm_bitreversal_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup ComplexFFT   
- * @{   
- */
-
-/**   
- * @details   
- * @brief Processing function for the fixed-point CFFT/CIFFT.  
- * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
- * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
- * @return none.  
- */
-
-void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc)
-{
-
-  if(S->ifftFlag == 1u)
-  {
-    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
-                                     S->pTwiddle, S->twidCoefModifier);
-  }
-  else
-  {
-    arm_radix2_butterfly_q15(pSrc, S->fftLen,
-                             S->pTwiddle, S->twidCoefModifier);
-  }
-
-  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**   
- * @} end of ComplexFFT group   
- */
-
-void arm_radix2_butterfly_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  unsigned i, j, k, l;
-  unsigned n1, n2, ia;
-  q15_t in;
-  q31_t T, S, R;
-  q31_t coeff, out1, out2;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 1;
-    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 1;
-    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUAD(coeff, R) >> 16;
-    out2 = __SMUSDX(coeff, R);
-
-#else
-
-    out1 = __SMUSDX(R, coeff) >> 16u;
-    out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    i++;
-    l++;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 1;
-    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 1;
-    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUAD(coeff, R) >> 16;
-    out2 = __SMUSDX(coeff, R);
-
-#else
-
-    out1 = __SMUSDX(R, coeff) >> 16u;
-    out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(coeff, R) >> 16;
-        out2 = __SMUSDX(coeff, R);
-
-#else
-
-        out1 = __SMUSDX(R, coeff) >> 16u;
-        out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        i += n1;
-
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(coeff, R) >> 16;
-        out2 = __SMUSDX(coeff, R);
-
-#else
-
-        out1 = __SMUSDX(R, coeff) >> 16u;
-        out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-    i += n1;
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-  }                             // groups loop end 
-
-
-#else
-
-  unsigned i, j, k, l;
-  unsigned n1, n2, ia;
-  q15_t xt, yt, cosVal, sinVal;
-
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
-      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
-      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
-                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
-                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
-                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
-                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-#endif //             #ifndef ARM_MATH_CM0_FAMILY
-
-}
-
-
-void arm_radix2_butterfly_inverse_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-#ifndef ARM_MATH_CM0_FAMILY
-
-  unsigned i, j, k, l;
-  unsigned n1, n2, ia;
-  q15_t in;
-  q31_t T, S, R;
-  q31_t coeff, out1, out2;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 1;
-    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 1;
-    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUSD(coeff, R) >> 16;
-    out2 = __SMUADX(coeff, R);
-#else
-
-    out1 = __SMUADX(R, coeff) >> 16u;
-    out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    i++;
-    l++;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 1;
-    T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 1;
-    S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUSD(coeff, R) >> 16;
-    out2 = __SMUADX(coeff, R);
-#else
-
-    out1 = __SMUADX(R, coeff) >> 16u;
-    out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(coeff, R) >> 16;
-        out2 = __SMUADX(coeff, R);
-
-#else
-
-        out1 = __SMUADX(R, coeff) >> 16u;
-        out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        i += n1;
-
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(coeff, R) >> 16;
-        out2 = __SMUADX(coeff, R);
-#else
-
-        out1 = __SMUADX(R, coeff) >> 16u;
-        out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-
-      T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-      S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-      R = __QSUB16(T, S);
-
-      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-      _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-#else
-
-
-  unsigned i, j, k, l;
-  unsigned n1, n2, ia;
-  q15_t xt, yt, cosVal, sinVal;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-
-      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
-      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
-                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
-                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
-                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
-                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-  }                             // groups loop end 
-
-
-#endif //             #ifndef ARM_MATH_CM0_FAMILY
-
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
deleted file mode 100644
index 6ed9a808..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.   
-*   
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_q31.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-void arm_radix2_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier);
-
-void arm_radix2_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier);
-
-void arm_bitreversal_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-/**   
-* @ingroup groupTransforms   
-*/
-
-/**   
-* @addtogroup ComplexFFT   
-* @{   
-*/
-
-/**   
-* @details   
-* @brief Processing function for the fixed-point CFFT/CIFFT.  
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
-* @return none.  
-*/
-
-void arm_cfft_radix2_q31(
-const arm_cfft_radix2_instance_q31 * S,
-q31_t * pSrc)
-{
-
-   if(S->ifftFlag == 1u)
-   {
-      arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
-      S->pTwiddle, S->twidCoefModifier);
-   }
-   else
-   {
-      arm_radix2_butterfly_q31(pSrc, S->fftLen,
-      S->pTwiddle, S->twidCoefModifier);
-   }
-
-   arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**   
-* @} end of ComplexFFT group   
-*/
-
-void arm_radix2_butterfly_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
-   unsigned i, j, k, l, m;
-   unsigned n1, n2, ia;
-   q31_t xt, yt, cosVal, sinVal;
-   q31_t p0, p1;
-
-   //N = fftLen; 
-   n2 = fftLen;
-
-   n1 = n2;
-   n2 = n2 >> 1;
-   ia = 0;
-
-   // loop for groups 
-   for (i = 0; i < n2; i++)
-   {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-      
-      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
-      mult_32x32_keep32_R(p0, xt, cosVal);
-      mult_32x32_keep32_R(p1, yt, cosVal);
-      multAcc_32x32_keep32_R(p0, yt, sinVal); 
-      multSub_32x32_keep32_R(p1, xt, sinVal);
-      
-      pSrc[2u * l] = p0;
-      pSrc[2u * l + 1u] = p1;
-
-   }                             // groups loop end 
-
-   twidCoefModifier <<= 1u;
-
-   // loop for stage 
-   for (k = fftLen / 2; k > 2; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      for (j = 0; j < n2; j++)
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia = ia + twidCoefModifier;
-
-         // loop for butterfly 
-         i = j;
-         m = fftLen / n1;
-         do
-         {
-            l = i + n2;
-            xt = pSrc[2 * i] - pSrc[2 * l];
-            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-            
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-            mult_32x32_keep32_R(p0, xt, cosVal);
-            mult_32x32_keep32_R(p1, yt, cosVal);
-            multAcc_32x32_keep32_R(p0, yt, sinVal);
-            multSub_32x32_keep32_R(p1, xt, sinVal);
-            
-            pSrc[2u * l] = p0;
-            pSrc[2u * l + 1u] = p1;
-            i += n1;
-            m--;
-         } while( m > 0);                   // butterfly loop end 
-
-      }                           // groups loop end 
-
-      twidCoefModifier <<= 1u;
-   }                             // stages loop end 
-
-   n1 = n2;
-   n2 = n2 >> 1;
-   ia = 0;
-
-   cosVal = pCoef[ia * 2];
-   sinVal = pCoef[(ia * 2) + 1];
-   ia = ia + twidCoefModifier;
-
-   // loop for butterfly 
-   for (i = 0; i < fftLen; i += n1)
-   {
-      l = i + n2;
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-      i += n1;
-      l = i + n2;
-
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-   }                             // butterfly loop end 
-
-}
-
-
-void arm_radix2_butterfly_inverse_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
-   unsigned i, j, k, l;
-   unsigned n1, n2, ia;
-   q31_t xt, yt, cosVal, sinVal;
-   q31_t p0, p1;
-
-   //N = fftLen; 
-   n2 = fftLen;
-
-   n1 = n2;
-   n2 = n2 >> 1;
-   ia = 0;
-
-   // loop for groups 
-   for (i = 0; i < n2; i++)
-   {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 1u) - (pSrc[2 * l] >> 1u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 1u) + (pSrc[2 * l] >> 1u)) >> 1u;
-      
-      yt = (pSrc[2 * i + 1] >> 1u) - (pSrc[2 * l + 1] >> 1u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 1u) + (pSrc[2 * i + 1] >> 1u)) >> 1u;
-
-      mult_32x32_keep32_R(p0, xt, cosVal);
-      mult_32x32_keep32_R(p1, yt, cosVal);
-      multSub_32x32_keep32_R(p0, yt, sinVal);
-      multAcc_32x32_keep32_R(p1, xt, sinVal);
-      
-      pSrc[2u * l] = p0;
-      pSrc[2u * l + 1u] = p1;
-   }                             // groups loop end 
-
-   twidCoefModifier = twidCoefModifier << 1u;
-
-   // loop for stage 
-   for (k = fftLen / 2; k > 2; k = k >> 1)
-   {
-      n1 = n2;
-      n2 = n2 >> 1;
-      ia = 0;
-
-      // loop for groups 
-      for (j = 0; j < n2; j++)
-      {
-         cosVal = pCoef[ia * 2];
-         sinVal = pCoef[(ia * 2) + 1];
-         ia = ia + twidCoefModifier;
-
-         // loop for butterfly 
-         for (i = j; i < fftLen; i += n1)
-         {
-            l = i + n2;
-            xt = pSrc[2 * i] - pSrc[2 * l];
-            pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-      
-            yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-            pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-            mult_32x32_keep32_R(p0, xt, cosVal);
-            mult_32x32_keep32_R(p1, yt, cosVal);
-            multSub_32x32_keep32_R(p0, yt, sinVal);
-            multAcc_32x32_keep32_R(p1, xt, sinVal);
-            
-            pSrc[2u * l] = p0;
-            pSrc[2u * l + 1u] = p1;
-         }                         // butterfly loop end 
-
-      }                           // groups loop end 
-
-      twidCoefModifier = twidCoefModifier << 1u;
-   }                             // stages loop end 
-
-   n1 = n2;
-   n2 = n2 >> 1;
-   ia = 0;
-
-   cosVal = pCoef[ia * 2];
-   sinVal = pCoef[(ia * 2) + 1];
-   ia = ia + twidCoefModifier;
-
-   // loop for butterfly 
-   for (i = 0; i < fftLen; i += n1)
-   {
-      l = i + n2;
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-      i += n1;
-      l = i + n2;
-
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-   }                             // butterfly loop end 
-
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
deleted file mode 100644
index c29927c3..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
+++ /dev/null
@@ -1,1210 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_f32.c    
-*    
-* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-extern void arm_bitreversal_f32(
-float32_t * pSrc,
-uint16_t fftSize,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab);
-
-/**    
-* @ingroup groupTransforms    
-*/
-
-/* ----------------------------------------------------------------------    
-** Internal helper function used by the FFTs    
-** ------------------------------------------------------------------- */
-
-/*    
-* @brief  Core function for the floating-point CFFT butterfly process.   
-* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
-* @param[in]      fftLen           length of the FFT.   
-* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
-* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.   
-*/
-
-void arm_radix4_butterfly_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
-
-   float32_t co1, co2, co3, si1, si2, si3;
-   uint32_t ia1, ia2, ia3;
-   uint32_t i0, i1, i2, i3;
-   uint32_t n1, n2, j, k;
-
-#ifndef ARM_MATH_CM0_FAMILY_FAMILY
-
-   /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
-   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
-   Ybminusd;
-   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
-   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
-   float32_t *ptr1;
-   float32_t p0,p1,p2,p3,p4,p5;
-   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
-
-   /*  Initializations for the first stage */
-   n2 = fftLen;
-   n1 = n2;
-
-   /* n2 = fftLen/4 */
-   n2 >>= 2u;
-   i0 = 0u;
-   ia1 = 0u;
-
-   j = n2;
-
-   /*  Calculation of first stage */
-   do
-   {
-      /*  index calculation for the input as, */
-      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-      i1 = i0 + n2;
-      i2 = i1 + n2;
-      i3 = i2 + n2;
-
-      xaIn = pSrc[(2u * i0)];
-      yaIn = pSrc[(2u * i0) + 1u];
-
-      xbIn = pSrc[(2u * i1)];
-      ybIn = pSrc[(2u * i1) + 1u];
-
-      xcIn = pSrc[(2u * i2)];
-      ycIn = pSrc[(2u * i2) + 1u];
-
-      xdIn = pSrc[(2u * i3)];
-      ydIn = pSrc[(2u * i3) + 1u];
-
-      /* xa + xc */
-      Xaplusc = xaIn + xcIn;
-      /* xb + xd */
-      Xbplusd = xbIn + xdIn;
-      /* ya + yc */
-      Yaplusc = yaIn + ycIn;
-      /* yb + yd */
-      Ybplusd = ybIn + ydIn;
-
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-
-      /* xa - xc */
-      Xaminusc = xaIn - xcIn;
-      /* xb - xd */
-      Xbminusd = xbIn - xdIn;
-      /* ya - yc */
-      Yaminusc = yaIn - ycIn;
-      /* yb - yd */
-      Ybminusd = ybIn - ydIn;
-
-      /* xa' = xa + xb + xc + xd */
-      pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-      /* ya' = ya + yb + yc + yd */
-      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-      /* (xa - xc) + (yb - yd) */
-      Xb12C_out = (Xaminusc + Ybminusd);
-      /* (ya - yc) + (xb - xd) */
-      Yb12C_out = (Yaminusc - Xbminusd);
-      /* (xa + xc) - (xb + xd) */
-      Xc12C_out = (Xaplusc - Xbplusd);
-      /* (ya + yc) - (yb + yd) */
-      Yc12C_out = (Yaplusc - Ybplusd);
-      /* (xa - xc) - (yb - yd) */
-      Xd12C_out = (Xaminusc - Ybminusd);
-      /* (ya - yc) + (xb - xd) */
-      Yd12C_out = (Xbminusd + Yaminusc);
-
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-
-      /*  index calculation for the coefficients */
-      ia3 = ia2 + ia1;
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      Xb12_out = Xb12C_out * co1;
-      Yb12_out = Yb12C_out * co1;
-      Xc12_out = Xc12C_out * co2;
-      Yc12_out = Yc12C_out * co2;
-      Xd12_out = Xd12C_out * co3;
-      Yd12_out = Yd12C_out * co3;
-         
-      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-      //Xb12_out -= Yb12C_out * si1;
-      p0 = Yb12C_out * si1;
-      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-      //Yb12_out += Xb12C_out * si1;
-      p1 = Xb12C_out * si1;
-      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-      //Xc12_out -= Yc12C_out * si2;
-      p2 = Yc12C_out * si2;
-      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-      //Yc12_out += Xc12C_out * si2;
-      p3 = Xc12C_out * si2;
-      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-      //Xd12_out -= Yd12C_out * si3;
-      p4 = Yd12C_out * si3;
-      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-      //Yd12_out += Xd12C_out * si3;
-      p5 = Xd12C_out * si3;
-      
-      Xb12_out += p0;
-      Yb12_out -= p1;
-      Xc12_out += p2;
-      Yc12_out -= p3;
-      Xd12_out += p4;
-      Yd12_out -= p5;
-
-      /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-      pSrc[2u * i1] = Xc12_out;
-
-      /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-      pSrc[(2u * i1) + 1u] = Yc12_out;
-
-      /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-      pSrc[2u * i2] = Xb12_out;
-
-      /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-      pSrc[(2u * i2) + 1u] = Yb12_out;
-
-      /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-      pSrc[2u * i3] = Xd12_out;
-
-      /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-      pSrc[(2u * i3) + 1u] = Yd12_out;
-
-      /*  Twiddle coefficients index modifier */
-      ia1 += twidCoefModifier;
-
-      /*  Updating input index */
-      i0++;
-
-   }
-   while(--j);
-
-   twidCoefModifier <<= 2u;
-
-   /*  Calculation of second stage to excluding last stage */
-   for (k = fftLen >> 2u; k > 4u; k >>= 2u)
-   {
-      /*  Initializations for the first stage */
-      n1 = n2;
-      n2 >>= 2u;
-      ia1 = 0u;
-
-      /*  Calculation of first stage */
-      j = 0;
-      do
-      {
-         /*  index calculation for the coefficients */
-         ia2 = ia1 + ia1;
-         ia3 = ia2 + ia1;
-         co1 = pCoef[ia1 * 2u];
-         si1 = pCoef[(ia1 * 2u) + 1u];
-         co2 = pCoef[ia2 * 2u];
-         si2 = pCoef[(ia2 * 2u) + 1u];
-         co3 = pCoef[ia3 * 2u];
-         si3 = pCoef[(ia3 * 2u) + 1u];
-
-         /*  Twiddle coefficients index modifier */
-         ia1 += twidCoefModifier;
-      
-         i0 = j;
-         do
-         {
-            /*  index calculation for the input as, */
-            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-            i1 = i0 + n2;
-            i2 = i1 + n2;
-            i3 = i2 + n2;
-
-            xaIn = pSrc[(2u * i0)];
-            yaIn = pSrc[(2u * i0) + 1u];
-
-            xbIn = pSrc[(2u * i1)];
-            ybIn = pSrc[(2u * i1) + 1u];
-
-            xcIn = pSrc[(2u * i2)];
-            ycIn = pSrc[(2u * i2) + 1u];
-
-            xdIn = pSrc[(2u * i3)];
-            ydIn = pSrc[(2u * i3) + 1u];
-
-            /* xa - xc */
-            Xaminusc = xaIn - xcIn;
-            /* (xb - xd) */
-            Xbminusd = xbIn - xdIn;
-            /* ya - yc */
-            Yaminusc = yaIn - ycIn;
-            /* (yb - yd) */
-            Ybminusd = ybIn - ydIn;
-
-            /* xa + xc */
-            Xaplusc = xaIn + xcIn;
-            /* xb + xd */
-            Xbplusd = xbIn + xdIn;
-            /* ya + yc */
-            Yaplusc = yaIn + ycIn;
-            /* yb + yd */
-            Ybplusd = ybIn + ydIn;
-
-            /* (xa - xc) + (yb - yd) */
-            Xb12C_out = (Xaminusc + Ybminusd);
-            /* (ya - yc) -  (xb - xd) */
-            Yb12C_out = (Yaminusc - Xbminusd);
-            /* xa + xc -(xb + xd) */
-            Xc12C_out = (Xaplusc - Xbplusd);
-            /* (ya + yc) - (yb + yd) */
-            Yc12C_out = (Yaplusc - Ybplusd);
-            /* (xa - xc) - (yb - yd) */
-            Xd12C_out = (Xaminusc - Ybminusd);
-            /* (ya - yc) +  (xb - xd) */
-            Yd12C_out = (Xbminusd + Yaminusc);
-
-            pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-            Xb12_out = Xb12C_out * co1;
-            Yb12_out = Yb12C_out * co1;
-            Xc12_out = Xc12C_out * co2;
-            Yc12_out = Yc12C_out * co2;
-            Xd12_out = Xd12C_out * co3;
-            Yd12_out = Yd12C_out * co3;
-         
-            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-            //Xb12_out -= Yb12C_out * si1;
-            p0 = Yb12C_out * si1;
-            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-            //Yb12_out += Xb12C_out * si1;
-            p1 = Xb12C_out * si1;
-            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-            //Xc12_out -= Yc12C_out * si2;
-            p2 = Yc12C_out * si2;
-            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-            //Yc12_out += Xc12C_out * si2;
-            p3 = Xc12C_out * si2;
-            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-            //Xd12_out -= Yd12C_out * si3;
-            p4 = Yd12C_out * si3;
-            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-            //Yd12_out += Xd12C_out * si3;
-            p5 = Xd12C_out * si3;
-            
-            Xb12_out += p0;
-            Yb12_out -= p1;
-            Xc12_out += p2;
-            Yc12_out -= p3;
-            Xd12_out += p4;
-            Yd12_out -= p5;
-
-            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-            pSrc[2u * i1] = Xc12_out;
-
-            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-            pSrc[(2u * i1) + 1u] = Yc12_out;
-
-            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-            pSrc[2u * i2] = Xb12_out;
-
-            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-            pSrc[(2u * i2) + 1u] = Yb12_out;
-
-            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-            pSrc[2u * i3] = Xd12_out;
-
-            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-            pSrc[(2u * i3) + 1u] = Yd12_out;
-
-            i0 += n1;
-         } while(i0 < fftLen);
-         j++;
-      } while(j <= (n2 - 1u));
-      twidCoefModifier <<= 2u;
-   }
-
-   j = fftLen >> 2;
-   ptr1 = &pSrc[0];
-
-   /*  Calculations of last stage */
-   do
-   {
-      xaIn = ptr1[0];
-      yaIn = ptr1[1];
-      xbIn = ptr1[2];
-      ybIn = ptr1[3];
-      xcIn = ptr1[4];
-      ycIn = ptr1[5];
-      xdIn = ptr1[6];
-      ydIn = ptr1[7];
-
-      /* xa + xc */
-      Xaplusc = xaIn + xcIn;
-
-      /* xa - xc */
-      Xaminusc = xaIn - xcIn;
-
-      /* ya + yc */
-      Yaplusc = yaIn + ycIn;
-
-      /* ya - yc */
-      Yaminusc = yaIn - ycIn;
-
-      /* xb + xd */
-      Xbplusd = xbIn + xdIn;
-
-      /* yb + yd */
-      Ybplusd = ybIn + ydIn;
-
-      /* (xb-xd) */
-      Xbminusd = xbIn - xdIn;
-
-      /* (yb-yd) */
-      Ybminusd = ybIn - ydIn;
-
-      /* xa' = xa + xb + xc + xd */
-      a0 = (Xaplusc + Xbplusd);
-      /* ya' = ya + yb + yc + yd */
-      a1 = (Yaplusc + Ybplusd);
-      /* xc' = (xa-xb+xc-xd) */
-      a2 = (Xaplusc - Xbplusd);
-      /* yc' = (ya-yb+yc-yd) */
-      a3 = (Yaplusc - Ybplusd);
-      /* xb' = (xa+yb-xc-yd) */
-      a4 = (Xaminusc + Ybminusd);
-      /* yb' = (ya-xb-yc+xd) */
-      a5 = (Yaminusc - Xbminusd);
-      /* xd' = (xa-yb-xc+yd)) */
-      a6 = (Xaminusc - Ybminusd);
-      /* yd' = (ya+xb-yc-xd) */
-      a7 = (Xbminusd + Yaminusc);
-   
-      ptr1[0] = a0;
-      ptr1[1] = a1;
-      ptr1[2] = a2;
-      ptr1[3] = a3;
-      ptr1[4] = a4;
-      ptr1[5] = a5;
-      ptr1[6] = a6;
-      ptr1[7] = a7;
-
-      /* increment pointer by 8 */
-      ptr1 += 8u;
-   } while(--j);
-
-#else
-
-   float32_t t1, t2, r1, r2, s1, s2;
-
-   /* Run the below code for Cortex-M0 */
-
-   /*  Initializations for the fft calculation */
-   n2 = fftLen;
-   n1 = n2;
-   for (k = fftLen; k > 1u; k >>= 2u)
-   {
-      /*  Initializations for the fft calculation */
-      n1 = n2;
-      n2 >>= 2u;
-      ia1 = 0u;
-
-      /*  FFT Calculation */
-      j = 0;
-      do
-      {
-         /*  index calculation for the coefficients */
-         ia2 = ia1 + ia1;
-         ia3 = ia2 + ia1;
-         co1 = pCoef[ia1 * 2u];
-         si1 = pCoef[(ia1 * 2u) + 1u];
-         co2 = pCoef[ia2 * 2u];
-         si2 = pCoef[(ia2 * 2u) + 1u];
-         co3 = pCoef[ia3 * 2u];
-         si3 = pCoef[(ia3 * 2u) + 1u];
-
-         /*  Twiddle coefficients index modifier */
-         ia1 = ia1 + twidCoefModifier;
-
-         i0 = j;
-         do
-         {
-            /*  index calculation for the input as, */
-            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-            i1 = i0 + n2;
-            i2 = i1 + n2;
-            i3 = i2 + n2;
-
-            /* xa + xc */
-            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
-            /* xa - xc */
-            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
-            /* ya + yc */
-            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-            /* ya - yc */
-            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-            /* xb + xd */
-            t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-            /* xa' = xa + xb + xc + xd */
-            pSrc[2u * i0] = r1 + t1;
-
-            /* xa + xc -(xb + xd) */
-            r1 = r1 - t1;
-
-            /* yb + yd */
-            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-            /* ya' = ya + yb + yc + yd */
-            pSrc[(2u * i0) + 1u] = s1 + t2;
-
-            /* (ya + yc) - (yb + yd) */
-            s1 = s1 - t2;
-
-            /* (yb - yd) */
-            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-            /* (xb - xd) */
-            t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-            /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-            pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
-
-            /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-            pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
-
-            /* (xa - xc) + (yb - yd) */
-            r1 = r2 + t1;
-
-            /* (xa - xc) - (yb - yd) */
-            r2 = r2 - t1;
-
-            /* (ya - yc) -  (xb - xd) */
-            s1 = s2 - t2;
-
-            /* (ya - yc) +  (xb - xd) */
-            s2 = s2 + t2;
-
-            /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-            pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
-
-            /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-            pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
-
-            /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-            pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
-
-            /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-            pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
-         
-            i0 += n1;
-         } while( i0 < fftLen);
-         j++;
-      } while(j <= (n2 - 1u));
-      twidCoefModifier <<= 2u;
-   }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
-
-}
-
-/*    
-* @brief  Core function for the floating-point CIFFT butterfly process.   
-* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
-* @param[in]      fftLen           length of the FFT.   
-* @param[in]      *pCoef           points to twiddle coefficient buffer.   
-* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @param[in]      onebyfftLen      value of 1/fftLen.   
-* @return none.   
-*/
-
-void arm_radix4_butterfly_inverse_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-float32_t * pCoef,
-uint16_t twidCoefModifier,
-float32_t onebyfftLen)
-{
-   float32_t co1, co2, co3, si1, si2, si3;
-   uint32_t ia1, ia2, ia3;
-   uint32_t i0, i1, i2, i3;
-   uint32_t n1, n2, j, k;
-
-#ifndef ARM_MATH_CM0_FAMILY_FAMILY
-
-   float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
-   float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
-   Ybminusd;
-   float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
-   float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
-   float32_t *ptr1;
-   float32_t p0,p1,p2,p3,p4,p5,p6,p7;
-   float32_t a0,a1,a2,a3,a4,a5,a6,a7;
-
-
-   /*  Initializations for the first stage */
-   n2 = fftLen;
-   n1 = n2;
-
-   /* n2 = fftLen/4 */
-   n2 >>= 2u;
-   i0 = 0u;
-   ia1 = 0u;
-
-   j = n2;
-
-   /*  Calculation of first stage */
-   do
-   {
-      /*  index calculation for the input as, */
-      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-      i1 = i0 + n2;
-      i2 = i1 + n2;
-      i3 = i2 + n2;
-
-      /*  Butterfly implementation */
-      xaIn = pSrc[(2u * i0)];
-      yaIn = pSrc[(2u * i0) + 1u];
-
-      xcIn = pSrc[(2u * i2)];
-      ycIn = pSrc[(2u * i2) + 1u];
-
-      xbIn = pSrc[(2u * i1)];
-      ybIn = pSrc[(2u * i1) + 1u];
-
-      xdIn = pSrc[(2u * i3)];
-      ydIn = pSrc[(2u * i3) + 1u];
-
-      /* xa + xc */
-      Xaplusc = xaIn + xcIn;
-      /* xb + xd */
-      Xbplusd = xbIn + xdIn;
-      /* ya + yc */
-      Yaplusc = yaIn + ycIn;
-      /* yb + yd */
-      Ybplusd = ybIn + ydIn;
-
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-
-      /* xa - xc */
-      Xaminusc = xaIn - xcIn;
-      /* xb - xd */
-      Xbminusd = xbIn - xdIn;
-      /* ya - yc */
-      Yaminusc = yaIn - ycIn;
-      /* yb - yd */
-      Ybminusd = ybIn - ydIn;
-
-      /* xa' = xa + xb + xc + xd */
-      pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-
-      /* ya' = ya + yb + yc + yd */
-      pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-      /* (xa - xc) - (yb - yd) */
-      Xb12C_out = (Xaminusc - Ybminusd);
-      /* (ya - yc) + (xb - xd) */
-      Yb12C_out = (Yaminusc + Xbminusd);
-      /* (xa + xc) - (xb + xd) */
-      Xc12C_out = (Xaplusc - Xbplusd);
-      /* (ya + yc) - (yb + yd) */
-      Yc12C_out = (Yaplusc - Ybplusd);
-      /* (xa - xc) + (yb - yd) */
-      Xd12C_out = (Xaminusc + Ybminusd);
-      /* (ya - yc) - (xb - xd) */
-      Yd12C_out = (Yaminusc - Xbminusd);
-
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-
-      /*  index calculation for the coefficients */
-      ia3 = ia2 + ia1;
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      Xb12_out = Xb12C_out * co1;
-      Yb12_out = Yb12C_out * co1;
-      Xc12_out = Xc12C_out * co2;
-      Yc12_out = Yc12C_out * co2;
-      Xd12_out = Xd12C_out * co3;
-      Yd12_out = Yd12C_out * co3;
-   
-      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-      //Xb12_out -= Yb12C_out * si1;
-      p0 = Yb12C_out * si1;
-      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-      //Yb12_out += Xb12C_out * si1;
-      p1 = Xb12C_out * si1;
-      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-      //Xc12_out -= Yc12C_out * si2;
-      p2 = Yc12C_out * si2;
-      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-      //Yc12_out += Xc12C_out * si2;
-      p3 = Xc12C_out * si2;
-      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-      //Xd12_out -= Yd12C_out * si3;
-      p4 = Yd12C_out * si3;
-      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-      //Yd12_out += Xd12C_out * si3;
-      p5 = Xd12C_out * si3;
-      
-      Xb12_out -= p0;
-      Yb12_out += p1;
-      Xc12_out -= p2;
-      Yc12_out += p3;
-      Xd12_out -= p4;
-      Yd12_out += p5;
-
-      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-      pSrc[2u * i1] = Xc12_out;
-
-      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-      pSrc[(2u * i1) + 1u] = Yc12_out;
-
-      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-      pSrc[2u * i2] = Xb12_out;
-
-      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-      pSrc[(2u * i2) + 1u] = Yb12_out;
-
-      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-      pSrc[2u * i3] = Xd12_out;
-
-      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-      pSrc[(2u * i3) + 1u] = Yd12_out;
-
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      /*  Updating input index */
-      i0 = i0 + 1u;
-
-   } while(--j);
-
-   twidCoefModifier <<= 2u;
-
-   /*  Calculation of second stage to excluding last stage */
-   for (k = fftLen >> 2u; k > 4u; k >>= 2u)
-   {
-      /*  Initializations for the first stage */
-      n1 = n2;
-      n2 >>= 2u;
-      ia1 = 0u;
-
-      /*  Calculation of first stage */
-      j = 0;
-      do
-      {
-         /*  index calculation for the coefficients */
-         ia2 = ia1 + ia1;
-         ia3 = ia2 + ia1;
-         co1 = pCoef[ia1 * 2u];
-         si1 = pCoef[(ia1 * 2u) + 1u];
-         co2 = pCoef[ia2 * 2u];
-         si2 = pCoef[(ia2 * 2u) + 1u];
-         co3 = pCoef[ia3 * 2u];
-         si3 = pCoef[(ia3 * 2u) + 1u];
-
-         /*  Twiddle coefficients index modifier */
-         ia1 = ia1 + twidCoefModifier;
-
-         i0 = j;
-         do
-         {
-            /*  index calculation for the input as, */
-            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-            i1 = i0 + n2;
-            i2 = i1 + n2;
-            i3 = i2 + n2;
-
-            xaIn = pSrc[(2u * i0)];
-            yaIn = pSrc[(2u * i0) + 1u];
-
-            xbIn = pSrc[(2u * i1)];
-            ybIn = pSrc[(2u * i1) + 1u];
-
-            xcIn = pSrc[(2u * i2)];
-            ycIn = pSrc[(2u * i2) + 1u];
-
-            xdIn = pSrc[(2u * i3)];
-            ydIn = pSrc[(2u * i3) + 1u];
-
-            /* xa - xc */
-            Xaminusc = xaIn - xcIn;
-            /* (xb - xd) */
-            Xbminusd = xbIn - xdIn;
-            /* ya - yc */
-            Yaminusc = yaIn - ycIn;
-            /* (yb - yd) */
-            Ybminusd = ybIn - ydIn;
-
-            /* xa + xc */
-            Xaplusc = xaIn + xcIn;
-            /* xb + xd */
-            Xbplusd = xbIn + xdIn;
-            /* ya + yc */
-            Yaplusc = yaIn + ycIn;
-            /* yb + yd */
-            Ybplusd = ybIn + ydIn;
-
-            /* (xa - xc) - (yb - yd) */
-            Xb12C_out = (Xaminusc - Ybminusd);
-            /* (ya - yc) +  (xb - xd) */
-            Yb12C_out = (Yaminusc + Xbminusd);
-            /* xa + xc -(xb + xd) */
-            Xc12C_out = (Xaplusc - Xbplusd);
-            /* (ya + yc) - (yb + yd) */
-            Yc12C_out = (Yaplusc - Ybplusd);
-            /* (xa - xc) + (yb - yd) */
-            Xd12C_out = (Xaminusc + Ybminusd);
-            /* (ya - yc) -  (xb - xd) */
-            Yd12C_out = (Yaminusc - Xbminusd);
-
-            pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-            pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-            Xb12_out = Xb12C_out * co1;
-            Yb12_out = Yb12C_out * co1;
-            Xc12_out = Xc12C_out * co2;
-            Yc12_out = Yc12C_out * co2;
-            Xd12_out = Xd12C_out * co3;
-            Yd12_out = Yd12C_out * co3;
-
-            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-            //Xb12_out -= Yb12C_out * si1;
-            p0 = Yb12C_out * si1;
-            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-            //Yb12_out += Xb12C_out * si1;
-            p1 = Xb12C_out * si1;
-            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-            //Xc12_out -= Yc12C_out * si2;
-            p2 = Yc12C_out * si2;
-            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-            //Yc12_out += Xc12C_out * si2;
-            p3 = Xc12C_out * si2;
-            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-            //Xd12_out -= Yd12C_out * si3;
-            p4 = Yd12C_out * si3;
-            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-            //Yd12_out += Xd12C_out * si3;
-            p5 = Xd12C_out * si3;
-            
-            Xb12_out -= p0;
-            Yb12_out += p1;
-            Xc12_out -= p2;
-            Yc12_out += p3;
-            Xd12_out -= p4;
-            Yd12_out += p5;
-
-            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-            pSrc[2u * i1] = Xc12_out;
-
-            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-            pSrc[(2u * i1) + 1u] = Yc12_out;
-
-            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-            pSrc[2u * i2] = Xb12_out;
-
-            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-            pSrc[(2u * i2) + 1u] = Yb12_out;
-
-            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-            pSrc[2u * i3] = Xd12_out;
-
-            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-            pSrc[(2u * i3) + 1u] = Yd12_out;
-
-            i0 += n1;
-         } while(i0 < fftLen);
-         j++;
-      } while(j <= (n2 - 1u));
-      twidCoefModifier <<= 2u;
-   }
-   /*  Initializations of last stage */
-
-   j = fftLen >> 2;
-   ptr1 = &pSrc[0];
-
-   /*  Calculations of last stage */
-   do
-   {
-      xaIn = ptr1[0];
-      yaIn = ptr1[1];
-      xbIn = ptr1[2];
-      ybIn = ptr1[3];
-      xcIn = ptr1[4];
-      ycIn = ptr1[5];
-      xdIn = ptr1[6];
-      ydIn = ptr1[7];
-
-      /*  Butterfly implementation */
-      /* xa + xc */
-      Xaplusc = xaIn + xcIn;
-
-      /* xa - xc */
-      Xaminusc = xaIn - xcIn;
-
-      /* ya + yc */
-      Yaplusc = yaIn + ycIn;
-
-      /* ya - yc */
-      Yaminusc = yaIn - ycIn;
-
-      /* xb + xd */
-      Xbplusd = xbIn + xdIn;
-
-      /* yb + yd */
-      Ybplusd = ybIn + ydIn;
-
-      /* (xb-xd) */
-      Xbminusd = xbIn - xdIn;
-
-      /* (yb-yd) */
-      Ybminusd = ybIn - ydIn;
-      
-      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
-      a0 = (Xaplusc + Xbplusd);
-      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
-      a1 = (Yaplusc + Ybplusd);
-      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
-      a2 = (Xaplusc - Xbplusd);
-      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
-      a3 = (Yaplusc - Ybplusd);
-      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
-      a4 = (Xaminusc - Ybminusd);
-      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
-      a5 = (Yaminusc + Xbminusd);
-      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
-      a6 = (Xaminusc + Ybminusd);
-      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
-      a7 = (Yaminusc - Xbminusd);
-   
-      p0 = a0 * onebyfftLen;
-      p1 = a1 * onebyfftLen;
-      p2 = a2 * onebyfftLen;
-      p3 = a3 * onebyfftLen;
-      p4 = a4 * onebyfftLen;
-      p5 = a5 * onebyfftLen;
-      p6 = a6 * onebyfftLen;
-      p7 = a7 * onebyfftLen;
-   
-      /* xa' = (xa+xb+xc+xd) * onebyfftLen */
-      ptr1[0] = p0;
-      /* ya' = (ya+yb+yc+yd) * onebyfftLen */
-      ptr1[1] = p1;
-      /* xc' = (xa-xb+xc-xd) * onebyfftLen */
-      ptr1[2] = p2;
-      /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
-      ptr1[3] = p3;
-      /* xb' = (xa-yb-xc+yd) * onebyfftLen */
-      ptr1[4] = p4;
-      /* yb' = (ya+xb-yc-xd) * onebyfftLen */
-      ptr1[5] = p5;
-      /* xd' = (xa-yb-xc+yd) * onebyfftLen */
-      ptr1[6] = p6;
-      /* yd' = (ya-xb-yc+xd) * onebyfftLen */
-      ptr1[7] = p7;
-
-      /* increment source pointer by 8 for next calculations */
-      ptr1 = ptr1 + 8u;
-
-   } while(--j);
-
-#else
-
-   float32_t t1, t2, r1, r2, s1, s2;
-
-   /* Run the below code for Cortex-M0 */
-
-   /*  Initializations for the first stage */
-   n2 = fftLen;
-   n1 = n2;
-
-   /*  Calculation of first stage */
-   for (k = fftLen; k > 4u; k >>= 2u)
-   {
-      /*  Initializations for the first stage */
-      n1 = n2;
-      n2 >>= 2u;
-      ia1 = 0u;
-
-      /*  Calculation of first stage */
-      j = 0;
-      do
-      {
-         /*  index calculation for the coefficients */
-         ia2 = ia1 + ia1;
-         ia3 = ia2 + ia1;
-         co1 = pCoef[ia1 * 2u];
-         si1 = pCoef[(ia1 * 2u) + 1u];
-         co2 = pCoef[ia2 * 2u];
-         si2 = pCoef[(ia2 * 2u) + 1u];
-         co3 = pCoef[ia3 * 2u];
-         si3 = pCoef[(ia3 * 2u) + 1u];
-
-         /*  Twiddle coefficients index modifier */
-         ia1 = ia1 + twidCoefModifier;
-
-         i0 = j;
-         do
-         {
-            /*  index calculation for the input as, */
-            /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-            i1 = i0 + n2;
-            i2 = i1 + n2;
-            i3 = i2 + n2;
-
-            /* xa + xc */
-            r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
-            /* xa - xc */
-            r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
-            /* ya + yc */
-            s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-            /* ya - yc */
-            s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-            /* xb + xd */
-            t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-            /* xa' = xa + xb + xc + xd */
-            pSrc[2u * i0] = r1 + t1;
-
-            /* xa + xc -(xb + xd) */
-            r1 = r1 - t1;
-
-            /* yb + yd */
-            t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-            /* ya' = ya + yb + yc + yd */
-            pSrc[(2u * i0) + 1u] = s1 + t2;
-
-            /* (ya + yc) - (yb + yd) */
-            s1 = s1 - t2;
-
-            /* (yb - yd) */
-            t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-            /* (xb - xd) */
-            t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-            /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-            pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
-
-            /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-            pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
-
-            /* (xa - xc) - (yb - yd) */
-            r1 = r2 - t1;
-
-            /* (xa - xc) + (yb - yd) */
-            r2 = r2 + t1;
-
-            /* (ya - yc) +  (xb - xd) */
-            s1 = s2 + t2;
-
-            /* (ya - yc) -  (xb - xd) */
-            s2 = s2 - t2;
-
-            /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-            pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
-
-            /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-            pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
-
-            /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-            pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
-
-            /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-            pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
-         
-            i0 += n1;
-         } while( i0 < fftLen);
-         j++;
-      } while(j <= (n2 - 1u));
-      twidCoefModifier <<= 2u;
-   }
-   /*  Initializations of last stage */
-   n1 = n2;
-   n2 >>= 2u;
-
-   /*  Calculations of last stage */
-   for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-   {
-      /*  index calculation for the input as, */
-      /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-      i1 = i0 + n2;
-      i2 = i1 + n2;
-      i3 = i2 + n2;
-
-      /*  Butterfly implementation */
-      /* xa + xc */
-      r1 = pSrc[2u * i0] + pSrc[2u * i2];
-
-      /* xa - xc */
-      r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-      /* ya + yc */
-      s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-      /* ya - yc */
-      s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-      /* xc + xd */
-      t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-      /* xa' = xa + xb + xc + xd */
-      pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
-
-      /* (xa + xb) - (xc + xd) */
-      r1 = r1 - t1;
-
-      /* yb + yd */
-      t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-      /* ya' = ya + yb + yc + yd */
-      pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
-
-      /* (ya + yc) - (yb + yd) */
-      s1 = s1 - t2;
-
-      /* (yb-yd) */
-      t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-      /* (xb-xd) */
-      t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-      /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-      pSrc[2u * i1] = r1 * onebyfftLen;
-
-      /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-      pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
-
-      /* (xa - xc) - (yb-yd) */
-      r1 = r2 - t1;
-
-      /* (xa - xc) + (yb-yd) */
-      r2 = r2 + t1;
-
-      /* (ya - yc) + (xb-xd) */
-      s1 = s2 + t2;
-
-      /* (ya - yc) - (xb-xd) */
-      s2 = s2 - t2;
-
-      /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-      pSrc[2u * i2] = r1 * onebyfftLen;
-
-      /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-      pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
-
-      /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-      pSrc[2u * i3] = r2 * onebyfftLen;
-
-      /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-      pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
-   }
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
-}
-
-/**    
-* @addtogroup ComplexFFT    
-* @{    
-*/
-
-/**    
-* @details    
-* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.   
-* @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
-* @return none.   
-*/
-
-void arm_cfft_radix4_f32(
-const arm_cfft_radix4_instance_f32 * S,
-float32_t * pSrc)
-{
-
-   if(S->ifftFlag == 1u)
-   {
-      /*  Complex IFFT radix-4  */
-      arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
-      S->twidCoefModifier, S->onebyfftLen);
-   }
-   else
-   {
-      /*  Complex FFT radix-4  */
-      arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
-      S->twidCoefModifier);
-   }
-
-   if(S->bitReverseFlag == 1u)
-   {
-      /*  Bit Reversal */
-      arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-   }
-
-}
-
-/**    
-* @} end of ComplexFFT group    
-*/
-
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
deleted file mode 100644
index 1e1ad7ca..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_f32.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-/**    
-* @brief  Initialization function for the floating-point CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superceded by \ref arm_cfft_f32 and will be removed
-* in the future.
-* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (float32_t *) twiddleCoef;
-
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.000244140625;
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.0009765625f;
-    break;
-
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    S->onebyfftLen = 0.00390625f;
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    S->onebyfftLen = 0.015625f;
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    S->onebyfftLen = 0.0625f;
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
deleted file mode 100644
index 7f29d675..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_q15.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-
-/**    
-* @brief Initialization function for the Q15 CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
-* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q15_t *) twiddleCoef_4096_q15;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-    S->twidCoefModifier = 4u;
-    S->bitRevFactor = 4u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
deleted file mode 100644
index a375a5f5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5   
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_q31.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-/**    
-*    
-* @brief  Initialization function for the Q31 CFFT/CIFFT.   
-* @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
-* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q31_t *) twiddleCoef_4096_q31;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of Instance structure depending on the FFT length */
-  switch (S->fftLen)
-  {
-    /*  Initializations of structure parameters for 4096 point FFT */
-  case 4096u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    break;
-
-    /*  Initializations of structure parameters for 1024 point FFT */
-  case 1024u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
deleted file mode 100644
index 761e43e1..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
+++ /dev/null
@@ -1,1924 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_q15.c    
-*    
-* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
-*				In-place bit reversal using bit reversal table    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-
-void arm_radix4_butterfly_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier);
-
-void arm_radix4_butterfly_inverse_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier);
-
-void arm_bitreversal_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab);
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-
-/**    
- * @details    
- * @brief Processing function for the Q15 CFFT/CIFFT.   
- * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q15 and will be removed
- * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.   
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.   
- * @return none.   
- *     
- * \par Input and output formats:    
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
- * Hence the output format is different for different FFT sizes.    
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
- * \par   
- * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"    
- * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"    
- */
-
-void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc)
-{
-  if(S->ifftFlag == 1u)
-  {
-    /*  Complex IFFT radix-4  */
-    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier);
-  }
-  else
-  {
-    /*  Complex FFT radix-4  */
-    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
-
-/*    
-* Radix-4 FFT algorithm used is :    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 FFT:    
-* Wn = co1 + j * (- si1)    
-* W2n = co2 + j * (- si2)    
-* W3n = co3 + j * (- si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
-*    
-*/
-
-/**    
- * @brief  Core function for the Q15 CFFT butterfly process.   
- * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t R, S, T, U;
-  q31_t C1, C2, C3, out1, out2;
-  uint32_t n1, n2, ic, i0, j, k;
-
-  q15_t *ptr1;
-  q15_t *pSi0;
-  q15_t *pSi1;
-  q15_t *pSi2;
-  q15_t *pSi3;
-
-  q31_t xaya, xbyb, xcyc, xdyd;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  j = n2;
-  
-  pSi0 = pSrc16;
-  pSi1 = pSi0 + 2 * n2;
-  pSi2 = pSi1 + 2 * n2;
-  pSi3 = pSi2 + 2 * n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T = _SIMD32_OFFSET(pSi0);
-    T = __SHADD16(T, 0); // this is just a SIMD arithmetic shift right by 1
-    T = __SHADD16(T, 0); // it turns out doing this twice is 2 cycles, the alternative takes 3 cycles
-    //in = ((int16_t) (T & 0xFFFF)) >> 2;       // alternative code that takes 3 cycles
-    //T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* Read yc (real), xc(imag) input */
-    S = _SIMD32_OFFSET(pSi2);
-    S = __SHADD16(S, 0);
-    S = __SHADD16(S, 0);
-
-    /* R = packed((ya + yc), (xa + xc) ) */
-    R = __QADD16(T, S);
-
-    /* S = packed((ya - yc), (xa - xc) ) */
-    S = __QSUB16(T, S);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T = _SIMD32_OFFSET(pSi1);
-    T = __SHADD16(T, 0);
-    T = __SHADD16(T, 0);
-
-    /* Read yd (real), xd(imag) input */
-    U = _SIMD32_OFFSET(pSi3);
-    U = __SHADD16(U, 0);
-    U = __SHADD16(U, 0);
-
-    /* T = packed((yb + yd), (xb + xd) ) */
-    T = __QADD16(T, U);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
-    pSi0 += 2;
-
-    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
-    R = __QSUB16(R, T);
-
-    /* co2 & si2 are read from SIMD Coefficient pointer */
-    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = __SMUAD(C2, R) >> 16u;
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = __SMUSDX(C2, R);
-
-#else
-
-    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out1 = __SMUSDX(R, C2) >> 16u;
-    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out2 = __SMUAD(C2, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /*  Reading i0+fftLen/4 */
-    /* T = packed(yb, xb) */
-    T = _SIMD32_OFFSET(pSi1);
-    T = __SHADD16(T, 0);
-    T = __SHADD16(T, 0);
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    _SIMD32_OFFSET(pSi1) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-    pSi1 += 2;
-
-    /*  Butterfly calculations */
-    /* U = packed(yd, xd) */
-    U = _SIMD32_OFFSET(pSi3);
-    U = __SHADD16(U, 0);
-    U = __SHADD16(U, 0);
-
-    /* T = packed(yb-yd, xb-xd) */
-    T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QASX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QSAX(S, T);
-
-#else
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QSAX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QASX(S, T);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* co1 & si1 are read from SIMD Coefficient pointer */
-    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-    /*  Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = __SMUAD(C1, S) >> 16u;
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = __SMUSDX(C1, S);
-
-#else
-
-    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out1 = __SMUSDX(S, C1) >> 16u;
-    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out2 = __SMUAD(C1, S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xb', yb') in little endian format */
-    _SIMD32_OFFSET(pSi2) =
-      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
-    pSi2 += 2;
-
-
-    /* co3 & si3 are read from SIMD Coefficient pointer */
-    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = __SMUAD(C3, R) >> 16u;
-    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = __SMUSDX(C3, R);
-
-#else
-
-    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out1 = __SMUSDX(R, C3) >> 16u;
-    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out2 = __SMUAD(C3, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xd', yd') in little endian format */
-    _SIMD32_OFFSET(pSi3) =
-      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-    pSi3 += 2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-      
-      pSi0 = pSrc16 + 2 * j;
-      pSi1 = pSi0 + 2 * n2;
-      pSi2 = pSi1 + 2 * n2;
-      pSi3 = pSi2 + 2 * n2;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T = _SIMD32_OFFSET(pSi0);
-
-        /* Read yc (real), xc(imag) input */
-        S = _SIMD32_OFFSET(pSi2);
-
-        /* R = packed( (ya + yc), (xa + xc)) */
-        R = __QADD16(T, S);
-
-        /* S = packed((ya - yc), (xa - xc)) */
-        S = __QSUB16(T, S);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSi1);
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSi3);
-
-        /* T = packed( (yb + yd), (xb + xd)) */
-        T = __QADD16(T, U);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = __SHADD16(R, T);
-        out1 = __SHADD16(out1, 0);
-        _SIMD32_OFFSET(pSi0) = out1;
-        pSi0 += 2 * n1;
-
-        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
-        R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = __SMUAD(C2, R) >> 16u;
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = __SMUSDX(C2, R);
-
-#else
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out1 = __SMUSDX(R, C2) >> 16u;
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out2 = __SMUAD(C2, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSi1);
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        _SIMD32_OFFSET(pSi1) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi1 += 2 * n1;
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSi3);
-
-        /* T = packed(yb-yd, xb-xd) */
-        T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHASX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHSAX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUAD(C1, S) >> 16u;
-        out2 = __SMUSDX(C1, S);
-
-#else
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHSAX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHASX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUSDX(S, C1) >> 16u;
-        out2 = __SMUAD(C1, S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        _SIMD32_OFFSET(pSi2) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi2 += 2 * n1;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(C3, R) >> 16u;
-        out2 = __SMUSDX(C3, R);
-
-#else
-
-        out1 = __SMUSDX(R, C3) >> 16u;
-        out2 = __SMUAD(C3, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-        _SIMD32_OFFSET(pSi3) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi3 += 2 * n1;
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-
-  ptr1 = &pSrc16[0];
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  do
-  {
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD32(ptr1)++;
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD32(ptr1)++;
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD32(ptr1)++;
-
-    /* Read xd (real), yd(imag) input */
-    xdyd = *__SIMD32(ptr1)++;
-
-    /* R = packed((ya + yc), (xa + xc)) */
-    R = __QADD16(xaya, xcyc);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
-    /* S = packed((ya - yc), (xa - xc)) */
-    S = __QSUB16(xaya, xcyc);
-
-    /* Read yd (real), xd(imag) input */
-    /* T = packed( (yb - yd), (xb - xd))  */
-    U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-#else
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-  } while(--j);
-
-  /* end of last stage process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
-  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u] >> 2u;
-    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u] >> 2u;
-    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
-    /* R0 = (ya + yc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    /* R1 = (xa + xc) */
-    R1 = __SSAT(T1 + S1, 16u);
-
-    /* S0 = (ya - yc) */
-    S0 = __SSAT(T0 - S0, 16);
-    /* S1 = (xa - xc) */
-    S1 = __SSAT(T1 - S1, 16);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
-
-    /* T0 = (yb + yd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    /* T1 = (xb + xd) */
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* ya' = ya + yb + yc + yd */
-    /* xa' = xa + xb + xc + xd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd) */
-    /* R1 = (xa + xc) - (xb + xd) */
-    R0 = __SSAT(R0 - T0, 16u);
-    R1 = __SSAT(R1 - T1, 16u);
-
-    /* co2 & si2 are read from Coefficient pointer */
-    Co2 = pCoef16[2u * ic * 2u];
-    Si2 = pCoef16[(2u * ic * 2u) + 1];
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
-    /*  Reading i0+fftLen/4 */
-    /* input is down scale by 4 to avoid overflow */
-    /* T0 = yb, T1 =  xb */
-    T0 = pSrc16[i1 * 2u] >> 2;
-    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    pSrc16[i1 * 2u] = out1;
-    pSrc16[(i1 * 2u) + 1] = out2;
-
-    /*  Butterfly calculations */
-    /* input is down scale by 4 to avoid overflow */
-    /* U0 = yd, U1 = xd */
-    U0 = pSrc16[i3 * 2u] >> 2;
-    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
-    /* T0 = yb-yd */
-    T0 = __SSAT(T0 - U0, 16);
-    /* T1 = xb-xd */
-    T1 = __SSAT(T1 - U1, 16);
-
-    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
-    R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
-    R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
-
-    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
-    S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16u);
-    S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16u);
-
-    /* co1 & si1 are read from Coefficient pointer */
-    Co1 = pCoef16[ic * 2u];
-    Si1 = pCoef16[(ic * 2u) + 1];
-    /*  Butterfly process for the i0+fftLen/2 sample */
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16);
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16);
-
-    /* writing output(xb', yb') in little endian format */
-    pSrc16[i2 * 2u] = out1;
-    pSrc16[(i2 * 2u) + 1] = out2;
-
-    /* Co3 & si3 are read from Coefficient pointer */
-    Co3 = pCoef16[3u * (ic * 2u)];
-    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
-    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
-    /* writing output(xd', yd') in little endian format */
-    pSrc16[i3 * 2u] = out1;
-    pSrc16[(i3 * 2u) + 1] = out2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      Co1 = pCoef16[ic * 2u];
-      Si1 = pCoef16[(ic * 2u) + 1u];
-      Co2 = pCoef16[2u * (ic * 2u)];
-      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
-      Co3 = pCoef16[3u * (ic * 2u)];
-      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T0 = pSrc16[i0 * 2u];
-        T1 = pSrc16[(i0 * 2u) + 1u];
-
-        /* Read yc (real), xc(imag) input */
-        S0 = pSrc16[i2 * 2u];
-        S1 = pSrc16[(i2 * 2u) + 1u];
-
-        /* R0 = (ya + yc), R1 = (xa + xc) */
-        R0 = __SSAT(T0 + S0, 16);
-        R1 = __SSAT(T1 + S1, 16);
-
-        /* S0 = (ya - yc), S1 =(xa - xc) */
-        S0 = __SSAT(T0 - S0, 16);
-        S1 = __SSAT(T1 - S1, 16);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-
-        /* T0 = (yb + yd), T1 = (xb + xd) */
-        T0 = __SSAT(T0 + U0, 16);
-        T1 = __SSAT(T1 + U1, 16);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
-        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
-        pSrc16[i0 * 2u] = out1;
-        pSrc16[(2u * i0) + 1u] = out2;
-
-        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-        R0 = (R0 >> 1u) - (T0 >> 1u);
-        R1 = (R1 >> 1u) - (T1 >> 1u);
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16u);
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        pSrc16[i1 * 2u] = out1;
-        pSrc16[(i1 * 2u) + 1u] = out2;
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = yb-yd, T1 = xb-xd */
-        T0 = __SSAT(T0 - U0, 16);
-        T1 = __SSAT(T1 - U1, 16);
-
-        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
-        R0 = (S0 >> 1u) - (T1 >> 1u);
-        R1 = (S1 >> 1u) + (T0 >> 1u);
-
-        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
-        S0 = (S0 >> 1u) + (T1 >> 1u);
-        S1 = (S1 >> 1u) - (T0 >> 1u);
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16u);
-
-        out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16u);
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        pSrc16[i2 * 2u] = out1;
-        pSrc16[(i2 * 2u) + 1u] = out2;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-        out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16u);
-
-        out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16u);
-        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
-        pSrc16[i3 * 2u] = out1;
-        pSrc16[(i3 * 2u) + 1u] = out2;
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  n1 = n2;
-  n2 >>= 2u;
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u];
-    T1 = pSrc16[(i0 * 2u) + 1u];
-
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u];
-    S1 = pSrc16[(i2 * 2u) + 1u];
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-
-    /* T0 = (yb + yd), T1 = (xb + xd)) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-    R0 = (R0 >> 1u) - (T0 >> 1u);
-    R1 = (R1 >> 1u) - (T1 >> 1u);
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-
-    /*  writing the butterfly processed i0 + fftLen/4 sample */
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    pSrc16[i1 * 2u] = R0;
-    pSrc16[(i1 * 2u) + 1u] = R1;
-
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-    /* T0 = (yb - yd), T1 = (xb - xd)  */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-
-    /*  writing the butterfly processed i0 + fftLen/2 sample */
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
-    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
-
-    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
-    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
-  }
-
-  /* end of last stage process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-
-/**    
- * @brief  Core function for the Q15 CIFFT butterfly process.   
- * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-/*    
-* Radix-4 IFFT algorithm used is :    
-*    
-* CIFFT uses same twiddle coefficients as CFFT function    
-*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
-*    
-*    
-* IFFT is implemented with following changes in equations from FFT    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 IFFT:    
-* Wn = co1 + j * (si1)    
-* W2n = co2 + j * (si2)    
-* W3n = co3 + j * (si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
-*    
-*/
-
-void arm_radix4_butterfly_inverse_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier)
-{
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t R, S, T, U;
-  q31_t C1, C2, C3, out1, out2;
-  uint32_t n1, n2, ic, i0, j, k;
-
-  q15_t *ptr1;
-  q15_t *pSi0;
-  q15_t *pSi1;
-  q15_t *pSi2;
-  q15_t *pSi3;
-
-  q31_t xaya, xbyb, xcyc, xdyd;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  j = n2;
-  
-  pSi0 = pSrc16;
-  pSi1 = pSi0 + 2 * n2;
-  pSi2 = pSi1 + 2 * n2;
-  pSi3 = pSi2 + 2 * n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T = _SIMD32_OFFSET(pSi0);
-    T = __SHADD16(T, 0);
-    T = __SHADD16(T, 0);
-
-    /* Read yc (real), xc(imag) input */
-    S = _SIMD32_OFFSET(pSi2);
-    S = __SHADD16(S, 0);
-    S = __SHADD16(S, 0);
-
-    /* R = packed((ya + yc), (xa + xc) ) */
-    R = __QADD16(T, S);
-
-    /* S = packed((ya - yc), (xa - xc) ) */
-    S = __QSUB16(T, S);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T = _SIMD32_OFFSET(pSi1);
-    T = __SHADD16(T, 0);
-    T = __SHADD16(T, 0);
-
-    /* Read yd (real), xd(imag) input */
-    U = _SIMD32_OFFSET(pSi3);
-    U = __SHADD16(U, 0);
-    U = __SHADD16(U, 0);
-
-    /* T = packed((yb + yd), (xb + xd) ) */
-    T = __QADD16(T, U);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    _SIMD32_OFFSET(pSi0) = __SHADD16(R, T);
-    pSi0 += 2;
-
-    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
-    R = __QSUB16(R, T);
-
-    /* co2 & si2 are read from SIMD Coefficient pointer */
-    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = __SMUSD(C2, R) >> 16u;
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = __SMUADX(C2, R);
-
-#else
-
-    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out1 = __SMUADX(C2, R) >> 16u;
-    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /*  Reading i0+fftLen/4 */
-    /* T = packed(yb, xb) */
-    T = _SIMD32_OFFSET(pSi1);
-    T = __SHADD16(T, 0);
-    T = __SHADD16(T, 0);
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    _SIMD32_OFFSET(pSi1) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-    pSi1 += 2;
-
-    /*  Butterfly calculations */
-    /* U = packed(yd, xd) */
-    U = _SIMD32_OFFSET(pSi3);
-    U = __SHADD16(U, 0);
-    U = __SHADD16(U, 0);
-
-    /* T = packed(yb-yd, xb-xd) */
-    T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QSAX(S, T);
-    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
-    S = __QASX(S, T);
-
-#else
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QASX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QSAX(S, T);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* co1 & si1 are read from SIMD Coefficient pointer */
-    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-    /*  Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = __SMUSD(C1, S) >> 16u;
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = __SMUADX(C1, S);
-
-#else
-
-    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out1 = __SMUADX(C1, S) >> 16u;
-    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xb', yb') in little endian format */
-    _SIMD32_OFFSET(pSi2) =
-      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
-    pSi2 += 2;
-
-
-    /* co3 & si3 are read from SIMD Coefficient pointer */
-    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = __SMUSD(C3, R) >> 16u;
-    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = __SMUADX(C3, R);
-
-#else
-
-    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out1 = __SMUADX(C3, R) >> 16u;
-    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xd', yd') in little endian format */
-    _SIMD32_OFFSET(pSi3) =
-      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-    pSi3 += 2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-      
-      pSi0 = pSrc16 + 2 * j;
-      pSi1 = pSi0 + 2 * n2;
-      pSi2 = pSi1 + 2 * n2;
-      pSi3 = pSi2 + 2 * n2;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T = _SIMD32_OFFSET(pSi0);
-
-        /* Read yc (real), xc(imag) input */
-        S = _SIMD32_OFFSET(pSi2);
-
-        /* R = packed( (ya + yc), (xa + xc)) */
-        R = __QADD16(T, S);
-
-        /* S = packed((ya - yc), (xa - xc)) */
-        S = __QSUB16(T, S);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSi1);
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSi3);
-
-        /* T = packed( (yb + yd), (xb + xd)) */
-        T = __QADD16(T, U);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = __SHADD16(R, T);
-        out1 = __SHADD16(out1, 0);
-        _SIMD32_OFFSET(pSi0) = out1;
-        pSi0 += 2 * n1;
-
-        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
-        R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = __SMUSD(C2, R) >> 16u;
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = __SMUADX(C2, R);
-
-#else
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out1 = __SMUADX(R, C2) >> 16u;
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSi1);
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        _SIMD32_OFFSET(pSi1) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi1 += 2 * n1;
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSi3);
-
-        /* T = packed(yb-yd, xb-xd) */
-        T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHSAX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHASX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUSD(C1, S) >> 16u;
-        out2 = __SMUADX(C1, S);
-
-#else
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHASX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHSAX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUADX(S, C1) >> 16u;
-        out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        _SIMD32_OFFSET(pSi2) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi2 += 2 * n1;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(C3, R) >> 16u;
-        out2 = __SMUADX(C3, R);
-
-#else
-
-        out1 = __SMUADX(C3, R) >> 16u;
-        out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-        _SIMD32_OFFSET(pSi3) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-        pSi3 += 2 * n1;
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-
-  ptr1 = &pSrc16[0];
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  do
-  {
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD32(ptr1)++;
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD32(ptr1)++;
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD32(ptr1)++;
-
-    /* Read xd (real), yd(imag) input */
-    xdyd = *__SIMD32(ptr1)++;
-
-    /* R = packed((ya + yc), (xa + xc)) */
-    R = __QADD16(xaya, xcyc);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
-    /* S = packed((ya - yc), (xa - xc)) */
-    S = __QSUB16(xaya, xcyc);
-
-    /* Read yd (real), xd(imag) input */
-    /* T = packed( (yb - yd), (xb - xd))  */
-    U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#else
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-  } while(--j);
-
-  /* end of last stage  process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
-  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  Start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u] >> 2u;
-    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u] >> 2u;
-    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-    /* Read yd (real), xd(imag) input */
-    /* input is down scale by 4 to avoid overflow */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
-    /* T0 = (yb + yd), T1 = (xb + xd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
-    R0 = __SSAT(R0 - T0, 16u);
-    R1 = __SSAT(R1 - T1, 16u);
-    /* co2 & si2 are read from Coefficient pointer */
-    Co2 = pCoef16[2u * ic * 2u];
-    Si2 = pCoef16[(2u * ic * 2u) + 1u];
-    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
-    out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16u);
-    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-    out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16u);
-
-    /*  Reading i0+fftLen/4 */
-    /* input is down scale by 4 to avoid overflow */
-    /* T0 = yb, T1 = xb */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    pSrc16[i1 * 2u] = out1;
-    pSrc16[(i1 * 2u) + 1u] = out2;
-
-    /*  Butterfly calculations */
-    /* input is down scale by 4 to avoid overflow */
-    /* U0 = yd, U1 = xd) */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
-    /* T0 = yb-yd, T1 = xb-xd) */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
-    R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16);
-    R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16);
-    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
-    S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16);
-    S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16);
-
-    /* co1 & si1 are read from Coefficient pointer */
-    Co1 = pCoef16[ic * 2u];
-    Si1 = pCoef16[(ic * 2u) + 1u];
-    /*  Butterfly process for the i0+fftLen/2 sample */
-    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
-    out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
-    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
-    out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
-    /* writing output(xb', yb') in little endian format */
-    pSrc16[i2 * 2u] = out1;
-    pSrc16[(i2 * 2u) + 1u] = out2;
-
-    /* Co3 & si3 are read from Coefficient pointer */
-    Co3 = pCoef16[3u * ic * 2u];
-    Si3 = pCoef16[(3u * ic * 2u) + 1u];
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
-    out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
-    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
-    out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
-    /* writing output(xd', yd') in little endian format */
-    pSrc16[i3 * 2u] = out1;
-    pSrc16[(i3 * 2u) + 1u] = out2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /*  End of first stage process */
-
-  /* data is in 4.11(q11) format */
-
-
-  /*  Start of Middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      Co1 = pCoef16[ic * 2u];
-      Si1 = pCoef16[(ic * 2u) + 1u];
-      Co2 = pCoef16[2u * ic * 2u];
-      Si2 = pCoef16[2u * ic * 2u + 1u];
-      Co3 = pCoef16[3u * ic * 2u];
-      Si3 = pCoef16[(3u * ic * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T0 = pSrc16[i0 * 2u];
-        T1 = pSrc16[(i0 * 2u) + 1u];
-
-        /* Read yc (real), xc(imag) input */
-        S0 = pSrc16[i2 * 2u];
-        S1 = pSrc16[(i2 * 2u) + 1u];
-
-
-        /* R0 = (ya + yc), R1 = (xa + xc) */
-        R0 = __SSAT(T0 + S0, 16u);
-        R1 = __SSAT(T1 + S1, 16u);
-        /* S0 = (ya - yc), S1 = (xa - xc) */
-        S0 = __SSAT(T0 - S0, 16u);
-        S1 = __SSAT(T1 - S1, 16u);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = (yb + yd), T1 = (xb + xd) */
-        T0 = __SSAT(T0 + U0, 16u);
-        T1 = __SSAT(T1 + U1, 16u);
-
-        /*  writing the butterfly processed i0 sample */
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
-        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
-        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-        R0 = (R0 >> 1u) - (T0 >> 1u);
-        R1 = (R1 >> 1u) - (T1 >> 1u);
-
-        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
-        out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16);
-        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-        out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16);
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-        pSrc16[i1 * 2u] = out1;
-        pSrc16[(i1 * 2u) + 1u] = out2;
-
-        /*  Butterfly calculations */
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = yb-yd, T1 = xb-xd) */
-        T0 = __SSAT(T0 - U0, 16u);
-        T1 = __SSAT(T1 - U1, 16u);
-
-        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
-        R0 = (S0 >> 1u) + (T1 >> 1u);
-        R1 = (S1 >> 1u) - (T0 >> 1u);
-
-        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
-        S0 = (S0 >> 1u) - (T1 >> 1u);
-        S1 = (S1 >> 1u) + (T0 >> 1u);
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16u);
-        out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16u);
-        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
-        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
-        pSrc16[i2 * 2u] = out1;
-        pSrc16[(i2 * 2u) + 1u] = out2;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-        out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16u);
-
-        out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16u);
-        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
-        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
-        pSrc16[i3 * 2u] = out1;
-        pSrc16[(i3 * 2u) + 1u] = out2;
-
-
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /*  End of Middle stages process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point   */
-  /* data is in 6.10(q10) format for the 64 point  */
-  /* data is in 4.12(q12) format for the 16 point  */
-
-  /* start of last stage process */
-
-
-  /*  Initializations for the last stage */
-  n1 = n2;
-  n2 >>= 2u;
-
-  /*  Butterfly implementation */
-  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u];
-    T1 = pSrc16[(i0 * 2u) + 1u];
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u];
-    S1 = pSrc16[(i2 * 2u) + 1u];
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-
-    /* T0 = (yb + yd), T1 = (xb + xd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-    R0 = (R0 >> 1u) - (T0 >> 1u);
-    R1 = (R1 >> 1u) - (T1 >> 1u);
-
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-
-    /*  writing the butterfly processed i0 + fftLen/4 sample */
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    pSrc16[i1 * 2u] = R0;
-    pSrc16[(i1 * 2u) + 1u] = R1;
-
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-    /* T0 = (yb - yd), T1 = (xb - xd) */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-
-    /*  writing the butterfly processed i0 + fftLen/2 sample */
-    /* xb' = (xa-yb-xc+yd) */
-    /* yb' = (ya+xb-yc-xd) */
-    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
-    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
-
-    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
-    /* xd' = (xa+yb-xc-yd) */
-    /* yd' = (ya-xb-yc+xd) */
-    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
-    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
-  }
-  /* end of last stage  process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
deleted file mode 100644
index 0fbb40b6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
+++ /dev/null
@@ -1,1404 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_q31.c    
-*    
-* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
-*				In-place bit reversal using bit reversal table    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-void arm_radix4_butterfly_inverse_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint32_t twidCoefModifier);
-
-void arm_radix4_butterfly_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-q31_t * pCoef,
-uint32_t twidCoefModifier);
-
-void arm_bitreversal_q31(
-q31_t * pSrc,
-uint32_t fftLen,
-uint16_t bitRevFactor,
-uint16_t * pBitRevTab);
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup ComplexFFT    
- * @{    
- */
-
-/**    
- * @details    
- * @brief Processing function for the Q31 CFFT/CIFFT.    
- * @deprecated Do not use this function.  It has been superseded by \ref arm_cfft_q31 and will be removed
- * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.   
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
- * @return none.    
- *     
- * \par Input and output formats:    
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
- * Hence the output format is different for different FFT sizes.    
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
- * \par   
- * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"    
- * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"    
- *    
- */
-
-void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc)
-{
-  if(S->ifftFlag == 1u)
-  {
-    /* Complex IFFT radix-4 */
-    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier);
-  }
-  else
-  {
-    /* Complex FFT radix-4 */
-    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-/**    
- * @} end of ComplexFFT group    
- */
-
-/*    
-* Radix-4 FFT algorithm used is :    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 FFT:    
-* Wn = co1 + j * (- si1)    
-* W2n = co2 + j * (- si2)    
-* W3n = co3 + j * (- si3)    
-*    
-*  Butterfly implementation:    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
-*    
-*/
-
-/**    
- * @brief  Core function for the Q31 CFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier)
-{
-#if defined(ARM_MATH_CM7)
-  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q63_t xaya, xbyb, xcyc, xdyd;
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-
-  /* start of first stage process */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  /*  Calculation of first stage */
-  do
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
-    /* xa - xc */
-    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
-    /* ya - yc */
-    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[2u * i0] = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
-
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
-    /* xb - xd */
-    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) + (yb - yd) */
-    r1 = r2 + t1;
-    /* (xa - xc) - (yb - yd) */
-    r2 = r2 - t1;
-
-    /* (ya - yc) - (xb - xd) */
-    s1 = s2 - t2;
-    /* (ya - yc) + (xb - xd) */
-    s2 = s2 + t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /* end of first stage process */
-
-  /* data is in 5.27(q27) format */
-
-
-  /* start of Middle stages process */
-
-
-  /* each stage in middle stages provides two down scaling of the input */
-
-  twidCoefModifier <<= 2u;
-
-
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSrc[2u * i0] + pSrc[2u * i2];
-        /* xa - xc */
-        r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
-
-        /* (xa - xc) + (yb - yd) */
-        r1 = r2 + t1;
-        /* (xa - xc) - (yb - yd) */
-        r2 = r2 - t1;
-
-        /* (ya - yc) -  (xb - xd) */
-        s1 = s2 - t2;
-        /* (ya - yc) +  (xb - xd) */
-        s2 = s2 + t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-#else
-  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q31_t *pSi0;
-  q31_t *pSi1;
-  q31_t *pSi2;
-  q31_t *pSi3;
-  q63_t xaya, xbyb, xcyc, xdyd;
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-
-  /* start of first stage process */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  ia1 = 0u;
-
-  j = n2;
-  
-  pSi0 = pSrc;
-  pSi1 = pSi0 + 2 * n2;
-  pSi2 = pSi1 + 2 * n2;
-  pSi3 = pSi2 + 2 * n2;
-
-  /*  Calculation of first stage */
-  do
-  {
-    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
-    /* xa - xc */
-    r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
-    /* ya - yc */
-    s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    *pSi0++ = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
-
-    /* ya' = ya + yb + yc + yd */
-    *pSi0++ = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
-    /* xb - xd */
-    t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) + (yb - yd) */
-    r1 = r2 + t1;
-    /* (xa - xc) - (yb - yd) */
-    r2 = r2 - t1;
-
-    /* (ya - yc) - (xb - xd) */
-    s1 = s2 - t2;
-    /* (ya - yc) + (xb - xd) */
-    s2 = s2 + t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-  } while(--j);
-
-  /* end of first stage process */
-
-  /* data is in 5.27(q27) format */
-
-
-  /* start of Middle stages process */
-
-
-  /* each stage in middle stages provides two down scaling of the input */
-
-  twidCoefModifier <<= 2u;
-
-
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-      
-      pSi0 = pSrc + 2 * j;
-      pSi1 = pSi0 + 2 * n2;
-      pSi2 = pSi1 + 2 * n2;
-      pSi3 = pSi2 + 2 * n2;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSi0[0] + pSi2[0];
-
-        /* xa - xc */
-        r2 = pSi0[0] - pSi2[0];
-
-
-        /* ya + yc */
-        s1 = pSi0[1] + pSi2[1];
-
-        /* ya - yc */
-        s2 = pSi0[1] - pSi2[1];
-
-
-        /* xb + xd */
-        t1 = pSi1[0] + pSi3[0];
-
-
-        /* xa' = xa + xb + xc + xd */
-        pSi0[0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-
-        /* yb + yd */
-        t2 = pSi1[1] + pSi3[1];
-
-        /* ya' = ya + yb + yc + yd */
-        pSi0[1] = (s1 + t2) >> 2u;
-        pSi0 += 2 * n1;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSi1[1] - pSi3[1];
-
-        /* (xb - xd) */
-        t2 = pSi1[0] - pSi3[0];
-
-
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        pSi1[1] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
-        pSi1 += 2 * n1;
-
-        /* (xa - xc) + (yb - yd) */
-        r1 = r2 + t1;
-        /* (xa - xc) - (yb - yd) */
-        r2 = r2 - t1;
-
-        /* (ya - yc) -  (xb - xd) */
-        s1 = s2 - t2;
-        /* (ya - yc) +  (xb - xd) */
-        s2 = s2 + t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-        pSi2 += 2 * n1;
-
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-        pSi3 += 2 * n1;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-#endif
-
-  /* End of Middle stages process */
-
-  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
-  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
-  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
-  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
-  /* start of Last stage process */
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    xa = (q31_t) xaya;
-    ya = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    xb = (q31_t) xbyb;
-    yb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    xc = (q31_t) xcyc;
-    yc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    xd = (q31_t) xdyd;
-    yd = (q31_t) (xdyd >> 32);
-
-#else
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    ya = (q31_t) xaya;
-    xa = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    yb = (q31_t) xbyb;
-    xb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    yc = (q31_t) xcyc;
-    xc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    yd = (q31_t) xdyd;
-    xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
-    /* xa' = xa + xb + xc + xd */
-    xa_out = xa + xb + xc + xd;
-
-    /* ya' = ya + yb + yc + yd */
-    ya_out = ya + yb + yc + yd;
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-    /* writing xa' and ya' */
-    *ptr1++ = xa_out;
-    *ptr1++ = ya_out;
-
-    xc_out = (xa - xb + xc - xd);
-    yc_out = (ya - yb + yc - yd);
-
-    /* writing xc' and yc' */
-    *ptr1++ = xc_out;
-    *ptr1++ = yc_out;
-
-    xb_out = (xa + yb - xc - yd);
-    yb_out = (ya - xb - yc + xd);
-
-    /* writing xb' and yb' */
-    *ptr1++ = xb_out;
-    *ptr1++ = yb_out;
-
-    xd_out = (xa - yb - xc + yd);
-    yd_out = (ya + xb - yc - xd);
-
-    /* writing xd' and yd' */
-    *ptr1++ = xd_out;
-    *ptr1++ = yd_out;
-
-
-  } while(--j);
-
-  /* output is in 11.21(q21) format for the 1024 point */
-  /* output is in 9.23(q23) format for the 256 point */
-  /* output is in 7.25(q25) format for the 64 point */
-  /* output is in 5.27(q27) format for the 16 point */
-
-  /* End of last stage process */
-
-}
-
-
-/**    
- * @brief  Core function for the Q31 CIFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-
-/*    
-* Radix-4 IFFT algorithm used is :    
-*    
-* CIFFT uses same twiddle coefficients as CFFT Function    
-*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
-*    
-*    
-* IFFT is implemented with following changes in equations from FFT    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 IFFT:    
-* Wn = co1 + j * (si1)    
-* W2n = co2 + j * (si2)    
-* W3n = co3 + j * (si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
-*    
-*/
-
-void arm_radix4_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier)
-{
-#if defined(ARM_MATH_CM7)
-  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q63_t xaya, xbyb, xcyc, xdyd;
-
-  /* input is be 1.31(q31) format for all FFT sizes */
-  /* Total process is divided into three stages */
-  /* process first stage, middle stages, & last stage */
-
-  /* Start of first stage process */
-
-  /* Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  do
-  {
-
-    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
-    /* xa - xc */
-    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
-    /* ya - yc */
-    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[2u * i0] = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
-    /* xb - xd */
-    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
-                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) - (yb - yd) */
-    r1 = r2 - t1;
-    /* (xa - xc) + (yb - yd) */
-    r2 = r2 + t1;
-
-    /* (ya - yc) + (xb - xd) */
-    s1 = s2 + t2;
-    /* (ya - yc) - (xb - xd) */
-    s2 = s2 - t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /* data is in 5.27(q27) format */
-  /* each stage provides two down scaling of the input */
-
-
-  /* Start of Middle stages process */
-
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of second stage to excluding last stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    for (j = 0; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSrc[2u * i0] + pSrc[2u * i2];
-        /* xa - xc */
-        r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
-                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] =
-          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
-           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
-
-        /* (xa - xc) - (yb - yd) */
-        r1 = r2 - t1;
-        /* (xa - xc) + (yb - yd) */
-        r2 = r2 + t1;
-
-        /* (ya - yc) +  (xb - xd) */
-        s1 = s2 + t2;
-        /* (ya - yc) -  (xb - xd) */
-        s2 = s2 - t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-#else
-  uint32_t n1, n2, ia1, ia2, ia3, i0, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q31_t *pSi0;
-  q31_t *pSi1;
-  q31_t *pSi2;
-  q31_t *pSi3;
-  q63_t xaya, xbyb, xcyc, xdyd;
-
-  /* input is be 1.31(q31) format for all FFT sizes */
-  /* Total process is divided into three stages */
-  /* process first stage, middle stages, & last stage */
-
-  /* Start of first stage process */
-
-  /* Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  ia1 = 0u;
-
-  j = n2;
-  
-  pSi0 = pSrc;
-  pSi1 = pSi0 + 2 * n2;
-  pSi2 = pSi1 + 2 * n2;
-  pSi3 = pSi2 + 2 * n2;
-
-  do
-  {
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSi0[0] >> 4u) + (pSi2[0] >> 4u);
-    /* xa - xc */
-    r2 = (pSi0[0] >> 4u) - (pSi2[0] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSi1[0] >> 4u) + (pSi3[0] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSi0[1] >> 4u) + (pSi2[1] >> 4u);
-    /* ya - yc */
-    s2 = (pSi0[1] >> 4u) - (pSi2[1] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    *pSi0++ = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSi1[1] >> 4u) + (pSi3[1] >> 4u);
-    /* ya' = ya + yb + yc + yd */
-    *pSi0++ = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSi1[1] >> 4u) - (pSi3[1] >> 4u);
-    /* xb - xd */
-    t2 = (pSi1[0] >> 4u) - (pSi3[0] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    *pSi1++ = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    *pSi1++ = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
-                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) - (yb - yd) */
-    r1 = r2 - t1;
-    /* (xa - xc) + (yb - yd) */
-    r2 = r2 + t1;
-
-    /* (ya - yc) + (xb - xd) */
-    s1 = s2 + t2;
-    /* (ya - yc) - (xb - xd) */
-    s2 = s2 - t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    *pSi2++ = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    *pSi2++ = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    *pSi3++ = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    *pSi3++ = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-  } while(--j);
-
-  /* data is in 5.27(q27) format */
-  /* each stage provides two down scaling of the input */
-
-
-  /* Start of Middle stages process */
-
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of second stage to excluding last stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    for (j = 0; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-      
-      pSi0 = pSrc + 2 * j;
-      pSi1 = pSi0 + 2 * n2;
-      pSi2 = pSi1 + 2 * n2;
-      pSi3 = pSi2 + 2 * n2;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSi0[0] + pSi2[0];
-
-        /* xa - xc */
-        r2 = pSi0[0] - pSi2[0];
-
-
-        /* ya + yc */
-        s1 = pSi0[1] + pSi2[1];
-
-        /* ya - yc */
-        s2 = pSi0[1] - pSi2[1];
-
-
-        /* xb + xd */
-        t1 = pSi1[0] + pSi3[0];
-
-
-        /* xa' = xa + xb + xc + xd */
-        pSi0[0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-        /* yb + yd */
-        t2 = pSi1[1] + pSi3[1];
-
-        /* ya' = ya + yb + yc + yd */
-        pSi0[1] = (s1 + t2) >> 2u;
-        pSi0 += 2 * n1;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSi1[1] - pSi3[1];
-
-        /* (xb - xd) */
-        t2 = pSi1[0] - pSi3[0];
-
-
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        pSi1[0] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
-                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        pSi1[1] =
-
-          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
-           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
-        pSi1 += 2 * n1;
-
-        /* (xa - xc) - (yb - yd) */
-        r1 = r2 - t1;
-        /* (xa - xc) + (yb - yd) */
-        r2 = r2 + t1;
-
-        /* (ya - yc) +  (xb - xd) */
-        s1 = s2 + t2;
-        /* (ya - yc) -  (xb - xd) */
-        s2 = s2 - t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        pSi2[0] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        pSi2[1] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-        pSi2 += 2 * n1;
-
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        pSi3[0] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        pSi3[1] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-        pSi3 += 2 * n1;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-#endif
-
-  /* End of Middle stages process */
-
-  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
-  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
-  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
-  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
-  /* Start of last stage process */
-
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-#ifndef ARM_MATH_BIG_ENDIAN
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    xa = (q31_t) xaya;
-    ya = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    xb = (q31_t) xbyb;
-    yb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    xc = (q31_t) xcyc;
-    yc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    xd = (q31_t) xdyd;
-    yd = (q31_t) (xdyd >> 32);
-
-#else
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    ya = (q31_t) xaya;
-    xa = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    yb = (q31_t) xbyb;
-    xb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    yc = (q31_t) xcyc;
-    xc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    yd = (q31_t) xdyd;
-    xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
-    /* xa' = xa + xb + xc + xd */
-    xa_out = xa + xb + xc + xd;
-
-    /* ya' = ya + yb + yc + yd */
-    ya_out = ya + yb + yc + yd;
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-    /* writing xa' and ya' */
-    *ptr1++ = xa_out;
-    *ptr1++ = ya_out;
-
-    xc_out = (xa - xb + xc - xd);
-    yc_out = (ya - yb + yc - yd);
-
-    /* writing xc' and yc' */
-    *ptr1++ = xc_out;
-    *ptr1++ = yc_out;
-
-    xb_out = (xa - yb - xc + yd);
-    yb_out = (ya + xb - yc - xd);
-
-    /* writing xb' and yb' */
-    *ptr1++ = xb_out;
-    *ptr1++ = yb_out;
-
-    xd_out = (xa + yb - xc - yd);
-    yd_out = (ya - xb - yc + xd);
-
-    /* writing xd' and yd' */
-    *ptr1++ = xd_out;
-    *ptr1++ = yd_out;
-
-  } while(--j);
-
-  /* output is in 11.21(q21) format for the 1024 point */
-  /* output is in 9.23(q23) format for the 256 point */
-  /* output is in 7.25(q25) format for the 64 point */
-  /* output is in 5.27(q27) format for the 16 point */
-
-  /* End of last stage process */
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
deleted file mode 100644
index 7ed8fded..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix8_f32.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix8_f32.c    
-*    
-* Description:	Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function        
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.      
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
-* @ingroup groupTransforms    
-*/
-
-/**    
-* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions    
-*    
-* \par    
-* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).    
-* Computational complexity of CFFT reduces drastically when compared to DFT.    
-* \par    
-* This set of functions implements CFFT/CIFFT    
-* for floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.    
-* Complex input is stored in input buffer in an interleaved fashion.    
-*    
-* \par    
-* The functions operate on blocks of input and output data and each call to the function processes    
-* 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.    
-* \par   
-* The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.    
-* 
 {real[0], imag[0], real[1], imag[1],..} 
    
-*    
-* \par Lengths supported by the transform:   
-* \par    
-* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm    
-* and the size of the FFT supported are of the lengths [ 64, 512, 4096].   
-*     
-*    
-* \par Algorithm:    
-*    
-* Complex Fast Fourier Transform:    
-* \par     
-* Input real and imaginary data:    
-* 
    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-* 
    
-* where N is length of FFT    
-* \par    
-* Output real and imaginary data:    
-* 
    
-* X(4r) = xa'+ j * ya'    
-* X(4r+1) = xb'+ j * yb'    
-* X(4r+2) = xc'+ j * yc'    
-* X(4r+3) = xd'+ j * yd'    
-* 
    
-* \par    
-* Twiddle factors for Radix-8 FFT:    
-* 
    
-* Wn = co1 + j * (- si1)    
-* W2n = co2 + j * (- si2)    
-* W3n = co3 + j * (- si3)    
-* 
    
-*    
-* \par    
-* \image html CFFT.gif "Radix-8 Decimation-in Frequency Complex Fast Fourier Transform"    
-*    
-* \par    
-* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.    
-* \par    
-*  Butterfly CFFT equations:    
-* 
    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
-* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
-* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
-* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
-* 
    
-*    
-* \par    
-* where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);    
-* bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);     
-* pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.    
-* twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;     
-* pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.    
-* onebyfftLen value of 1/fftLen to calculate CIFFT;    
-*   
-* \par Fixed-Point Behavior    
-* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.    
-* Refer to the function specific documentation below for usage guidelines.    
-*/
-
-
-/*    
-* @brief  Core function for the floating-point CFFT butterfly process.   
-* @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
-* @param[in]      fftLen           length of the FFT.   
-* @param[in]      *pCoef           points to the twiddle coefficient buffer.   
-* @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.   
-*/
-
-void arm_radix8_butterfly_f32(
-float32_t * pSrc,
-uint16_t fftLen,
-const float32_t * pCoef,
-uint16_t twidCoefModifier)
-{
-   uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
-   uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
-   uint32_t id;
-   uint32_t n1, n2, j;
-   
-   float32_t r1, r2, r3, r4, r5, r6, r7, r8;
-   float32_t t1, t2;
-   float32_t s1, s2, s3, s4, s5, s6, s7, s8;
-   float32_t p1, p2, p3, p4;
-   float32_t co2, co3, co4, co5, co6, co7, co8;
-   float32_t si2, si3, si4, si5, si6, si7, si8;
-   const float32_t C81 = 0.70710678118f;
-
-   n2 = fftLen;
-   
-   do 
-   {
-      n1 = n2;
-      n2 = n2 >> 3;
-      i1 = 0;
-      
-      do
-      {
-         i2 = i1 + n2;
-         i3 = i2 + n2;
-         i4 = i3 + n2;
-         i5 = i4 + n2;
-         i6 = i5 + n2;
-         i7 = i6 + n2;
-         i8 = i7 + n2;
-         r1 = pSrc[2 * i1] + pSrc[2 * i5];
-         r5 = pSrc[2 * i1] - pSrc[2 * i5];
-         r2 = pSrc[2 * i2] + pSrc[2 * i6];
-         r6 = pSrc[2 * i2] - pSrc[2 * i6];
-         r3 = pSrc[2 * i3] + pSrc[2 * i7];
-         r7 = pSrc[2 * i3] - pSrc[2 * i7];
-         r4 = pSrc[2 * i4] + pSrc[2 * i8];
-         r8 = pSrc[2 * i4] - pSrc[2 * i8];
-         t1 = r1 - r3;
-         r1 = r1 + r3;
-         r3 = r2 - r4;
-         r2 = r2 + r4;
-         pSrc[2 * i1] = r1 + r2;   
-         pSrc[2 * i5] = r1 - r2;
-         r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
-         s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
-         r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
-         s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
-         s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
-         s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
-         r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
-         s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
-         t2 = r1 - s3;
-         r1 = r1 + s3;
-         s3 = r2 - r4;
-         r2 = r2 + r4;
-         pSrc[2 * i1 + 1] = r1 + r2;
-         pSrc[2 * i5 + 1] = r1 - r2;
-         pSrc[2 * i3]     = t1 + s3;
-         pSrc[2 * i7]     = t1 - s3;
-         pSrc[2 * i3 + 1] = t2 - r3;
-         pSrc[2 * i7 + 1] = t2 + r3;
-         r1 = (r6 - r8) * C81;
-         r6 = (r6 + r8) * C81;
-         r2 = (s6 - s8) * C81;
-         s6 = (s6 + s8) * C81;
-         t1 = r5 - r1;
-         r5 = r5 + r1;
-         r8 = r7 - r6;
-         r7 = r7 + r6;
-         t2 = s5 - r2;
-         s5 = s5 + r2;
-         s8 = s7 - s6;
-         s7 = s7 + s6;
-         pSrc[2 * i2]     = r5 + s7;
-         pSrc[2 * i8]     = r5 - s7;
-         pSrc[2 * i6]     = t1 + s8;
-         pSrc[2 * i4]     = t1 - s8;
-         pSrc[2 * i2 + 1] = s5 - r7;
-         pSrc[2 * i8 + 1] = s5 + r7;
-         pSrc[2 * i6 + 1] = t2 - r8;
-         pSrc[2 * i4 + 1] = t2 + r8;
-         
-         i1 += n1;
-      } while(i1 < fftLen);
-      
-      if(n2 < 8)
-         break;
-      
-      ia1 = 0;
-      j = 1;
-      
-      do
-      {      
-         /*  index calculation for the coefficients */
-         id  = ia1 + twidCoefModifier;
-         ia1 = id;
-         ia2 = ia1 + id;
-         ia3 = ia2 + id;
-         ia4 = ia3 + id;
-         ia5 = ia4 + id;
-         ia6 = ia5 + id;
-         ia7 = ia6 + id;
-                  
-         co2 = pCoef[2 * ia1];
-         co3 = pCoef[2 * ia2];
-         co4 = pCoef[2 * ia3];
-         co5 = pCoef[2 * ia4];
-         co6 = pCoef[2 * ia5];
-         co7 = pCoef[2 * ia6];
-         co8 = pCoef[2 * ia7];
-         si2 = pCoef[2 * ia1 + 1];
-         si3 = pCoef[2 * ia2 + 1];
-         si4 = pCoef[2 * ia3 + 1];
-         si5 = pCoef[2 * ia4 + 1];
-         si6 = pCoef[2 * ia5 + 1];
-         si7 = pCoef[2 * ia6 + 1];
-         si8 = pCoef[2 * ia7 + 1];         
-         
-         i1 = j;
-         
-         do
-         {
-            /*  index calculation for the input */
-            i2 = i1 + n2;
-            i3 = i2 + n2;
-            i4 = i3 + n2;
-            i5 = i4 + n2;
-            i6 = i5 + n2;
-            i7 = i6 + n2;
-            i8 = i7 + n2;
-            r1 = pSrc[2 * i1] + pSrc[2 * i5];
-            r5 = pSrc[2 * i1] - pSrc[2 * i5];
-            r2 = pSrc[2 * i2] + pSrc[2 * i6];
-            r6 = pSrc[2 * i2] - pSrc[2 * i6];
-            r3 = pSrc[2 * i3] + pSrc[2 * i7];
-            r7 = pSrc[2 * i3] - pSrc[2 * i7];
-            r4 = pSrc[2 * i4] + pSrc[2 * i8];
-            r8 = pSrc[2 * i4] - pSrc[2 * i8];
-            t1 = r1 - r3;
-            r1 = r1 + r3;
-            r3 = r2 - r4;
-            r2 = r2 + r4;
-            pSrc[2 * i1] = r1 + r2;
-            r2 = r1 - r2;
-            s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
-            s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
-            s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
-            s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
-            s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
-            s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
-            s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
-            s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
-            t2 = s1 - s3;
-            s1 = s1 + s3;
-            s3 = s2 - s4;
-            s2 = s2 + s4;
-            r1 = t1 + s3;
-            t1 = t1 - s3;
-            pSrc[2 * i1 + 1] = s1 + s2;
-            s2 = s1 - s2;
-            s1 = t2 - r3;
-            t2 = t2 + r3;
-            p1 = co5 * r2;
-            p2 = si5 * s2;
-            p3 = co5 * s2;
-            p4 = si5 * r2;
-            pSrc[2 * i5]     = p1 + p2;
-            pSrc[2 * i5 + 1] = p3 - p4;
-            p1 = co3 * r1;
-            p2 = si3 * s1;
-            p3 = co3 * s1;
-            p4 = si3 * r1;
-            pSrc[2 * i3]     = p1 + p2;
-            pSrc[2 * i3 + 1] = p3 - p4;
-            p1 = co7 * t1;
-            p2 = si7 * t2;
-            p3 = co7 * t2;
-            p4 = si7 * t1;
-            pSrc[2 * i7]     = p1 + p2;
-            pSrc[2 * i7 + 1] = p3 - p4;
-            r1 = (r6 - r8) * C81;
-            r6 = (r6 + r8) * C81;
-            s1 = (s6 - s8) * C81;
-            s6 = (s6 + s8) * C81;
-            t1 = r5 - r1;
-            r5 = r5 + r1;
-            r8 = r7 - r6;
-            r7 = r7 + r6;
-            t2 = s5 - s1;
-            s5 = s5 + s1;
-            s8 = s7 - s6;
-            s7 = s7 + s6;
-            r1 = r5 + s7;
-            r5 = r5 - s7;
-            r6 = t1 + s8;
-            t1 = t1 - s8;
-            s1 = s5 - r7;
-            s5 = s5 + r7;
-            s6 = t2 - r8;
-            t2 = t2 + r8;
-            p1 = co2 * r1;
-            p2 = si2 * s1;
-            p3 = co2 * s1;
-            p4 = si2 * r1;
-            pSrc[2 * i2]     = p1 + p2;
-            pSrc[2 * i2 + 1] = p3 - p4;
-            p1 = co8 * r5;
-            p2 = si8 * s5;
-            p3 = co8 * s5;
-            p4 = si8 * r5;
-            pSrc[2 * i8]     = p1 + p2;
-            pSrc[2 * i8 + 1] = p3 - p4;
-            p1 = co6 * r6;
-            p2 = si6 * s6;
-            p3 = co6 * s6;
-            p4 = si6 * r6;
-            pSrc[2 * i6]     = p1 + p2;
-            pSrc[2 * i6 + 1] = p3 - p4;
-            p1 = co4 * t1;
-            p2 = si4 * t2;
-            p3 = co4 * t2;
-            p4 = si4 * t1;
-            pSrc[2 * i4]     = p1 + p2;
-            pSrc[2 * i4 + 1] = p3 - p4;
-            
-            i1 += n1;
-         } while(i1 < fftLen);
-         
-         j++;
-      } while(j < n2);
-      
-      twidCoefModifier <<= 3;
-   } while(n2 > 7);   
-}
-
-/**    
-* @} end of Radix8_CFFT_CIFFT group    
-*/
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
deleted file mode 100644
index 5ee7efaa..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
+++ /dev/null
@@ -1,461 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_f32.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 F32.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.      
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @defgroup DCT4_IDCT4 DCT Type IV Functions    
- * Representation of signals by minimum number of values is important for storage and transmission.    
- * The possibility of large discontinuity between the beginning and end of a period of a signal    
- * in DFT can be avoided by extending the signal so that it is even-symmetric.    
- * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the    
- * spectrum and is very widely used in signal and image coding applications.    
- * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.    
- * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.    
- *    
- * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.    
- * Reordering of the input data makes the computation of DCT just a problem of    
- * computing the DFT of a real signal with a few additional operations.    
- * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.    
- *     
- * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.    
- * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.    
- * DCT2 implementation can be described in the following steps:    
- * - Re-ordering input    
- * - Calculating Real FFT    
- * - Multiplication of weights and Real FFT output and getting real part from the product.    
- *    
- * This process is explained by the block diagram below:    
- * \image html DCT4.gif "Discrete Cosine Transform - type-IV"    
- *    
- * \par Algorithm:    
- * The N-point type-IV DCT is defined as a real, linear transformation by the formula:    
- * \image html DCT4Equation.gif    
- * where k = 0,1,2,.....N-1    
- *\par    
- * Its inverse is defined as follows:    
- * \image html IDCT4Equation.gif    
- * where n = 0,1,2,.....N-1    
- *\par    
- * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).    
- * The symmetry of the transform matrix indicates that the fast algorithms for the forward    
- * and inverse transform computation are identical.    
- * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.    
- *    
- * \par Lengths supported by the transform:    
- *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().    
- * The library provides separate functions for Q15, Q31, and floating-point data types.    
- * \par Instance Structure    
- * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.    
- * A separate instance structure must be defined for each transform.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Manually initialize the instance structure as follows:    
- * 
    
- *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    
- *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
- *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
- * 
   
- * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;   
- * \c normalize is normalizing factor used and is equal to sqrt(2/N);    
- * \c pTwiddle points to the twiddle factor table;   
- * \c pCosFactor points to the cosFactor table;   
- * \c pRfft points to the real FFT instance;   
- * \c pCfft points to the complex FFT instance;   
- * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()   
- * and arm_rfft_f32() respectively for details regarding static initialization.   
- *   
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the DCT4 transform functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
- /**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- */
-
-void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer)
-{
-  uint32_t i;                                    /* Loop counter */
-  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
-  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
-  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
-  float32_t in;                                  /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
-  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as,    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = (uint32_t) S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
-        /*----------------------------------------------------------------------    
-	 *  Step3: Multiply the FFT output with the weights.    
-	 *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = ((uint32_t) S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ * (float32_t) 0.5;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = ((uint32_t) S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = (uint32_t) S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
-        /*----------------------------------------------------------------------    
-	 *  Step3: Multiply the FFT output with the weights.    
-	 *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ * (float32_t) 0.5;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* Initializing the loop counter */
-  i = ((uint32_t) S->N - 1u);
-
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
deleted file mode 100644
index efc6501e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
+++ /dev/null
@@ -1,16519 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_f32.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 F32    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*    weights[2*i]= cos(i*c);    
-*    weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* Where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const float32_t Weights_128[256] = {
-  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
-  -0.012271538285719925f,
-  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
-  -0.036807222941358832f,
-  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
-  -0.061320736302208578f,
-  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
-  -0.085797312344439894f,
-  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
-  -0.110222207293883060f,
-  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
-  -0.134580708507126170f,
-  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
-  -0.158858143333861450f,
-  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
-  -0.183039887955140950f,
-  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
-  -0.207111376192218560f,
-  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
-  -0.231058108280671110f,
-  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
-  -0.254865659604514570f,
-  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
-  -0.278519689385053060f,
-  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
-  -0.302005949319228080f,
-  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
-  -0.325310292162262930f,
-  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
-  -0.348418680249434560f,
-  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
-  -0.371317193951837540f,
-  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
-  -0.393992040061048100f,
-  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
-  -0.416429560097637150f,
-  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
-  -0.438616238538527660f,
-  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
-  -0.460538710958240010f,
-  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
-  -0.482183772079122720f,
-  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
-  -0.503538383725717580f,
-  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
-  -0.524589682678468950f,
-  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
-  -0.545324988422046460f,
-  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
-  -0.565731810783613120f,
-  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
-  -0.585797857456438860f,
-  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
-  -0.605511041404325550f,
-  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
-  -0.624859488142386340f,
-  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
-  -0.643831542889791390f,
-  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
-  -0.662415777590171780f,
-  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
-  -0.680600997795453020f,
-  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
-  -0.698376249408972920f,
-  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
-  -0.715730825283818590f,
-  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
-  -0.732654271672412820f,
-  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
-  -0.749136394523459260f,
-  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
-  -0.765167265622458960f,
-  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
-  -0.780737228572094380f,
-  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
-  -0.795836904608883460f,
-  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
-  -0.810457198252594770f,
-  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
-  -0.824589302785025290f,
-  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
-  -0.838224705554837970f,
-  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
-  -0.851355193105265200f,
-  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
-  -0.863972856121586700f,
-  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
-  -0.876070094195406600f,
-  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
-  -0.887639620402853930f,
-  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
-  -0.898674465693953820f,
-  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
-  -0.909167983090522270f,
-  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
-  -0.919113851690057770f,
-  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
-  -0.928506080473215480f,
-  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
-  -0.937339011912574960f,
-  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
-  -0.945607325380521280f,
-  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
-  -0.953306040354193750f,
-  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
-  -0.960430519415565790f,
-  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
-  -0.966976471044852070f,
-  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
-  -0.972939952205560070f,
-  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
-  -0.978317370719627650f,
-  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
-  -0.983105487431216290f,
-  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
-  -0.987301418157858430f,
-  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
-  -0.990902635427780010f,
-  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
-  -0.993906970002356060f,
-  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
-  -0.996312612182778000f,
-  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
-  -0.998118112900149180f,
-  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
-  -0.999322384588349540f,
-  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
-  -0.999924701839144500f
-};
-
-static const float32_t Weights_512[1024] = {
-  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
-  -0.003067956762965976f,
-  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
-  -0.009203754782059819f,
-  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
-  -0.015339206284988100f,
-  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
-  -0.021474080275469508f,
-  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
-  -0.027608145778965740f,
-  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
-  -0.033741171851377580f,
-  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
-  -0.039872927587739811f,
-  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
-  -0.046003182130914623f,
-  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
-  -0.052131704680283324f,
-  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
-  -0.058258264500435752f,
-  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
-  -0.064382630929857465f,
-  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
-  -0.070504573389613856f,
-  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
-  -0.076623861392031492f,
-  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
-  -0.082740264549375692f,
-  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
-  -0.088853552582524600f,
-  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
-  -0.094963495329638992f,
-  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
-  -0.101069862754827820f,
-  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
-  -0.107172424956808840f,
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-    -0.999227529910869610,
-  0.039106535483329839, -0.999235046864595850, 0.038914933845027241,
-    -0.999242527079305830,
-  0.038723330775933762, -0.999249970554724420, 0.038531726283093877,
-    -0.999257377290578060,
-  0.038340120373552791, -0.999264747286594420, 0.038148513054354856,
-    -0.999272080542502610,
-  0.037956904332545366, -0.999279377058032710, 0.037765294215169005,
-    -0.999286636832916740,
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-    -0.999301046159680070,
-  0.037190455560088091, -0.999308195711029470, 0.036998839930894332,
-    -0.999315308520673070,
-  0.036807222941358991, -0.999322384588349540, 0.036615604598527057,
-    -0.999329423913798420,
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-    -0.999343392336980220,
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-    -0.999357213788164000,
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-    -0.999370888265317060,
-  0.035274238898213947, -0.999377670388002850, 0.035082609982644702,
-    -0.999384415766428560,
-  0.034890979777187955, -0.999391124400346050, 0.034699348288889847,
-    -0.999397796289508640,
-  0.034507715524795889, -0.999404431433671300, 0.034316081491951658,
-    -0.999411029832589780,
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-    -0.999424116393725640,
-  0.033741171851377642, -0.999430604555461730, 0.033549532813992221,
-    -0.999437055970991530,
-  0.033357892543086159, -0.999443470640077770, 0.033166251045705968,
-    -0.999449848562484530,
-  0.032974608328897315, -0.999456189737977340, 0.032782964399706793,
-    -0.999462494166323160,
-  0.032591319265180385, -0.999468761847290050, 0.032399672932364114,
-    -0.999474992780647780,
-  0.032208025408304704, -0.999481186966166950, 0.032016376700048046,
-    -0.999487344403620080,
-  0.031824726814640963, -0.999493465092780590, 0.031633075759129645,
-    -0.999499549033423640,
-  0.031441423540560343, -0.999505596225325310, 0.031249770165979990,
-    -0.999511606668263440,
-  0.031058115642434700, -0.999517580362016990, 0.030866459976971503,
-    -0.999523517306366350,
-  0.030674803176636581, -0.999529417501093140, 0.030483145248477058,
-    -0.999535280945980540,
-  0.030291486199539423, -0.999541107640812940, 0.030099826036870208,
-    -0.999546897585375960,
-  0.029908164767516655, -0.999552650779456990, 0.029716502398525156,
-    -0.999558367222844300,
-  0.029524838936943035, -0.999564046915327740, 0.029333174389816984,
-    -0.999569689856698580,
-  0.029141508764193740, -0.999575296046749220, 0.028949842067120746,
-    -0.999580865485273700,
-  0.028758174305644590, -0.999586398172067070, 0.028566505486812797,
-    -0.999591894106925950,
-  0.028374835617672258, -0.999597353289648380, 0.028183164705269902,
-    -0.999602775720033530,
-  0.027991492756653365, -0.999608161397882110, 0.027799819778869434,
-    -0.999613510322995950,
-  0.027608145778965820, -0.999618822495178640, 0.027416470763989606,
-    -0.999624097914234570,
-  0.027224794740987910, -0.999629336579970110, 0.027033117717008563,
-    -0.999634538492192300,
-  0.026841439699098527, -0.999639703650710200, 0.026649760694305708,
-    -0.999644832055333610,
-  0.026458080709677145, -0.999649923705874240, 0.026266399752260809,
-    -0.999654978602144690,
-  0.026074717829104040, -0.999659996743959220, 0.025883034947254208,
-    -0.999664978131133310,
-  0.025691351113759395, -0.999669922763483760, 0.025499666335666818,
-    -0.999674830640828740,
-  0.025307980620024630, -0.999679701762987930, 0.025116293973880335,
-    -0.999684536129782140,
-  0.024924606404281485, -0.999689333741033640, 0.024732917918276334,
-    -0.999694094596566000,
-  0.024541228522912264, -0.999698818696204250, 0.024349538225237600,
-    -0.999703506039774650,
-  0.024157847032300020, -0.999708156627104880, 0.023966154951147241,
-    -0.999712770458023870,
-  0.023774461988827676, -0.999717347532362190, 0.023582768152388880,
-    -0.999721887849951310,
-  0.023391073448879338, -0.999726391410624470, 0.023199377885346890,
-    -0.999730858214216030,
-  0.023007681468839410, -0.999735288260561680, 0.022815984206405477,
-    -0.999739681549498660,
-  0.022624286105092803, -0.999744038080865430, 0.022432587171950024,
-    -0.999748357854501780,
-  0.022240887414024919, -0.999752640870248840, 0.022049186838366180,
-    -0.999756887127949080,
-  0.021857485452021874, -0.999761096627446610, 0.021665783262040089,
-    -0.999765269368586450,
-  0.021474080275469605, -0.999769405351215280, 0.021282376499358355,
-    -0.999773504575180990,
-  0.021090671940755180, -0.999777567040332940, 0.020898966606708289,
-    -0.999781592746521670,
-  0.020707260504265912, -0.999785581693599210, 0.020515553640476986,
-    -0.999789533881418780,
-  0.020323846022389572, -0.999793449309835270, 0.020132137657052664,
-    -0.999797327978704690,
-  0.019940428551514598, -0.999801169887884260, 0.019748718712823757,
-    -0.999804975037232870,
-  0.019557008148029204, -0.999808743426610520, 0.019365296864179146,
-    -0.999812475055878780,
-  0.019173584868322699, -0.999816169924900410, 0.018981872167508348,
-    -0.999819828033539420,
-  0.018790158768784596, -0.999823449381661570, 0.018598444679200642,
-    -0.999827033969133420,
-  0.018406729905804820, -0.999830581795823400, 0.018215014455646376,
-    -0.999834092861600960,
-  0.018023298335773701, -0.999837567166337090, 0.017831581553236088,
-    -0.999841004709904000,
-  0.017639864115082195, -0.999844405492175240, 0.017448146028360704,
-    -0.999847769513025900,
-  0.017256427300120978, -0.999851096772332190, 0.017064707937411529,
-    -0.999854387269971890,
-  0.016872987947281773, -0.999857641005823860, 0.016681267336780482,
-    -0.999860857979768540,
-  0.016489546112956454, -0.999864038191687680, 0.016297824282859176,
-    -0.999867181641464380,
-  0.016106101853537263, -0.999870288328982950, 0.015914378832040249,
-    -0.999873358254129260,
-  0.015722655225417017, -0.999876391416790410, 0.015530931040716478,
-    -0.999879387816854930,
-  0.015339206284988220, -0.999882347454212560, 0.015147480965280975,
-    -0.999885270328754520,
-  0.014955755088644378, -0.999888156440373320, 0.014764028662127416,
-    -0.999891005788962950,
-  0.014572301692779104, -0.999893818374418490, 0.014380574187649138,
-    -0.999896594196636680,
-  0.014188846153786343, -0.999899333255515390, 0.013997117598240459,
-    -0.999902035550953920,
-  0.013805388528060349, -0.999904701082852900, 0.013613658950295789,
-    -0.999907329851114300,
-  0.013421928871995907, -0.999909921855641540, 0.013230198300209845,
-    -0.999912477096339240,
-  0.013038467241987433, -0.999914995573113470, 0.012846735704377631,
-    -0.999917477285871770,
-  0.012655003694430301, -0.999919922234522750, 0.012463271219194662,
-    -0.999922330418976490,
-  0.012271538285719944, -0.999924701839144500, 0.012079804901056066,
-    -0.999927036494939640,
-  0.011888071072252072, -0.999929334386276070, 0.011696336806357907,
-    -0.999931595513069200,
-  0.011504602110422875, -0.999933819875236000, 0.011312866991496287,
-    -0.999936007472694620,
-  0.011121131456628141, -0.999938158305364590, 0.010929395512867561,
-    -0.999940272373166960,
-  0.010737659167264572, -0.999942349676023910, 0.010545922426868548,
-    -0.999944390213859060,
-  0.010354185298728884, -0.999946393986597460, 0.010162447789895645,
-    -0.999948360994165400,
-  0.009970709907418029, -0.999950291236490480, 0.009778971658346134,
-    -0.999952184713501780,
-  0.009587233049729183, -0.999954041425129780, 0.009395494088617302,
-    -0.999955861371306100,
-  0.009203754782059960, -0.999957644551963900, 0.009012015137106642,
-    -0.999959390967037450,
-  0.008820275160807512, -0.999961100616462820, 0.008628534860211857,
-    -0.999962773500176930,
-  0.008436794242369860, -0.999964409618118280, 0.008245053314331058,
-    -0.999966008970226920,
-  0.008053312083144991, -0.999967571556443780, 0.007861570555861883,
-    -0.999969097376711580,
-  0.007669828739531077, -0.999970586430974140, 0.007478086641202815,
-    -0.999972038719176730,
-  0.007286344267926684, -0.999973454241265940, 0.007094601626752279,
-    -0.999974832997189810,
-  0.006902858724729877, -0.999976174986897610, 0.006711115568908869,
-    -0.999977480210339940,
-  0.006519372166339549, -0.999978748667468830, 0.006327628524071549,
-    -0.999979980358237650,
-  0.006135884649154515, -0.999981175282601110, 0.005944140548638765,
-    -0.999982333440515350,
-  0.005752396229573737, -0.999983454831937730, 0.005560651699009764,
-    -0.999984539456826970,
-  0.005368906963996303, -0.999985587315143200, 0.005177162031583702,
-    -0.999986598406848000,
-  0.004985416908821652, -0.999987572731904080, 0.004793671602759852,
-    -0.999988510290275690,
-  0.004601926120448672, -0.999989411081928400, 0.004410180468937601,
-    -0.999990275106828920,
-  0.004218434655277024, -0.999991102364945590, 0.004026688686516664,
-    -0.999991892856248010,
-  0.003834942569706248, -0.999992646580707190, 0.003643196311896179,
-    -0.999993363538295150,
-  0.003451449920135975, -0.999994043728985820, 0.003259703401476044,
-    -0.999994687152754080,
-  0.003067956762966138, -0.999995293809576190, 0.002876210011656010,
-    -0.999995863699429940,
-  0.002684463154596083, -0.999996396822294350, 0.002492716198835898,
-    -0.999996893178149880,
-  0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
-    -0.999997775588762350,
-  0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
-    -0.999998510931137790,
-  0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
-    -0.999999099205167830,
-  0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
-    -0.999999540410766110,
-  0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
-    -0.999999834547867670,
-  0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
-    -0.999999981616429330,
-
-};
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
-* \par    
-* C command to generate the table    
-* \par    
-* 
 for(i = 0; i< N; i++)    
-* {    
-*    cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-*/
-static const float32_t cos_factors_128[128] = {
-  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
-  0.999077727752645360f,
-  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
-  0.995767414467659820f,
-  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
-  0.990058210262297120f,
-  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
-  0.981963869109555240f,
-  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
-  0.971503890986251780f,
-  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
-  0.958703474895871600f,
-  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
-  0.943593458161960390f,
-  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
-  0.926210242138311380f,
-  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
-  0.906595704514915330f,
-  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
-  0.884797098430937790f,
-  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
-  0.860866938637767310f,
-  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
-  0.834862874986380010f,
-  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
-  0.806847553543799330f,
-  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
-  0.776888465673232440f,
-  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
-  0.745057785441466060f,
-  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
-  0.711432195745216430f,
-  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
-  0.676092703575316030f,
-  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
-  0.639124444863775730f,
-  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
-  0.600616479383868970f,
-  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
-  0.560661576197336030f,
-  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
-  0.519355990165589530f,
-  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
-  0.476799230063322250f,
-  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
-  0.433093818853152010f,
-  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
-  0.388345046698826300f,
-  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
-  0.342660717311994380f,
-  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
-  0.296150888243623960f,
-  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
-  0.248927605745720260f,
-  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
-  0.201104634842091960f,
-  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
-  0.152797185258443410f,
-  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
-  0.104121633872054730f,
-  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
-  0.055195244349690031f,
-  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
-  0.006135884649154515f
-};
-
-static const float32_t cos_factors_512[512] = {
-  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
-  0.999942349676023910f,
-  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
-  0.999735288260561680f,
-  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
-  0.999377670388002850f,
-  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
-  0.998869549914283560f,
-  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
-  0.998211003360478190f,
-  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
-  0.997402129901275300f,
-  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
-  0.996443051350042630f,
-  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
-  0.995333912140482280f,
-  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
-  0.994074879304879370f,
-  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
-  0.992666142448948020f,
-  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
-  0.991107913723276890f,
-  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
-  0.989400427791380380f,
-  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
-  0.987543941794359230f,
-  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
-  0.985538735312176060f,
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-  0.983385110321551180f,
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-  0.087325535206192226f,
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-  0.075094300847921291f,
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-  0.062851757564161420f,
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-  0.050599749036899337f,
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-  0.038340120373552791f,
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-  0.013805388528060349f,
-  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
-  0.001533980186284766f
-};
-
-static const float32_t cos_factors_2048[2048] = {
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-  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
-  0.999983454831937730f,
-  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
-  0.999961100616462820f,
-  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
-  0.999929334386276070f,
-  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
-  0.999888156440373320f,
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-  0.999837567166337090f,
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-  0.999777567040332940f,
-  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
-  0.999708156627104880f,
-  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
-  0.999629336579970110f,
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-  0.999541107640812940f,
-  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
-  0.999443470640077770f,
-  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
-  0.999336426496761240f,
-  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
-  0.999219976218403530f,
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-  0.999094120901079070f,
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-  0.998958861729386080f,
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-  0.998814199976435390f,
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-  0.998660137003838490f,
-  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
-  0.998496674261694640f,
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-  0.998323813288577560f,
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-  0.997949903246001190f,
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-  0.997748857695925690f,
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-  0.997538420953611340f,
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-  0.997318594999768600f,
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-  0.997089381903483400f,
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-  0.996850783822196610f,
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-  0.996602803001684130f,
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-  0.996345441776035900f,
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-  0.996078702567633980f,
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-  0.995802587887129160f,
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-  0.995517100333418110f,
-  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
-  0.995222242593618360f,
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-  0.994918017443043200f,
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-  0.110603357728661910f,
-  0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f,
-  0.107553703503615710f,
-  0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f,
-  0.104503036942150550f,
-  0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f,
-  0.101451386758302160f,
-  0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f,
-  0.098398781675363881f,
-  0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f,
-  0.095345250425617742f,
-  0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f,
-  0.092290821750062355f,
-  0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f,
-  0.089235524398144139f,
-  0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f,
-  0.086179387127484922f,
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-  0.083122438703613077f,
-  0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f,
-  0.080064707899690932f,
-  0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f,
-  0.077006223496245585f,
-  0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f,
-  0.073947014280897269f,
-  0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f,
-  0.070887109048087787f,
-  0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f,
-  0.067826536598810966f,
-  0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f,
-  0.064765325740339871f,
-  0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f,
-  0.061703505285957416f,
-  0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f,
-  0.058641104054683348f,
-  0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
-  0.055578150871004817f,
-  0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
-  0.052514674564603257f,
-  0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f,
-  0.049450703970084824f,
-  0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
-  0.046386267926707213f,
-  0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f,
-  0.043321395278109784f,
-  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
-  0.040256114872041358f,
-  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
-  0.037190455560088091f,
-  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
-  0.034124446197403423f,
-  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
-  0.031058115642434700f,
-  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
-  0.027991492756653365f,
-  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
-  0.024924606404281485f,
-  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
-  0.021857485452021874f,
-  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
-  0.018790158768784596f,
-  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
-  0.015722655225417017f,
-  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
-  0.012655003694430301f,
-  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
-  0.009587233049729183f,
-  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
-  0.006519372166339549f,
-  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
-  0.003451449920135975f,
-  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
-  0.000383495187571497f
-};
-
-static const float32_t cos_factors_8192[8192] = {
-  1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
-    1.999999549602533100,
-  1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
-    1.999997931848645600,
-  1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
-    1.999995137547503600,
-  1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
-    1.999991166700750800,
-  1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
-    1.999986019310723500,
-  1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
-    1.999979695380449400,
-  1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
-    1.999972194913648900,
-  1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
-    1.999963517914734100,
-  1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
-    1.999953664388809800,
-  1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
-    1.999942634341672600,
-  1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
-    1.999930427779810900,
-  1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
-    1.999917044710405500,
-  1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
-    1.999902485141329400,
-  1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
-    1.999886749081147800,
-  1.999882631240436700, 1.999878439869758200, 1.999874174969266300,
-    1.999869836539117700,
-  1.999865424579472000, 1.999860939090491600, 1.999856380072341000,
-    1.999851747525188200,
-  1.999847041449203300, 1.999842261844559700, 1.999837408711432600,
-    1.999832482050000900,
-  1.999827481860445300, 1.999822408142949900, 1.999817260897701400,
-    1.999812040124888700,
-  1.999806745824704000, 1.999801377997341800, 1.999795936642999600,
-    1.999790421761877400,
-  1.999784833354177900, 1.999779171420106700, 1.999773435959872000,
-    1.999767626973684400,
-  1.999761744461757700, 1.999755788424308200, 1.999749758861554900,
-    1.999743655773719400,
-  1.999737479161026100, 1.999731229023702200, 1.999724905361977200,
-    1.999718508176084000,
-  1.999712037466257600, 1.999705493232735800, 1.999698875475759600,
-    1.999692184195571900,
-  1.999685419392419000, 1.999678581066549400, 1.999671669218214600,
-    1.999664683847668800,
-  1.999657624955168700, 1.999650492540973900, 1.999643286605346800,
-    1.999636007148552400,
-  1.999628654170857900, 1.999621227672533800, 1.999613727653853500,
-    1.999606154115092500,
-  1.999598507056529000, 1.999590786478444600, 1.999582992381123000,
-    1.999575124764850800,
-  1.999567183629917100, 1.999559168976613900, 1.999551080805236100,
-    1.999542919116081000,
-  1.999534683909448600, 1.999526375185641800, 1.999517992944965800,
-    1.999509537187729200,
-  1.999501007914242600, 1.999492405124819700, 1.999483728819776900,
-    1.999474978999432800,
-  1.999466155664109600, 1.999457258814131500, 1.999448288449825500,
-    1.999439244571521700,
-  1.999430127179552500, 1.999420936274252800, 1.999411671855960900,
-    1.999402333925017300,
-  1.999392922481765500, 1.999383437526551300, 1.999373879059723500,
-    1.999364247081633500,
-  1.999354541592635500, 1.999344762593086500, 1.999334910083345700,
-    1.999324984063775700,
-  1.999314984534741100, 1.999304911496609700, 1.999294764949752100,
-    1.999284544894541100,
-  1.999274251331352400, 1.999263884260564600, 1.999253443682558900,
-    1.999242929597719200,
-  1.999232342006432000, 1.999221680909086400, 1.999210946306074500,
-    1.999200138197791100,
-  1.999189256584633600, 1.999178301467001900, 1.999167272845298900,
-    1.999156170719930100,
-  1.999144995091303600, 1.999133745959830600, 1.999122423325924200,
-    1.999111027190001000,
-  1.999099557552479900, 1.999088014413782800, 1.999076397774334000,
-    1.999064707634560700,
-  1.999052943994892300, 1.999041106855761900, 1.999029196217604100,
-    1.999017212080857400,
-  1.999005154445962200, 1.998993023313361700, 1.998980818683502100,
-    1.998968540556831800,
-  1.998956188933802800, 1.998943763814868800, 1.998931265200486900,
-    1.998918693091116200,
-  1.998906047487219600, 1.998893328389261400, 1.998880535797709700,
-    1.998867669713034500,
-  1.998854730135709400, 1.998841717066209400, 1.998828630505013400,
-    1.998815470452602400,
-  1.998802236909460500, 1.998788929876074100, 1.998775549352932400,
-    1.998762095340527400,
-  1.998748567839354000, 1.998734966849909000, 1.998721292372693100,
-    1.998707544408208700,
-  1.998693722956961500, 1.998679828019459300, 1.998665859596213500,
-    1.998651817687737300,
-  1.998637702294547000, 1.998623513417161700, 1.998609251056103100,
-    1.998594915211895600,
-  1.998580505885066100, 1.998566023076144600, 1.998551466785663400,
-    1.998536837014157900,
-  1.998522133762165900, 1.998507357030227900, 1.998492506818887200,
-    1.998477583128690100,
-  1.998462585960185000, 1.998447515313923400, 1.998432371190459500,
-    1.998417153590349900,
-  1.998401862514154200, 1.998386497962434800, 1.998371059935756300,
-    1.998355548434686400,
-  1.998339963459795400, 1.998324305011656600, 1.998308573090845200,
-    1.998292767697940100,
-  1.998276888833522300, 1.998260936498175400, 1.998244910692486000,
-    1.998228811417043700,
-  1.998212638672439900, 1.998196392459269400, 1.998180072778129600,
-    1.998163679629620500,
-  1.998147213014344900, 1.998130672932908000, 1.998114059385918400,
-    1.998097372373986300,
-  1.998080611897725700, 1.998063777957752600, 1.998046870554686100,
-    1.998029889689147700,
-  1.998012835361761900, 1.997995707573155600, 1.997978506323958600,
-    1.997961231614803200,
-  1.997943883446324800, 1.997926461819161000, 1.997908966733952500,
-    1.997891398191342400,
-  1.997873756191977000, 1.997856040736504500, 1.997838251825576400,
-    1.997820389459846700,
-  1.997802453639972300, 1.997784444366612600, 1.997766361640429800,
-    1.997748205462088500,
-  1.997729975832256600, 1.997711672751604200, 1.997693296220804000,
-    1.997674846240532000,
-  1.997656322811466500, 1.997637725934288300, 1.997619055609681600,
-    1.997600311838332500,
-  1.997581494620930300, 1.997562603958166600, 1.997543639850736200,
-    1.997524602299336500,
-  1.997505491304667000, 1.997486306867430900, 1.997467048988333000,
-    1.997447717668082000,
-  1.997428312907388200, 1.997408834706965000, 1.997389283067528800,
-    1.997369657989798400,
-  1.997349959474495200, 1.997330187522343700, 1.997310342134070800,
-    1.997290423310406100,
-  1.997270431052081900, 1.997250365359833200, 1.997230226234397900,
-    1.997210013676516700,
-  1.997189727686932400, 1.997169368266390900, 1.997148935415640600,
-    1.997128429135433400,
-  1.997107849426522600, 1.997087196289665000, 1.997066469725620200,
-    1.997045669735150000,
-  1.997024796319019300, 1.997003849477995600, 1.996982829212848900,
-    1.996961735524351900,
-  1.996940568413280600, 1.996919327880412900, 1.996898013926530000,
-    1.996876626552415400,
-  1.996855165758855600, 1.996833631546639300, 1.996812023916558800,
-    1.996790342869408000,
-  1.996768588405984300, 1.996746760527087700, 1.996724859233520500,
-    1.996702884526087900,
-  1.996680836405598100, 1.996658714872861800, 1.996636519928692000,
-    1.996614251573904900,
-  1.996591909809319400, 1.996569494635756600, 1.996547006054041100,
-    1.996524444064999400,
-  1.996501808669461000, 1.996479099868258400, 1.996456317662226300,
-    1.996433462052202600,
-  1.996410533039027400, 1.996387530623543900, 1.996364454806597500,
-    1.996341305589037100,
-  1.996318082971713500, 1.996294786955480800, 1.996271417541195300,
-    1.996247974729716200,
-  1.996224458521905600, 1.996200868918628100, 1.996177205920750800,
-    1.996153469529144100,
-  1.996129659744680300, 1.996105776568235100, 1.996081820000686500,
-    1.996057790042915500,
-  1.996033686695805300, 1.996009509960242400, 1.995985259837115500,
-    1.995960936327316300,
-  1.995936539431739000, 1.995912069151280800, 1.995887525486841300,
-    1.995862908439323100,
-  1.995838218009630800, 1.995813454198672700, 1.995788617007359100,
-    1.995763706436603200,
-  1.995738722487320600, 1.995713665160430600, 1.995688534456853800,
-    1.995663330377514400,
-  1.995638052923339300, 1.995612702095257400, 1.995587277894201400,
-    1.995561780321105600,
-  1.995536209376907600, 1.995510565062547800, 1.995484847378968600,
-    1.995459056327116000,
-  1.995433191907938000, 1.995407254122385700, 1.995381242971412600,
-    1.995355158455975200,
-  1.995329000577032800, 1.995302769335546500, 1.995276464732481200,
-    1.995250086768804100,
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-    1.995143841327413400,
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-    1.995036422194304700,
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-    1.994927829432669800,
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-    1.994818063106391000,
-  1.994790438162897600, 1.994762739876662100, 1.994734968248702800,
-    1.994707123280041100,
-  1.994679204971700100, 1.994651213324707000, 1.994623148340090700,
-    1.994595010018883000,
-  1.994566798362118300, 1.994538513370834200, 1.994510155046070700,
-    1.994481723388870100,
-  1.994453218400277900, 1.994424640081342100, 1.994395988433113700,
-    1.994367263456646100,
-  1.994338465152995000, 1.994309593523219600, 1.994280648568381500,
-    1.994251630289544600,
-  1.994222538687776100, 1.994193373764145500, 1.994164135519725000,
-    1.994134823955589800,
-  1.994105439072817700, 1.994075980872488800, 1.994046449355686200,
-    1.994016844523496000,
-  1.993987166377006600, 1.993957414917308700, 1.993927590145496900,
-    1.993897692062667200,
-  1.993867720669919400, 1.993837675968354700, 1.993807557959078600,
-    1.993777366643197900,
-  1.993747102021822900, 1.993716764096066200, 1.993686352867043200,
-    1.993655868335872300,
-  1.993625310503674100, 1.993594679371572200, 1.993563974940692800,
-    1.993533197212164800,
-  1.993502346187119700, 1.993471421866692200, 1.993440424252018900,
-    1.993409353344239600,
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-    1.993284336804950900,
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-    1.993158147667842800,
-  1.993126417173840500, 1.993094613398277400, 1.993062736342323000,
-    1.993030786007148800,
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-    1.992902251897793000,
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-    1.992772545415388200,
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-    1.992106430102373400,
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-    1.991969691008174100,
-  1.991935323133897000, 1.991900882021852200, 1.991866367673306200,
-    1.991831780089527500,
-  1.991797119271788300, 1.991762385221362600, 1.991727577939527600,
-    1.991692697427563300,
-  1.991657743686751700, 1.991622716718378400, 1.991587616523731000,
-    1.991552443104099800,
-  1.991517196460778500, 1.991481876595062800, 1.991446483508251500,
-    1.991411017201645500,
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-    0.017065329181012358,
-  0.016681847633368677, 0.016298365472381587, 0.015914882712149747,
-    0.015531399366773606,
-  0.015147915450352307, 0.014764430976985016, 0.014380945960772247,
-    0.013997460415812761,
-  0.013613974356207112, 0.013230487796054543, 0.012847000749454314,
-    0.012463513230507034,
-  0.012080025253311559, 0.011696536831968529, 0.011313047980577277,
-    0.010929558713237145,
-  0.010546069044048827, 0.010162578987111254, 0.009779088556525145,
-    0.009395597766389905,
-  0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
-    0.007861631292354124,
-  0.007478138915970929, 0.007094646264638386, 0.006711153352455981,
-    0.006327660193523208,
-  0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
-    0.004793685372293270,
-  0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
-    0.003259707731061291,
-  0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
-    0.001725728172227238,
-  0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
-    0.000191747598192208,
-
-};
-
-/**    
- * @brief  Initialization function for the floating-point DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.   
- * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.   
- * @param[in]     N			 length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingF32Table.gif    
- */
-
-arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize)
-{
-  /*  Initialize the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  float32_t *twiddlePtr[4] =
-    { (float32_t *) Weights_128, (float32_t *) Weights_512,
-    (float32_t *) Weights_2048, (float32_t *) Weights_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  float32_t *pCosFactor[4] =
-    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
-    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT */
-  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
deleted file mode 100644
index 7a78aa8e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
+++ /dev/null
@@ -1,4284 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_q15.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 Q15    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   weights[2*i]= cos(i*c);    
-*   weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* Converted the output to q15 format by multiplying with 2^31 and saturated if required.    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const q15_t ALIGN4 WeightsQ15_128[256] = {
-  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
-  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
-  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
-  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
-  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
-  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
-  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
-  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
-  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
-  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
-  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
-  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
-  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
-  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
-  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
-  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
-  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
-  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
-  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
-  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
-  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
-  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
-  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
-  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
-  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
-  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
-  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
-  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
-  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
-  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
-  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
-  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
-};
-
-static const q15_t ALIGN4 WeightsQ15_512[1024] = {
-  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
-  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
-  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
-  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
-  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
-  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
-  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
-  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
-  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
-  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
-  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
-  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
-  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
-  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
-  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
-  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
-  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
-  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
-  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
-  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
-  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
-  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
-  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
-  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
-  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
-  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
-  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
-  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
-  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
-  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
-  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
-  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
-  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
-  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
-  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
-  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
-  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
-  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
-  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
-  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
-  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
-  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
-  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
-  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
-  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
-  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
-  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
-  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
-  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
-  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
-  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
-  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
-  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
-  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
-  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
-  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
-  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
-  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
-  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
-  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
-  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
-  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
-  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
-  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
-  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
-  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
-  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
-  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
-  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
-  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
-  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
-  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
-  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
-  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
-  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
-  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
-  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
-  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
-  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
-  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
-  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
-  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
-  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
-  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
-  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
-  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
-  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
-  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
-  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
-  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
-  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
-  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
-  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
-  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
-  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
-  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
-  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
-  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
-  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
-  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
-  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
-  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
-  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
-  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
-  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
-  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
-  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
-  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
-  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
-  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
-  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
-  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
-  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
-  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
-  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
-  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
-  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
-  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
-  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
-  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
-  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
-  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
-  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
-  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
-  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
-  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
-  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
-  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
-};
-
-static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
-  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
-  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
-  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
-  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
-  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
-  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
-  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
-  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
-  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
-  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
-  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
-  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
-  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
-  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
-  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
-  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
-  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
-  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
-  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
-  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
-  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
-  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
-  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
-  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
-  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
-  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
-  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
-  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
-  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
-  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
-  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
-  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
-  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
-  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
-  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
-  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
-  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
-  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
-  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
-  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
-  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
-  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
-  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
-  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
-  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
-  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
-  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
-  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
-  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
-  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
-  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
-  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
-  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
-  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
-  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
-  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
-  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
-  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
-  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
-  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
-  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
-  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
-  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
-  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
-  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
-  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
-  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
-  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
-  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
-  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
-  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
-  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
-  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
-  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
-  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
-  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
-  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
-  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
-  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
-  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
-  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
-  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
-  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
-  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
-  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
-  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
-  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
-  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
-  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
-  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
-  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
-  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
-  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
-  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
-  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
-  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
-  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
-  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
-  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
-  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
-  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
-  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
-  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
-  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
-  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
-  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
-  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
-  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
-  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
-  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
-  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
-  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
-  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
-  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
-  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
-  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
-  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
-  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
-  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
-  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
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-  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
-  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
-  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
-  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
-  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
-  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
-  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
-  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
-  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
-  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
-  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
-  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
-  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
-  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
-  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
-  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
-  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
-  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
-  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
-  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
-  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
-  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
-  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
-  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
-  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
-  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
-  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
-  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
-  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
-  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
-  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
-  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
-  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
-  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
-  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
-  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
-  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
-  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
-  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
-  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
-  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
-  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
-  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
-  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
-  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
-  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
-  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
-  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
-  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
-  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
-  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
-  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
-  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
-  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
-  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
-};
-
-static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
-  0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
-  0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
-  0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
-  0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
-  0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
-  0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
-  0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
-  0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
-  0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
-  0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
-  0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
-  0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
-  0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
-  0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
-  0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
-  0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
-  0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
-  0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
-  0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
-  0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
-  0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
-  0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
-  0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
-  0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
-  0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
-  0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
-  0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
-  0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
-  0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
-  0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
-  0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
-  0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
-  0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
-  0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
-  0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
-  0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
-  0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
-  0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
-  0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
-  0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
-  0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
-  0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
-  0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
-  0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
-  0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
-  0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
-  0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
-  0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
-  0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
-  0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
-  0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
-  0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
-  0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
-  0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
-  0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
-  0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
-  0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
-  0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
-  0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
-  0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
-  0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
-  0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
-  0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
-  0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
-  0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
-  0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
-  0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
-  0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
-  0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
-  0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
-  0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
-  0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
-  0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
-  0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
-  0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
-  0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
-  0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
-  0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
-  0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
-  0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
-  0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
-  0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
-  0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
-  0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
-  0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
-  0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
-  0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
-  0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
-  0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
-  0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
-  0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
-  0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
-  0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
-  0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
-  0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
-  0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
-  0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
-  0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
-  0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
-  0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
-  0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
-  0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
-  0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
-  0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
-  0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
-  0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
-  0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
-  0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
-  0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
-  0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
-  0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
-  0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
-  0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
-  0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
-  0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
-  0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
-  0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
-  0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
-  0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
-  0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
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-  0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
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-  0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
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-  0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
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-  0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
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-  0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
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-  0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
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-  0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
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-  0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
-  0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
-  0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
-  0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
-  0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
-  0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
-  0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
-  0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
-  0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
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-  0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
-  0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
-  0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
-  0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
-  0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
-  0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
-  0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
-  0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
-  0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
-  0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
-  0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
-  0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
-  0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
-  0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
-  0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
-  0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
-  0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
-  0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
-  0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
-  0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
-  0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
-  0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
-  0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
-  0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
-  0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
-  0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
-  0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
-  0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
-  0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
-  0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
-  0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
-  0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
-  0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
-  0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
-  0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
-  0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
-  0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
-  0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
-  0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
-  0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
-  0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
-  0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
-  0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
-  0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
-  0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
-  0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
-  0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
-  0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
-  0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
-  0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
-  0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
-  0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
-  0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
-  0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
-  0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
-  0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
-  0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
-  0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
-  0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
-  0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
-  0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
-  0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
-  0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
-  0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
-  0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
-  0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
-  0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
-  0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
-  0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
-  0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
-  0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
-  0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
-  0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
-  0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
-  0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
-  0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
-  0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
-  0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
-  0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
-  0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
-  0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
-  0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
-  0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
-  0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
-  0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
-  0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
-  0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
-  0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
-  0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
-  0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
-  0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
-  0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
-  0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
-  0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
-  0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
-  0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
-  0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
-  0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
-  0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
-  0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
-  0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
-  0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
-  0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
-  0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
-  0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
-  0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
-  0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
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-  0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
-  0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
-  0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
-  0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
-  0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
-  0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
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-  0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
-  0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
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-  0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
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-  0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
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-  0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
-  0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
-  0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
-  0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
-  0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,
-  0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,
-  0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,
-  0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,
-  0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,
-  0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,
-  0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,
-  0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,
-  0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,
-  0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,
-  0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,
-  0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,
-  0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,
-  0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,
-  0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,
-  0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,
-  0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,
-  0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,
-  0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,
-  0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,
-  0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,
-  0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,
-  0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,
-  0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,
-  0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,
-  0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,
-  0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,
-  0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,
-  0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,
-  0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,
-  0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,
-  0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,
-  0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,
-  0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,
-  0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,
-  0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,
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-  0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
-  0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
-  0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
-  0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
-  0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
-  0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
-  0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
-  0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
-  0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
-  0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
-  0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
-  0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
-  0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
-  0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
-  0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
-  0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
-  0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
-  0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
-  0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
-  0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
-  0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
-  0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
-  0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
-  0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
-  0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
-  0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
-  0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
-  0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
-  0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
-  0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
-  0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
-  0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
-  0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
-  0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
-  0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
-  0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
-  0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
-  0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
-  0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
-  0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
-  0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
-  0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
-  0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
-  0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
-  0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
-  0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
-  0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
-  0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
-  0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
-  0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
-  0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
-  0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
-  0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
-  0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
-  0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
-  0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
-  0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
-  0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
-  0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
-  0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
-  0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
-  0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
-};
-
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-* \par    
-* Then converted to q15 format by multiplying with 2^31 and saturated if required.    
-    
-*/
-
-static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
-  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
-  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
-  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
-  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
-  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
-  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
-  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
-  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
-  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
-  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
-  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
-  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
-  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
-  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
-  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
-  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
-  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
-  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
-  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
-  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
-  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
-  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
-  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
-  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
-  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
-  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
-  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
-  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
-  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
-  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
-  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
-  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
-  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
-  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
-  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
-  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
-  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
-  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
-  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
-  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
-  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
-  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
-  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
-  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
-  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
-  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
-  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
-  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
-  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
-  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
-  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
-  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
-  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
-  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
-  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
-  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
-  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
-  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
-  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
-  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
-  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
-  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
-  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
-  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
-  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
-  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
-  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
-  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
-  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
-  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
-  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
-  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
-  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
-  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
-  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
-  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
-  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
-  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
-  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
-  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
-  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
-  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
-  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
-  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
-  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
-  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
-  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
-  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
-  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
-  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
-  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
-  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
-  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
-  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
-  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
-  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
-  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
-  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
-  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
-  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
-  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
-  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
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-  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
-  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
-  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
-  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
-  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
-  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
-  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
-  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
-  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
-  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
-  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
-  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
-  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
-  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
-  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
-  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
-  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
-  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
-  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
-  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
-  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
-  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
-  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
-  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
-  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
-  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
-  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
-  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
-  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
-  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
-  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
-  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
-  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
-  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
-  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
-  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
-  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
-  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
-  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
-  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
-  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
-  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
-  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
-  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
-  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
-  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
-  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
-  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
-  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
-  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
-  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
-  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
-  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
-  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
-  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
-  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
-  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
-  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
-  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
-  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
-  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
-  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
-  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
-  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
-  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
-  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
-  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
-  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
-  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
-
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
-  0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
-  0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
-  0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
-  0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
-  0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
-  0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
-  0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
-  0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
-  0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
-  0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
-  0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
-  0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
-  0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
-  0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
-  0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
-  0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
-  0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
-  0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
-  0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
-  0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
-  0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
-  0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
-  0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
-  0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
-  0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
-  0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
-  0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
-  0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
-  0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
-  0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
-  0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
-  0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
-  0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
-  0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
-  0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
-  0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
-  0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
-  0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
-  0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
-  0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
-  0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
-  0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
-  0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
-  0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
-  0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
-  0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
-  0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
-  0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
-  0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
-  0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
-  0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
-  0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
-  0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,
-  0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
-  0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,
-  0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,
-  0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,
-  0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,
-  0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,
-  0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,
-  0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,
-  0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
-  0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,
-  0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,
-  0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
-  0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
-  0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
-  0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
-  0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
-  0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
-  0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
-  0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
-  0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
-  0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
-  0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
-  0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
-  0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
-  0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
-  0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
-  0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
-  0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
-  0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
-  0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
-  0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
-  0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
-  0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
-  0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
-  0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
-  0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
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-  0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
-  0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
-  0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
-  0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
-  0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
-  0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
-  0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
-  0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
-  0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
-  0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
-  0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
-  0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
-  0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
-  0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
-  0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
-  0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
-  0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
-  0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
-  0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
-  0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
-  0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
-  0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
-  0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
-  0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
-  0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
-  0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
-  0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
-  0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
-  0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
-  0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
-  0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
-  0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
-  0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
-  0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
-  0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
-  0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
-  0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
-  0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
-  0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
-  0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
-  0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
-  0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
-  0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
-  0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
-  0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
-  0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
-  0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
-  0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
-  0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
-  0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
-  0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
-  0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
-  0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
-  0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
-  0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
-  0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
-  0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
-  0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
-  0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
-  0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
-  0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
-  0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
-  0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
-  0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
-  0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
-  0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
-  0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
-  0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
-  0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
-  0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
-  0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
-  0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
-  0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
-  0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
-  0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
-  0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
-  0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
-  0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
-  0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
-  0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
-  0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
-  0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
-  0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
-  0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
-  0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
-  0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
-  0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
-  0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
-  0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
-  0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
-  0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
-  0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
-  0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
-  0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
-  0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
-  0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
-  0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
-  0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
-  0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
-  0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
-  0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
-  0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
-  0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
-  0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
-  0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
-  0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
-  0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
-  0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
-  0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
-  0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
-  0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
-  0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
-  0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
-};
-
-/**    
- * @brief  Initialization function for the Q15 DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.   
- * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.   
- * @param[in]     N          length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingQ15Table.gif    
- */
-
-arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
-    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  q15_t *pCosFactor[4] =
-    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
-    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT */
-  arm_rfft_init_q15(S->pRfft, S->N, 0u, 1u);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
deleted file mode 100644
index 1aa9081f..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
+++ /dev/null
@@ -1,8364 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_q31.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 Q31    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   weights[2*i]= cos(i*c);    
-*   weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* Convert the output to q31 format by multiplying with 2^31 and saturated if required.    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const q31_t WeightsQ31_128[256] = {
-  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
-  0xfb49e6a3,
-  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
-  0x7f872bf3, 0xf50497fb,
-  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
-  0x7ed5e5c6, 0xeec60f31,
-  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
-  0x7dd6668f, 0xe8922622,
-  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
-  0x7c894bde, 0xe26cb01b,
-  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
-  0x7aef6323, 0xdc597781,
-  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
-  0x7909a92d, 0xd65c3b7b,
-  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
-  0x76d94989, 0xd078ad9e,
-  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
-  0x745f9dd1, 0xcab26fa9,
-  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
-  0x719e2cd2, 0xc50d1149,
-  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
-  0x6e96a99d, 0xbf8c0de3,
-  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
-  0x6b4af279, 0xba32ca71,
-  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
-  0x67bd0fbd, 0xb5049368,
-  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
-  0x63ef3290, 0xb0049ab3,
-  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
-  0x5fe3b38d, 0xab35f5b5,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
-  0x5b9d1154, 0xa69b9b68,
-  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
-  0x571deefa, 0xa2386284,
-  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
-  0x5269126e, 0x9e0effc1,
-  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
-  0x4d8162c4, 0x9a22042d,
-  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
-  0x4869e665, 0x9673db94,
-  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
-  0x4325c135, 0x9306cb04,
-  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
-  0x3db832a6, 0x8fdcef66,
-  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
-  0x382493b0, 0x8cf83c30,
-  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
-  0x326e54c7, 0x8a5a7a31,
-  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
-  0x2c98fbba, 0x88054677,
-  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
-  0x26a82186, 0x85fa1153,
-  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
-  0x209f701c, 0x843a1d70,
-  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
-  0x1a82a026, 0x82c67f14,
-  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
-  0x145576b1, 0x81a01b6d,
-  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
-  0xe1bc2e4, 0x80c7a80a,
-  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
-  0x7d95b9e, 0x803daa6a,
-  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
-  0x1921d20, 0x800277a6,
-};
-
-static const q31_t WeightsQ31_512[1024] = {
-  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
-  0xfed2694f,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
-  0x7ff871a2, 0xfd40565c,
-  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
-  0x7fed5791, 0xfbae5e89,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
-  0x7fdd4eec, 0xfa1c9157,
-  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
-  0x7fc85854, 0xf88afe42,
-  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
-  0x7fae7495, 0xf6f9b4c6,
-  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
-  0x7f8fa4b0, 0xf568c45b,
-  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
-  0x7f6be9d4, 0xf3d83c77,
-  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
-  0x7f434563, 0xf2482c8a,
-  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
-  0x7f15b8ee, 0xf0b8a401,
-  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
-  0x7ee34636, 0xef29b243,
-  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
-  0x7eabef2c, 0xed9b66b2,
-  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
-  0x7e6fb5f4, 0xec0dd0a8,
-  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
-  0x7e2e9cdf, 0xea80ff7a,
-  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
-  0x7de8a670, 0xe8f50273,
-  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
-  0x7d9dd55a, 0xe769e8d8,
-  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
-  0x7d4e2c7f, 0xe5dfc1e5,
-  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
-  0x7cf9aef0, 0xe4569ccb,
-  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
-  0x7ca05ff1, 0xe2ce88b3,
-  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
-  0x7c4242f2, 0xe14794ba,
-  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
-  0x7bdf5b94, 0xdfc1cff3,
-  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
-  0x7b77ada8, 0xde3d4964,
-  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
-  0x7b0b3d2c, 0xdcba1008,
-  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
-  0x7a9a0e50, 0xdb3832cd,
-  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
-  0x7a24256f, 0xd9b7c094,
-  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
-  0x79a98715, 0xd838c82d,
-  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
-  0x792a37fe, 0xd6bb585e,
-  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
-  0x78a63d11, 0xd53f7fda,
-  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
-  0x781d9b65, 0xd3c54d47,
-  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
-  0x7790583e, 0xd24ccf39,
-  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
-  0x76fe790e, 0xd0d61434,
-  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
-  0x76680376, 0xcf612aaa,
-  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
-  0x75ccfd42, 0xcdee20fc,
-  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
-  0x752d6c6c, 0xcc7d0578,
-  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
-  0x7489571c, 0xcb0de658,
-  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
-  0x73e0c3a3, 0xc9a0d1c5,
-  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
-  0x7333b883, 0xc835d5d0,
-  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
-  0x72823c67, 0xc6cd0079,
-  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
-  0x71cc5626, 0xc5665fa9,
-  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
-  0x71120cc5, 0xc4020133,
-  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
-  0x70536771, 0xc29ff2d4,
-  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
-  0x6f906d84, 0xc1404233,
-  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
-  0x6ec92683, 0xbfe2fcdf,
-  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
-  0x6dfd9a1c, 0xbe88304f,
-  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
-  0x6d2dd027, 0xbd2fe9e2,
-  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
-  0x6c59d0a9, 0xbbda36dd,
-  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
-  0x6b81a3cd, 0xba87246d,
-  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
-  0x6aa551e9, 0xb936bfa4,
-  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
-  0x69c4e37a, 0xb7e9157a,
-  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
-  0x68e06129, 0xb69e32cd,
-  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
-  0x67f7d3c5, 0xb556245e,
-  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
-  0x670b4444, 0xb410f6d3,
-  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
-  0x661abbc5, 0xb2ceb6b5,
-  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
-  0x6526438f, 0xb18f7071,
-  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
-  0x642de50d, 0xb0533055,
-  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
-  0x6331a9d4, 0xaf1a0293,
-  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
-  0x62319b9d, 0xade3f33e,
-  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
-  0x612dc447, 0xacb10e4b,
-  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
-  0x60262dd6, 0xab815f8d,
-  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
-  0x5f1ae274, 0xaa54f2ba,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
-  0x5e0bec6e, 0xa92bd367,
-  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
-  0x5cf95638, 0xa8060d08,
-  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
-  0x5be32a67, 0xa6e3aaf2,
-  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
-  0x5ac973b5, 0xa5c4b855,
-  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
-  0x59ac3cfd, 0xa4a94043,
-  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
-  0x588b9140, 0xa3914da8,
-  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
-  0x57677b9d, 0xa27ceb4f,
-  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
-  0x56400758, 0xa16c23e1,
-  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
-  0x55153fd4, 0xa05f01e1,
-  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
-  0x53e73097, 0x9f558fb0,
-  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
-  0x52b5e546, 0x9e4fd78a,
-  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
-  0x518169a5, 0x9d4de385,
-  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
-  0x5049c999, 0x9c4fbd93,
-  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
-  0x4f0f1126, 0x9b556f81,
-  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
-  0x4dd14c6e, 0x9a5f02f5,
-  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
-  0x4c9087b1, 0x996c816f,
-  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
-  0x4b4ccf4d, 0x987df449,
-  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
-  0x4a062fbd, 0x979364b5,
-  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
-  0x48bcb599, 0x96acdbbe,
-  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
-  0x47706d93, 0x95ca6247,
-  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
-  0x4621647d, 0x94ec010b,
-  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
-  0x44cfa740, 0x9411c09e,
-  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
-  0x437b42e1, 0x933ba968,
-  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
-  0x42244481, 0x9269c3ac,
-  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
-  0x40cab958, 0x919c1781,
-  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
-  0x3f6eaeb8, 0x90d2acd4,
-  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
-  0x3e10320d, 0x900d8b69,
-  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
-  0x3caf50da, 0x8f4cbadb,
-  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
-  0x3b4c18ba, 0x8e904298,
-  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
-  0x39e6975e, 0x8dd829e4,
-  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
-  0x387eda8e, 0x8d2477d8,
-  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
-  0x3714f02a, 0x8c753362,
-  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
-  0x35a8e625, 0x8bca6343,
-  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
-  0x343aca87, 0x8b240e11,
-  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
-  0x32caab6f, 0x8a823a36,
-  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
-  0x3158970e, 0x89e4edef,
-  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
-  0x2fe49ba7, 0x894c2f4c,
-  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
-  0x2e6ec792, 0x88b80432,
-  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
-  0x2cf72939, 0x88287256,
-  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
-  0x2b7dcf17, 0x879d7f41,
-  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
-  0x2a02c7b8, 0x8717304e,
-  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
-  0x288621b9, 0x86958aac,
-  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
-  0x2707ebc7, 0x86189359,
-  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
-  0x2588349d, 0x85a04f28,
-  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
-  0x24070b08, 0x852cc2bb,
-  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
-  0x22847de0, 0x84bdf286,
-  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
-  0x21009c0c, 0x8453e2cf,
-  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
-  0x1f7b7481, 0x83ee97ad,
-  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
-  0x1df5163f, 0x838e1507,
-  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
-  0x1c6d9053, 0x83325e97,
-  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
-  0x1ae4f1d6, 0x82db77e5,
-  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
-  0x195b49ea, 0x8289644b,
-  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
-  0x17d0a7bc, 0x823c26f3,
-  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
-  0x16451a83, 0x81f3c2d7,
-  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
-  0x14b8b17f, 0x81b03ac2,
-  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
-  0x132b7bf9, 0x8171914e,
-  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
-  0x119d8941, 0x8137c8e6,
-  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
-  0x100ee8ad, 0x8102e3c4,
-  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
-  0xe7fa99e, 0x80d2e3f2,
-  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
-  0xcefdb76, 0x80a7cb49,
-  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
-  0xb5f8d9f, 0x80819b74,
-  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
-  0x9cecf89, 0x806055eb,
-  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
-  0x83db0a7, 0x8043fbf6,
-  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
-  0x6ac406f, 0x802c8ead,
-  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
-  0x51a8e5c, 0x801a0ef8,
-  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
-  0x388a9ea, 0x800c7d8c,
-  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
-  0x1f6a297, 0x8003daf1,
-  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
-  0x6487e3, 0x8000277a,
-};
-
-static const q31_t WeightsQ31_2048[4096] = {
-  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
-  0xffb49a12,
-  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
-  0x7fff8719, 0xff501258,
-  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
-  0x7ffed572, 0xfeeb8b0a,
-  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
-  0x7ffdd4d7, 0xfe870467,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
-  0x7ffc8549, 0xfe227eac,
-  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
-  0x7ffae6c7, 0xfdbdfa18,
-  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
-  0x7ff8f954, 0xfd5976e9,
-  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
-  0x7ff6bcf0, 0xfcf4f55c,
-  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
-  0x7ff4319d, 0xfc9075af,
-  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
-  0x7ff1575d, 0xfc2bf821,
-  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
-  0x7fee2e30, 0xfbc77cf0,
-  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
-  0x7feab61a, 0xfb630459,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
-  0x7fe6ef1c, 0xfafe8e9b,
-  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
-  0x7fe2d938, 0xfa9a1bf3,
-  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
-  0x7fde7471, 0xfa35ac9f,
-  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
-  0x7fd9c0ca, 0xf9d140de,
-  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
-  0x7fd4be46, 0xf96cd8ed,
-  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
-  0x7fcf6ce8, 0xf908750a,
-  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
-  0x7fc9ccb2, 0xf8a41574,
-  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
-  0x7fc3dda9, 0xf83fba68,
-  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
-  0x7fbd9fd0, 0xf7db6423,
-  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
-  0x7fb7132b, 0xf77712e5,
-  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
-  0x7fb037bf, 0xf712c6ea,
-  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
-  0x7fa90d8e, 0xf6ae8071,
-  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
-  0x7fa1949e, 0xf64a3fb8,
-  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
-  0x7f99ccf4, 0xf5e604fc,
-  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
-  0x7f91b694, 0xf581d07b,
-  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
-  0x7f895182, 0xf51da273,
-  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
-  0x7f809dc5, 0xf4b97b21,
-  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
-  0x7f779b62, 0xf4555ac5,
-  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
-  0x7f6e4a5e, 0xf3f1419a,
-  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
-  0x7f64aabf, 0xf38d2fe0,
-  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
-  0x7f5abc8a, 0xf32925d3,
-  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
-  0x7f507fc7, 0xf2c523b2,
-  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
-  0x7f45f47b, 0xf26129ba,
-  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
-  0x7f3b1aad, 0xf1fd3829,
-  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
-  0x7f2ff263, 0xf1994f3d,
-  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
-  0x7f247ba5, 0xf1356f32,
-  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
-  0x7f18b679, 0xf0d19848,
-  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
-  0x7f0ca2e7, 0xf06dcaba,
-  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
-  0x7f0040f6, 0xf00a06c8,
-  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
-  0x7ef390ae, 0xefa64cae,
-  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
-  0x7ee69217, 0xef429caa,
-  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
-  0x7ed94538, 0xeedef6f9,
-  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
-  0x7ecbaa1a, 0xee7b5bd9,
-  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
-  0x7ebdc0c6, 0xee17cb88,
-  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
-  0x7eaf8943, 0xedb44642,
-  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
-  0x7ea1039b, 0xed50cc46,
-  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
-  0x7e922fd6, 0xeced5dd0,
-  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
-  0x7e830dff, 0xec89fb1e,
-  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
-  0x7e739e1d, 0xec26a46d,
-  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
-  0x7e63e03b, 0xebc359fb,
-  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
-  0x7e53d462, 0xeb601c04,
-  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
-  0x7e437a9c, 0xeafceac6,
-  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
-  0x7e32d2f4, 0xea99c67e,
-  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
-  0x7e21dd73, 0xea36af69,
-  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
-  0x7e109a24, 0xe9d3a5c5,
-  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
-  0x7dff0911, 0xe970a9ce,
-  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
-  0x7ded2a47, 0xe90dbbc2,
-  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
-  0x7ddafdce, 0xe8aadbde,
-  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
-  0x7dc883b4, 0xe8480a5d,
-  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
-  0x7db5bc02, 0xe7e5477f,
-  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
-  0x7da2a6c6, 0xe782937e,
-  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
-  0x7d8f4409, 0xe71fee99,
-  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
-  0x7d7b93da, 0xe6bd590d,
-  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
-  0x7d679642, 0xe65ad315,
-  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
-  0x7d534b50, 0xe5f85cef,
-  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
-  0x7d3eb30f, 0xe595f6d7,
-  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
-  0x7d29cd8c, 0xe533a10a,
-  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
-  0x7d149ad5, 0xe4d15bc6,
-  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
-  0x7cff1af5, 0xe46f2745,
-  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
-  0x7ce94dfb, 0xe40d03c6,
-  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
-  0x7cd333f3, 0xe3aaf184,
-  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
-  0x7cbcccec, 0xe348f0bd,
-  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
-  0x7ca618f3, 0xe2e701ac,
-  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
-  0x7c8f1817, 0xe285248d,
-  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
-  0x7c77ca65, 0xe223599e,
-  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
-  0x7c602fec, 0xe1c1a11b,
-  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
-  0x7c4848ba, 0xe15ffb3f,
-  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
-  0x7c3014de, 0xe0fe6848,
-  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
-  0x7c179467, 0xe09ce871,
-  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
-  0x7bfec765, 0xe03b7bf6,
-  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
-  0x7be5ade6, 0xdfda2314,
-  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
-  0x7bcc47fa, 0xdf78de07,
-  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
-  0x7bb295b0, 0xdf17ad0a,
-  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
-  0x7b989719, 0xdeb69059,
-  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
-  0x7b7e4c45, 0xde558831,
-  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
-  0x7b63b543, 0xddf494ce,
-  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
-  0x7b48d225, 0xdd93b66a,
-  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
-  0x7b2da2fa, 0xdd32ed43,
-  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
-  0x7b1227d3, 0xdcd23993,
-  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
-  0x7af660c2, 0xdc719b96,
-  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
-  0x7ada4dd8, 0xdc111388,
-  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
-  0x7abdef25, 0xdbb0a1a4,
-  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
-  0x7aa144bc, 0xdb504626,
-  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
-  0x7a844eae, 0xdaf00149,
-  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
-  0x7a670d0d, 0xda8fd349,
-  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
-  0x7a497feb, 0xda2fbc61,
-  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
-  0x7a2ba75a, 0xd9cfbccd,
-  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
-  0x7a0d836d, 0xd96fd4c7,
-  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
-  0x79ef1436, 0xd910048a,
-  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
-  0x79d059c8, 0xd8b04c52,
-  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
-  0x79b15435, 0xd850ac5a,
-  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
-  0x79920392, 0xd7f124dd,
-  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
-  0x797267f2, 0xd791b616,
-  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
-  0x79528167, 0xd732603f,
-  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
-  0x79325006, 0xd6d32393,
-  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
-  0x7911d3e2, 0xd674004e,
-  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
-  0x78f10d0f, 0xd614f6a9,
-  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
-  0x78cffba3, 0xd5b606e0,
-  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
-  0x78ae9fb0, 0xd557312d,
-  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
-  0x788cf94c, 0xd4f875ca,
-  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
-  0x786b088c, 0xd499d4f2,
-  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
-  0x7848cd83, 0xd43b4ee0,
-  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
-  0x78264849, 0xd3dce3cd,
-  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
-  0x780378f1, 0xd37e93f4,
-  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
-  0x77e05f91, 0xd3205f8f,
-  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
-  0x77bcfc3f, 0xd2c246d8,
-  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
-  0x77994f11, 0xd2644a0a,
-  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
-  0x7775581d, 0xd206695d,
-  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
-  0x77511778, 0xd1a8a50d,
-  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
-  0x772c8d3a, 0xd14afd52,
-  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
-  0x7707b979, 0xd0ed7267,
-  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
-  0x76e29c4b, 0xd0900486,
-  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
-  0x76bd35c7, 0xd032b3e7,
-  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
-  0x76978605, 0xcfd580c6,
-  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
-  0x76718d1c, 0xcf786b5a,
-  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
-  0x764b4b23, 0xcf1b73de,
-  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
-  0x7624c031, 0xcebe9a8a,
-  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
-  0x75fdec60, 0xce61df99,
-  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
-  0x75d6cfc5, 0xce054343,
-  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
-  0x75af6a7b, 0xcda8c5c1,
-  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
-  0x7587bc98, 0xcd4c674d,
-  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
-  0x755fc635, 0xccf0281f,
-  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
-  0x7537876c, 0xcc940871,
-  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
-  0x750f0054, 0xcc38087b,
-  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
-  0x74e63108, 0xcbdc2876,
-  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
-  0x74bd199f, 0xcb80689a,
-  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
-  0x7493ba34, 0xcb24c921,
-  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
-  0x746a12df, 0xcac94a42,
-  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
-  0x744023bc, 0xca6dec37,
-  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
-  0x7415ece2, 0xca12af37,
-  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
-  0x73eb6e6e, 0xc9b7937a,
-  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
-  0x73c0a878, 0xc95c993a,
-  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
-  0x73959b1b, 0xc901c0ae,
-  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
-  0x736a4671, 0xc8a70a0e,
-  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
-  0x733eaa96, 0xc84c7593,
-  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
-  0x7312c7a5, 0xc7f20373,
-  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
-  0x72e69db7, 0xc797b3e7,
-  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
-  0x72ba2cea, 0xc73d8727,
-  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
-  0x728d7557, 0xc6e37d69,
-  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
-  0x7260771b, 0xc68996e7,
-  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
-  0x72333251, 0xc62fd3d6,
-  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
-  0x7205a716, 0xc5d6346f,
-  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
-  0x71d7d585, 0xc57cb8e9,
-  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
-  0x71a9bdba, 0xc523617a,
-  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
-  0x717b5fd3, 0xc4ca2e5b,
-  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
-  0x714cbbeb, 0xc4711fc2,
-  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
-  0x711dd220, 0xc41835e6,
-  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
-  0x70eea28e, 0xc3bf70fd,
-  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
-  0x70bf2d53, 0xc366d140,
-  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
-  0x708f728b, 0xc30e56e4,
-  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
-  0x705f7255, 0xc2b6021f,
-  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
-  0x702f2ccd, 0xc25dd329,
-  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
-  0x6ffea212, 0xc205ca38,
-  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
-  0x6fcdd241, 0xc1ade781,
-  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
-  0x6f9cbd79, 0xc1562b3d,
-  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
-  0x6f6b63d8, 0xc0fe959f,
-  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
-  0x6f39c57d, 0xc0a726df,
-  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
-  0x6f07e285, 0xc04fdf32,
-  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
-  0x6ed5bb10, 0xbff8bece,
-  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
-  0x6ea34f3d, 0xbfa1c5ea,
-  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
-  0x6e709f2a, 0xbf4af4ba,
-  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
-  0x6e3daaf8, 0xbef44b74,
-  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
-  0x6e0a72c5, 0xbe9dca4e,
-  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
-  0x6dd6f6b1, 0xbe47717c,
-  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
-  0x6da336dc, 0xbdf14135,
-  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
-  0x6d6f3365, 0xbd9b39ad,
-  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
-  0x6d3aec6e, 0xbd455b1a,
-  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
-  0x6d066215, 0xbcefa5b0,
-  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
-  0x6cd1947c, 0xbc9a19a5,
-  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
-  0x6c9c83c3, 0xbc44b72c,
-  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
-  0x6c67300b, 0xbbef7e7c,
-  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
-  0x6c319975, 0xbb9a6fc7,
-  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
-  0x6bfbc021, 0xbb458b43,
-  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
-  0x6bc5a431, 0xbaf0d125,
-  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
-  0x6b8f45c7, 0xba9c41a0,
-  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
-  0x6b58a503, 0xba47dce8,
-  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
-  0x6b21c208, 0xb9f3a332,
-  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
-  0x6aea9cf8, 0xb99f94b2,
-  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
-  0x6ab335f4, 0xb94bb19b,
-  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
-  0x6a7b8d1e, 0xb8f7fa21,
-  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
-  0x6a43a29a, 0xb8a46e78,
-  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
-  0x6a0b7689, 0xb8510ed4,
-  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
-  0x69d3090e, 0xb7fddb67,
-  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
-  0x699a5a4c, 0xb7aad465,
-  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
-  0x69616a65, 0xb757fa01,
-  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
-  0x6928397e, 0xb7054c6f,
-  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
-  0x68eec7b9, 0xb6b2cbe2,
-  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
-  0x68b5153a, 0xb660788c,
-  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
-  0x687b2224, 0xb60e529f,
-  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
-  0x6840ee9b, 0xb5bc5a50,
-  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
-  0x68067ac3, 0xb56a8fd0,
-  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
-  0x67cbc6c0, 0xb518f351,
-  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
-  0x6790d2b6, 0xb4c78507,
-  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
-  0x67559eca, 0xb4764523,
-  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
-  0x671a2b20, 0xb42533d8,
-  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
-  0x66de77dc, 0xb3d45157,
-  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
-  0x66a28524, 0xb3839dd3,
-  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
-  0x6666531d, 0xb333197c,
-  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
-  0x6629e1ec, 0xb2e2c486,
-  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
-  0x65ed31b5, 0xb2929f21,
-  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
-  0x65b0429f, 0xb242a97e,
-  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
-  0x657314cf, 0xb1f2e3d0,
-  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
-  0x6535a86b, 0xb1a34e47,
-  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
-  0x64f7fd98, 0xb153e915,
-  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
-  0x64ba147d, 0xb104b46a,
-  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
-  0x647bed3f, 0xb0b5b077,
-  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
-  0x643d8806, 0xb066dd6d,
-  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
-  0x63fee4f8, 0xb0183b7d,
-  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
-  0x63c0043b, 0xafc9cad7,
-  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
-  0x6380e5f6, 0xaf7b8bac,
-  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
-  0x63418a50, 0xaf2d7e2b,
-  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
-  0x6301f171, 0xaedfa285,
-  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
-  0x62c21b7e, 0xae91f8eb,
-  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
-  0x628208a1, 0xae44818b,
-  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
-  0x6241b8ff, 0xadf73c96,
-  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
-  0x62012cc2, 0xadaa2a3b,
-  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
-  0x61c06410, 0xad5d4aaa,
-  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
-  0x617f5f12, 0xad109e12,
-  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
-  0x613e1df0, 0xacc424a3,
-  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
-  0x60fca0d2, 0xac77de8b,
-  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
-  0x60bae7e1, 0xac2bcbfa,
-  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
-  0x6078f344, 0xabdfed1f,
-  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
-  0x6036c325, 0xab944229,
-  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
-  0x5ff457ad, 0xab48cb46,
-  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
-  0x5fb1b104, 0xaafd88a4,
-  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
-  0x5f6ecf53, 0xaab27a73,
-  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
-  0x5f2bb2c5, 0xaa67a0e0,
-  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
-  0x5ee85b82, 0xaa1cfc1a,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
-  0x5ea4c9b3, 0xa9d28c4e,
-  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
-  0x5e60fd84, 0xa98851ac,
-  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
-  0x5e1cf71c, 0xa93e4c5f,
-  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
-  0x5dd8b6a7, 0xa8f47c97,
-  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
-  0x5d943c4e, 0xa8aae280,
-  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
-  0x5d4f883b, 0xa8617e48,
-  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
-  0x5d0a9a9a, 0xa818501c,
-  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
-  0x5cc57394, 0xa7cf582a,
-  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
-  0x5c801354, 0xa786969e,
-  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
-  0x5c3a7a05, 0xa73e0ba5,
-  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
-  0x5bf4a7d2, 0xa6f5b76d,
-  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
-  0x5bae9ce7, 0xa6ad9a21,
-  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
-  0x5b68596d, 0xa665b3ee,
-  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
-  0x5b21dd90, 0xa61e0501,
-  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
-  0x5adb297d, 0xa5d68d85,
-  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
-  0x5a943d5e, 0xa58f4da8,
-  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
-  0x5a4d1960, 0xa5484594,
-  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
-  0x5a05bdae, 0xa5017575,
-  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
-  0x59be2a74, 0xa4badd78,
-  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
-  0x59765fde, 0xa4747dc7,
-  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
-  0x592e5e19, 0xa42e568f,
-  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
-  0x58e62552, 0xa3e867fa,
-  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
-  0x589db5b3, 0xa3a2b234,
-  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
-  0x58550f6c, 0xa35d3567,
-  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
-  0x580c32a7, 0xa317f1bf,
-  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
-  0x57c31f92, 0xa2d2e766,
-  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
-  0x5779d65b, 0xa28e1687,
-  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
-  0x5730572e, 0xa2497f4c,
-  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
-  0x56e6a239, 0xa20521e0,
-  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
-  0x569cb7a8, 0xa1c0fe6c,
-  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
-  0x565297ab, 0xa17d151b,
-  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
-  0x5608426e, 0xa1396617,
-  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
-  0x55bdb81f, 0xa0f5f189,
-  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
-  0x5572f8ed, 0xa0b2b79b,
-  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
-  0x55280505, 0xa06fb876,
-  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
-  0x54dcdc96, 0xa02cf444,
-  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
-  0x54917fce, 0x9fea6b2f,
-  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
-  0x5445eedb, 0x9fa81d5e,
-  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
-  0x53fa29ed, 0x9f660afb,
-  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
-  0x53ae3131, 0x9f24342f,
-  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
-  0x536204d7, 0x9ee29922,
-  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
-  0x5315a50e, 0x9ea139fd,
-  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
-  0x52c91204, 0x9e6016e8,
-  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
-  0x527c4bea, 0x9e1f300b,
-  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
-  0x522f52ee, 0x9dde858e,
-  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
-  0x51e22740, 0x9d9e179a,
-  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
-  0x5194c910, 0x9d5de656,
-  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
-  0x5147388c, 0x9d1df1e9,
-  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
-  0x50f975e6, 0x9cde3a7b,
-  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
-  0x50ab814d, 0x9c9ec033,
-  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
-  0x505d5af1, 0x9c5f8339,
-  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
-  0x500f0302, 0x9c2083b3,
-  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
-  0x4fc079b1, 0x9be1c1c8,
-  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
-  0x4f71bf2e, 0x9ba33da0,
-  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
-  0x4f22d3aa, 0x9b64f760,
-  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
-  0x4ed3b755, 0x9b26ef2f,
-  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
-  0x4e846a60, 0x9ae92533,
-  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
-  0x4e34ecfc, 0x9aab9993,
-  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
-  0x4de53f5a, 0x9a6e4c74,
-  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
-  0x4d9561ac, 0x9a313dfc,
-  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
-  0x4d455422, 0x99f46e51,
-  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
-  0x4cf516ee, 0x99b7dd99,
-  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
-  0x4ca4aa41, 0x997b8bf8,
-  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
-  0x4c540e4e, 0x993f7993,
-  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
-  0x4c034345, 0x9903a691,
-  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
-  0x4bb24958, 0x98c81316,
-  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
-  0x4b6120bb, 0x988cbf46,
-  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
-  0x4b0fc99d, 0x9851ab46,
-  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
-  0x4abe4433, 0x9816d73b,
-  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
-  0x4a6c90ad, 0x97dc4349,
-  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
-  0x4a1aaf3f, 0x97a1ef94,
-  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
-  0x49c8a01b, 0x9767dc41,
-  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
-  0x49766373, 0x972e0971,
-  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
-  0x4923f97b, 0x96f4774b,
-  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
-  0x48d16265, 0x96bb25f0,
-  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
-  0x487e9e64, 0x96821585,
-  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
-  0x482badab, 0x9649462d,
-  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
-  0x47d8906d, 0x9610b80a,
-  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
-  0x478546de, 0x95d86b3f,
-  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
-  0x4731d131, 0x95a05ff0,
-  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
-  0x46de2f99, 0x9568963f,
-  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
-  0x468a624a, 0x95310e4e,
-  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
-  0x46366978, 0x94f9c83f,
-  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
-  0x45e24556, 0x94c2c435,
-  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
-  0x458df619, 0x948c0252,
-  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
-  0x45397bf4, 0x945582b7,
-  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
-  0x44e4d71c, 0x941f4585,
-  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
-  0x449007c4, 0x93e94adf,
-  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
-  0x443b0e21, 0x93b392e6,
-  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
-  0x43e5ea68, 0x937e1dbb,
-  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
-  0x43909ccd, 0x9348eb7e,
-  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
-  0x433b2585, 0x9313fc51,
-  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
-  0x42e584c3, 0x92df5054,
-  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
-  0x428fbabe, 0x92aae7a8,
-  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
-  0x4239c7aa, 0x9276c26d,
-  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
-  0x41e3abbc, 0x9242e0c4,
-  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
-  0x418d6729, 0x920f42cb,
-  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
-  0x4136fa27, 0x91dbe8a4,
-  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
-  0x40e064ea, 0x91a8d26d,
-  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
-  0x4089a7a8, 0x91760047,
-  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
-  0x4032c297, 0x91437250,
-  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
-  0x3fdbb5ec, 0x911128a8,
-  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
-  0x3f8481dd, 0x90df236e,
-  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
-  0x3f2d26a0, 0x90ad62c0,
-  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
-  0x3ed5a46b, 0x907be6be,
-  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
-  0x3e7dfb73, 0x904aaf86,
-  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
-  0x3e262bee, 0x9019bd36,
-  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
-  0x3dce3614, 0x8fe90fec,
-  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
-  0x3d761a19, 0x8fb8a7c7,
-  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
-  0x3d1dd835, 0x8f8884e4,
-  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
-  0x3cc5709e, 0x8f58a761,
-  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
-  0x3c6ce38a, 0x8f290f5c,
-  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
-  0x3c143130, 0x8ef9bcf2,
-  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
-  0x3bbb59c7, 0x8ecab040,
-  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
-  0x3b625d86, 0x8e9be963,
-  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
-  0x3b093ca3, 0x8e6d6877,
-  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
-  0x3aaff755, 0x8e3f2d9b,
-  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
-  0x3a568dd4, 0x8e1138ea,
-  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
-  0x39fd0056, 0x8de38a80,
-  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
-  0x39a34f13, 0x8db6227a,
-  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
-  0x39497a43, 0x8d8900f3,
-  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
-  0x38ef821c, 0x8d5c2609,
-  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
-  0x389566d6, 0x8d2f91d5,
-  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
-  0x383b28a9, 0x8d034474,
-  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
-  0x37e0c7cc, 0x8cd73e01,
-  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
-  0x37864477, 0x8cab7e98,
-  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
-  0x372b9ee3, 0x8c800652,
-  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
-  0x36d0d746, 0x8c54d54c,
-  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
-  0x3675edd9, 0x8c29eb9f,
-  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
-  0x361ae2d3, 0x8bff4966,
-  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
-  0x35bfb66e, 0x8bd4eebc,
-  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
-  0x356468e2, 0x8baadbba,
-  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
-  0x3508fa66, 0x8b81107b,
-  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
-  0x34ad6b32, 0x8b578d18,
-  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
-  0x3451bb81, 0x8b2e51ab,
-  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
-  0x33f5eb89, 0x8b055e4d,
-  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
-  0x3399fb85, 0x8adcb318,
-  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
-  0x333debab, 0x8ab45024,
-  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
-  0x32e1bc36, 0x8a8c358b,
-  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
-  0x32856d5e, 0x8a646365,
-  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
-  0x3228ff5c, 0x8a3cd9cc,
-  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
-  0x31cc7269, 0x8a1598d6,
-  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
-  0x316fc6be, 0x89eea09d,
-  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
-  0x3112fc95, 0x89c7f138,
-  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
-  0x30b61426, 0x89a18ac0,
-  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
-  0x30590dab, 0x897b6d4c,
-  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
-  0x2ffbe95d, 0x895598f3,
-  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
-  0x2f9ea775, 0x89300dce,
-  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
-  0x2f41482e, 0x890acbf2,
-  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
-  0x2ee3cbc1, 0x88e5d378,
-  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
-  0x2e863267, 0x88c12475,
-  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
-  0x2e287c5a, 0x889cbf01,
-  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
-  0x2dcaa9d5, 0x8878a332,
-  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
-  0x2d6cbb10, 0x8854d11e,
-  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
-  0x2d0eb046, 0x883148db,
-  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
-  0x2cb089b1, 0x880e0a7f,
-  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
-  0x2c52478a, 0x87eb1621,
-  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
-  0x2bf3ea0d, 0x87c86bd5,
-  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
-  0x2b957173, 0x87a60bb1,
-  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
-  0x2b36ddf7, 0x8783f5ca,
-  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
-  0x2ad82fd2, 0x87622a35,
-  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
-  0x2a796740, 0x8740a907,
-  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
-  0x2a1a847b, 0x871f7255,
-  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
-  0x29bb87bc, 0x86fe8633,
-  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
-  0x295c7140, 0x86dde4b5,
-  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
-  0x28fd4140, 0x86bd8df0,
-  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
-  0x289df7f8, 0x869d81f8,
-  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
-  0x283e95a1, 0x867dc0e0,
-  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
-  0x27df1a77, 0x865e4abb,
-  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
-  0x277f86b5, 0x863f1f9e,
-  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
-  0x271fda96, 0x86203f9c,
-  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
-  0x26c01655, 0x8601aac7,
-  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
-  0x26603a2c, 0x85e36132,
-  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
-  0x26004657, 0x85c562f1,
-  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
-  0x25a03b11, 0x85a7b015,
-  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
-  0x25401896, 0x858a48b1,
-  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
-  0x24dfdf20, 0x856d2cd7,
-  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
-  0x247f8eec, 0x85505c99,
-  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
-  0x241f2833, 0x8533d809,
-  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
-  0x23beab33, 0x85179f39,
-  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
-  0x235e1826, 0x84fbb239,
-  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
-  0x22fd6f48, 0x84e0111b,
-  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
-  0x229cb0d5, 0x84c4bbf0,
-  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
-  0x223bdd08, 0x84a9b2ca,
-  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
-  0x21daf41d, 0x848ef5b7,
-  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
-  0x2179f64f, 0x847484ca,
-  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
-  0x2118e3dc, 0x845a6012,
-  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
-  0x20b7bcfe, 0x844087a0,
-  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
-  0x205681f1, 0x8426fb84,
-  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
-  0x1ff532f2, 0x840dbbcc,
-  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
-  0x1f93d03c, 0x83f4c889,
-  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
-  0x1f325a0b, 0x83dc21cb,
-  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
-  0x1ed0d09d, 0x83c3c7a0,
-  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
-  0x1e6f342c, 0x83abba17,
-  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
-  0x1e0d84f5, 0x8393f940,
-  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
-  0x1dabc334, 0x837c8528,
-  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
-  0x1d49ef26, 0x83655ddf,
-  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
-  0x1ce80906, 0x834e8373,
-  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
-  0x1c861113, 0x8337f5f1,
-  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
-  0x1c240786, 0x8321b568,
-  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
-  0x1bc1ec9e, 0x830bc1e6,
-  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
-  0x1b5fc097, 0x82f61b77,
-  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
-  0x1afd83ad, 0x82e0c22a,
-  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
-  0x1a9b361d, 0x82cbb60b,
-  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
-  0x1a38d823, 0x82b6f727,
-  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
-  0x19d669fc, 0x82a2858c,
-  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
-  0x1973ebe6, 0x828e6146,
-  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
-  0x19115e1c, 0x827a8a61,
-  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
-  0x18aec0db, 0x826700e9,
-  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
-  0x184c1461, 0x8253c4eb,
-  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
-  0x17e958ea, 0x8240d673,
-  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
-  0x17868eb3, 0x822e358b,
-  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
-  0x1723b5f9, 0x821be240,
-  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
-  0x16c0cef9, 0x8209dc9e,
-  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
-  0x165dd9f0, 0x81f824ae,
-  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
-  0x15fad71b, 0x81e6ba7c,
-  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
-  0x1597c6b7, 0x81d59e13,
-  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
-  0x1534a901, 0x81c4cf7d,
-  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
-  0x14d17e36, 0x81b44ec4,
-  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
-  0x146e4694, 0x81a41bf4,
-  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
-  0x140b0258, 0x81943715,
-  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
-  0x13a7b1bf, 0x8184a032,
-  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
-  0x13445505, 0x81755754,
-  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
-  0x12e0ec6a, 0x81665c84,
-  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
-  0x127d7829, 0x8157afcd,
-  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
-  0x1219f880, 0x81495136,
-  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
-  0x11b66dad, 0x813b40ca,
-  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
-  0x1152d7ed, 0x812d7e8f,
-  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
-  0x10ef377d, 0x81200a90,
-  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
-  0x108b8c9b, 0x8112e4d4,
-  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
-  0x1027d784, 0x81060d63,
-  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
-  0xfc41876, 0x80f98446,
-  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
-  0xf604faf, 0x80ed4984,
-  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
-  0xefc7d6b, 0x80e15d24,
-  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
-  0xe98a1e9, 0x80d5bf2e,
-  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
-  0xe34bd66, 0x80ca6fa9,
-  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
-  0xdd0d01f, 0x80bf6e9c,
-  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
-  0xd6cda53, 0x80b4bc0e,
-  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
-  0xd08dc3f, 0x80aa5806,
-  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
-  0xca4d620, 0x80a04289,
-  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
-  0xc40c835, 0x80967b9f,
-  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
-  0xbdcb2bb, 0x808d034c,
-  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
-  0xb7895f0, 0x8083d998,
-  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
-  0xb147211, 0x807afe87,
-  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
-  0xab0475c, 0x8072721f,
-  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
-  0xa4c1610, 0x806a3466,
-  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
-  0x9e7de6a, 0x80624560,
-  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
-  0x983a0a7, 0x805aa512,
-  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
-  0x91f5d06, 0x80535381,
-  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
-  0x8bb13c5, 0x804c50b2,
-  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
-  0x856c520, 0x80459ca9,
-  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
-  0x7f27157, 0x803f376a,
-  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
-  0x78e18a7, 0x803920f8,
-  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
-  0x729bb4e, 0x80335959,
-  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
-  0x6c5598a, 0x802de08e,
-  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
-  0x660f398, 0x8028b69c,
-  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
-  0x5fc89b8, 0x8023db86,
-  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
-  0x5981c26, 0x801f4f4f,
-  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
-  0x533ab20, 0x801b11fa,
-  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
-  0x4cf36e5, 0x80172388,
-  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
-  0x46abfb3, 0x801383fe,
-  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
-  0x40645c7, 0x8010335c,
-  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
-  0x3a1c960, 0x800d31a5,
-  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
-  0x33d4abb, 0x800a7edb,
-  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
-  0x2d8ca16, 0x80081b00,
-  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
-  0x27447b0, 0x80060614,
-  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
-  0x20fc3c6, 0x8004401a,
-  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
-  0x1ab3e97, 0x8002c912,
-  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
-  0x146b860, 0x8001a0fd,
-  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
-  0xe23160, 0x8000c7dc,
-  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
-  0x80003daf,
-  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
-  0x80000278,
-};
-
-static const q31_t WeightsQ31_8192[16384] = {
-  0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
-    0xffed2684,
-  0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
-    0x7ffff872, 0xffd40489,
-  0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
-    0x7fffed57, 0xffbae290,
-  0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
-    0x7fffdd4d, 0xffa1c09a,
-  0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
-    0x7fffc854, 0xff889ea7,
-  0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
-    0x7fffae6c, 0xff6f7cba,
-  0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
-    0x7fff8f94, 0xff565ad1,
-  0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
-    0x7fff6bcd, 0xff3d38ef,
-  0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
-    0x7fff4317, 0xff241715,
-  0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
-    0x7fff1572, 0xff0af543,
-  0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
-    0x7ffee2dd, 0xfef1d37b,
-  0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
-    0x7ffeab59, 0xfed8b1bd,
-  0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
-    0x7ffe6ee5, 0xfebf900a,
-  0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
-    0x7ffe2d83, 0xfea66e64,
-  0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
-    0x7ffde731, 0xfe8d4ccb,
-  0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
-    0x7ffd9bf0, 0xfe742b41,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
-    0x7ffd4bc0, 0xfe5b09c5,
-  0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
-    0x7ffcf6a0, 0xfe41e85a,
-  0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
-    0x7ffc9c92, 0xfe28c700,
-  0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
-    0x7ffc3d94, 0xfe0fa5b8,
-  0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
-    0x7ffbd9a7, 0xfdf68484,
-  0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
-    0x7ffb70cb, 0xfddd6363,
-  0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
-    0x7ffb0300, 0xfdc44258,
-  0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
-    0x7ffa9045, 0xfdab2162,
-  0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
-    0x7ffa189c, 0xfd920084,
-  0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
-    0x7ff99c03, 0xfd78dfbd,
-  0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
-    0x7ff91a7b, 0xfd5fbf10,
-  0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
-    0x7ff89405, 0xfd469e7c,
-  0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
-    0x7ff8089f, 0xfd2d7e04,
-  0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
-    0x7ff7784a, 0xfd145da7,
-  0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
-    0x7ff6e307, 0xfcfb3d67,
-  0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
-    0x7ff648d4, 0xfce21d45,
-  0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
-    0x7ff5a9b2, 0xfcc8fd41,
-  0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
-    0x7ff505a2, 0xfcafdd5e,
-  0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
-    0x7ff45ca3, 0xfc96bd9b,
-  0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
-    0x7ff3aeb4, 0xfc7d9df9,
-  0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
-    0x7ff2fbd7, 0xfc647e7b,
-  0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
-    0x7ff2440b, 0xfc4b5f20,
-  0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
-    0x7ff18751, 0xfc323fe9,
-  0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
-    0x7ff0c5a7, 0xfc1920d8,
-  0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
-    0x7fefff0f, 0xfc0001ee,
-  0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
-    0x7fef3388, 0xfbe6e32b,
-  0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
-    0x7fee6313, 0xfbcdc490,
-  0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
-    0x7fed8daf, 0xfbb4a61f,
-  0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
-    0x7fecb35c, 0xfb9b87d8,
-  0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
-    0x7febd41b, 0xfb8269bd,
-  0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
-    0x7feaefeb, 0xfb694bce,
-  0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
-    0x7fea06cd, 0xfb502e0c,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
-    0x7fe918c0, 0xfb371078,
-  0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
-    0x7fe825c5, 0xfb1df314,
-  0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
-    0x7fe72ddb, 0xfb04d5e0,
-  0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
-    0x7fe63103, 0xfaebb8dd,
-  0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
-    0x7fe52f3d, 0xfad29c0c,
-  0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
-    0x7fe42889, 0xfab97f6e,
-  0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
-    0x7fe31ce6, 0xfaa06305,
-  0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
-    0x7fe20c55, 0xfa8746d0,
-  0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
-    0x7fe0f6d6, 0xfa6e2ad1,
-  0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
-    0x7fdfdc69, 0xfa550f0a,
-  0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
-    0x7fdebd0d, 0xfa3bf37a,
-  0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
-    0x7fdd98c4, 0xfa22d823,
-  0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
-    0x7fdc6f8d, 0xfa09bd06,
-  0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
-    0x7fdb4167, 0xf9f0a224,
-  0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
-    0x7fda0e54, 0xf9d7877e,
-  0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
-    0x7fd8d653, 0xf9be6d15,
-  0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
-    0x7fd79965, 0xf9a552e9,
-  0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
-    0x7fd65788, 0xf98c38fc,
-  0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
-    0x7fd510be, 0xf9731f4e,
-  0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
-    0x7fd3c506, 0xf95a05e2,
-  0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
-    0x7fd27460, 0xf940ecb7,
-  0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
-    0x7fd11ecd, 0xf927d3ce,
-  0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
-    0x7fcfc44d, 0xf90ebb29,
-  0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
-    0x7fce64df, 0xf8f5a2c9,
-  0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
-    0x7fcd0083, 0xf8dc8aae,
-  0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
-    0x7fcb973b, 0xf8c372d9,
-  0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
-    0x7fca2905, 0xf8aa5b4c,
-  0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
-    0x7fc8b5e1, 0xf8914407,
-  0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
-    0x7fc73dd1, 0xf8782d0c,
-  0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
-    0x7fc5c0d3, 0xf85f165b,
-  0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
-    0x7fc43ee9, 0xf845fff5,
-  0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
-    0x7fc2b811, 0xf82ce9dc,
-  0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
-    0x7fc12c4d, 0xf813d410,
-  0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
-    0x7fbf9b9b, 0xf7fabe92,
-  0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
-    0x7fbe05fd, 0xf7e1a963,
-  0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
-    0x7fbc6b72, 0xf7c89484,
-  0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
-    0x7fbacbfa, 0xf7af7ff6,
-  0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
-    0x7fb92796, 0xf7966bbb,
-  0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
-    0x7fb77e45, 0xf77d57d2,
-  0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
-    0x7fb5d007, 0xf764443d,
-  0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
-    0x7fb41cdd, 0xf74b30fe,
-  0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
-    0x7fb264c7, 0xf7321e14,
-  0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
-    0x7fb0a7c4, 0xf7190b81,
-  0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
-    0x7faee5d5, 0xf6fff946,
-  0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
-    0x7fad1efa, 0xf6e6e764,
-  0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
-    0x7fab5333, 0xf6cdd5dc,
-  0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
-    0x7fa98280, 0xf6b4c4ae,
-  0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
-    0x7fa7ace1, 0xf69bb3dd,
-  0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
-    0x7fa5d256, 0xf682a367,
-  0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
-    0x7fa3f2df, 0xf6699350,
-  0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
-    0x7fa20e7c, 0xf6508397,
-  0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
-    0x7fa0252e, 0xf637743e,
-  0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
-    0x7f9e36f4, 0xf61e6545,
-  0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
-    0x7f9c43ce, 0xf60556ae,
-  0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
-    0x7f9a4bbd, 0xf5ec4879,
-  0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
-    0x7f984ec1, 0xf5d33aa8,
-  0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
-    0x7f964cd9, 0xf5ba2d3b,
-  0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
-    0x7f944606, 0xf5a12034,
-  0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
-    0x7f923a48, 0xf5881393,
-  0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
-    0x7f90299f, 0xf56f0759,
-  0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
-    0x7f8e140a, 0xf555fb88,
-  0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
-    0x7f8bf98b, 0xf53cf01f,
-  0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
-    0x7f89da21, 0xf523e521,
-  0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
-    0x7f87b5cd, 0xf50ada8f,
-  0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
-    0x7f858c8d, 0xf4f1d068,
-  0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
-    0x7f835e64, 0xf4d8c6ae,
-  0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
-    0x7f812b4f, 0xf4bfbd63,
-  0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
-    0x7f7ef350, 0xf4a6b486,
-  0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
-    0x7f7cb667, 0xf48dac1a,
-  0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
-    0x7f7a7494, 0xf474a41f,
-  0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
-    0x7f782dd6, 0xf45b9c95,
-  0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
-    0x7f75e22e, 0xf442957e,
-  0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
-    0x7f73919d, 0xf4298edc,
-  0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
-    0x7f713c21, 0xf41088ae,
-  0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
-    0x7f6ee1bc, 0xf3f782f6,
-  0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
-    0x7f6c826d, 0xf3de7db4,
-  0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
-    0x7f6a1e34, 0xf3c578eb,
-  0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
-    0x7f67b512, 0xf3ac749a,
-  0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
-    0x7f654706, 0xf39370c2,
-  0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
-    0x7f62d411, 0xf37a6d66,
-  0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
-    0x7f605c33, 0xf3616a85,
-  0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
-    0x7f5ddf6b, 0xf3486820,
-  0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
-    0x7f5b5dbb, 0xf32f6639,
-  0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
-    0x7f58d721, 0xf31664d1,
-  0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
-    0x7f564b9f, 0xf2fd63e8,
-  0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
-    0x7f53bb34, 0xf2e4637f,
-  0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
-    0x7f5125e0, 0xf2cb6398,
-  0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
-    0x7f4e8ba4, 0xf2b26433,
-  0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
-    0x7f4bec7f, 0xf2996551,
-  0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
-    0x7f494872, 0xf28066f4,
-  0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
-    0x7f469f7d, 0xf267691b,
-  0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
-    0x7f43f19f, 0xf24e6bc9,
-  0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
-    0x7f413ed9, 0xf2356efe,
-  0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
-    0x7f3e872c, 0xf21c72bc,
-  0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
-    0x7f3bca96, 0xf2037702,
-  0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
-    0x7f390919, 0xf1ea7bd2,
-  0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
-    0x7f3642b4, 0xf1d1812e,
-  0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
-    0x7f337768, 0xf1b88715,
-  0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
-    0x7f30a734, 0xf19f8d89,
-  0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
-    0x7f2dd219, 0xf186948c,
-  0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
-    0x7f2af817, 0xf16d9c1d,
-  0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
-    0x7f28192d, 0xf154a43d,
-  0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
-    0x7f25355d, 0xf13bacef,
-  0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
-    0x7f224ca6, 0xf122b632,
-  0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
-    0x7f1f5f08, 0xf109c009,
-  0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
-    0x7f1c6c83, 0xf0f0ca72,
-  0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
-    0x7f197518, 0xf0d7d571,
-  0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
-    0x7f1678c6, 0xf0bee105,
-  0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
-    0x7f13778e, 0xf0a5ed2f,
-  0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
-    0x7f107170, 0xf08cf9f1,
-  0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
-    0x7f0d666c, 0xf074074c,
-  0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
-    0x7f0a5682, 0xf05b1540,
-  0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
-    0x7f0741b2, 0xf04223ce,
-  0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
-    0x7f0427fc, 0xf02932f8,
-  0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
-    0x7f010961, 0xf01042be,
-  0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
-    0x7efde5e0, 0xeff75321,
-  0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
-    0x7efabd7a, 0xefde6423,
-  0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
-    0x7ef7902f, 0xefc575c3,
-  0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
-    0x7ef45dfe, 0xefac8804,
-  0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
-    0x7ef126e9, 0xef939ae6,
-  0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
-    0x7eedeaee, 0xef7aae6b,
-  0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
-    0x7eeaaa0f, 0xef61c292,
-  0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
-    0x7ee7644c, 0xef48d75d,
-  0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
-    0x7ee419a3, 0xef2feccd,
-  0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
-    0x7ee0ca17, 0xef1702e4,
-  0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
-    0x7edd75a6, 0xeefe19a1,
-  0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
-    0x7eda1c51, 0xeee53105,
-  0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
-    0x7ed6be18, 0xeecc4913,
-  0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
-    0x7ed35afb, 0xeeb361cb,
-  0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
-    0x7ecff2fb, 0xee9a7b2d,
-  0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
-    0x7ecc8617, 0xee81953b,
-  0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
-    0x7ec9144f, 0xee68aff6,
-  0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
-    0x7ec59da5, 0xee4fcb5e,
-  0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
-    0x7ec22217, 0xee36e775,
-  0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
-    0x7ebea1a6, 0xee1e043b,
-  0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
-    0x7ebb1c52, 0xee0521b2,
-  0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
-    0x7eb7921b, 0xedec3fda,
-  0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
-    0x7eb40301, 0xedd35eb5,
-  0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
-    0x7eb06f05, 0xedba7e43,
-  0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
-    0x7eacd627, 0xeda19e85,
-  0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
-    0x7ea93867, 0xed88bf7d,
-  0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
-    0x7ea595c4, 0xed6fe12b,
-  0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
-    0x7ea1ee3f, 0xed570390,
-  0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
-    0x7e9e41d9, 0xed3e26ad,
-  0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
-    0x7e9a9091, 0xed254a84,
-  0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
-    0x7e96da67, 0xed0c6f14,
-  0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
-    0x7e931f5c, 0xecf39460,
-  0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
-    0x7e8f5f70, 0xecdaba67,
-  0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
-    0x7e8b9aa3, 0xecc1e12c,
-  0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
-    0x7e87d0f5, 0xeca908ae,
-  0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
-    0x7e840265, 0xec9030f0,
-  0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
-    0x7e802ef6, 0xec7759f1,
-  0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
-    0x7e7c56a5, 0xec5e83b3,
-  0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
-    0x7e787975, 0xec45ae36,
-  0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
-    0x7e749764, 0xec2cd97d,
-  0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
-    0x7e70b073, 0xec140587,
-  0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
-    0x7e6cc4a2, 0xebfb3256,
-  0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
-    0x7e68d3f2, 0xebe25fea,
-  0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
-    0x7e64de62, 0xebc98e45,
-  0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
-    0x7e60e3f2, 0xebb0bd67,
-  0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
-    0x7e5ce4a3, 0xeb97ed52,
-  0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
-    0x7e58e075, 0xeb7f1e06,
-  0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
-    0x7e54d768, 0xeb664f84,
-  0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
-    0x7e50c97c, 0xeb4d81ce,
-  0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
-    0x7e4cb6b1, 0xeb34b4e4,
-  0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
-    0x7e489f08, 0xeb1be8c8,
-  0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
-    0x7e448281, 0xeb031d79,
-  0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
-    0x7e40611b, 0xeaea52fa,
-  0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
-    0x7e3c3ad7, 0xead1894b,
-  0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
-    0x7e380fb5, 0xeab8c06c,
-  0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
-    0x7e33dfb6, 0xea9ff860,
-  0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
-    0x7e2faad9, 0xea873127,
-  0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
-    0x7e2b711f, 0xea6e6ac2,
-  0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
-    0x7e273287, 0xea55a531,
-  0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
-    0x7e22ef12, 0xea3ce077,
-  0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
-    0x7e1ea6c1, 0xea241c93,
-  0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
-    0x7e1a5992, 0xea0b5987,
-  0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
-    0x7e160787, 0xe9f29753,
-  0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
-    0x7e11b0a0, 0xe9d9d5fa,
-  0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
-    0x7e0d54dc, 0xe9c1157a,
-  0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
-    0x7e08f43d, 0xe9a855d7,
-  0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
-    0x7e048ec1, 0xe98f9710,
-  0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
-    0x7e00246a, 0xe976d926,
-  0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
-    0x7dfbb537, 0xe95e1c1b,
-  0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
-    0x7df74128, 0xe9455fef,
-  0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
-    0x7df2c83f, 0xe92ca4a4,
-  0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
-    0x7dee4a7a, 0xe913ea39,
-  0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
-    0x7de9c7da, 0xe8fb30b1,
-  0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
-    0x7de54060, 0xe8e2780d,
-  0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
-    0x7de0b40b, 0xe8c9c04c,
-  0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
-    0x7ddc22dc, 0xe8b10971,
-  0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
-    0x7dd78cd3, 0xe898537b,
-  0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
-    0x7dd2f1f0, 0xe87f9e6c,
-  0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
-    0x7dce5232, 0xe866ea46,
-  0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
-    0x7dc9ad9c, 0xe84e3708,
-  0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
-    0x7dc5042b, 0xe83584b4,
-  0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
-    0x7dc055e2, 0xe81cd34b,
-  0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
-    0x7dbba2bf, 0xe80422ce,
-  0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
-    0x7db6eac3, 0xe7eb733e,
-  0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
-    0x7db22def, 0xe7d2c49b,
-  0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
-    0x7dad6c42, 0xe7ba16e7,
-  0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
-    0x7da8a5bc, 0xe7a16a22,
-  0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
-    0x7da3da5f, 0xe788be4e,
-  0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
-    0x7d9f0a29, 0xe770136b,
-  0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
-    0x7d9a351c, 0xe757697b,
-  0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
-    0x7d955b37, 0xe73ec07e,
-  0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
-    0x7d907c7a, 0xe7261875,
-  0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
-    0x7d8b98e6, 0xe70d7162,
-  0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
-    0x7d86b07c, 0xe6f4cb45,
-  0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
-    0x7d81c33a, 0xe6dc261f,
-  0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
-    0x7d7cd121, 0xe6c381f1,
-  0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
-    0x7d77da32, 0xe6aadebc,
-  0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
-    0x7d72de6d, 0xe6923c82,
-  0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
-    0x7d6dddd2, 0xe6799b42,
-  0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
-    0x7d68d860, 0xe660fafe,
-  0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
-    0x7d63ce19, 0xe6485bb7,
-  0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
-    0x7d5ebefc, 0xe62fbd6e,
-  0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
-    0x7d59ab0a, 0xe6172024,
-  0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
-    0x7d549243, 0xe5fe83d9,
-  0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
-    0x7d4f74a7, 0xe5e5e88f,
-  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
-    0x7d4a5236, 0xe5cd4e47,
-  0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
-    0x7d452af1, 0xe5b4b501,
-  0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
-    0x7d3ffed7, 0xe59c1cbf,
-  0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
-    0x7d3acde9, 0xe5838581,
-  0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
-    0x7d359827, 0xe56aef49,
-  0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
-    0x7d305d91, 0xe5525a17,
-  0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
-    0x7d2b1e28, 0xe539c5ec,
-  0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
-    0x7d25d9eb, 0xe52132c9,
-  0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
-    0x7d2090db, 0xe508a0b0,
-  0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
-    0x7d1b42f9, 0xe4f00fa1,
-  0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
-    0x7d15f043, 0xe4d77f9d,
-  0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
-    0x7d1098bb, 0xe4bef0a5,
-  0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
-    0x7d0b3c60, 0xe4a662ba,
-  0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
-    0x7d05db34, 0xe48dd5dd,
-  0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
-    0x7d007535, 0xe4754a0e,
-  0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
-    0x7cfb0a65, 0xe45cbf50,
-  0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
-    0x7cf59ac4, 0xe44435a2,
-  0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
-    0x7cf02651, 0xe42bad07,
-  0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
-    0x7ceaad0c, 0xe413257d,
-  0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
-    0x7ce52ef7, 0xe3fa9f08,
-  0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
-    0x7cdfac12, 0xe3e219a7,
-  0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
-    0x7cda245c, 0xe3c9955b,
-  0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
-    0x7cd497d5, 0xe3b11226,
-  0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
-    0x7ccf067f, 0xe3989008,
-  0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
-    0x7cc97059, 0xe3800f03,
-  0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
-    0x7cc3d563, 0xe3678f17,
-  0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
-    0x7cbe359e, 0xe34f1045,
-  0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
-    0x7cb8910a, 0xe336928e,
-  0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
-    0x7cb2e7a6, 0xe31e15f4,
-  0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
-    0x7cad3974, 0xe3059a76,
-  0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
-    0x7ca78674, 0xe2ed2017,
-  0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
-    0x7ca1cea5, 0xe2d4a6d6,
-  0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
-    0x7c9c1208, 0xe2bc2eb5,
-  0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
-    0x7c96509d, 0xe2a3b7b5,
-  0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
-    0x7c908a65, 0xe28b41d7,
-  0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
-    0x7c8abf5f, 0xe272cd1c,
-  0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
-    0x7c84ef8c, 0xe25a5984,
-  0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
-    0x7c7f1aed, 0xe241e711,
-  0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
-    0x7c794180, 0xe22975c4,
-  0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
-    0x7c736347, 0xe211059d,
-  0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
-    0x7c6d8041, 0xe1f8969d,
-  0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
-    0x7c679870, 0xe1e028c6,
-  0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
-    0x7c61abd3, 0xe1c7bc18,
-  0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
-    0x7c5bba6a, 0xe1af5094,
-  0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
-    0x7c55c436, 0xe196e63c,
-  0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
-    0x7c4fc936, 0xe17e7d0f,
-  0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
-    0x7c49c96c, 0xe1661510,
-  0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
-    0x7c43c4d7, 0xe14dae3f,
-  0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
-    0x7c3dbb78, 0xe135489d,
-  0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
-    0x7c37ad4e, 0xe11ce42a,
-  0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
-    0x7c319a5a, 0xe10480e9,
-  0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
-    0x7c2b829d, 0xe0ec1ed9,
-  0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
-    0x7c256616, 0xe0d3bdfc,
-  0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
-    0x7c1f44c6, 0xe0bb5e53,
-  0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
-    0x7c191ead, 0xe0a2ffde,
-  0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
-    0x7c12f3cb, 0xe08aa29f,
-  0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
-    0x7c0cc421, 0xe0724696,
-  0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
-    0x7c068fae, 0xe059ebc5,
-  0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
-    0x7c005673, 0xe041922c,
-  0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
-    0x7bfa1870, 0xe02939cc,
-  0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
-    0x7bf3d5a6, 0xe010e2a7,
-  0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
-    0x7bed8e14, 0xdff88cbc,
-  0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
-    0x7be741bb, 0xdfe0380e,
-  0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
-    0x7be0f09b, 0xdfc7e49d,
-  0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
-    0x7bda9ab5, 0xdfaf926a,
-  0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
-    0x7bd44008, 0xdf974176,
-  0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
-    0x7bcde095, 0xdf7ef1c2,
-  0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
-    0x7bc77c5d, 0xdf66a34e,
-  0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
-    0x7bc1135e, 0xdf4e561c,
-  0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
-    0x7bbaa59a, 0xdf360a2d,
-  0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
-    0x7bb43311, 0xdf1dbf82,
-  0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
-    0x7badbbc3, 0xdf05761b,
-  0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
-    0x7ba73fb1, 0xdeed2dfa,
-  0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
-    0x7ba0beda, 0xded4e71f,
-  0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
-    0x7b9a393f, 0xdebca18b,
-  0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
-    0x7b93aee0, 0xdea45d40,
-  0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
-    0x7b8d1fbd, 0xde8c1a3e,
-  0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
-    0x7b868bd7, 0xde73d886,
-  0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
-    0x7b7ff32e, 0xde5b9819,
-  0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
-    0x7b7955c2, 0xde4358f8,
-  0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
-    0x7b72b393, 0xde2b1b24,
-  0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
-    0x7b6c0ca2, 0xde12de9e,
-  0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
-    0x7b6560ee, 0xddfaa367,
-  0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
-    0x7b5eb079, 0xdde26980,
-  0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
-    0x7b57fb42, 0xddca30e9,
-  0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
-    0x7b51414a, 0xddb1f9a4,
-  0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
-    0x7b4a8291, 0xdd99c3b2,
-  0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
-    0x7b43bf17, 0xdd818f13,
-  0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
-    0x7b3cf6dc, 0xdd695bc9,
-  0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
-    0x7b3629e1, 0xdd5129d4,
-  0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
-    0x7b2f5826, 0xdd38f935,
-  0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
-    0x7b2881ac, 0xdd20c9ed,
-  0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
-    0x7b21a671, 0xdd089bfe,
-  0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
-    0x7b1ac678, 0xdcf06f68,
-  0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
-    0x7b13e1bf, 0xdcd8442b,
-  0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
-    0x7b0cf848, 0xdcc01a4a,
-  0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
-    0x7b060a12, 0xdca7f1c5,
-  0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
-    0x7aff171e, 0xdc8fca9c,
-  0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
-    0x7af81f6c, 0xdc77a4d2,
-  0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
-    0x7af122fd, 0xdc5f8066,
-  0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
-    0x7aea21d0, 0xdc475d59,
-  0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
-    0x7ae31be6, 0xdc2f3bad,
-  0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
-    0x7adc113f, 0xdc171b63,
-  0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
-    0x7ad501dc, 0xdbfefc7b,
-  0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
-    0x7acdedbc, 0xdbe6def6,
-  0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
-    0x7ac6d4e0, 0xdbcec2d6,
-  0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
-    0x7abfb749, 0xdbb6a81b,
-  0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
-    0x7ab894f6, 0xdb9e8ec6,
-  0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
-    0x7ab16de7, 0xdb8676d8,
-  0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
-    0x7aaa421e, 0xdb6e6052,
-  0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
-    0x7aa3119a, 0xdb564b35,
-  0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
-    0x7a9bdc5c, 0xdb3e3781,
-  0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
-    0x7a94a264, 0xdb262539,
-  0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
-    0x7a8d63b2, 0xdb0e145c,
-  0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
-    0x7a862046, 0xdaf604ec,
-  0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
-    0x7a7ed821, 0xdaddf6ea,
-  0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
-    0x7a778b43, 0xdac5ea56,
-  0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
-    0x7a7039ad, 0xdaaddf31,
-  0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
-    0x7a68e35e, 0xda95d57d,
-  0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
-    0x7a618857, 0xda7dcd3a,
-  0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
-    0x7a5a2898, 0xda65c669,
-  0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
-    0x7a52c421, 0xda4dc10b,
-  0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
-    0x7a4b5af3, 0xda35bd22,
-  0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
-    0x7a43ed0e, 0xda1dbaad,
-  0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
-    0x7a3c7a73, 0xda05b9ae,
-  0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
-    0x7a350321, 0xd9edba26,
-  0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
-    0x7a2d8719, 0xd9d5bc16,
-  0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
-    0x7a26065b, 0xd9bdbf7e,
-  0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
-    0x7a1e80e7, 0xd9a5c461,
-  0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
-    0x7a16f6be, 0xd98dcabd,
-  0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
-    0x7a0f67e0, 0xd975d295,
-  0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
-    0x7a07d44e, 0xd95ddbea,
-  0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
-    0x7a003c07, 0xd945e6bb,
-  0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
-    0x79f89f0c, 0xd92df30b,
-  0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
-    0x79f0fd5d, 0xd91600da,
-  0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
-    0x79e956fb, 0xd8fe1029,
-  0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
-    0x79e1abe6, 0xd8e620fa,
-  0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
-    0x79d9fc1d, 0xd8ce334c,
-  0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
-    0x79d247a2, 0xd8b64720,
-  0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
-    0x79ca8e75, 0xd89e5c79,
-  0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
-    0x79c2d095, 0xd8867356,
-  0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
-    0x79bb0e04, 0xd86e8bb9,
-  0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
-    0x79b346c2, 0xd856a5a3,
-  0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
-    0x79ab7ace, 0xd83ec114,
-  0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
-    0x79a3aa29, 0xd826de0d,
-  0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
-    0x799bd4d4, 0xd80efc8f,
-  0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
-    0x7993facf, 0xd7f71c9c,
-  0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
-    0x798c1c1a, 0xd7df3e34,
-  0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
-    0x798438b5, 0xd7c76158,
-  0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
-    0x797c50a1, 0xd7af8609,
-  0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
-    0x797463de, 0xd797ac48,
-  0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
-    0x796c726c, 0xd77fd415,
-  0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
-    0x79647c4c, 0xd767fd72,
-  0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
-    0x795c817d, 0xd7502860,
-  0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
-    0x79548201, 0xd73854e0,
-  0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
-    0x794c7dd7, 0xd72082f2,
-  0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
-    0x79447500, 0xd708b297,
-  0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
-    0x793c677d, 0xd6f0e3d1,
-  0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
-    0x7934554d, 0xd6d916a0,
-  0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
-    0x792c3e70, 0xd6c14b05,
-  0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
-    0x792422e8, 0xd6a98101,
-  0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
-    0x791c02b4, 0xd691b895,
-  0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
-    0x7913ddd4, 0xd679f1c2,
-  0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
-    0x790bb44a, 0xd6622c89,
-  0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
-    0x79038615, 0xd64a68eb,
-  0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
-    0x78fb5336, 0xd632a6e8,
-  0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
-    0x78f31bac, 0xd61ae682,
-  0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
-    0x78eadf79, 0xd60327b9,
-  0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
-    0x78e29e9d, 0xd5eb6a8f,
-  0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
-    0x78da5917, 0xd5d3af04,
-  0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
-    0x78d20ee9, 0xd5bbf519,
-  0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
-    0x78c9c012, 0xd5a43cd0,
-  0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
-    0x78c16c93, 0xd58c8628,
-  0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
-    0x78b9146c, 0xd574d124,
-  0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
-    0x78b0b79e, 0xd55d1dc3,
-  0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
-    0x78a85628, 0xd5456c07,
-  0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
-    0x789ff00c, 0xd52dbbf1,
-  0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
-    0x78978549, 0xd5160d82,
-  0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
-    0x788f15e0, 0xd4fe60ba,
-  0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
-    0x7886a1d1, 0xd4e6b59a,
-  0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
-    0x787e291d, 0xd4cf0c24,
-  0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
-    0x7875abc3, 0xd4b76458,
-  0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
-    0x786d29c5, 0xd49fbe37,
-  0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
-    0x7864a322, 0xd48819c3,
-  0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
-    0x785c17db, 0xd47076fb,
-  0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
-    0x785387ef, 0xd458d5e2,
-  0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
-    0x784af361, 0xd4413677,
-  0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
-    0x78425a2f, 0xd42998bc,
-  0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
-    0x7839bc5a, 0xd411fcb2,
-  0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
-    0x783119e2, 0xd3fa6259,
-  0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
-    0x782872c8, 0xd3e2c9b2,
-  0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
-    0x781fc70d, 0xd3cb32c0,
-  0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
-    0x781716b0, 0xd3b39d81,
-  0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
-    0x780e61b1, 0xd39c09f7,
-  0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
-    0x7805a812, 0xd3847824,
-  0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
-    0x77fce9d2, 0xd36ce808,
-  0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
-    0x77f426f2, 0xd35559a4,
-  0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
-    0x77eb5f71, 0xd33dccf8,
-  0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
-    0x77e29352, 0xd3264206,
-  0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
-    0x77d9c293, 0xd30eb8cf,
-  0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
-    0x77d0ed35, 0xd2f73154,
-  0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
-    0x77c81339, 0xd2dfab95,
-  0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
-    0x77bf349f, 0xd2c82793,
-  0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
-    0x77b65166, 0xd2b0a54f,
-  0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
-    0x77ad6990, 0xd29924cb,
-  0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
-    0x77a47d1d, 0xd281a607,
-  0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
-    0x779b8c0e, 0xd26a2904,
-  0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
-    0x77929661, 0xd252adc3,
-  0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
-    0x77899c19, 0xd23b3444,
-  0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
-    0x77809d35, 0xd223bc8a,
-  0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
-    0x777799b5, 0xd20c4694,
-  0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
-    0x776e919a, 0xd1f4d263,
-  0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
-    0x776584e5, 0xd1dd5ff9,
-  0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
-    0x775c7395, 0xd1c5ef56,
-  0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
-    0x77535dab, 0xd1ae807c,
-  0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
-    0x774a4327, 0xd197136b,
-  0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
-    0x7741240a, 0xd17fa823,
-  0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
-    0x77380054, 0xd1683ea7,
-  0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
-    0x772ed805, 0xd150d6f6,
-  0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
-    0x7725ab1f, 0xd1397113,
-  0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
-    0x771c79a0, 0xd1220cfc,
-  0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
-    0x77134389, 0xd10aaab5,
-  0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
-    0x770a08dc, 0xd0f34a3d,
-  0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
-    0x7700c997, 0xd0dbeb95,
-  0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
-    0x76f785bc, 0xd0c48ebf,
-  0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
-    0x76ee3d4b, 0xd0ad33ba,
-  0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
-    0x76e4f044, 0xd095da89,
-  0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
-    0x76db9ea7, 0xd07e832c,
-  0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
-    0x76d24876, 0xd0672da3,
-  0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
-    0x76c8edb0, 0xd04fd9f1,
-  0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
-    0x76bf8e55, 0xd0388815,
-  0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
-    0x76b62a66, 0xd0213810,
-  0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
-    0x76acc1e4, 0xd009e9e4,
-  0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
-    0x76a354cf, 0xcff29d92,
-  0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
-    0x7699e326, 0xcfdb531a,
-  0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
-    0x76906ceb, 0xcfc40a7c,
-  0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
-    0x7686f21e, 0xcfacc3bb,
-  0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
-    0x767d72bf, 0xcf957ed7,
-  0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
-    0x7673eecf, 0xcf7e3bd1,
-  0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
-    0x766a664d, 0xcf66faa9,
-  0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
-    0x7660d93b, 0xcf4fbb61,
-  0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
-    0x76574798, 0xcf387dfa,
-  0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
-    0x764db166, 0xcf214274,
-  0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
-    0x764416a4, 0xcf0a08d0,
-  0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
-    0x763a7752, 0xcef2d110,
-  0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
-    0x7630d372, 0xcedb9b33,
-  0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
-    0x76272b03, 0xcec4673c,
-  0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
-    0x761d7e06, 0xcead352b,
-  0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
-    0x7613cc7c, 0xce960500,
-  0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
-    0x760a1664, 0xce7ed6bd,
-  0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
-    0x76005bbf, 0xce67aa63,
-  0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
-    0x75f69c8d, 0xce507ff2,
-  0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
-    0x75ecd8cf, 0xce39576c,
-  0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
-    0x75e31086, 0xce2230d0,
-  0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
-    0x75d943b0, 0xce0b0c21,
-  0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
-    0x75cf7250, 0xcdf3e95f,
-  0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
-    0x75c59c65, 0xcddcc88b,
-  0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
-    0x75bbc1ef, 0xcdc5a9a6,
-  0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
-    0x75b1e2f0, 0xcdae8cb1,
-  0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
-    0x75a7ff67, 0xcd9771ac,
-  0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
-    0x759e1755, 0xcd805899,
-  0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
-    0x75942ab9, 0xcd694178,
-  0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
-    0x758a3996, 0xcd522c4a,
-  0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
-    0x758043ea, 0xcd3b1911,
-  0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
-    0x757649b7, 0xcd2407cc,
-  0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
-    0x756c4afc, 0xcd0cf87e,
-  0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
-    0x756247bb, 0xccf5eb26,
-  0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
-    0x75583ff3, 0xccdedfc7,
-  0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
-    0x754e33a4, 0xccc7d65f,
-  0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
-    0x754422d0, 0xccb0cef2,
-  0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
-    0x753a0d77, 0xcc99c97e,
-  0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
-    0x752ff399, 0xcc82c607,
-  0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
-    0x7525d536, 0xcc6bc48b,
-  0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
-    0x751bb24f, 0xcc54c50c,
-  0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
-    0x75118ae4, 0xcc3dc78b,
-  0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
-    0x75075ef5, 0xcc26cc09,
-  0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
-    0x74fd2e84, 0xcc0fd287,
-  0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
-    0x74f2f990, 0xcbf8db05,
-  0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
-    0x74e8c01a, 0xcbe1e585,
-  0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
-    0x74de8221, 0xcbcaf208,
-  0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
-    0x74d43fa8, 0xcbb4008d,
-  0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
-    0x74c9f8ad, 0xcb9d1117,
-  0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
-    0x74bfad32, 0xcb8623a5,
-  0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
-    0x74b55d36, 0xcb6f383a,
-  0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
-    0x74ab08bb, 0xcb584ed6,
-  0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
-    0x74a0afc0, 0xcb416779,
-  0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
-    0x74965246, 0xcb2a8224,
-  0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
-    0x748bf04d, 0xcb139ed9,
-  0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
-    0x748189d7, 0xcafcbd99,
-  0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
-    0x74771ee2, 0xcae5de64,
-  0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
-    0x746caf70, 0xcacf013a,
-  0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
-    0x74623b80, 0xcab8261e,
-  0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
-    0x7457c314, 0xcaa14d10,
-  0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
-    0x744d462c, 0xca8a7610,
-  0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
-    0x7442c4c8, 0xca73a120,
-  0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
-    0x74383ee9, 0xca5cce40,
-  0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
-    0x742db48e, 0xca45fd72,
-  0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
-    0x742325b9, 0xca2f2eb6,
-  0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
-    0x74189269, 0xca18620e,
-  0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
-    0x740dfaa0, 0xca019779,
-  0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
-    0x74035e5d, 0xc9eacef9,
-  0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
-    0x73f8bda2, 0xc9d4088f,
-  0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
-    0x73ee186e, 0xc9bd443c,
-  0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
-    0x73e36ec1, 0xc9a68200,
-  0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
-    0x73d8c09d, 0xc98fc1dc,
-  0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
-    0x73ce0e01, 0xc97903d2,
-  0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
-    0x73c356ef, 0xc96247e2,
-  0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
-    0x73b89b66, 0xc94b8e0d,
-  0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
-    0x73addb67, 0xc934d654,
-  0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
-    0x73a316f2, 0xc91e20b8,
-  0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
-    0x73984e07, 0xc9076d39,
-  0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
-    0x738d80a8, 0xc8f0bbd9,
-  0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
-    0x7382aed5, 0xc8da0c99,
-  0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
-    0x7377d88d, 0xc8c35f78,
-  0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
-    0x736cfdd2, 0xc8acb479,
-  0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
-    0x73621ea4, 0xc8960b9c,
-  0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
-    0x73573b03, 0xc87f64e2,
-  0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
-    0x734c52ef, 0xc868c04b,
-  0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
-    0x7341666a, 0xc8521dd9,
-  0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
-    0x73367572, 0xc83b7d8d,
-  0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
-    0x732b800a, 0xc824df67,
-  0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
-    0x73208632, 0xc80e4369,
-  0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
-    0x731587e8, 0xc7f7a992,
-  0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
-    0x730a8530, 0xc7e111e5,
-  0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
-    0x72ff7e07, 0xc7ca7c61,
-  0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
-    0x72f47270, 0xc7b3e909,
-  0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
-    0x72e9626a, 0xc79d57db,
-  0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
-    0x72de4df6, 0xc786c8db,
-  0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
-    0x72d33514, 0xc7703c08,
-  0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
-    0x72c817c6, 0xc759b163,
-  0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
-    0x72bcf60a, 0xc74328ed,
-  0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
-    0x72b1cfe1, 0xc72ca2a7,
-  0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
-    0x72a6a54d, 0xc7161e92,
-  0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
-    0x729b764d, 0xc6ff9cae,
-  0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
-    0x729042e3, 0xc6e91cfd,
-  0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
-    0x72850b0d, 0xc6d29f80,
-  0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
-    0x7279cecd, 0xc6bc2437,
-  0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
-    0x726e8e23, 0xc6a5ab23,
-  0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
-    0x72634910, 0xc68f3446,
-  0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
-    0x7257ff94, 0xc678bf9f,
-  0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
-    0x724cb1b0, 0xc6624d30,
-  0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
-    0x72415f63, 0xc64bdcf9,
-  0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
-    0x723608af, 0xc6356efc,
-  0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
-    0x722aad93, 0xc61f033a,
-  0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
-    0x721f4e11, 0xc60899b2,
-  0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
-    0x7213ea28, 0xc5f23267,
-  0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
-    0x720881d9, 0xc5dbcd59,
-  0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
-    0x71fd1525, 0xc5c56a89,
-  0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
-    0x71f1a40c, 0xc5af09f7,
-  0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
-    0x71e62e8f, 0xc598aba5,
-  0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
-    0x71dab4ad, 0xc5824f93,
-  0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
-    0x71cf3667, 0xc56bf5c2,
-  0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
-    0x71c3b3bf, 0xc5559e34,
-  0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
-    0x71b82cb3, 0xc53f48e9,
-  0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
-    0x71aca145, 0xc528f5e1,
-  0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
-    0x71a11175, 0xc512a51f,
-  0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
-    0x71957d44, 0xc4fc56a2,
-  0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
-    0x7189e4b2, 0xc4e60a6b,
-  0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
-    0x717e47bf, 0xc4cfc07c,
-  0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
-    0x7172a66c, 0xc4b978d4,
-  0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
-    0x716700b9, 0xc4a33376,
-  0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
-    0x715b56a7, 0xc48cf062,
-  0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
-    0x714fa836, 0xc476af98,
-  0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
-    0x7143f567, 0xc460711b,
-  0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
-    0x71383e3a, 0xc44a34e9,
-  0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
-    0x712c82b0, 0xc433fb05,
-  0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
-    0x7120c2c8, 0xc41dc36f,
-  0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
-    0x7114fe84, 0xc4078e28,
-  0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
-    0x710935e4, 0xc3f15b31,
-  0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
-    0x70fd68e9, 0xc3db2a8b,
-  0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
-    0x70f19792, 0xc3c4fc36,
-  0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
-    0x70e5c1e1, 0xc3aed034,
-  0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
-    0x70d9e7d5, 0xc398a685,
-  0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
-    0x70ce096f, 0xc3827f2a,
-  0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
-    0x70c226b0, 0xc36c5a24,
-  0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
-    0x70b63f99, 0xc3563774,
-  0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
-    0x70aa5428, 0xc340171b,
-  0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
-    0x709e6460, 0xc329f919,
-  0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
-    0x70927041, 0xc313dd70,
-  0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
-    0x708677ca, 0xc2fdc420,
-  0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
-    0x707a7afd, 0xc2e7ad2a,
-  0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
-    0x706e79d9, 0xc2d1988f,
-  0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
-    0x70627460, 0xc2bb8650,
-  0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
-    0x70566a92, 0xc2a5766e,
-  0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
-    0x704a5c6f, 0xc28f68e9,
-  0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
-    0x703e49f8, 0xc2795dc3,
-  0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
-    0x7032332d, 0xc26354fc,
-  0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
-    0x7026180e, 0xc24d4e95,
-  0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
-    0x7019f89d, 0xc2374a8f,
-  0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
-    0x700dd4da, 0xc22148ea,
-  0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
-    0x7001acc4, 0xc20b49a9,
-  0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
-    0x6ff5805d, 0xc1f54cca,
-  0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
-    0x6fe94fa5, 0xc1df5251,
-  0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
-    0x6fdd1a9c, 0xc1c95a3c,
-  0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
-    0x6fd0e144, 0xc1b3648d,
-  0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
-    0x6fc4a39c, 0xc19d7145,
-  0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
-    0x6fb861a4, 0xc1878065,
-  0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
-    0x6fac1b5f, 0xc17191ee,
-  0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
-    0x6f9fd0cb, 0xc15ba5df,
-  0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
-    0x6f9381e9, 0xc145bc3c,
-  0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
-    0x6f872eba, 0xc12fd503,
-  0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
-    0x6f7ad73e, 0xc119f036,
-  0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
-    0x6f6e7b76, 0xc1040dd6,
-  0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
-    0x6f621b62, 0xc0ee2de3,
-  0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
-    0x6f55b703, 0xc0d8505f,
-  0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
-    0x6f494e5a, 0xc0c2754b,
-  0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
-    0x6f3ce165, 0xc0ac9ca6,
-  0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
-    0x6f307027, 0xc096c673,
-  0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
-    0x6f23faa0, 0xc080f2b1,
-  0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
-    0x6f1780cf, 0xc06b2162,
-  0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
-    0x6f0b02b6, 0xc0555287,
-  0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
-    0x6efe8056, 0xc03f8620,
-  0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
-    0x6ef1f9ad, 0xc029bc2e,
-  0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
-    0x6ee56ebe, 0xc013f4b2,
-  0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
-    0x6ed8df88, 0xbffe2fad,
-  0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
-    0x6ecc4c0d, 0xbfe86d20,
-  0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
-    0x6ebfb44b, 0xbfd2ad0b,
-  0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
-    0x6eb31845, 0xbfbcef70,
-  0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
-    0x6ea677fa, 0xbfa7344f,
-  0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
-    0x6e99d36b, 0xbf917ba9,
-  0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
-    0x6e8d2a99, 0xbf7bc57f,
-  0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
-    0x6e807d83, 0xbf6611d2,
-  0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
-    0x6e73cc2b, 0xbf5060a2,
-  0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
-    0x6e671690, 0xbf3ab1f1,
-  0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
-    0x6e5a5cb4, 0xbf2505bf,
-  0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
-    0x6e4d9e97, 0xbf0f5c0d,
-  0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
-    0x6e40dc39, 0xbef9b4dc,
-  0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
-    0x6e34159b, 0xbee4102d,
-  0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
-    0x6e274abe, 0xbece6e00,
-  0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
-    0x6e1a7ba1, 0xbeb8ce57,
-  0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
-    0x6e0da845, 0xbea33132,
-  0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
-    0x6e00d0ac, 0xbe8d9692,
-  0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
-    0x6df3f4d4, 0xbe77fe78,
-  0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
-    0x6de714c0, 0xbe6268e5,
-  0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
-    0x6dda306f, 0xbe4cd5da,
-  0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
-    0x6dcd47e1, 0xbe374557,
-  0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
-    0x6dc05b18, 0xbe21b75d,
-  0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
-    0x6db36a14, 0xbe0c2bed,
-  0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
-    0x6da674d5, 0xbdf6a309,
-  0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
-    0x6d997b5b, 0xbde11cb0,
-  0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
-    0x6d8c7da8, 0xbdcb98e3,
-  0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
-    0x6d7f7bbc, 0xbdb617a4,
-  0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
-    0x6d727597, 0xbda098f3,
-  0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
-    0x6d656b3a, 0xbd8b1cd2,
-  0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
-    0x6d585ca6, 0xbd75a340,
-  0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
-    0x6d4b49da, 0xbd602c3f,
-  0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
-    0x6d3e32d7, 0xbd4ab7cf,
-  0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
-    0x6d31179e, 0xbd3545f2,
-  0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
-    0x6d23f830, 0xbd1fd6a8,
-  0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
-    0x6d16d48c, 0xbd0a69f2,
-  0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
-    0x6d09acb4, 0xbcf4ffd1,
-  0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
-    0x6cfc80a7, 0xbcdf9846,
-  0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
-    0x6cef5067, 0xbcca3351,
-  0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
-    0x6ce21bf4, 0xbcb4d0f4,
-  0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
-    0x6cd4e34e, 0xbc9f712e,
-  0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
-    0x6cc7a676, 0xbc8a1402,
-  0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
-    0x6cba656c, 0xbc74b96f,
-  0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
-    0x6cad2031, 0xbc5f6177,
-  0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
-    0x6c9fd6c6, 0xbc4a0c1b,
-  0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
-    0x6c92892a, 0xbc34b95b,
-  0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
-    0x6c85375f, 0xbc1f6938,
-  0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
-    0x6c77e165, 0xbc0a1bb3,
-  0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
-    0x6c6a873d, 0xbbf4d0cc,
-  0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
-    0x6c5d28e6, 0xbbdf8885,
-  0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
-    0x6c4fc662, 0xbbca42df,
-  0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
-    0x6c425fb1, 0xbbb4ffda,
-  0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
-    0x6c34f4d3, 0xbb9fbf77,
-  0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
-    0x6c2785ca, 0xbb8a81b6,
-  0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
-    0x6c1a1295, 0xbb754699,
-  0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
-    0x6c0c9b35, 0xbb600e21,
-  0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
-    0x6bff1faa, 0xbb4ad84e,
-  0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
-    0x6bf19ff6, 0xbb35a521,
-  0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
-    0x6be41c18, 0xbb20749c,
-  0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
-    0x6bd69412, 0xbb0b46bd,
-  0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
-    0x6bc907e3, 0xbaf61b88,
-  0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
-    0x6bbb778d, 0xbae0f2fc,
-  0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
-    0x6bade30f, 0xbacbcd1a,
-  0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
-    0x6ba04a6a, 0xbab6a9e3,
-  0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
-    0x6b92ada0, 0xbaa18958,
-  0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
-    0x6b850caf, 0xba8c6b79,
-  0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
-    0x6b776799, 0xba775048,
-  0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
-    0x6b69be5f, 0xba6237c5,
-  0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
-    0x6b5c1101, 0xba4d21f2,
-  0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
-    0x6b4e5f7f, 0xba380ece,
-  0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
-    0x6b40a9d9, 0xba22fe5b,
-  0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
-    0x6b32f012, 0xba0df099,
-  0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
-    0x6b253228, 0xb9f8e58a,
-  0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
-    0x6b17701d, 0xb9e3dd2e,
-  0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
-    0x6b09a9f1, 0xb9ced786,
-  0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
-    0x6afbdfa4, 0xb9b9d493,
-  0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
-    0x6aee1138, 0xb9a4d455,
-  0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
-    0x6ae03eac, 0xb98fd6cd,
-  0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
-    0x6ad26802, 0xb97adbfd,
-  0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
-    0x6ac48d39, 0xb965e3e5,
-  0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
-    0x6ab6ae52, 0xb950ee86,
-  0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
-    0x6aa8cb4e, 0xb93bfbe0,
-  0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
-    0x6a9ae42e, 0xb9270bf5,
-  0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
-    0x6a8cf8f1, 0xb9121ec5,
-  0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
-    0x6a7f0999, 0xb8fd3451,
-  0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
-    0x6a711625, 0xb8e84c99,
-  0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
-    0x6a631e97, 0xb8d367a0,
-  0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
-    0x6a5522ef, 0xb8be8565,
-  0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
-    0x6a47232e, 0xb8a9a5e9,
-  0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
-    0x6a391f54, 0xb894c92d,
-  0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
-    0x6a2b1761, 0xb87fef33,
-  0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
-    0x6a1d0b57, 0xb86b17f9,
-  0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
-    0x6a0efb35, 0xb8564383,
-  0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
-    0x6a00e6fc, 0xb84171cf,
-  0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
-    0x69f2cead, 0xb82ca2e0,
-  0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
-    0x69e4b249, 0xb817d6b6,
-  0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
-    0x69d691cf, 0xb8030d51,
-  0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
-    0x69c86d41, 0xb7ee46b3,
-  0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
-    0x69ba449f, 0xb7d982dc,
-  0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
-    0x69ac17e9, 0xb7c4c1cd,
-  0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
-    0x699de721, 0xb7b00387,
-  0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
-    0x698fb246, 0xb79b480b,
-  0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
-    0x69817959, 0xb7868f59,
-  0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
-    0x69733c5b, 0xb771d972,
-  0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
-    0x6964fb4c, 0xb75d2658,
-  0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
-    0x6956b62d, 0xb748760b,
-  0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
-    0x69486cfe, 0xb733c88b,
-  0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
-    0x693a1fc0, 0xb71f1dd9,
-  0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
-    0x692bce73, 0xb70a75f7,
-  0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
-    0x691d7919, 0xb6f5d0e5,
-  0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
-    0x690f1fb1, 0xb6e12ea4,
-  0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
-    0x6900c23c, 0xb6cc8f35,
-  0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
-    0x68f260bb, 0xb6b7f298,
-  0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
-    0x68e3fb2e, 0xb6a358ce,
-  0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
-    0x68d59196, 0xb68ec1d9,
-  0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
-    0x68c723f3, 0xb67a2db8,
-  0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
-    0x68b8b247, 0xb6659c6d,
-  0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
-    0x68aa3c90, 0xb6510df8,
-  0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
-    0x689bc2d1, 0xb63c825b,
-  0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
-    0x688d4509, 0xb627f995,
-  0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
-    0x687ec339, 0xb61373a9,
-  0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
-    0x68703d62, 0xb5fef095,
-  0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
-    0x6861b384, 0xb5ea705d,
-  0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
-    0x685325a0, 0xb5d5f2ff,
-  0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
-    0x684493b6, 0xb5c1787e,
-  0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
-    0x6835fdc7, 0xb5ad00d9,
-  0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
-    0x682763d4, 0xb5988c12,
-  0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
-    0x6818c5dd, 0xb5841a29,
-  0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
-    0x680a23e2, 0xb56fab1f,
-  0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
-    0x67fb7de5, 0xb55b3ef5,
-  0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
-    0x67ecd3e5, 0xb546d5ac,
-  0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
-    0x67de25e3, 0xb5326f45,
-  0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
-    0x67cf73e1, 0xb51e0bbf,
-  0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
-    0x67c0bddd, 0xb509ab1d,
-  0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
-    0x67b203da, 0xb4f54d5f,
-  0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
-    0x67a345d8, 0xb4e0f285,
-  0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
-    0x679483d6, 0xb4cc9a90,
-  0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
-    0x6785bdd6, 0xb4b84582,
-  0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
-    0x6776f3d9, 0xb4a3f35b,
-  0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
-    0x676825de, 0xb48fa41c,
-  0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
-    0x675953e7, 0xb47b57c5,
-  0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
-    0x674a7df4, 0xb4670e57,
-  0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
-    0x673ba405, 0xb452c7d4,
-  0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
-    0x672cc61c, 0xb43e843b,
-  0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
-    0x671de438, 0xb42a438e,
-  0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
-    0x670efe5a, 0xb41605ce,
-  0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
-    0x67001483, 0xb401cafb,
-  0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
-    0x66f126b4, 0xb3ed9316,
-  0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
-    0x66e234ed, 0xb3d95e1f,
-  0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
-    0x66d33f2e, 0xb3c52c19,
-  0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
-    0x66c44579, 0xb3b0fd02,
-  0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
-    0x66b547cd, 0xb39cd0dd,
-  0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
-    0x66a6462b, 0xb388a7aa,
-  0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
-    0x66974095, 0xb3748169,
-  0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
-    0x66883709, 0xb3605e1c,
-  0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
-    0x6679298a, 0xb34c3dc3,
-  0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
-    0x666a1818, 0xb338205f,
-  0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
-    0x665b02b3, 0xb32405f1,
-  0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
-    0x664be95b, 0xb30fee79,
-  0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
-    0x663ccc12, 0xb2fbd9f9,
-  0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
-    0x662daad8, 0xb2e7c871,
-  0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
-    0x661e85ad, 0xb2d3b9e2,
-  0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
-    0x660f5c93, 0xb2bfae4c,
-  0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
-    0x66002f89, 0xb2aba5b1,
-  0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
-    0x65f0fe91, 0xb297a011,
-  0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
-    0x65e1c9aa, 0xb2839d6d,
-  0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
-    0x65d290d6, 0xb26f9dc6,
-  0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
-    0x65c35415, 0xb25ba11d,
-  0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
-    0x65b41367, 0xb247a771,
-  0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
-    0x65a4cece, 0xb233b0c5,
-  0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
-    0x6595864a, 0xb21fbd19,
-  0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
-    0x658639db, 0xb20bcc6d,
-  0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
-    0x6576e982, 0xb1f7dec2,
-  0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
-    0x6567953f, 0xb1e3f41a,
-  0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
-    0x65583d14, 0xb1d00c75,
-  0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
-    0x6548e101, 0xb1bc27d3,
-  0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
-    0x65398105, 0xb1a84636,
-  0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
-    0x652a1d23, 0xb194679e,
-  0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
-    0x651ab55b, 0xb1808c0c,
-  0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
-    0x650b49ac, 0xb16cb380,
-  0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
-    0x64fbda18, 0xb158ddfd,
-  0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
-    0x64ec66a0, 0xb1450b81,
-  0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
-    0x64dcef44, 0xb1313c0e,
-  0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
-    0x64cd7404, 0xb11d6fa6,
-  0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
-    0x64bdf4e1, 0xb109a648,
-  0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
-    0x64ae71dc, 0xb0f5dff5,
-  0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
-    0x649eeaf5, 0xb0e21cae,
-  0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
-    0x648f602d, 0xb0ce5c74,
-  0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
-    0x647fd185, 0xb0ba9f48,
-  0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
-    0x64703efc, 0xb0a6e52a,
-  0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
-    0x6460a895, 0xb0932e1b,
-  0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
-    0x64510e4e, 0xb07f7a1c,
-  0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
-    0x6441702a, 0xb06bc92e,
-  0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
-    0x6431ce28, 0xb0581b51,
-  0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
-    0x6422284a, 0xb0447087,
-  0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
-    0x64127e8f, 0xb030c8cf,
-  0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
-    0x6402d0f8, 0xb01d242b,
-  0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
-    0x63f31f86, 0xb009829c,
-  0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
-    0x63e36a3a, 0xaff5e421,
-  0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
-    0x63d3b114, 0xafe248bd,
-  0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
-    0x63c3f415, 0xafceb06f,
-  0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
-    0x63b4333d, 0xafbb1b39,
-  0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
-    0x63a46e8d, 0xafa7891b,
-  0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
-    0x6394a606, 0xaf93fa16,
-  0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
-    0x6384d9a7, 0xaf806e2b,
-  0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
-    0x63750973, 0xaf6ce55a,
-  0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
-    0x63653569, 0xaf595fa4,
-  0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
-    0x63555d8a, 0xaf45dd0b,
-  0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
-    0x634581d6, 0xaf325d8e,
-  0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
-    0x6335a24f, 0xaf1ee12e,
-  0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
-    0x6325bef5, 0xaf0b67ed,
-  0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
-    0x6315d7c8, 0xaef7f1cb,
-  0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
-    0x6305ecc9, 0xaee47ec9,
-  0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
-    0x62f5fdf9, 0xaed10ee7,
-  0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
-    0x62e60b58, 0xaebda227,
-  0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
-    0x62d614e7, 0xaeaa3888,
-  0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
-    0x62c61aa7, 0xae96d20c,
-  0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
-    0x62b61c98, 0xae836eb4,
-  0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
-    0x62a61aba, 0xae700e80,
-  0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
-    0x6296150f, 0xae5cb171,
-  0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
-    0x62860b97, 0xae495787,
-  0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
-    0x6275fe52, 0xae3600c4,
-  0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
-    0x6265ed42, 0xae22ad29,
-  0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
-    0x6255d866, 0xae0f5cb5,
-  0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
-    0x6245bfc0, 0xadfc0f6a,
-  0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
-    0x6235a351, 0xade8c548,
-  0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
-    0x62258317, 0xadd57e51,
-  0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
-    0x62155f16, 0xadc23a85,
-  0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
-    0x6205374c, 0xadaef9e4,
-  0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
-    0x61f50bba, 0xad9bbc70,
-  0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
-    0x61e4dc62, 0xad888229,
-  0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
-    0x61d4a944, 0xad754b0f,
-  0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
-    0x61c47260, 0xad621725,
-  0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
-    0x61b437b7, 0xad4ee66a,
-  0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
-    0x61a3f94a, 0xad3bb8df,
-  0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
-    0x6193b719, 0xad288e85,
-  0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
-    0x61837126, 0xad15675c,
-  0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
-    0x61732770, 0xad024366,
-  0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
-    0x6162d9f8, 0xacef22a3,
-  0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
-    0x615288be, 0xacdc0514,
-  0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
-    0x614233c5, 0xacc8eab9,
-  0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
-    0x6131db0b, 0xacb5d394,
-  0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
-    0x61217e92, 0xaca2bfa4,
-  0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
-    0x61111e5b, 0xac8faeec,
-  0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
-    0x6100ba65, 0xac7ca16b,
-  0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
-    0x60f052b2, 0xac699722,
-  0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
-    0x60dfe743, 0xac569012,
-  0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
-    0x60cf7817, 0xac438c3c,
-  0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
-    0x60bf0530, 0xac308ba0,
-  0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
-    0x60ae8e8d, 0xac1d8e40,
-  0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
-    0x609e1431, 0xac0a941b,
-  0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
-    0x608d961b, 0xabf79d33,
-  0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
-    0x607d144c, 0xabe4a988,
-  0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
-    0x606c8ec5, 0xabd1b91c,
-  0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
-    0x605c0587, 0xabbecbee,
-  0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
-    0x604b7891, 0xababe200,
-  0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
-    0x603ae7e5, 0xab98fb52,
-  0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
-    0x602a5383, 0xab8617e6,
-  0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
-    0x6019bb6b, 0xab7337bb,
-  0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
-    0x60091fa0, 0xab605ad2,
-  0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
-    0x5ff88021, 0xab4d812d,
-  0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
-    0x5fe7dcee, 0xab3aaacb,
-  0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
-    0x5fd73609, 0xab27d7ae,
-  0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
-    0x5fc68b72, 0xab1507d7,
-  0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
-    0x5fb5dd29, 0xab023b46,
-  0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
-    0x5fa52b31, 0xaaef71fb,
-  0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
-    0x5f947588, 0xaadcabf8,
-  0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
-    0x5f83bc2f, 0xaac9e93e,
-  0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
-    0x5f72ff28, 0xaab729cc,
-  0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
-    0x5f623e73, 0xaaa46da4,
-  0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
-    0x5f517a11, 0xaa91b4c7,
-  0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
-    0x5f40b202, 0xaa7eff34,
-  0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
-    0x5f2fe647, 0xaa6c4cee,
-  0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
-    0x5f1f16e0, 0xaa599df4,
-  0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
-    0x5f0e43ce, 0xaa46f248,
-  0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
-    0x5efd6d13, 0xaa3449e9,
-  0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
-    0x5eec92ae, 0xaa21a4d9,
-  0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
-    0x5edbb49f, 0xaa0f0319,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
-    0x5ecad2e9, 0xa9fc64a9,
-  0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
-    0x5eb9ed8b, 0xa9e9c98a,
-  0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
-    0x5ea90487, 0xa9d731bd,
-  0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
-    0x5e9817dc, 0xa9c49d42,
-  0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
-    0x5e87278b, 0xa9b20c1a,
-  0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
-    0x5e763395, 0xa99f7e46,
-  0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
-    0x5e653bfc, 0xa98cf3c6,
-  0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
-    0x5e5440be, 0xa97a6c9c,
-  0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
-    0x5e4341de, 0xa967e8c7,
-  0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
-    0x5e323f5b, 0xa9556849,
-  0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
-    0x5e213936, 0xa942eb23,
-  0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
-    0x5e102f71, 0xa9307155,
-  0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
-    0x5dff220b, 0xa91dfadf,
-  0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
-    0x5dee1105, 0xa90b87c3,
-  0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
-    0x5ddcfc61, 0xa8f91801,
-  0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
-    0x5dcbe41d, 0xa8e6ab9a,
-  0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
-    0x5dbac83d, 0xa8d4428f,
-  0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
-    0x5da9a8bf, 0xa8c1dce0,
-  0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
-    0x5d9885a5, 0xa8af7a8e,
-  0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
-    0x5d875eef, 0xa89d1b99,
-  0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
-    0x5d76349d, 0xa88ac004,
-  0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
-    0x5d6506b2, 0xa87867cd,
-  0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
-    0x5d53d52d, 0xa86612f6,
-  0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
-    0x5d42a00e, 0xa853c180,
-  0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
-    0x5d316757, 0xa841736c,
-  0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
-    0x5d202b09, 0xa82f28b9,
-  0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
-    0x5d0eeb23, 0xa81ce169,
-  0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
-    0x5cfda7a7, 0xa80a9d7c,
-  0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
-    0x5cec6095, 0xa7f85cf3,
-  0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
-    0x5cdb15ed, 0xa7e61fd0,
-  0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
-    0x5cc9c7b2, 0xa7d3e611,
-  0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
-    0x5cb875e3, 0xa7c1afb9,
-  0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
-    0x5ca72080, 0xa7af7cc8,
-  0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
-    0x5c95c78b, 0xa79d4d3f,
-  0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
-    0x5c846b05, 0xa78b211e,
-  0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
-    0x5c730aed, 0xa778f866,
-  0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
-    0x5c61a745, 0xa766d317,
-  0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
-    0x5c50400d, 0xa754b134,
-  0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
-    0x5c3ed545, 0xa74292bb,
-  0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
-    0x5c2d66f0, 0xa73077ae,
-  0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
-    0x5c1bf50d, 0xa71e600d,
-  0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
-    0x5c0a7f9c, 0xa70c4bda,
-  0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
-    0x5bf906a0, 0xa6fa3b15,
-  0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
-    0x5be78a17, 0xa6e82dbe,
-  0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
-    0x5bd60a03, 0xa6d623d7,
-  0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
-    0x5bc48666, 0xa6c41d60,
-  0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
-    0x5bb2ff3e, 0xa6b21a59,
-  0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
-    0x5ba1748d, 0xa6a01ac4,
-  0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
-    0x5b8fe654, 0xa68e1ea1,
-  0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
-    0x5b7e5493, 0xa67c25f0,
-  0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
-    0x5b6cbf4c, 0xa66a30b3,
-  0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
-    0x5b5b267e, 0xa6583eeb,
-  0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
-    0x5b498a2a, 0xa6465097,
-  0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
-    0x5b37ea51, 0xa63465b9,
-  0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
-    0x5b2646f4, 0xa6227e50,
-  0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
-    0x5b14a014, 0xa6109a5f,
-  0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
-    0x5b02f5b0, 0xa5feb9e6,
-  0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
-    0x5af147ca, 0xa5ecdce5,
-  0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
-    0x5adf9663, 0xa5db035c,
-  0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
-    0x5acde17b, 0xa5c92d4e,
-  0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
-    0x5abc2912, 0xa5b75aba,
-  0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
-    0x5aaa6d2b, 0xa5a58ba1,
-  0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
-    0x5a98adc4, 0xa593c004,
-  0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
-    0x5a86eadf, 0xa581f7e3,
-  0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
-    0x5a75247c, 0xa570333f,
-  0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
-    0x5a635a9d, 0xa55e7219,
-  0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
-    0x5a518d42, 0xa54cb472,
-  0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
-    0x5a3fbc6b, 0xa53afa49,
-  0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
-    0x5a2de81a, 0xa52943a1,
-  0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
-    0x5a1c104f, 0xa5179079,
-  0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
-    0x5a0a350a, 0xa505e0d2,
-  0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
-    0x59f8564c, 0xa4f434ae,
-  0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
-    0x59e67417, 0xa4e28c0c,
-  0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
-    0x59d48e6a, 0xa4d0e6ed,
-  0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
-    0x59c2a547, 0xa4bf4552,
-  0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
-    0x59b0b8ae, 0xa4ada73c,
-  0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
-    0x599ec8a0, 0xa49c0cab,
-  0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
-    0x598cd51d, 0xa48a75a0,
-  0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
-    0x597ade26, 0xa478e21b,
-  0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
-    0x5968e3bc, 0xa467521e,
-  0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
-    0x5956e5e0, 0xa455c5a9,
-  0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
-    0x5944e492, 0xa4443cbd,
-  0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
-    0x5932dfd3, 0xa432b75a,
-  0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
-    0x5920d7a3, 0xa4213581,
-  0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
-    0x590ecc04, 0xa40fb733,
-  0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
-    0x58fcbcf6, 0xa3fe3c71,
-  0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
-    0x58eaaa7a, 0xa3ecc53a,
-  0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
-    0x58d89490, 0xa3db5190,
-  0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
-    0x58c67b39, 0xa3c9e174,
-  0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
-    0x58b45e76, 0xa3b874e5,
-  0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
-    0x58a23e48, 0xa3a70be6,
-  0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
-    0x58901aaf, 0xa395a675,
-  0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
-    0x587df3ab, 0xa3844495,
-  0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
-    0x586bc93f, 0xa372e646,
-  0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
-    0x58599b69, 0xa3618b88,
-  0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
-    0x58476a2c, 0xa350345c,
-  0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
-    0x58353587, 0xa33ee0c3,
-  0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
-    0x5822fd7c, 0xa32d90be,
-  0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
-    0x5810c20b, 0xa31c444c,
-  0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
-    0x57fe8335, 0xa30afb70,
-  0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
-    0x57ec40fa, 0xa2f9b629,
-  0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
-    0x57d9fb5c, 0xa2e87477,
-  0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
-    0x57c7b25a, 0xa2d7365d,
-  0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
-    0x57b565f6, 0xa2c5fbda,
-  0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
-    0x57a31631, 0xa2b4c4f0,
-  0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
-    0x5790c30a, 0xa2a3919e,
-  0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
-    0x577e6c84, 0xa29261e5,
-  0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
-    0x576c129d, 0xa28135c7,
-  0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
-    0x5759b558, 0xa2700d43,
-  0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
-    0x574754b5, 0xa25ee85b,
-  0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
-    0x5734f0b5, 0xa24dc70f,
-  0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
-    0x57228957, 0xa23ca95f,
-  0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
-    0x57101e9e, 0xa22b8f4d,
-  0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
-    0x56fdb08a, 0xa21a78d9,
-  0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
-    0x56eb3f1a, 0xa2096604,
-  0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
-    0x56d8ca51, 0xa1f856ce,
-  0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
-    0x56c6522f, 0xa1e74b38,
-  0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
-    0x56b3d6b5, 0xa1d64343,
-  0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
-    0x56a157e3, 0xa1c53ef0,
-  0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
-    0x568ed5b9, 0xa1b43e3e,
-  0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
-    0x567c503a, 0xa1a3412f,
-  0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
-    0x5669c765, 0xa19247c3,
-  0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
-    0x56573b3b, 0xa18151fb,
-  0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
-    0x5644abbc, 0xa1705fd8,
-  0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
-    0x563218eb, 0xa15f715a,
-  0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
-    0x561f82c7, 0xa14e8682,
-  0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
-    0x560ce950, 0xa13d9f51,
-  0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
-    0x55fa4c89, 0xa12cbbc7,
-  0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
-    0x55e7ac71, 0xa11bdbe4,
-  0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
-    0x55d50909, 0xa10affab,
-  0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
-    0x55c26251, 0xa0fa271a,
-  0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
-    0x55afb84c, 0xa0e95234,
-  0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
-    0x559d0af9, 0xa0d880f7,
-  0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
-    0x558a5a58, 0xa0c7b366,
-  0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
-    0x5577a66c, 0xa0b6e981,
-  0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
-    0x5564ef34, 0xa0a62348,
-  0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
-    0x555234b1, 0xa09560bc,
-  0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
-    0x553f76e4, 0xa084a1de,
-  0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
-    0x552cb5ce, 0xa073e6af,
-  0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
-    0x5519f16f, 0xa0632f2e,
-  0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
-    0x550729c9, 0xa0527b5d,
-  0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
-    0x54f45edb, 0xa041cb3c,
-  0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
-    0x54e190a6, 0xa0311ecd,
-  0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
-    0x54cebf2c, 0xa020760e,
-  0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
-    0x54bbea6d, 0xa00fd102,
-  0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
-    0x54a91269, 0x9fff2fa9,
-  0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
-    0x54963722, 0x9fee9204,
-  0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
-    0x54835898, 0x9fddf812,
-  0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
-    0x547076cc, 0x9fcd61d6,
-  0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
-    0x545d91bf, 0x9fbccf4f,
-  0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
-    0x544aa971, 0x9fac407e,
-  0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
-    0x5437bde3, 0x9f9bb563,
-  0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
-    0x5424cf16, 0x9f8b2e00,
-  0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
-    0x5411dd0a, 0x9f7aaa55,
-  0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
-    0x53fee7c1, 0x9f6a2a63,
-  0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
-    0x53ebef3a, 0x9f59ae29,
-  0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
-    0x53d8f378, 0x9f4935aa,
-  0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
-    0x53c5f479, 0x9f38c0e5,
-  0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
-    0x53b2f240, 0x9f284fdc,
-  0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
-    0x539feccd, 0x9f17e28e,
-  0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
-    0x538ce421, 0x9f0778fd,
-  0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
-    0x5379d83c, 0x9ef71328,
-  0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
-    0x5366c91f, 0x9ee6b112,
-  0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
-    0x5353b6cb, 0x9ed652ba,
-  0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
-    0x5340a140, 0x9ec5f820,
-  0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
-    0x532d8880, 0x9eb5a146,
-  0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
-    0x531a6c8b, 0x9ea54e2d,
-  0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
-    0x53074d62, 0x9e94fed4,
-  0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
-    0x52f42b05, 0x9e84b33d,
-  0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
-    0x52e10576, 0x9e746b68,
-  0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
-    0x52cddcb5, 0x9e642756,
-  0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
-    0x52bab0c2, 0x9e53e707,
-  0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
-    0x52a7819f, 0x9e43aa7c,
-  0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
-    0x52944f4c, 0x9e3371b5,
-  0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
-    0x528119ca, 0x9e233cb4,
-  0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
-    0x526de11a, 0x9e130b79,
-  0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
-    0x525aa53c, 0x9e02de04,
-  0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
-    0x52476631, 0x9df2b456,
-  0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
-    0x523423fb, 0x9de28e70,
-  0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
-    0x5220de99, 0x9dd26c53,
-  0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
-    0x520d960c, 0x9dc24dfe,
-  0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
-    0x51fa4a56, 0x9db23373,
-  0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
-    0x51e6fb76, 0x9da21cb2,
-  0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
-    0x51d3a96f, 0x9d9209bd,
-  0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
-    0x51c0543f, 0x9d81fa92,
-  0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
-    0x51acfbe9, 0x9d71ef34,
-  0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
-    0x5199a06d, 0x9d61e7a2,
-  0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
-    0x518641cb, 0x9d51e3dd,
-  0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
-    0x5172e005, 0x9d41e3e7,
-  0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
-    0x515f7b1a, 0x9d31e7bf,
-  0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
-    0x514c130d, 0x9d21ef66,
-  0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
-    0x5138a7dd, 0x9d11fadd,
-  0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
-    0x5125398c, 0x9d020a25,
-  0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
-    0x5111c81a, 0x9cf21d3d,
-  0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
-    0x50fe5388, 0x9ce23427,
-  0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
-    0x50eadbd6, 0x9cd24ee4,
-  0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
-    0x50d76106, 0x9cc26d73,
-  0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
-    0x50c3e317, 0x9cb28fd5,
-  0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
-    0x50b0620c, 0x9ca2b60c,
-  0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
-    0x509cdde4, 0x9c92e017,
-  0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
-    0x508956a1, 0x9c830df8,
-  0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
-    0x5075cc43, 0x9c733faf,
-  0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
-    0x50623ecb, 0x9c63753c,
-  0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
-    0x504eae39, 0x9c53aea0,
-  0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
-    0x503b1a8f, 0x9c43ebdc,
-  0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
-    0x502783cd, 0x9c342cf0,
-  0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
-    0x5013e9f4, 0x9c2471de,
-  0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
-    0x50004d04, 0x9c14baa4,
-  0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
-    0x4fecacff, 0x9c050745,
-  0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
-    0x4fd909e5, 0x9bf557c1,
-  0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
-    0x4fc563b7, 0x9be5ac18,
-  0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
-    0x4fb1ba76, 0x9bd6044b,
-  0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
-    0x4f9e0e22, 0x9bc6605b,
-  0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
-    0x4f8a5ebd, 0x9bb6c048,
-  0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
-    0x4f76ac46, 0x9ba72413,
-  0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
-    0x4f62f6bf, 0x9b978bbc,
-  0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
-    0x4f4f3e29, 0x9b87f744,
-  0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
-    0x4f3b8284, 0x9b7866ab,
-  0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
-    0x4f27c3d1, 0x9b68d9f3,
-  0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
-    0x4f140210, 0x9b59511c,
-  0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
-    0x4f003d43, 0x9b49cc26,
-  0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
-    0x4eec756b, 0x9b3a4b11,
-  0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
-    0x4ed8aa87, 0x9b2acde0,
-  0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
-    0x4ec4dc99, 0x9b1b5492,
-  0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
-    0x4eb10ba2, 0x9b0bdf27,
-  0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
-    0x4e9d37a3, 0x9afc6da1,
-  0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
-    0x4e89609b, 0x9aed0000,
-  0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
-    0x4e75868c, 0x9add9644,
-  0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
-    0x4e61a977, 0x9ace306f,
-  0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
-    0x4e4dc95c, 0x9abece80,
-  0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
-    0x4e39e63d, 0x9aaf7079,
-  0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
-    0x4e260019, 0x9aa01659,
-  0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
-    0x4e1216f2, 0x9a90c022,
-  0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
-    0x4dfe2ac9, 0x9a816dd5,
-  0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
-    0x4dea3b9d, 0x9a721f71,
-  0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
-    0x4dd64971, 0x9a62d4f7,
-  0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
-    0x4dc25445, 0x9a538e68,
-  0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
-    0x4dae5c19, 0x9a444bc5,
-  0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
-    0x4d9a60ee, 0x9a350d0d,
-  0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
-    0x4d8662c6, 0x9a25d243,
-  0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
-    0x4d7261a0, 0x9a169b65,
-  0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
-    0x4d5e5d7e, 0x9a076875,
-  0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
-    0x4d4a5661, 0x99f83974,
-  0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
-    0x4d364c48, 0x99e90e62,
-  0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
-    0x4d223f36, 0x99d9e73f,
-  0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
-    0x4d0e2f2a, 0x99cac40d,
-  0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
-    0x4cfa1c26, 0x99bba4cb,
-  0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
-    0x4ce6062a, 0x99ac897b,
-  0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
-    0x4cd1ed37, 0x999d721c,
-  0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
-    0x4cbdd14e, 0x998e5eb1,
-  0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
-    0x4ca9b26f, 0x997f4f38,
-  0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
-    0x4c95909c, 0x997043b2,
-  0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
-    0x4c816bd5, 0x99613c22,
-  0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
-    0x4c6d441b, 0x99523885,
-  0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
-    0x4c59196f, 0x994338df,
-  0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
-    0x4c44ebd1, 0x99343d2e,
-  0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
-    0x4c30bb42, 0x99254574,
-  0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
-    0x4c1c87c3, 0x991651b1,
-  0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
-    0x4c085156, 0x990761e5,
-  0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
-    0x4bf417f9, 0x98f87612,
-  0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
-    0x4bdfdbaf, 0x98e98e38,
-  0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
-    0x4bcb9c79, 0x98daaa57,
-  0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
-    0x4bb75a56, 0x98cbca70,
-  0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
-    0x4ba31548, 0x98bcee84,
-  0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
-    0x4b8ecd4f, 0x98ae1693,
-  0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
-    0x4b7a826d, 0x989f429e,
-  0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
-    0x4b6634a2, 0x989072a5,
-  0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
-    0x4b51e3ee, 0x9881a6a9,
-  0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
-    0x4b3d9053, 0x9872deaa,
-  0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
-    0x4b2939d2, 0x98641aa9,
-  0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
-    0x4b14e06b, 0x98555aa7,
-  0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
-    0x4b00841f, 0x98469ea4,
-  0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
-    0x4aec24ee, 0x9837e6a1,
-  0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
-    0x4ad7c2da, 0x9829329e,
-  0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
-    0x4ac35de4, 0x981a829c,
-  0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
-    0x4aaef60b, 0x980bd69b,
-  0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
-    0x4a9a8b52, 0x97fd2e9c,
-  0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
-    0x4a861db8, 0x97ee8aa0,
-  0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
-    0x4a71ad3e, 0x97dfeaa7,
-  0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
-    0x4a5d39e6, 0x97d14eb2,
-  0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
-    0x4a48c3b0, 0x97c2b6c1,
-  0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
-    0x4a344a9d, 0x97b422d4,
-  0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
-    0x4a1fcead, 0x97a592ed,
-  0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
-    0x4a0b4fe2, 0x9797070c,
-  0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
-    0x49f6ce3c, 0x97887f32,
-  0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
-    0x49e249bc, 0x9779fb5e,
-  0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
-    0x49cdc263, 0x976b7b92,
-  0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
-    0x49b93832, 0x975cffcf,
-  0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
-    0x49a4ab28, 0x974e8813,
-  0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
-    0x49901b48, 0x97401462,
-  0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
-    0x497b8892, 0x9731a4ba,
-  0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
-    0x4966f307, 0x9723391c,
-  0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
-    0x49525aa7, 0x9714d18a,
-  0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
-    0x493dbf74, 0x97066e03,
-  0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
-    0x4929216e, 0x96f80e88,
-  0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
-    0x49148095, 0x96e9b319,
-  0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
-    0x48ffdcec, 0x96db5bb8,
-  0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
-    0x48eb3672, 0x96cd0865,
-  0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
-    0x48d68d28, 0x96beb91f,
-  0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
-    0x48c1e10f, 0x96b06de9,
-  0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
-    0x48ad3228, 0x96a226c2,
-  0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
-    0x48988074, 0x9693e3ab,
-  0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
-    0x4883cbf4, 0x9685a4a4,
-  0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
-    0x486f14a8, 0x967769af,
-  0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
-    0x485a5a90, 0x966932cb,
-  0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
-    0x48459daf, 0x965afff9,
-  0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
-    0x4830de05, 0x964cd139,
-  0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
-    0x481c1b92, 0x963ea68d,
-  0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
-    0x48075657, 0x96307ff5,
-  0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
-    0x47f28e56, 0x96225d71,
-  0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
-    0x47ddc38e, 0x96143f02,
-  0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
-    0x47c8f601, 0x960624a9,
-  0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
-    0x47b425af, 0x95f80e65,
-  0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
-    0x479f529a, 0x95e9fc38,
-  0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
-    0x478a7cc2, 0x95dbee21,
-  0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
-    0x4775a428, 0x95cde423,
-  0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
-    0x4760c8cd, 0x95bfde3c,
-  0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
-    0x474beab1, 0x95b1dc6e,
-  0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
-    0x473709d5, 0x95a3deb9,
-  0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
-    0x4722263b, 0x9595e51e,
-  0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
-    0x470d3fe3, 0x9587ef9e,
-  0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
-    0x46f856cd, 0x9579fe38,
-  0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
-    0x46e36afb, 0x956c10ed,
-  0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
-    0x46ce7c6d, 0x955e27bf,
-  0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
-    0x46b98b24, 0x955042ac,
-  0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
-    0x46a49722, 0x954261b7,
-  0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
-    0x468fa066, 0x953484df,
-  0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
-    0x467aa6f2, 0x9526ac25,
-  0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
-    0x4665aac6, 0x9518d78a,
-  0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
-    0x4650abe3, 0x950b070e,
-  0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
-    0x463baa4a, 0x94fd3ab1,
-  0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
-    0x4626a5fd, 0x94ef7275,
-  0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
-    0x46119efa, 0x94e1ae59,
-  0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
-    0x45fc9545, 0x94d3ee5f,
-  0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
-    0x45e788dc, 0x94c63286,
-  0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
-    0x45d279c2, 0x94b87ad0,
-  0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
-    0x45bd67f6, 0x94aac73c,
-  0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
-    0x45a8537a, 0x949d17cc,
-  0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
-    0x45933c4f, 0x948f6c7f,
-  0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
-    0x457e2275, 0x9481c557,
-  0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
-    0x456905ed, 0x94742254,
-  0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
-    0x4553e6b8, 0x94668376,
-  0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
-    0x453ec4d7, 0x9458e8bf,
-  0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
-    0x4529a04b, 0x944b522d,
-  0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
-    0x45147913, 0x943dbfc3,
-  0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
-    0x44ff4f32, 0x94303180,
-  0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
-    0x44ea22a9, 0x9422a766,
-  0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
-    0x44d4f376, 0x94152174,
-  0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
-    0x44bfc19d, 0x94079fab,
-  0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
-    0x44aa8d1d, 0x93fa220b,
-  0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
-    0x449555f7, 0x93eca896,
-  0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
-    0x44801c2d, 0x93df334c,
-  0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
-    0x446adfbe, 0x93d1c22c,
-  0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
-    0x4455a0ac, 0x93c45539,
-  0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
-    0x44405ef8, 0x93b6ec71,
-  0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
-    0x442b1aa2, 0x93a987d6,
-  0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
-    0x4415d3ab, 0x939c2769,
-  0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
-    0x44008a14, 0x938ecb29,
-  0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
-    0x43eb3ddf, 0x93817318,
-  0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
-    0x43d5ef0a, 0x93741f35,
-  0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
-    0x43c09d99, 0x9366cf82,
-  0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
-    0x43ab498a, 0x935983ff,
-  0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
-    0x4395f2e0, 0x934c3cab,
-  0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
-    0x4380999b, 0x933ef989,
-  0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
-    0x436b3dbb, 0x9331ba98,
-  0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
-    0x4355df42, 0x93247fd9,
-  0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
-    0x43407e31, 0x9317494c,
-  0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
-    0x432b1a87, 0x930a16f3,
-  0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
-    0x4315b447, 0x92fce8cc,
-  0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
-    0x43004b71, 0x92efbeda,
-  0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
-    0x42eae005, 0x92e2991c,
-  0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
-    0x42d57205, 0x92d57792,
-  0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
-    0x42c00172, 0x92c85a3f,
-  0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
-    0x42aa8e4b, 0x92bb4121,
-  0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
-    0x42951893, 0x92ae2c3a,
-  0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
-    0x427fa049, 0x92a11b89,
-  0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
-    0x426a256f, 0x92940f10,
-  0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
-    0x4254a806, 0x928706cf,
-  0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
-    0x423f280e, 0x927a02c7,
-  0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
-    0x4229a588, 0x926d02f7,
-  0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
-    0x42142075, 0x92600761,
-  0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
-    0x41fe98d6, 0x92531005,
-  0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
-    0x41e90eac, 0x92461ce3,
-  0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
-    0x41d381f7, 0x92392dfc,
-  0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
-    0x41bdf2b9, 0x922c4351,
-  0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
-    0x41a860f1, 0x921f5ce1,
-  0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
-    0x4192cca2, 0x92127aae,
-  0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
-    0x417d35cb, 0x92059cb8,
-  0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
-    0x41679c6f, 0x91f8c300,
-  0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
-    0x4152008c, 0x91ebed85,
-  0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
-    0x413c6225, 0x91df1c49,
-  0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
-    0x4126c13a, 0x91d24f4c,
-  0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
-    0x41111dcc, 0x91c5868e,
-  0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
-    0x40fb77dc, 0x91b8c210,
-  0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
-    0x40e5cf6a, 0x91ac01d2,
-  0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
-    0x40d02478, 0x919f45d6,
-  0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
-    0x40ba7706, 0x91928e1a,
-  0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
-    0x40a4c716, 0x9185daa1,
-  0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
-    0x408f14a7, 0x91792b6a,
-  0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
-    0x40795fbc, 0x916c8076,
-  0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
-    0x4063a854, 0x915fd9c5,
-  0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
-    0x404dee70, 0x91533758,
-  0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
-    0x40383212, 0x9146992f,
-  0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
-    0x4022733a, 0x9139ff4b,
-  0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
-    0x400cb1e9, 0x912d69ad,
-  0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
-    0x3ff6ee1f, 0x9120d854,
-  0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
-    0x3fe127df, 0x91144b41,
-  0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
-    0x3fcb5f28, 0x9107c276,
-  0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
-    0x3fb593fb, 0x90fb3df1,
-  0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
-    0x3f9fc65a, 0x90eebdb4,
-  0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
-    0x3f89f645, 0x90e241bf,
-  0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
-    0x3f7423bc, 0x90d5ca13,
-  0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
-    0x3f5e4ec2, 0x90c956b1,
-  0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
-    0x3f487755, 0x90bce797,
-  0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
-    0x3f329d79, 0x90b07cc8,
-  0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
-    0x3f1cc12c, 0x90a41644,
-  0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
-    0x3f06e271, 0x9097b40a,
-  0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
-    0x3ef10148, 0x908b561c,
-  0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
-    0x3edb1db1, 0x907efc7a,
-  0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
-    0x3ec537ae, 0x9072a725,
-  0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
-    0x3eaf4f40, 0x9066561d,
-  0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
-    0x3e996467, 0x905a0962,
-  0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
-    0x3e837724, 0x904dc0f5,
-  0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
-    0x3e6d8778, 0x90417cd6,
-  0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
-    0x3e579564, 0x90353d06,
-  0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
-    0x3e41a0e8, 0x90290186,
-  0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
-    0x3e2baa07, 0x901cca55,
-  0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
-    0x3e15b0bf, 0x90109775,
-  0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
-    0x3dffb513, 0x900468e5,
-  0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
-    0x3de9b703, 0x8ff83ea7,
-  0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
-    0x3dd3b690, 0x8fec18ba,
-  0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
-    0x3dbdb3ba, 0x8fdff720,
-  0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
-    0x3da7ae84, 0x8fd3d9d8,
-  0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
-    0x3d91a6ed, 0x8fc7c0e3,
-  0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
-    0x3d7b9cf6, 0x8fbbac42,
-  0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
-    0x3d6590a0, 0x8faf9bf5,
-  0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
-    0x3d4f81ec, 0x8fa38ffc,
-  0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
-    0x3d3970dc, 0x8f978859,
-  0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
-    0x3d235d6f, 0x8f8b850a,
-  0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
-    0x3d0d47a6, 0x8f7f8612,
-  0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
-    0x3cf72f83, 0x8f738b70,
-  0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
-    0x3ce11507, 0x8f679525,
-  0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
-    0x3ccaf831, 0x8f5ba331,
-  0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
-    0x3cb4d904, 0x8f4fb595,
-  0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
-    0x3c9eb77f, 0x8f43cc50,
-  0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
-    0x3c8893a4, 0x8f37e765,
-  0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
-    0x3c726d73, 0x8f2c06d3,
-  0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
-    0x3c5c44ee, 0x8f202a9a,
-  0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
-    0x3c461a16, 0x8f1452bb,
-  0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
-    0x3c2fecea, 0x8f087f37,
-  0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
-    0x3c19bd6c, 0x8efcb00e,
-  0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
-    0x3c038b9e, 0x8ef0e540,
-  0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
-    0x3bed577e, 0x8ee51ece,
-  0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
-    0x3bd72110, 0x8ed95cb8,
-  0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
-    0x3bc0e853, 0x8ecd9eff,
-  0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
-    0x3baaad48, 0x8ec1e5a4,
-  0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
-    0x3b946ff0, 0x8eb630a6,
-  0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
-    0x3b7e304c, 0x8eaa8006,
-  0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
-    0x3b67ee5d, 0x8e9ed3c4,
-  0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
-    0x3b51aa24, 0x8e932be2,
-  0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
-    0x3b3b63a1, 0x8e87885f,
-  0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
-    0x3b251ad6, 0x8e7be93c,
-  0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
-    0x3b0ecfc3, 0x8e704e79,
-  0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
-    0x3af88269, 0x8e64b817,
-  0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
-    0x3ae232c9, 0x8e592617,
-  0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
-    0x3acbe0e3, 0x8e4d9878,
-  0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
-    0x3ab58cba, 0x8e420f3b,
-  0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
-    0x3a9f364d, 0x8e368a61,
-  0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
-    0x3a88dd9d, 0x8e2b09e9,
-  0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
-    0x3a7282ac, 0x8e1f8dd6,
-  0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
-    0x3a5c257a, 0x8e141626,
-  0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
-    0x3a45c608, 0x8e08a2db,
-  0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
-    0x3a2f6457, 0x8dfd33f4,
-  0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
-    0x3a190068, 0x8df1c973,
-  0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
-    0x3a029a3b, 0x8de66357,
-  0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
-    0x39ec31d1, 0x8ddb01a1,
-  0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
-    0x39d5c72c, 0x8dcfa452,
-  0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
-    0x39bf5a4d, 0x8dc44b6a,
-  0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
-    0x39a8eb33, 0x8db8f6ea,
-  0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
-    0x399279e0, 0x8dada6d1,
-  0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
-    0x397c0655, 0x8da25b21,
-  0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
-    0x39659092, 0x8d9713d9,
-  0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
-    0x394f1899, 0x8d8bd0fb,
-  0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
-    0x39389e6b, 0x8d809286,
-  0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
-    0x39222208, 0x8d75587b,
-  0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
-    0x390ba371, 0x8d6a22db,
-  0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
-    0x38f522a6, 0x8d5ef1a5,
-  0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
-    0x38de9faa, 0x8d53c4db,
-  0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
-    0x38c81a7c, 0x8d489c7d,
-  0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
-    0x38b1931e, 0x8d3d788b,
-  0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
-    0x389b0991, 0x8d325905,
-  0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
-    0x38847dd5, 0x8d273ded,
-  0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
-    0x386defeb, 0x8d1c2742,
-  0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
-    0x38575fd4, 0x8d111505,
-  0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
-    0x3840cd90, 0x8d060737,
-  0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
-    0x382a3922, 0x8cfafdd7,
-  0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
-    0x3813a28a, 0x8ceff8e6,
-  0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
-    0x37fd09c8, 0x8ce4f865,
-  0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
-    0x37e66edd, 0x8cd9fc54,
-  0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
-    0x37cfd1cb, 0x8ccf04b3,
-  0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
-    0x37b93292, 0x8cc41184,
-  0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
-    0x37a29132, 0x8cb922c6,
-  0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
-    0x378bedae, 0x8cae3879,
-  0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
-    0x37754806, 0x8ca3529f,
-  0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
-    0x375ea03a, 0x8c987137,
-  0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
-    0x3747f64c, 0x8c8d9442,
-  0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
-    0x37314a3c, 0x8c82bbc0,
-  0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
-    0x371a9c0b, 0x8c77e7b3,
-  0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
-    0x3703ebbb, 0x8c6d181a,
-  0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
-    0x36ed394b, 0x8c624cf5,
-  0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
-    0x36d684be, 0x8c578645,
-  0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
-    0x36bfce13, 0x8c4cc40b,
-  0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
-    0x36a9154c, 0x8c420647,
-  0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
-    0x36925a69, 0x8c374cf9,
-  0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
-    0x367b9d6c, 0x8c2c9822,
-  0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
-    0x3664de55, 0x8c21e7c2,
-  0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
-    0x364e1d25, 0x8c173bda,
-  0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
-    0x363759de, 0x8c0c9469,
-  0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
-    0x3620947f, 0x8c01f171,
-  0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
-    0x3609cd0a, 0x8bf752f2,
-  0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
-    0x35f3037f, 0x8becb8ec,
-  0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
-    0x35dc37e0, 0x8be22360,
-  0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
-    0x35c56a2e, 0x8bd7924d,
-  0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
-    0x35ae9a69, 0x8bcd05b5,
-  0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
-    0x3597c892, 0x8bc27d98,
-  0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
-    0x3580f4aa, 0x8bb7f9f6,
-  0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
-    0x356a1eb2, 0x8bad7ad0,
-  0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
-    0x355346ab, 0x8ba30026,
-  0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
-    0x353c6c95, 0x8b9889f8,
-  0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
-    0x35259073, 0x8b8e1848,
-  0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
-    0x350eb243, 0x8b83ab14,
-  0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
-    0x34f7d208, 0x8b79425e,
-  0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
-    0x34e0efc2, 0x8b6ede26,
-  0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
-    0x34ca0b73, 0x8b647e6d,
-  0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
-    0x34b3251a, 0x8b5a2333,
-  0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
-    0x349c3cb9, 0x8b4fcc77,
-  0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
-    0x34855251, 0x8b457a3c,
-  0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
-    0x346e65e3, 0x8b3b2c80,
-  0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
-    0x3457776f, 0x8b30e345,
-  0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
-    0x344086f6, 0x8b269e8b,
-  0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
-    0x3429947a, 0x8b1c5e52,
-  0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
-    0x34129ffb, 0x8b12229b,
-  0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
-    0x33fba97a, 0x8b07eb66,
-  0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
-    0x33e4b0f8, 0x8afdb8b3,
-  0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
-    0x33cdb676, 0x8af38a83,
-  0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
-    0x33b6b9f4, 0x8ae960d6,
-  0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
-    0x339fbb74, 0x8adf3bad,
-  0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
-    0x3388baf7, 0x8ad51b08,
-  0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
-    0x3371b87d, 0x8acafee8,
-  0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
-    0x335ab407, 0x8ac0e74c,
-  0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
-    0x3343ad97, 0x8ab6d435,
-  0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
-    0x332ca52c, 0x8aacc5a4,
-  0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
-    0x33159ac8, 0x8aa2bb99,
-  0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
-    0x32fe8e6d, 0x8a98b614,
-  0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
-    0x32e7801a, 0x8a8eb516,
-  0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
-    0x32d06fd0, 0x8a84b89e,
-  0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
-    0x32b95d91, 0x8a7ac0af,
-  0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
-    0x32a2495d, 0x8a70cd47,
-  0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
-    0x328b3336, 0x8a66de68,
-  0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
-    0x32741b1c, 0x8a5cf411,
-  0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
-    0x325d0110, 0x8a530e43,
-  0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
-    0x3245e512, 0x8a492cff,
-  0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
-    0x322ec725, 0x8a3f5045,
-  0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
-    0x3217a748, 0x8a357814,
-  0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
-    0x3200857d, 0x8a2ba46e,
-  0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
-    0x31e961c5, 0x8a21d554,
-  0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
-    0x31d23c1f, 0x8a180ac4,
-  0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
-    0x31bb148f, 0x8a0e44c0,
-  0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
-    0x31a3eb13, 0x8a048348,
-  0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
-    0x318cbfad, 0x89fac65d,
-  0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
-    0x3175925e, 0x89f10dff,
-  0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
-    0x315e6328, 0x89e75a2d,
-  0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
-    0x31473209, 0x89ddaae9,
-  0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
-    0x312fff05, 0x89d40033,
-  0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
-    0x3118ca1b, 0x89ca5a0c,
-  0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
-    0x3101934d, 0x89c0b873,
-  0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
-    0x30ea5a9a, 0x89b71b69,
-  0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
-    0x30d32006, 0x89ad82ef,
-  0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
-    0x30bbe38f, 0x89a3ef04,
-  0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
-    0x30a4a537, 0x899a5faa,
-  0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
-    0x308d64ff, 0x8990d4e0,
-  0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
-    0x307622e8, 0x89874ea7,
-  0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
-    0x305edef3, 0x897dccff,
-  0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
-    0x30479920, 0x89744fe9,
-  0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
-    0x30305171, 0x896ad765,
-  0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
-    0x301907e6, 0x89616373,
-  0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
-    0x3001bc80, 0x8957f414,
-  0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
-    0x2fea6f41, 0x894e8948,
-  0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
-    0x2fd32028, 0x89452310,
-  0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
-    0x2fbbcf38, 0x893bc16b,
-  0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
-    0x2fa47c71, 0x8932645b,
-  0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
-    0x2f8d27d3, 0x89290bdf,
-  0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
-    0x2f75d160, 0x891fb7f8,
-  0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
-    0x2f5e7919, 0x891668a6,
-  0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
-    0x2f471efe, 0x890d1dea,
-  0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
-    0x2f2fc310, 0x8903d7c4,
-  0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
-    0x2f186551, 0x88fa9634,
-  0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
-    0x2f0105c1, 0x88f1593b,
-  0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
-    0x2ee9a461, 0x88e820d9,
-  0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
-    0x2ed24132, 0x88deed0e,
-  0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
-    0x2ebadc35, 0x88d5bddb,
-  0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
-    0x2ea3756b, 0x88cc9340,
-  0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
-    0x2e8c0cd4, 0x88c36d3e,
-  0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
-    0x2e74a272, 0x88ba4bd4,
-  0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
-    0x2e5d3646, 0x88b12f04,
-  0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
-    0x2e45c850, 0x88a816cd,
-  0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
-    0x2e2e5891, 0x889f0330,
-  0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
-    0x2e16e70b, 0x8895f42d,
-  0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
-    0x2dff73bd, 0x888ce9c5,
-  0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
-    0x2de7feaa, 0x8883e3f8,
-  0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
-    0x2dd087d1, 0x887ae2c6,
-  0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
-    0x2db90f35, 0x8871e630,
-  0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
-    0x2da194d5, 0x8868ee35,
-  0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
-    0x2d8a18b3, 0x885ffad7,
-  0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
-    0x2d729acf, 0x88570c16,
-  0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
-    0x2d5b1b2b, 0x884e21f1,
-  0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
-    0x2d4399c7, 0x88453c6a,
-  0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
-    0x2d2c16a4, 0x883c5b81,
-  0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
-    0x2d1491c4, 0x88337f35,
-  0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
-    0x2cfd0b26, 0x882aa788,
-  0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
-    0x2ce582cd, 0x8821d47a,
-  0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
-    0x2ccdf8b8, 0x8819060a,
-  0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
-    0x2cb66ce9, 0x88103c3b,
-  0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
-    0x2c9edf61, 0x8807770a,
-  0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
-    0x2c875021, 0x87feb67a,
-  0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
-    0x2c6fbf29, 0x87f5fa8b,
-  0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
-    0x2c582c7b, 0x87ed433c,
-  0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
-    0x2c409816, 0x87e4908e,
-  0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
-    0x2c2901fd, 0x87dbe281,
-  0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
-    0x2c116a31, 0x87d33916,
-  0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
-    0x2bf9d0b1, 0x87ca944e,
-  0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
-    0x2be2357f, 0x87c1f427,
-  0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
-    0x2bca989d, 0x87b958a4,
-  0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
-    0x2bb2fa0a, 0x87b0c1c4,
-  0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
-    0x2b9b59c7, 0x87a82f87,
-  0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
-    0x2b83b7d7, 0x879fa1ed,
-  0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
-    0x2b6c1438, 0x879718f8,
-  0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
-    0x2b546eee, 0x878e94a7,
-  0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
-    0x2b3cc7f7, 0x878614fb,
-  0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
-    0x2b251f56, 0x877d99f4,
-  0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
-    0x2b0d750b, 0x87752392,
-  0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
-    0x2af5c917, 0x876cb1d6,
-  0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
-    0x2ade1b7c, 0x876444c1,
-  0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
-    0x2ac66c39, 0x875bdc51,
-  0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
-    0x2aaebb50, 0x87537888,
-  0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
-    0x2a9708c1, 0x874b1966,
-  0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
-    0x2a7f548e, 0x8742beec,
-  0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
-    0x2a679eb8, 0x873a6919,
-  0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
-    0x2a4fe740, 0x873217ee,
-  0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
-    0x2a382e25, 0x8729cb6b,
-  0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
-    0x2a20736a, 0x87218391,
-  0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
-    0x2a08b710, 0x87194060,
-  0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
-    0x29f0f916, 0x871101d8,
-  0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
-    0x29d9397f, 0x8708c7fa,
-  0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
-    0x29c1784a, 0x870092c5,
-  0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
-    0x29a9b579, 0x86f8623b,
-  0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
-    0x2991f10e, 0x86f0365c,
-  0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
-    0x297a2b07, 0x86e80f27,
-  0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
-    0x29626368, 0x86dfec9d,
-  0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
-    0x294a9a30, 0x86d7cebf,
-  0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
-    0x2932cf60, 0x86cfb58c,
-  0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
-    0x291b02fa, 0x86c7a106,
-  0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
-    0x290334ff, 0x86bf912c,
-  0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
-    0x28eb656e, 0x86b785ff,
-  0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
-    0x28d3944a, 0x86af7f7e,
-  0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
-    0x28bbc192, 0x86a77dab,
-  0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
-    0x28a3ed49, 0x869f8086,
-  0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
-    0x288c176e, 0x8697880f,
-  0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
-    0x28744004, 0x868f9445,
-  0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
-    0x285c670a, 0x8687a52b,
-  0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
-    0x28448c81, 0x867fbabf,
-  0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
-    0x282cb06c, 0x8677d503,
-  0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
-    0x2814d2c9, 0x866ff3f6,
-  0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
-    0x27fcf39c, 0x86681798,
-  0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
-    0x27e512e3, 0x86603feb,
-  0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
-    0x27cd30a1, 0x86586cee,
-  0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
-    0x27b54cd6, 0x86509ea2,
-  0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
-    0x279d6783, 0x8648d507,
-  0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
-    0x278580a9, 0x8641101d,
-  0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
-    0x276d9849, 0x86394fe5,
-  0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
-    0x2755ae64, 0x8631945e,
-  0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
-    0x273dc2fa, 0x8629dd8a,
-  0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
-    0x2725d60e, 0x86222b68,
-  0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
-    0x270de79f, 0x861a7df9,
-  0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
-    0x26f5f7ae, 0x8612d53d,
-  0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
-    0x26de063d, 0x860b3135,
-  0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
-    0x26c6134d, 0x860391e0,
-  0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
-    0x26ae1edd, 0x85fbf73f,
-  0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
-    0x269628f0, 0x85f46152,
-  0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
-    0x267e3186, 0x85ecd01a,
-  0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
-    0x266638a1, 0x85e54397,
-  0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
-    0x264e3e40, 0x85ddbbc9,
-  0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
-    0x26364265, 0x85d638b0,
-  0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
-    0x261e4511, 0x85ceba4d,
-  0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
-    0x26064645, 0x85c740a0,
-  0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
-    0x25ee4601, 0x85bfcba9,
-  0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
-    0x25d64447, 0x85b85b68,
-  0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
-    0x25be4118, 0x85b0efdf,
-  0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
-    0x25a63c74, 0x85a9890d,
-  0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
-    0x258e365d, 0x85a226f2,
-  0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
-    0x25762ed3, 0x859ac98f,
-  0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
-    0x255e25d7, 0x859370e4,
-  0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
-    0x25461b6b, 0x858c1cf1,
-  0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
-    0x252e0f8e, 0x8584cdb7,
-  0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
-    0x25160243, 0x857d8335,
-  0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
-    0x24fdf389, 0x85763d6d,
-  0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
-    0x24e5e363, 0x856efc5e,
-  0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
-    0x24cdd1d0, 0x8567c009,
-  0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
-    0x24b5bed2, 0x8560886d,
-  0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
-    0x249daa6a, 0x8559558c,
-  0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
-    0x24859498, 0x85522766,
-  0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
-    0x246d7d5e, 0x854afdfa,
-  0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
-    0x245564bd, 0x8543d949,
-  0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
-    0x243d4ab4, 0x853cb954,
-  0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
-    0x24252f47, 0x85359e1a,
-  0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
-    0x240d1274, 0x852e879d,
-  0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
-    0x23f4f43e, 0x852775db,
-  0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
-    0x23dcd4a4, 0x852068d6,
-  0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
-    0x23c4b3a9, 0x8519608d,
-  0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
-    0x23ac914d, 0x85125d02,
-  0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
-    0x23946d90, 0x850b5e34,
-  0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
-    0x237c4875, 0x85046423,
-  0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
-    0x236421fb, 0x84fd6ed0,
-  0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
-    0x234bfa24, 0x84f67e3b,
-  0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
-    0x2333d0f1, 0x84ef9265,
-  0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
-    0x231ba662, 0x84e8ab4d,
-  0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
-    0x23037a78, 0x84e1c8f3,
-  0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
-    0x22eb4d36, 0x84daeb5a,
-  0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
-    0x22d31e9a, 0x84d4127f,
-  0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
-    0x22baeea7, 0x84cd3e64,
-  0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
-    0x22a2bd5d, 0x84c66f09,
-  0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
-    0x228a8abd, 0x84bfa46e,
-  0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
-    0x227256c8, 0x84b8de94,
-  0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
-    0x225a217f, 0x84b21d7a,
-  0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
-    0x2241eae3, 0x84ab6122,
-  0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
-    0x2229b2f6, 0x84a4a98a,
-  0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
-    0x221179b7, 0x849df6b4,
-  0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
-    0x21f93f27, 0x849748a0,
-  0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
-    0x21e10349, 0x84909f4e,
-  0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
-    0x21c8c61c, 0x8489fabe,
-  0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
-    0x21b087a1, 0x84835af0,
-  0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
-    0x219847da, 0x847cbfe5,
-  0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
-    0x218006c8, 0x8476299e,
-  0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
-    0x2167c46b, 0x846f9819,
-  0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
-    0x214f80c4, 0x84690b58,
-  0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
-    0x21373bd4, 0x8462835b,
-  0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
-    0x211ef59d, 0x845c0022,
-  0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
-    0x2106ae1e, 0x845581ad,
-  0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
-    0x20ee655a, 0x844f07fd,
-  0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
-    0x20d61b51, 0x84489311,
-  0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
-    0x20bdd003, 0x844222eb,
-  0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
-    0x20a58373, 0x843bb78a,
-  0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
-    0x208d35a0, 0x843550ee,
-  0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
-    0x2074e68c, 0x842eef18,
-  0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
-    0x205c9638, 0x84289209,
-  0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
-    0x204444a4, 0x842239bf,
-  0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
-    0x202bf1d2, 0x841be63c,
-  0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
-    0x20139dc2, 0x84159780,
-  0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
-    0x1ffb4876, 0x840f4d8a,
-  0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
-    0x1fe2f1ee, 0x8409085c,
-  0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
-    0x1fca9a2b, 0x8402c7f6,
-  0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
-    0x1fb2412f, 0x83fc8c57,
-  0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
-    0x1f99e6fa, 0x83f65580,
-  0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
-    0x1f818b8d, 0x83f02371,
-  0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
-    0x1f692ee9, 0x83e9f62b,
-  0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
-    0x1f50d10e, 0x83e3cdad,
-  0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
-    0x1f3871ff, 0x83dda9f9,
-  0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
-    0x1f2011bc, 0x83d78b0d,
-  0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
-    0x1f07b045, 0x83d170eb,
-  0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
-    0x1eef4d9d, 0x83cb5b93,
-  0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
-    0x1ed6e9c3, 0x83c54b04,
-  0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
-    0x1ebe84b8, 0x83bf3f3f,
-  0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
-    0x1ea61e7e, 0x83b93845,
-  0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
-    0x1e8db716, 0x83b33616,
-  0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
-    0x1e754e80, 0x83ad38b1,
-  0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
-    0x1e5ce4be, 0x83a74017,
-  0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
-    0x1e4479cf, 0x83a14c48,
-  0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
-    0x1e2c0db6, 0x839b5d45,
-  0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
-    0x1e13a074, 0x8395730e,
-  0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
-    0x1dfb3208, 0x838f8da2,
-  0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
-    0x1de2c275, 0x8389ad03,
-  0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
-    0x1dca51ba, 0x8383d130,
-  0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
-    0x1db1dfda, 0x837dfa2a,
-  0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
-    0x1d996cd4, 0x837827f0,
-  0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
-    0x1d80f8ab, 0x83725a84,
-  0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
-    0x1d68835e, 0x836c91e5,
-  0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
-    0x1d500cef, 0x8366ce14,
-  0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
-    0x1d37955e, 0x83610f10,
-  0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
-    0x1d1f1cae, 0x835b54da,
-  0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
-    0x1d06a2dd, 0x83559f72,
-  0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
-    0x1cee27ef, 0x834feed9,
-  0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
-    0x1cd5abe3, 0x834a430e,
-  0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
-    0x1cbd2eba, 0x83449c12,
-  0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
-    0x1ca4b075, 0x833ef9e6,
-  0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
-    0x1c8c3116, 0x83395c88,
-  0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
-    0x1c73b09d, 0x8333c3fa,
-  0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
-    0x1c5b2f0c, 0x832e303c,
-  0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
-    0x1c42ac62, 0x8328a14d,
-  0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
-    0x1c2a28a2, 0x8323172f,
-  0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
-    0x1c11a3cb, 0x831d91e1,
-  0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
-    0x1bf91de0, 0x83181164,
-  0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
-    0x1be096e0, 0x831295b7,
-  0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
-    0x1bc80ece, 0x830d1edc,
-  0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
-    0x1baf85a9, 0x8307acd1,
-  0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
-    0x1b96fb73, 0x83023f98,
-  0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
-    0x1b7e702c, 0x82fcd731,
-  0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
-    0x1b65e3d7, 0x82f7739c,
-  0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
-    0x1b4d5672, 0x82f214d8,
-  0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
-    0x1b34c801, 0x82ecbae7,
-  0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
-    0x1b1c3883, 0x82e765c8,
-  0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
-    0x1b03a7f9, 0x82e2157c,
-  0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
-    0x1aeb1665, 0x82dcca02,
-  0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
-    0x1ad283c7, 0x82d7835c,
-  0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
-    0x1ab9f020, 0x82d24189,
-  0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
-    0x1aa15b71, 0x82cd048a,
-  0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
-    0x1a88c5bc, 0x82c7cc5e,
-  0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
-    0x1a702f01, 0x82c29906,
-  0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
-    0x1a579741, 0x82bd6a82,
-  0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
-    0x1a3efe7c, 0x82b840d2,
-  0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
-    0x1a2664b5, 0x82b31bf7,
-  0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
-    0x1a0dc9ec, 0x82adfbf0,
-  0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
-    0x19f52e22, 0x82a8e0bf,
-  0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
-    0x19dc9157, 0x82a3ca62,
-  0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
-    0x19c3f38d, 0x829eb8db,
-  0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
-    0x19ab54c5, 0x8299ac29,
-  0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
-    0x1992b4ff, 0x8294a44c,
-  0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
-    0x197a143e, 0x828fa146,
-  0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
-    0x19617280, 0x828aa316,
-  0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
-    0x1948cfc8, 0x8285a9bb,
-  0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
-    0x19302c17, 0x8280b538,
-  0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
-    0x1917876d, 0x827bc58a,
-  0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
-    0x18fee1cb, 0x8276dab4,
-  0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
-    0x18e63b33, 0x8271f4b5,
-  0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
-    0x18cd93a5, 0x826d138d,
-  0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
-    0x18b4eb22, 0x8268373c,
-  0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
-    0x189c41ab, 0x82635fc2,
-  0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
-    0x18839742, 0x825e8d21,
-  0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
-    0x186aebe6, 0x8259bf57,
-  0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
-    0x18523f9a, 0x8254f666,
-  0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
-    0x1839925d, 0x8250324d,
-  0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
-    0x1820e431, 0x824b730c,
-  0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
-    0x18083518, 0x8246b8a4,
-  0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
-    0x17ef8511, 0x82420315,
-  0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
-    0x17d6d41d, 0x823d525e,
-  0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
-    0x17be223f, 0x8238a681,
-  0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
-    0x17a56f76, 0x8233ff7e,
-  0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
-    0x178cbbc4, 0x822f5d54,
-  0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
-    0x17740729, 0x822ac004,
-  0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
-    0x175b51a7, 0x8226278d,
-  0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
-    0x17429b3e, 0x822193f1,
-  0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
-    0x1729e3f0, 0x821d052f,
-  0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
-    0x17112bbd, 0x82187b47,
-  0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
-    0x16f872a7, 0x8213f63a,
-  0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
-    0x16dfb8ae, 0x820f7608,
-  0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
-    0x16c6fdd3, 0x820afab1,
-  0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
-    0x16ae4217, 0x82068435,
-  0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
-    0x1695857b, 0x82021294,
-  0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
-    0x167cc801, 0x81fda5cf,
-  0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
-    0x166409a8, 0x81f93de6,
-  0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
-    0x164b4a73, 0x81f4dad8,
-  0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
-    0x16328a61, 0x81f07ca6,
-  0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
-    0x1619c975, 0x81ec2351,
-  0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
-    0x160107ae, 0x81e7ced8,
-  0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
-    0x15e8450e, 0x81e37f3b,
-  0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
-    0x15cf8196, 0x81df347b,
-  0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
-    0x15b6bd47, 0x81daee98,
-  0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
-    0x159df821, 0x81d6ad92,
-  0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
-    0x15853226, 0x81d27169,
-  0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
-    0x156c6b57, 0x81ce3a1d,
-  0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
-    0x1553a3b4, 0x81ca07af,
-  0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
-    0x153adb3f, 0x81c5da1e,
-  0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
-    0x152211f8, 0x81c1b16b,
-  0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
-    0x150947e1, 0x81bd8d97,
-  0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
-    0x14f07cf9, 0x81b96ea0,
-  0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
-    0x14d7b144, 0x81b55488,
-  0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
-    0x14bee4c0, 0x81b13f4e,
-  0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
-    0x14a61770, 0x81ad2ef2,
-  0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
-    0x148d4954, 0x81a92376,
-  0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
-    0x14747a6d, 0x81a51cd8,
-  0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
-    0x145baabd, 0x81a11b1a,
-  0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
-    0x1442da43, 0x819d1e3a,
-  0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
-    0x142a0902, 0x8199263a,
-  0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
-    0x141136f9, 0x8195331a,
-  0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
-    0x13f8642a, 0x819144d9,
-  0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
-    0x13df9097, 0x818d5b78,
-  0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
-    0x13c6bc3f, 0x818976f8,
-  0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
-    0x13ade724, 0x81859757,
-  0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
-    0x13951146, 0x8181bc96,
-  0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
-    0x137c3aa8, 0x817de6b6,
-  0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
-    0x13636349, 0x817a15b7,
-  0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
-    0x134a8b2b, 0x81764998,
-  0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
-    0x1331b24e, 0x8172825a,
-  0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
-    0x1318d8b4, 0x816ebffe,
-  0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
-    0x12fffe5d, 0x816b0282,
-  0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
-    0x12e7234b, 0x816749e8,
-  0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
-    0x12ce477f, 0x8163962f,
-  0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
-    0x12b56af9, 0x815fe758,
-  0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
-    0x129c8dba, 0x815c3d62,
-  0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
-    0x1283afc3, 0x8158984e,
-  0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
-    0x126ad116, 0x8154f81d,
-  0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
-    0x1251f1b3, 0x81515ccd,
-  0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
-    0x1239119b, 0x814dc660,
-  0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
-    0x122030cf, 0x814a34d6,
-  0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
-    0x12074f50, 0x8146a82e,
-  0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
-    0x11ee6d20, 0x81432068,
-  0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
-    0x11d58a3e, 0x813f9d86,
-  0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
-    0x11bca6ad, 0x813c1f86,
-  0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
-    0x11a3c26c, 0x8138a66a,
-  0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
-    0x118add7d, 0x81353230,
-  0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
-    0x1171f7e2, 0x8131c2db,
-  0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
-    0x1159119a, 0x812e5868,
-  0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
-    0x11402aa6, 0x812af2da,
-  0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
-    0x11274309, 0x8127922f,
-  0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
-    0x110e5ac2, 0x81243668,
-  0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
-    0x10f571d3, 0x8120df85,
-  0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
-    0x10dc883c, 0x811d8d86,
-  0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
-    0x10c39dff, 0x811a406c,
-  0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
-    0x10aab31d, 0x8116f836,
-  0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
-    0x1091c796, 0x8113b4e5,
-  0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
-    0x1078db6c, 0x81107678,
-  0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
-    0x105fee9f, 0x810d3cf0,
-  0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
-    0x10470130, 0x810a084d,
-  0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
-    0x102e1321, 0x8106d88f,
-  0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
-    0x10152472, 0x8103adb6,
-  0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
-    0xffc3524, 0x810087c3,
-  0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
-    0xfe34539, 0x80fd66b5,
-  0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
-    0xfca54b1, 0x80fa4a8c,
-  0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
-    0xfb1638d, 0x80f73349,
-  0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
-    0xf9871ce, 0x80f420ec,
-  0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
-    0xf7f7f75, 0x80f11375,
-  0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
-    0xf668c83, 0x80ee0ae4,
-  0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
-    0xf4d98f9, 0x80eb0739,
-  0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
-    0xf34a4d8, 0x80e80874,
-  0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
-    0xf1bb021, 0x80e50e96,
-  0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
-    0xf02bad5, 0x80e2199e,
-  0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
-    0xee9c4f5, 0x80df298c,
-  0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
-    0xed0ce82, 0x80dc3e62,
-  0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
-    0xeb7d77c, 0x80d9581e,
-  0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
-    0xe9edfe5, 0x80d676c1,
-  0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
-    0xe85e7be, 0x80d39a4b,
-  0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
-    0xe6cef07, 0x80d0c2bc,
-  0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
-    0xe53f5c2, 0x80cdf015,
-  0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
-    0xe3afbf0, 0x80cb2255,
-  0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
-    0xe220191, 0x80c8597c,
-  0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
-    0xe0906a7, 0x80c5958b,
-  0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
-    0xdf00b32, 0x80c2d682,
-  0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
-    0xdd70f34, 0x80c01c60,
-  0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
-    0xdbe12ad, 0x80bd6727,
-  0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
-    0xda5159f, 0x80bab6d5,
-  0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
-    0xd8c1809, 0x80b80b6c,
-  0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
-    0xd7319ee, 0x80b564ea,
-  0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
-    0xd5a1b4f, 0x80b2c351,
-  0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
-    0xd411c2b, 0x80b026a1,
-  0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
-    0xd281c85, 0x80ad8ed9,
-  0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
-    0xd0f1c5d, 0x80aafbf9,
-  0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
-    0xcf61bb4, 0x80a86e03,
-  0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
-    0xcdd1a8b, 0x80a5e4f5,
-  0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
-    0xcc418e3, 0x80a360d0,
-  0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
-    0xcab16bd, 0x80a0e194,
-  0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
-    0xc92141a, 0x809e6741,
-  0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
-    0xc7910fb, 0x809bf1d7,
-  0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
-    0xc600d61, 0x80998157,
-  0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
-    0xc47094d, 0x809715c0,
-  0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
-    0xc2e04c0, 0x8094af13,
-  0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
-    0xc14ffba, 0x80924d4f,
-  0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
-    0xbfbfa3d, 0x808ff074,
-  0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
-    0xbe2f44a, 0x808d9884,
-  0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
-    0xbc9ede2, 0x808b457d,
-  0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
-    0xbb0e705, 0x8088f761,
-  0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
-    0xb97dfb5, 0x8086ae2e,
-  0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
-    0xb7ed7f2, 0x808469e5,
-  0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
-    0xb65cfbe, 0x80822a87,
-  0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
-    0xb4cc719, 0x807ff013,
-  0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
-    0xb33be05, 0x807dba89,
-  0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
-    0xb1ab483, 0x807b89ea,
-  0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
-    0xb01aa92, 0x80795e36,
-  0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
-    0xae8a036, 0x8077376c,
-  0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
-    0xacf956d, 0x8075158c,
-  0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
-    0xab68a3a, 0x8072f898,
-  0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
-    0xa9d7e9d, 0x8070e08e,
-  0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
-    0xa847297, 0x806ecd6f,
-  0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
-    0xa6b662a, 0x806cbf3c,
-  0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
-    0xa525955, 0x806ab5f3,
-  0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
-    0xa394c1b, 0x8068b196,
-  0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
-    0xa203e7c, 0x8066b224,
-  0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
-    0xa073079, 0x8064b79d,
-  0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
-    0x9ee2213, 0x8062c202,
-  0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
-    0x9d5134b, 0x8060d152,
-  0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
-    0x9bc0421, 0x805ee58e,
-  0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
-    0x9a2f498, 0x805cfeb5,
-  0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
-    0x989e4b0, 0x805b1cc8,
-  0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
-    0x970d46a, 0x80593fc7,
-  0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
-    0x957c3c6, 0x805767b2,
-  0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
-    0x93eb2c6, 0x80559489,
-  0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
-    0x925a16b, 0x8053c64c,
-  0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
-    0x90c8fb6, 0x8051fcfb,
-  0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
-    0x8f37da7, 0x80503896,
-  0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
-    0x8da6b40, 0x804e791d,
-  0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
-    0x8c15882, 0x804cbe90,
-  0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
-    0x8a8456d, 0x804b08f0,
-  0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
-    0x88f3203, 0x8049583d,
-  0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
-    0x8761e44, 0x8047ac75,
-  0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
-    0x85d0a32, 0x8046059b,
-  0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
-    0x843f5cd, 0x804463ad,
-  0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
-    0x82ae117, 0x8042c6ab,
-  0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
-    0x811cc10, 0x80412e96,
-  0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
-    0x7f8b6b9, 0x803f9b6f,
-  0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
-    0x7dfa114, 0x803e0d34,
-  0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
-    0x7c68b21, 0x803c83e5,
-  0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
-    0x7ad74e1, 0x803aff84,
-  0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
-    0x7945e56, 0x80398010,
-  0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
-    0x77b4780, 0x80380589,
-  0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
-    0x762305f, 0x80368fef,
-  0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
-    0x74918f6, 0x80351f43,
-  0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
-    0x7300145, 0x8033b383,
-  0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
-    0x716e94e, 0x80324cb1,
-  0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
-    0x6fdd110, 0x8030eacd,
-  0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
-    0x6e4b88d, 0x802f8dd5,
-  0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
-    0x6cb9fc6, 0x802e35cb,
-  0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
-    0x6b286bc, 0x802ce2af,
-  0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
-    0x6996d70, 0x802b9480,
-  0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
-    0x68053e3, 0x802a4b3f,
-  0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
-    0x6673a16, 0x802906ec,
-  0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
-    0x64e2009, 0x8027c786,
-  0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
-    0x63505be, 0x80268d0e,
-  0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
-    0x61beb36, 0x80255784,
-  0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
-    0x602d072, 0x802426e8,
-  0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
-    0x5e9b572, 0x8022fb3a,
-  0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
-    0x5d09a38, 0x8021d47a,
-  0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
-    0x5b77ec5, 0x8020b2a7,
-  0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
-    0x59e6319, 0x801f95c3,
-  0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
-    0x5854736, 0x801e7dcd,
-  0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
-    0x56c2b1c, 0x801d6ac5,
-  0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
-    0x5530ecd, 0x801c5cab,
-  0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
-    0x539f249, 0x801b537f,
-  0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
-    0x520d592, 0x801a4f42,
-  0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
-    0x507b8a8, 0x80194ff3,
-  0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
-    0x4ee9b8c, 0x80185592,
-  0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
-    0x4d57e40, 0x80176020,
-  0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
-    0x4bc60c4, 0x80166f9c,
-  0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
-    0x4a34319, 0x80158406,
-  0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
-    0x48a2540, 0x80149d5f,
-  0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
-    0x471073b, 0x8013bba7,
-  0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
-    0x457e90a, 0x8012dedd,
-  0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
-    0x43ecaae, 0x80120701,
-  0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
-    0x425ac28, 0x80113414,
-  0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
-    0x40c8d79, 0x80106616,
-  0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
-    0x3f36ea2, 0x800f9d07,
-  0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
-    0x3da4fa4, 0x800ed8e6,
-  0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
-    0x3c13080, 0x800e19b4,
-  0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
-    0x3a81137, 0x800d5f71,
-  0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
-    0x38ef1ca, 0x800caa1c,
-  0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
-    0x375d23a, 0x800bf9b7,
-  0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
-    0x35cb288, 0x800b4e40,
-  0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
-    0x34392b4, 0x800aa7b8,
-  0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
-    0x32a72c1, 0x800a061f,
-  0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
-    0x31152ae, 0x80096975,
-  0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
-    0x2f8327d, 0x8008d1ba,
-  0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
-    0x2df122e, 0x80083eed,
-  0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
-    0x2c5f1c3, 0x8007b110,
-  0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
-    0x2acd13d, 0x80072822,
-  0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
-    0x293b09c, 0x8006a423,
-  0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
-    0x27a8fe2, 0x80062513,
-  0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
-    0x2616f10, 0x8005aaf2,
-  0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
-    0x2484e26, 0x800535c0,
-  0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
-    0x22f2d25, 0x8004c57d,
-  0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
-    0x2160c0f, 0x80045a29,
-  0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
-    0x1fceae4, 0x8003f3c5,
-  0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
-    0x1e3c9a6, 0x8003924f,
-  0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
-    0x1caa855, 0x800335c9,
-  0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
-    0x1b186f3, 0x8002de32,
-  0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
-    0x198657f, 0x80028b8a,
-  0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
-    0x17f43fc, 0x80023dd2,
-  0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
-    0x166226a, 0x8001f508,
-  0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
-    0x14d00ca, 0x8001b12e,
-  0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
-    0x133df1e, 0x80017243,
-  0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
-    0x11abd66, 0x80013847,
-  0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
-    0x1019ba2, 0x8001033b,
-  0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
-    0x8000d31e,
-  0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
-    0x8000a7f0,
-  0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
-    0x800081b1,
-  0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
-    0x80006062,
-  0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
-    0x80004402,
-  0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
-    0x80002c91,
-  0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
-    0x80001a10,
-  0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
-    0x80000c7e,
-  0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
-    0x800003db,
-  0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
-    0x80000027,
-
-};
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-* \par    
-* Then converted to q31 format by multiplying with 2^31 and saturated if required.    
-*/
-
-
-static const q31_t cos_factorsQ31_128[128] = {
-  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
-  0x7f97cebd, 0x7f754e80,
-  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
-  0x7dfa98a8, 0x7db0fdf8,
-  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
-  0x7b26cb4f, 0x7ab6cba4,
-  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
-  0x77235f2d, 0x768e0ea6,
-  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
-  0x71fa3949, 0x71410805,
-  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
-  0x6bb812d1, 0x6adcc964,
-  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
-  0x646c59bf, 0x637114cc,
-  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
-  0x5c290acc, 0x5b1035cf,
-  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
-  0x53028518, 0x51ced46e,
-  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
-  0x490f57ee, 0x47c3c22f,
-  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
-  0x3e680b2c, 0x3d07c1d6,
-  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
-  0x3326e2c3, 0x31b54a5e,
-  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
-  0x27679df4, 0x25e845b6,
-  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
-  0x1b4732ef, 0x19bdcbf3,
-  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
-  0xee38766, 0xd53db92,
-  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
-  0xc90f88,
-};
-
-static const q31_t cos_factorsQ31_512[512] = {
-  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
-  0x7ff97c18, 0x7ff75370,
-  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
-  0x7fdf9508, 0x7fdaf519,
-  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
-  0x7fb1f5fc, 0x7faadf7c,
-  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
-  0x7f70a5fe, 0x7f671a05,
-  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
-  0x7f1baf1e, 0x7f0faf25,
-  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
-  0x7eb31e78, 0x7ea4ac58,
-  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
-  0x7e37042a, 0x7e26221f,
-  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
-  0x7da77359, 0x7d9423fc,
-  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
-  0x7d048228, 0x7ceec873,
-  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
-  0x7c4e49b7, 0x7c362904,
-  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
-  0x7b84e61f, 0x7b6a6227,
-  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
-  0x7aa8766f, 0x7a8b9348,
-  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
-  0x79b91ca4, 0x7999dec4,
-  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
-  0x78b6fda8, 0x789569df,
-  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
-  0x77a24148, 0x777e5cc3,
-  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
-  0x767b1231, 0x7654e279,
-  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
-  0x75419de7, 0x751928e0,
-  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
-  0x73f614c0, 0x73cb60a8,
-  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
-  0x7298a9dd, 0x726bbd48,
-  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
-  0x7129931f, 0x70fa74fc,
-  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
-  0x6fa90921, 0x6f77c0b3,
-  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
-  0x6e174730, 0x6de3dc11,
-  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
-  0x6c748b3f, 0x6c3f055d,
-  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
-  0x6ac115e2, 0x6a897d7d,
-  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
-  0x68fd2a3d, 0x68c387e9,
-  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
-  0x67290e02, 0x66ed6aa1,
-  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
-  0x6545095f, 0x65076e25,
-  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
-  0x635166f9, 0x6311dd64,
-  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
-  0x614e73da, 0x610d05b7,
-  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
-  0x5f3c7f6b, 0x5ef936d1,
-  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
-  0x5d1bdb65, 0x5cd6c2b5,
-  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
-  0x5aecdbc5, 0x5aa5fda5,
-  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
-  0x58afd6bd, 0x58673e1b,
-  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
-  0x566524aa, 0x561adcb9,
-  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
-  0x540d2005, 0x53c13439,
-  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
-  0x51a82555, 0x515aa162,
-  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
-  0x4f369320, 0x4ee782fb,
-  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
-  0x4cb8c9dd, 0x4c6839b7,
-  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
-  0x4a2f2be6, 0x49dd282a,
-  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
-  0x479a1d67, 0x4746b2bc,
-  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
-  0x44fa0450, 0x44a53f93,
-  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
-  0x424f4845, 0x41f93689,
-  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
-  0x3f9a5290, 0x3f430119,
-  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
-  0x3cdb8e09, 0x3c830a50,
-  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
-  0x3a136712, 0x39b9bebc,
-  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
-  0x37424b7b, 0x36e78c5b,
-  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
-  0x3468aa76, 0x340ce28b,
-  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
-  0x3186f487, 0x312a31f8,
-  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
-  0x2e9d9b70, 0x2e3fec8b,
-  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
-  0x2bad1221, 0x2b4e8558,
-  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
-  0x28b5cca5, 0x2856708d,
-  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
-  0x25b84012, 0x2558235f,
-  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
-  0x22b4e274, 0x225413f8,
-  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
-  0x1fac2abf, 0x1f4ab968,
-  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
-  0x1c9e90b8, 0x1c3c8b8c,
-  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
-  0x198c8ce7, 0x192a0304,
-  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
-  0x1676987f, 0x16139918,
-  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
-  0x135d2d53, 0x12f9c7aa,
-  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
-  0x1040c5bb, 0xfdd0926,
-  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
-  0xcbdd865,
-  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
-  0x99cb0a7,
-  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
-  0x67a0d76,
-  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
-  0x3566a96,
-  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
-  0x3243f5,
-};
-
-static const q31_t cos_factorsQ31_2048[2048] = {
-  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
-  0x7fff97c1, 0x7fff7536,
-  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
-  0x7ffdf93c, 0x7ffdaf37,
-  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
-  0x7ffb1ee9, 0x7ffaad6a,
-  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
-  0x7ff708ce, 0x7ff66fd7,
-  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
-  0x7ff1b6f6, 0x7ff0f688,
-  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
-  0x7feb296d, 0x7fea418b,
-  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
-  0x7fe36045, 0x7fe250ef,
-  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
-  0x7fda5b8f, 0x7fd924ca,
-  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
-  0x7fd01b63, 0x7fcebd31,
-  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
-  0x7fc49fda, 0x7fc31a3d,
-  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
-  0x7fb7e90f, 0x7fb63c0d,
-  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
-  0x7fa9f723, 0x7fa822bf,
-  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
-  0x7f9aca37, 0x7f98ce76,
-  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
-  0x7f8a6272, 0x7f883f58,
-  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
-  0x7f78bffb, 0x7f76758e,
-  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
-  0x7f65e2ff, 0x7f637144,
-  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
-  0x7f51cbab, 0x7f4f32a9,
-  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
-  0x7f3c7a31, 0x7f39b9ee,
-  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
-  0x7f25eec7, 0x7f230749,
-  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
-  0x7f0e29a3, 0x7f0b1af2,
-  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
-  0x7ef52b00, 0x7ef1f524,
-  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
-  0x7edaf31c, 0x7ed7961c,
-  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
-  0x7ebf8237, 0x7ebbfe1c,
-  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
-  0x7ea2d896, 0x7e9f2d68,
-  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
-  0x7e84f67e, 0x7e812447,
-  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
-  0x7e65dc3b, 0x7e61e303,
-  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
-  0x7e458a17, 0x7e4169e9,
-  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
-  0x7e240064, 0x7e1fb94a,
-  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
-  0x7e013f74, 0x7dfcd178,
-  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
-  0x7ddd479d, 0x7dd8b2ca,
-  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
-  0x7db81936, 0x7db35d98,
-  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
-  0x7d91b49e, 0x7d8cd240,
-  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
-  0x7d6a1a31, 0x7d65111f,
-  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
-  0x7d414a51, 0x7d3c1a98,
-  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
-  0x7d174564, 0x7d11ef11,
-  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
-  0x7cec0bd1, 0x7ce68ef0,
-  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
-  0x7cbf9e03, 0x7cb9faa2,
-  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
-  0x7c91fc66, 0x7c8c3294,
-  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
-  0x7c63276d, 0x7c5d3737,
-  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
-  0x7c331f8a, 0x7c2d08ff,
-  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
-  0x7c01e534, 0x7bfba863,
-  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
-  0x7bcf78e5, 0x7bc915dd,
-  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
-  0x7b9bdb18, 0x7b9551ea,
-  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
-  0x7b670c4d, 0x7b605d09,
-  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
-  0x7b310d07, 0x7b2a37bc,
-  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
-  0x7af9ddcb, 0x7af2e28b,
-  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
-  0x7ac17f20, 0x7aba5dfc,
-  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
-  0x7a87f192, 0x7a80aa9c,
-  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
-  0x7a4d35b0, 0x7a45c8f9,
-  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
-  0x7a114c09, 0x7a09b9a4,
-  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
-  0x79d43532, 0x79cc7d31,
-  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
-  0x7995f1c1, 0x798e1438,
-  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
-  0x79568250, 0x794e7f52,
-  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
-  0x7915e77c, 0x790dbf1d,
-  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
-  0x78d421e4, 0x78cbd437,
-  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
-  0x7891322a, 0x7888bf45,
-  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
-  0x784d18f4, 0x784480ea,
-  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
-  0x7807d6e9, 0x77ff19d1,
-  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
-  0x77c16cb4, 0x77b88aa3,
-  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
-  0x7779db03, 0x7770d40f,
-  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
-  0x77312287, 0x7727f6c6,
-  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
-  0x76e743f4, 0x76ddf37c,
-  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
-  0x769c3ffe, 0x7692cae8,
-  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
-  0x76501760, 0x76467dc2,
-  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
-  0x7602cad5, 0x75f90cc7,
-  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
-  0x75b45b1d, 0x75aa78b6,
-  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
-  0x7564c8f8, 0x755ac251,
-  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
-  0x7514152b, 0x7509ea5d,
-  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
-  0x74c2407d, 0x74b7f1a1,
-  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
-  0x746f4bb8, 0x7464d8e8,
-  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
-  0x741b37a9, 0x7410a0fe,
-  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
-  0x73c6051f, 0x73bb4ab3,
-  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
-  0x736fb4ec, 0x7364d6da,
-  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
-  0x731847e5, 0x730d4648,
-  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
-  0x72bfbee3, 0x72b499d6,
-  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
-  0x72661abf, 0x725ad25d,
-  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
-  0x720b5c57, 0x71fff0bc,
-  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
-  0x71af848a, 0x71a3f5d2,
-  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
-  0x7152943b, 0x7146e284,
-  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
-  0x70f48c50, 0x70e8b7b5,
-  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
-  0x70956db1, 0x70897650,
-  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
-  0x70353947, 0x70291f3e,
-  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
-  0x6fd3f001, 0x6fc7b36d,
-  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
-  0x6f7192cf, 0x6f6533ce,
-  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
-  0x6f0e22a3, 0x6f01a155,
-  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
-  0x6ea9a073, 0x6e9cfcf5,
-  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
-  0x6e440d37, 0x6e3747a9,
-  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
-  0x6ddd69e9, 0x6dd0826a,
-  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
-  0x6d75b786, 0x6d68ae37,
-  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
-  0x6d0cf70f, 0x6cffcc0f,
-  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
-  0x6ca32985, 0x6c95dcf6,
-  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
-  0x6c384fef, 0x6c2ae1f0,
-  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
-  0x6bcc6b53, 0x6bbedc06,
-  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
-  0x6b5f7cbc, 0x6b51cc42,
-  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
-  0x6af18536, 0x6ae3b3b2,
-  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
-  0x6a8285d1, 0x6a749365,
-  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
-  0x6a127f9f, 0x6a046c6c,
-  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
-  0x69a173b5, 0x69933fde,
-  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
-  0x692f6328, 0x69210ed1,
-  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
-  0x68bc4f13, 0x68adda5f,
-  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
-  0x68483891, 0x6839a3a4,
-  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
-  0x67d320c1, 0x67c46bbe,
-  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
-  0x675d08c4, 0x674e33d0,
-  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
-  0x66e5f1be, 0x66d6fcfd,
-  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
-  0x666ddcd3, 0x665ec86b,
-  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
-  0x65f4cb2d, 0x65e59742,
-  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
-  0x657abdf6, 0x656b6aae,
-  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
-  0x64ffb65b, 0x64f043dc,
-  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
-  0x6483b58c, 0x647423fb,
-  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
-  0x6406bcba, 0x63f70c3f,
-  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
-  0x6388cd1b, 0x6378fddc,
-  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
-  0x6309e7e4, 0x62f9fa09,
-  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
-  0x628a0e50, 0x627a01fe,
-  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
-  0x62094199, 0x61f916f9,
-  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
-  0x618782fd, 0x61773a37,
-  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
-  0x6104d3bc, 0x60f46cf9,
-  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
-  0x60813519, 0x6070b080,
-  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
-  0x5ffca859, 0x5fec0613,
-  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
-  0x5f772ec2, 0x5f666ef9,
-  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
-  0x5ef0c99f, 0x5edfec7b,
-  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
-  0x5e697a39, 0x5e587fe5,
-  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
-  0x5de141e1, 0x5dd02a85,
-  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
-  0x5d5821e4, 0x5d46edac,
-  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
-  0x5cce1b97, 0x5cbccaac,
-  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
-  0x5c43304d, 0x5c31c2db,
-  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
-  0x5bb7615d, 0x5ba5d78e,
-  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
-  0x5b2ab020, 0x5b190a20,
-  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
-  0x5a9d1df1, 0x5a8b5bec,
-  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
-  0x5a0eac2e, 0x59fcce4f,
-  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
-  0x597f5c36, 0x596d62a9,
-  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
-  0x58ef2f6b, 0x58dd1a5d,
-  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
-  0x585e2730, 0x584bf6cd,
-  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
-  0x57cc44ec, 0x57b9f960,
-  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
-  0x57398a05, 0x5727237f,
-  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
-  0x56a5f7e7, 0x56937694,
-  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
-  0x56118ffe, 0x55fef40a,
-  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
-  0x557c53b6, 0x55699d51,
-  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
-  0x54e64482, 0x54d373d9,
-  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
-  0x544f63d2, 0x543c7914,
-  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
-  0x53b7b31c, 0x53a4ae77,
-  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
-  0x531f33d5, 0x530c1579,
-  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
-  0x5285e777, 0x5272af92,
-  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
-  0x51ebcf7a, 0x51d87e3c,
-  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
-  0x5150ed5c, 0x513d82f4,
-  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
-  0x50b5429a, 0x50a1bf39,
-  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
-  0x5018d0b4, 0x5005348a,
-  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
-  0x4f7b992d, 0x4f67e46a,
-  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
-  0x4edd9d89, 0x4ec9d05e,
-  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
-  0x4e3edf4d, 0x4e2af9ea,
-  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
-  0x4d9f6001, 0x4d8b6298,
-  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
-  0x4cff212e, 0x4ceb0bf0,
-  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
-  0x4c5e2460, 0x4c49f77f,
-  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
-  0x4bbc6b25, 0x4ba826d1,
-  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
-  0x4b19f70a, 0x4b059b77,
-  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
-  0x4a76c9a2, 0x4a625701,
-  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
-  0x49d2e47e, 0x49be5b02,
-  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
-  0x492e4933, 0x4919a90f,
-  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
-  0x4888f957, 0x487442be,
-  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
-  0x47e2f682, 0x47ce29a7,
-  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
-  0x473c424e, 0x47275f63,
-  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
-  0x4694de56, 0x467fe590,
-  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
-  0x45eccc37, 0x45d7bdc9,
-  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
-  0x45440d90, 0x452ee9ae,
-  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
-  0x449aa400, 0x44856adf,
-  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
-  0x43f0912b, 0x43db42fe,
-  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
-  0x4345d6b3, 0x433073b0,
-  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
-  0x429a763f, 0x4284fe99,
-  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
-  0x41ee7174, 0x41d8e561,
-  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
-  0x4141c9fb, 0x412c29b1,
-  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
-  0x4094817f, 0x407ecd32,
-  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
-  0x3fe699aa, 0x3fd0d191,
-  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
-  0x3f38142a, 0x3f22387a,
-  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
-  0x3e88f2ae, 0x3e73039d,
-  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
-  0x3dd936e6, 0x3dc334a9,
-  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
-  0x3d28e282, 0x3d12cd51,
-  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
-  0x3c77f737, 0x3c61cf48,
-  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
-  0x3bc676b9, 0x3bb03c42,
-  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
-  0x3b1462be, 0x3afe15f6,
-  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
-  0x3a61bcfd, 0x3a4b5e1b,
-  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
-  0x39ae872f, 0x3998166a,
-  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
-  0x38fac30e, 0x38e4409e,
-  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
-  0x38467255, 0x382fde72,
-  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
-  0x379196c3, 0x377af1a3,
-  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
-  0x36dc3214, 0x36c57bf0,
-  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
-  0x36264609, 0x360f7f19,
-  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
-  0x356fd461, 0x3558fcde,
-  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
-  0x34b8dee1, 0x34a1f702,
-  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
-  0x3401674a, 0x33ea6f48,
-  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
-  0x33496f62, 0x33326776,
-  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
-  0x3290f8ef, 0x3279e151,
-  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
-  0x31d805b7, 0x31c0dea1,
-  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
-  0x311e9783, 0x3107612e,
-  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
-  0x3064b01d, 0x304d6ac1,
-  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
-  0x2faa514f, 0x2f92fd26,
-  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
-  0x2eef7ce5, 0x2ed81a29,
-  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
-  0x2e3434ac, 0x2e1cc397,
-  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
-  0x2d787a72, 0x2d60fb3e,
-  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
-  0x2cbc5006, 0x2ca4c2ed,
-  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
-  0x2bffb73a, 0x2be81c74,
-  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
-  0x2b42b1dd, 0x2b2b09a6,
-  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
-  0x2a8541c3, 0x2a6d8c55,
-  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
-  0x29c768be, 0x29afa654,
-  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
-  0x290928a3, 0x28f15978,
-  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
-  0x284a8349, 0x2832a796,
-  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
-  0x278b7a84, 0x27739285,
-  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
-  0x26cc102d, 0x26b41c1d,
-  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
-  0x260c461b, 0x25f44635,
-  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
-  0x254c1e28, 0x253412a8,
-  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
-  0x248b9a2f, 0x2473834f,
-  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
-  0x23cabc09, 0x23b29a05,
-  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
-  0x23098593, 0x22f158a7,
-  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
-  0x2247f8aa, 0x222fc111,
-  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
-  0x2186172b, 0x216dd521,
-  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
-  0x20c3e2f5, 0x20ab96b5,
-  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
-  0x20015de7, 0x1fe907ae,
-  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
-  0x1f3e89e0, 0x1f2629ea,
-  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
-  0x1e7b68c2, 0x1e62ff4a,
-  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
-  0x1db7fc6d, 0x1d9f89b1,
-  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
-  0x1cf446c5, 0x1cdbcb00,
-  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
-  0x1c3049ac, 0x1c17c51b,
-  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
-  0x1b6c0705, 0x1b5379e5,
-  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
-  0x1aa780b6, 0x1a8eeb42,
-  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
-  0x19e2b8a2, 0x19ca1b17,
-  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
-  0x191db0af, 0x19050b4b,
-  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
-  0x18586ac3, 0x183fbdc3,
-  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
-  0x1792e8c6, 0x177a3466,
-  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
-  0x16cd2c9f, 0x16b4711b,
-  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
-  0x16073834, 0x15ee75cb,
-  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
-  0x15410d70, 0x1528445d,
-  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
-  0x147aae3a, 0x1461debc,
-  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
-  0x13b41c7d, 0x139b46d0,
-  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
-  0x12ed5a21, 0x12d47e83,
-  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
-  0x12266913, 0x120d87c1,
-  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
-  0x115f4b3c, 0x11466473,
-  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
-  0x10980287, 0x107f1686,
-  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
-  0xfd090e1, 0xfb79fe4,
-  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
-  0xef0027b,
-  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
-  0xe284036,
-  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
-  0xd605b03,
-  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
-  0xc9854cf,
-  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
-  0xbd02f87,
-  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
-  0xb07ed19,
-  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
-  0xa3f8f73,
-  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
-  0x9771884,
-  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
-  0x8ae8a3a,
-  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
-  0x7e5e685,
-  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
-  0x71d2f52,
-  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
-  0x6546692,
-  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
-  0x58b8e34,
-  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
-  0x4c2a827,
-  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
-  0x3f9b65b,
-  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
-  0x330bac1,
-  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
-  0x267b747,
-  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
-  0x19eaddd,
-  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
-  0xd5a075,
-  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
-  0xc90fe,
-
-};
-
-static const q31_t cos_factorsQ31_8192[8192] = {
-  0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
-    0x7ffff97c, 0x7ffff753,
-  0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
-    0x7fffdf94, 0x7fffdaf3,
-  0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
-    0x7fffb1ee, 0x7fffaad6,
-  0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
-    0x7fff708b, 0x7fff66fc,
-  0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
-    0x7fff1b6b, 0x7fff0f64,
-  0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
-    0x7ffeb28e, 0x7ffea40f,
-  0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
-    0x7ffe35f4, 0x7ffe24fe,
-  0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
-    0x7ffda59d, 0x7ffd922f,
-  0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
-    0x7ffd0189, 0x7ffceba4,
-  0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
-    0x7ffc49b9, 0x7ffc315b,
-  0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
-    0x7ffb7e2b, 0x7ffb6356,
-  0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
-    0x7ffa9ee2, 0x7ffa8195,
-  0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
-    0x7ff9abdb, 0x7ff98c17,
-  0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
-    0x7ff8a519, 0x7ff882dd,
-  0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
-    0x7ff78a9a, 0x7ff765e7,
-  0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
-    0x7ff65c5f, 0x7ff63535,
-  0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
-    0x7ff51a69, 0x7ff4f0c7,
-  0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
-    0x7ff3c4b7, 0x7ff3989e,
-  0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
-    0x7ff25b4a, 0x7ff22cb9,
-  0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
-    0x7ff0de22, 0x7ff0ad19,
-  0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
-    0x7fef4d3e, 0x7fef19bf,
-  0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
-    0x7feda8a0, 0x7fed72aa,
-  0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
-    0x7febf048, 0x7febb7da,
-  0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
-    0x7fea2436, 0x7fe9e950,
-  0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
-    0x7fe84469, 0x7fe8070d,
-  0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
-    0x7fe650e3, 0x7fe61110,
-  0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
-    0x7fe449a4, 0x7fe40759,
-  0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
-    0x7fe22eac, 0x7fe1e9ea,
-  0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
-    0x7fdffffb, 0x7fdfb8c2,
-  0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
-    0x7fddbd92, 0x7fdd73e2,
-  0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
-    0x7fdb6771, 0x7fdb1b4a,
-  0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
-    0x7fd8fd98, 0x7fd8aefa,
-  0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
-    0x7fd68009, 0x7fd62ef4,
-  0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
-    0x7fd3eec2, 0x7fd39b36,
-  0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
-    0x7fd149c5, 0x7fd0f3c2,
-  0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
-    0x7fce9112, 0x7fce3898,
-  0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
-    0x7fcbc4a9, 0x7fcb69b9,
-  0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
-    0x7fc8e48b, 0x7fc88724,
-  0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
-    0x7fc5f0b8, 0x7fc590db,
-  0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
-    0x7fc2e931, 0x7fc286de,
-  0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
-    0x7fbfcdf6, 0x7fbf692c,
-  0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
-    0x7fbc9f08, 0x7fbc37c8,
-  0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
-    0x7fb95c67, 0x7fb8f2b0,
-  0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
-    0x7fb60614, 0x7fb599e7,
-  0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
-    0x7fb29c0f, 0x7fb22d6c,
-  0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
-    0x7faf1e58, 0x7faead3f,
-  0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
-    0x7fab8cf1, 0x7fab1962,
-  0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
-    0x7fa7e7d9, 0x7fa771d4,
-  0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
-    0x7fa42f12, 0x7fa3b697,
-  0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
-    0x7fa0629c, 0x7f9fe7ab,
-  0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
-    0x7f9c8278, 0x7f9c0511,
-  0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
-    0x7f988ea5, 0x7f980ec8,
-  0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
-    0x7f948725, 0x7f9404d3,
-  0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
-    0x7f906bf9, 0x7f8fe731,
-  0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
-    0x7f8c3d20, 0x7f8bb5e3,
-  0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
-    0x7f87fa9c, 0x7f8770ea,
-  0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
-    0x7f83a46e, 0x7f831846,
-  0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
-    0x7f7f3a95, 0x7f7eabf8,
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-    0x7c2c45d8, 0x7c2abf4f,
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-  0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
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-  0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
-    0x7c07567f, 0x7c05c8c9,
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-    0x7bfae073, 0x7bf9505a,
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-    0x7bee5749, 0x7becc4cc,
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-    0x7be1bb02, 0x7be02621,
-  0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
-    0x7bd50ba1, 0x7bd3745d,
-  0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
-    0x7bc84927, 0x7bc6af80,
-  0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
-    0x7bbb7396, 0x7bb9d78c,
-  0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
-    0x7bae8af0, 0x7bacec84,
-  0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
-    0x7ba18f38, 0x7b9fee69,
-  0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
-    0x7b94806e, 0x7b92dd3e,
-  0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
-    0x7b875e96, 0x7b85b904,
-  0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
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-  0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
-    0x7b6ce1c2, 0x7b6b376e,
-  0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
-    0x7b5f86ca, 0x7b5dda15,
-  0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
-    0x7b5218cc, 0x7b5069b6,
-  0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
-    0x7b4497c9, 0x7b42e652,
-  0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
-    0x7b3703c3, 0x7b354fed,
-  0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
-    0x7b295cbe, 0x7b27a687,
-  0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
-    0x7b1ba2b9, 0x7b19ea23,
-  0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
-    0x7b0dd5b9, 0x7b0c1ac4,
-  0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
-    0x7afff5bf, 0x7afe386a,
-  0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
-    0x7af202cd, 0x7af0431a,
-  0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
-    0x7ae3fce6, 0x7ae23ad4,
-  0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
-    0x7ad5e40a, 0x7ad41f9a,
-  0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
-    0x7ac7b83e, 0x7ac5f170,
-  0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
-    0x7ab97982, 0x7ab7b056,
-  0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
-    0x7aab27da, 0x7aa95c50,
-  0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
-    0x7a9cc346, 0x7a9af55f,
-  0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
-    0x7a8e4bca, 0x7a8c7b87,
-  0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
-    0x7a7fc168, 0x7a7deec8,
-  0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
-    0x7a712422, 0x7a6f4f25,
-  0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
-    0x7a6273fa, 0x7a609ca1,
-  0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
-    0x7a53b0f2, 0x7a51d73d,
-  0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
-    0x7a44db0d, 0x7a42fefd,
-  0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
-    0x7a35f24d, 0x7a3413e2,
-  0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
-    0x7a26f6b4, 0x7a2515ee,
-  0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
-    0x7a17e845, 0x7a160524,
-  0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
-    0x7a08c702, 0x7a06e187,
-  0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
-    0x79f992ed, 0x79f7ab18,
-  0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
-    0x79ea4c09, 0x79e861da,
-  0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
-    0x79daf258, 0x79d905d0,
-  0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
-    0x79cb85dc, 0x79c996fb,
-  0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
-    0x79bc0698, 0x79ba155e,
-  0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
-    0x79ac748e, 0x79aa80fb,
-  0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
-    0x799ccfc1, 0x799ad9d5,
-  0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
-    0x798d1832, 0x798b1fef,
-  0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
-    0x797d4de5, 0x797b534a,
-  0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
-    0x796d70dc, 0x796b73e9,
-  0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
-    0x795d8118, 0x795b81cf,
-  0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
-    0x794d7e9e, 0x794b7cfe,
-  0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
-    0x793d696f, 0x793b6578,
-  0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
-    0x792d418d, 0x792b3b40,
-  0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
-    0x791d06fb, 0x791afe59,
-  0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
-    0x790cb9bd, 0x790aaec5,
-  0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
-    0x78fc59d3, 0x78fa4c86,
-  0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
-    0x78ebe741, 0x78e9d79f,
-  0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
-    0x78db6209, 0x78d95012,
-  0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
-    0x78caca2e, 0x78c8b5e3,
-  0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
-    0x78ba1fb2, 0x78b80913,
-  0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
-    0x78a96298, 0x78a749a6,
-  0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
-    0x789892e3, 0x7896779d,
-  0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
-    0x7887b094, 0x788592fc,
-  0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
-    0x7876bbb0, 0x78749bc5,
-  0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
-    0x7865b437, 0x786391fa,
-  0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
-    0x78549a2e, 0x7852759e,
-  0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
-    0x78436d96, 0x784146b5,
-  0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
-    0x78322e72, 0x78300540,
-  0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
-    0x7820dcc5, 0x781eb142,
-  0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
-    0x780f7892, 0x780d4abe,
-  0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
-    0x77fe01db, 0x77fbd1b6,
-  0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
-    0x77ec78a2, 0x77ea462e,
-  0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
-    0x77dadcec, 0x77d8a828,
-  0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
-    0x77c92eb9, 0x77c6f7a6,
-  0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
-    0x77b76e0e, 0x77b534ac,
-  0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
-    0x77a59aec, 0x77a35f3c,
-  0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
-    0x7793b557, 0x77917759,
-  0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
-    0x7781bd52, 0x777f7d05,
-  0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
-    0x776fb2de, 0x776d7044,
-  0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
-    0x775d95ff, 0x775b5118,
-  0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
-    0x774b66b8, 0x77491f84,
-  0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
-    0x7739250b, 0x7736db8b,
-  0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
-    0x7726d0fc, 0x7724852f,
-  0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
-    0x77146a8c, 0x77121c74,
-  0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
-    0x7701f1c0, 0x76ffa15c,
-  0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
-    0x76ef6699, 0x76ed13ea,
-  0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
-    0x76dcc91b, 0x76da7421,
-  0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
-    0x76ca1948, 0x76c7c204,
-  0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
-    0x76b75724, 0x76b4fd96,
-  0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
-    0x76a482b1, 0x76a226da,
-  0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
-    0x76919bf3, 0x768f3dd2,
-  0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
-    0x767ea2eb, 0x767c4281,
-  0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
-    0x766b979d, 0x766934eb,
-  0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
-    0x76587a0d, 0x76561512,
-  0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
-    0x76454a3c, 0x7642e2f9,
-  0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
-    0x7632082e, 0x762f9ea4,
-  0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
-    0x761eb3e6, 0x761c4815,
-  0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
-    0x760b4d67, 0x7608df4f,
-  0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
-    0x75f7d4b3, 0x75f56455,
-  0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
-    0x75e449ce, 0x75e1d72b,
-  0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
-    0x75d0acbc, 0x75ce37d2,
-  0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
-    0x75bcfd7e, 0x75ba864f,
-  0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
-    0x75a93c18, 0x75a6c2a4,
-  0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
-    0x7595688c, 0x7592ecd4,
-  0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
-    0x758182df, 0x757f04e3,
-  0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
-    0x756d8b13, 0x756b0ad3,
-  0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
-    0x7559812b, 0x7556fea8,
-  0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
-    0x7545652a, 0x7542e065,
-  0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
-    0x75313714, 0x752eb00c,
-  0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
-    0x751cf6eb, 0x751a6da0,
-  0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
-    0x7508a4b2, 0x75061926,
-  0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
-    0x74f4406d, 0x74f1b2a0,
-  0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
-    0x74dfca20, 0x74dd3a11,
-  0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
-    0x74cb41cc, 0x74c8af7d,
-  0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
-    0x74b6a775, 0x74b412e6,
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-    0x74a1fb1e, 0x749f6450,
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-    0x72c97bad, 0x72c6b3cc,
-  0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
-    0x72b334e4, 0x72b06acd,
-  0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
-    0x729cdc6b, 0x729a101e,
-  0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
-    0x72867245, 0x7283a3c3,
-  0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
-    0x726ff676, 0x726d25bf,
-  0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
-    0x72596901, 0x72569615,
-  0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
-    0x7242c9ea, 0x723ff4ca,
-  0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
-    0x722c1934, 0x722941e0,
-  0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
-    0x721556e3, 0x72127d5c,
-  0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
-    0x71fe82f9, 0x71fba740,
-  0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
-    0x71e79d7c, 0x71e4bf90,
-  0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
-    0x71d0a66d, 0x71cdc650,
-  0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
-    0x71b99dd2, 0x71b6bb83,
-  0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
-    0x71a283ad, 0x719f9f2c,
-  0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
-    0x718b5801, 0x71887151,
-  0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
-    0x71741ad3, 0x717131f3,
-  0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
-    0x715ccc26, 0x7159e116,
-  0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
-    0x71456bfe, 0x71427ebf,
-  0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
-    0x712dfa5e, 0x712b0af0,
-  0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
-    0x7116774a, 0x711385ad,
-  0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
-    0x70fee2c5, 0x70fbeefb,
-  0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
-    0x70e73cd4, 0x70e446dc,
-  0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
-    0x70cf8579, 0x70cc8d54,
-  0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
-    0x70b7bcb8, 0x70b4c267,
-  0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
-    0x709fe296, 0x709ce619,
-  0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
-    0x7087f715, 0x7084f86d,
-  0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
-    0x706ffa3a, 0x706cf967,
-  0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
-    0x7057ec08, 0x7054e90a,
-  0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
-    0x703fcc83, 0x703cc75b,
-  0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
-    0x70279baf, 0x7024945d,
-  0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
-    0x700f598e, 0x700c5013,
-  0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
-    0x6ff70626, 0x6ff3fa82,
-  0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
-    0x6fdea17a, 0x6fdb93ae,
-  0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
-    0x6fc62b8d, 0x6fc31b99,
-  0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
-    0x6fada464, 0x6faa9248,
-  0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
-    0x6f950c01, 0x6f91f7bf,
-  0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
-    0x6f7c626a, 0x6f794c01,
-  0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
-    0x6f63a7a1, 0x6f608f13,
-  0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
-    0x6f4adbab, 0x6f47c0f7,
-  0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
-    0x6f31fe8b, 0x6f2ee1b2,
-  0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
-    0x6f191045, 0x6f15f148,
-  0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
-    0x6f0010de, 0x6efcefbd,
-  0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
-    0x6ee70058, 0x6ee3dd13,
-  0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
-    0x6ecddeb8, 0x6ecab950,
-  0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
-    0x6eb4ac02, 0x6eb18477,
-  0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
-    0x6e9b6839, 0x6e983e8d,
-  0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
-    0x6e821361, 0x6e7ee794,
-  0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
-    0x6e68ad7f, 0x6e657f90,
-  0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
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-  0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
-    0x6e35aeab, 0x6e327c7b,
-  0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
-    0x6e1c15c0, 0x6e18e171,
-  0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
-    0x6e026bda, 0x6dff356c,
-  0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
-    0x6de8b0fe, 0x6de57871,
-  0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
-    0x6dcee52e, 0x6dcbaa83,
-  0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
-    0x6db5086f, 0x6db1cba7,
-  0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
-    0x6d9b1ac6, 0x6d97dbe0,
-  0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
-    0x6d811c35, 0x6d7ddb33,
-  0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
-    0x6d670cc1, 0x6d63c9a3,
-  0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
-    0x6d4cec6e, 0x6d49a734,
-  0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
-    0x6d32bb40, 0x6d2f73eb,
-  0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
-    0x6d18793b, 0x6d152fcc,
-  0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
-    0x6cfe2663, 0x6cfadada,
-  0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
-    0x6ce3c2bd, 0x6ce0751a,
-  0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
-    0x6cc94e4b, 0x6cc5fe8f,
-  0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
-    0x6caec913, 0x6cab773e,
-  0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
-    0x6c943318, 0x6c90df2c,
-  0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
-    0x6c798c5f, 0x6c76365b,
-  0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
-    0x6c5ed4eb, 0x6c5b7cd0,
-  0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
-    0x6c440cc1, 0x6c40b28f,
-  0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
-    0x6c2933e5, 0x6c25d79d,
-  0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
-    0x6c0e4a5b, 0x6c0aebfe,
-  0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
-    0x6bf35027, 0x6befefb5,
-  0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
-    0x6bd8454d, 0x6bd4e2c6,
-  0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
-    0x6bbd29d2, 0x6bb9c537,
-  0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
-    0x6ba1fdb9, 0x6b9e970b,
-  0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
-    0x6b86c107, 0x6b835846,
-  0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
-    0x6b6b73c0, 0x6b6808ed,
-  0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
-    0x6b5015e9, 0x6b4ca904,
-  0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
-    0x6b34a785, 0x6b31388e,
-  0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
-    0x6b192898, 0x6b15b791,
-  0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
-    0x6afd9928, 0x6afa2610,
-  0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
-    0x6ae1f937, 0x6ade8410,
-  0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
-    0x6ac648cb, 0x6ac2d195,
-  0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
-    0x6aaa87e8, 0x6aa70ea4,
-  0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
-    0x6a8eb692, 0x6a8b3b3f,
-  0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
-    0x6a72d4cd, 0x6a6f576d,
-  0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
-    0x6a56e29e, 0x6a536331,
-  0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
-    0x6a3ae008, 0x6a375e8f,
-  0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
-    0x6a1ecd11, 0x6a1b498c,
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-    0x5bc6b70b, 0x5bc255b2,
-  0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
-    0x5ba3a615, 0x5b9f42f7,
-  0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
-    0x5b8086fd, 0x5b7c221c,
-  0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
-    0x5b5d59c9, 0x5b58f324,
-  0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
-    0x5b3a1e7e, 0x5b35b617,
-  0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
-    0x5b16d521, 0x5b126af8,
-  0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
-    0x5af37db8, 0x5aef11cf,
-  0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
-    0x5ad01849, 0x5acbaa9f,
-  0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
-    0x5aaca4d8, 0x5aa8356f,
-  0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
-    0x5a89236c, 0x5a84b243,
-  0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
-    0x5a65940a, 0x5a612123,
-  0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
-    0x5a41f6b7, 0x5a3d8212,
-  0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
-    0x5a1e4b79, 0x5a19d517,
-  0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
-    0x59fa9255, 0x59f61a36,
-  0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
-    0x59d6cb50, 0x59d25176,
-  0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
-    0x59b2f671, 0x59ae7add,
-  0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
-    0x598f13bd, 0x598a966e,
-  0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
-    0x596b233a, 0x5966a431,
-  0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
-    0x594724ec, 0x5942a42a,
-  0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
-    0x592318d9, 0x591e9660,
-  0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
-    0x58feff08, 0x58fa7ad7,
-  0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
-    0x58dad77d, 0x58d65195,
-  0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
-    0x58b6a23e, 0x58b21aa0,
-  0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
-    0x58925f52, 0x588dd5fe,
-  0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
-    0x586e0ebc, 0x586983b4,
-  0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
-    0x5849b083, 0x584523c7,
-  0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
-    0x582544ad, 0x5820b63e,
-  0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
-    0x5800cb3f, 0x57fc3b1d,
-  0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
-    0x57dc443f, 0x57d7b26b,
-  0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
-    0x57b7afb2, 0x57b31c2d,
-  0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
-    0x57930d9e, 0x578e7869,
-  0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
-    0x576e5e09, 0x5769c724,
-  0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
-    0x5749a0f9, 0x57450864,
-  0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
-    0x5724d672, 0x57203c2f,
-  0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
-    0x56fffe7b, 0x56fb628b,
-  0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
-    0x56db1919, 0x56d67b7c,
-  0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
-    0x56b62653, 0x56b18709,
-  0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
-    0x5691262d, 0x568c8538,
-  0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
-    0x566c18ae, 0x5667760e,
-  0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
-    0x5646fddb, 0x56425991,
-  0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
-    0x5621d5ba, 0x561d2fc6,
-  0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
-    0x55fca050, 0x55f7f8b4,
-  0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
-    0x55d75da4, 0x55d2b460,
-  0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
-    0x55b20dbb, 0x55ad62d0,
-  0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
-    0x558cb09b, 0x55880409,
-  0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
-    0x55674649, 0x55629812,
-  0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
-    0x5541cecc, 0x553d1ef0,
-  0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
-    0x551c4a29, 0x551798a8,
-  0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
-    0x54f6b866, 0x54f20542,
-  0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
-    0x54d11989, 0x54cc64c2,
-  0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
-    0x54ab6d97, 0x54a6b72e,
-  0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
-    0x5485b497, 0x5480fc8c,
-  0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
-    0x545fee8e, 0x545b34e3,
-  0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
-    0x543a1b82, 0x54356037,
-  0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
-    0x54143b79, 0x540f7e8e,
-  0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
-    0x53ee4e78, 0x53e98fef,
-  0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
-    0x53c85486, 0x53c3945f,
-  0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
-    0x53a24da9, 0x539d8be5,
-  0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
-    0x537c39e6, 0x53777685,
-  0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
-    0x53561942, 0x53515447,
-  0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
-    0x532febc5, 0x532b252f,
-  0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
-    0x5309b174, 0x5304e943,
-  0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
-    0x52e36a55, 0x52dea08a,
-  0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
-    0x52bd166d, 0x52b84b0a,
-  0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
-    0x5296b5c3, 0x5291e8c8,
-  0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
-    0x5270485c, 0x526b79ca,
-  0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
-    0x5249ce3f, 0x5244fe17,
-  0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
-    0x52234771, 0x521e75b3,
-  0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
-    0x51fcb3f9, 0x51f7e0a6,
-  0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
-    0x51d613dc, 0x51d13ef5,
-  0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
-    0x51af6720, 0x51aa90a5,
-  0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
-    0x5188adcb, 0x5183d5be,
-  0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
-    0x5161e7e4, 0x515d0e45,
-  0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
-    0x513b156f, 0x51363a3f,
-  0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
-    0x51143674, 0x510f59b3,
-  0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
-    0x50ed4af8, 0x50e86ca8,
-  0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
-    0x50c65301, 0x50c17322,
-  0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
-    0x509f4e95, 0x509a6d28,
-  0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
-    0x50783dba, 0x50735abf,
-  0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
-    0x50512077, 0x504c3bef,
-  0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
-    0x5029f6d1, 0x502510bd,
-  0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
-    0x5002c0cd, 0x4ffdd92f,
-  0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
-    0x4fdb7e74, 0x4fd6954b,
-  0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
-    0x4fb42fc9, 0x4faf4517,
-  0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
-    0x4f8cd4d4, 0x4f87e899,
-  0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
-    0x4f656d9b, 0x4f607fd7,
-  0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
-    0x4f3dfa23, 0x4f390ad8,
-  0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
-    0x4f167a73, 0x4f1189a1,
-  0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
-    0x4eeeee90, 0x4ee9fc39,
-  0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
-    0x4ec75682, 0x4ec262a5,
-  0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
-    0x4e9fb24d, 0x4e9abcec,
-  0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
-    0x4e7801f8, 0x4e730b14,
-  0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
-    0x4e50458a, 0x4e4b4d22,
-  0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
-    0x4e287d08, 0x4e23831e,
-  0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
-    0x4e00a878, 0x4dfbad0d,
-  0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
-    0x4dd8c7e1, 0x4dd3caf6,
-  0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
-    0x4db0db48, 0x4dabdcdd,
-  0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
-    0x4d88e2b5, 0x4d83e2cb,
-  0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
-    0x4d60de2c, 0x4d5bdcc4,
-  0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
-    0x4d38cdb5, 0x4d33cad0,
-  0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
-    0x4d10b155, 0x4d0bacf3,
-  0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
-    0x4ce88913, 0x4ce38335,
-  0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
-    0x4cc054f4, 0x4cbb4d9b,
-  0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
-    0x4c981500, 0x4c930c2d,
-  0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
-    0x4c6fc93b, 0x4c6abeef,
-  0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
-    0x4c4771ae, 0x4c4265e8,
-  0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
-    0x4c1f0e5c, 0x4c1a011f,
-  0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
-    0x4bf69f4e, 0x4bf19099,
-  0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
-    0x4bce2488, 0x4bc9145d,
-  0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
-    0x4ba59e12, 0x4ba08c72,
-  0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
-    0x4b7d0bf2, 0x4b77f8dc,
-  0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
-    0x4b546e2d, 0x4b4f59a4,
-  0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
-    0x4b2bc4cb, 0x4b26aece,
-  0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
-    0x4b030fd1, 0x4afdf861,
-  0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
-    0x4ada4f45, 0x4ad53664,
-  0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
-    0x4ab1832f, 0x4aac68dc,
-  0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
-    0x4a88ab93, 0x4a838fd1,
-  0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
-    0x4a5fc879, 0x4a5aab48,
-  0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
-    0x4a36d9e7, 0x4a31bb47,
-  0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
-    0x4a0ddfe4, 0x4a08bfd5,
-  0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
-    0x49e4da74, 0x49dfb8f9,
-  0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
-    0x49bbc9a0, 0x49b6a6b8,
-  0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
-    0x4992ad6c, 0x498d8919,
-  0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
-    0x496985e0, 0x49646023,
-  0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
-    0x49405302, 0x493b2bdb,
-  0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
-    0x491714d8, 0x4911ec47,
-  0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
-    0x48edcb68, 0x48e8a170,
-  0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
-    0x48c476b9, 0x48bf4b59,
-  0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
-    0x489b16d2, 0x4895ea0b,
-  0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
-    0x4871abb8, 0x486c7d8c,
-  0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
-    0x48483572, 0x484305e1,
-  0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
-    0x481eb407, 0x48198311,
-  0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
-    0x47f5277d, 0x47eff523,
-  0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
-    0x47cb8fd9, 0x47c65c1d,
-  0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
-    0x47a1ed24, 0x479cb806,
-  0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
-    0x47783f62, 0x477308e3,
-  0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
-    0x474e869b, 0x47494ebc,
-  0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
-    0x4724c2d5, 0x471f8996,
-  0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
-    0x46faf416, 0x46f5b979,
-  0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
-    0x46d11a65, 0x46cbde6a,
-  0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
-    0x46a735c8, 0x46a1f870,
-  0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
-    0x467d4646, 0x46780792,
-  0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
-    0x46534be5, 0x464e0bd6,
-  0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
-    0x462946ac, 0x46240542,
-  0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
-    0x45ff36a1, 0x45f9f3dd,
-  0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
-    0x45d51bcb, 0x45cfd7ae,
-  0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
-    0x45aaf630, 0x45a5b0bb,
-  0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
-    0x4580c5d6, 0x457b7f0a,
-  0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
-    0x45568ac4, 0x455142a2,
-  0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
-    0x452c4502, 0x4526fb89,
-  0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
-    0x4501f494, 0x44fca9c6,
-  0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
-    0x44d79982, 0x44d24d60,
-  0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
-    0x44ad33d2, 0x44a7e65d,
-  0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
-    0x4482c38b, 0x447d74c4,
-  0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
-    0x445848b3, 0x4452f89b,
-  0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
-    0x442dc351, 0x442871e8,
-  0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
-    0x4403336c, 0x43fde0b2,
-  0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
-    0x43d8990a, 0x43d34501,
-  0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
-    0x43adf431, 0x43a89ed9,
-  0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
-    0x438344e8, 0x437dee43,
-  0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
-    0x43588b36, 0x43533344,
-  0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
-    0x432dc721, 0x43286de4,
-  0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
-    0x4302f8b0, 0x42fd9e28,
-  0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
-    0x42d81fe9, 0x42d2c417,
-  0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
-    0x42ad3cd4, 0x42a7dfb8,
-  0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
-    0x42824f76, 0x427cf112,
-  0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
-    0x425757d7, 0x4251f82b,
-  0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
-    0x422c55fd, 0x4226f50a,
-  0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
-    0x420149ee, 0x41fbe7b5,
-  0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
-    0x41d633b1, 0x41d0d033,
-  0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
-    0x41ab134e, 0x41a5ae8b,
-  0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
-    0x417fe8ca, 0x417a82c3,
-  0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
-    0x4154b42c, 0x414f4ce2,
-  0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
-    0x4129757b, 0x41240cef,
-  0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
-    0x40fe2cbd, 0x40f8c2f1,
-  0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
-    0x40d2d9f9, 0x40cd6eed,
-  0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
-    0x40a77d37, 0x40a210eb,
-  0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
-    0x407c167c, 0x4076a8f1,
-  0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
-    0x4050a5cf, 0x404b3707,
-  0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
-    0x40252b37, 0x401fbb32,
-  0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
-    0x3ff9a6bb, 0x3ff4357a,
-  0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
-    0x3fce1861, 0x3fc8a5e5,
-  0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
-    0x3fa28031, 0x3f9d0c7a,
-  0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
-    0x3f76de30, 0x3f71693f,
-  0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
-    0x3f4b3265, 0x3f45bc3c,
-  0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
-    0x3f1f7cd8, 0x3f1a0577,
-  0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
-    0x3ef3bd8f, 0x3eee44f7,
-  0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
-    0x3ec7f491, 0x3ec27ac2,
-  0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
-    0x3e9c21e4, 0x3e96a6e0,
-  0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
-    0x3e70458f, 0x3e6ac957,
-  0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
-    0x3e445f99, 0x3e3ee22e,
-  0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
-    0x3e18700a, 0x3e12f16b,
-  0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
-    0x3dec76e6, 0x3de6f716,
-  0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
-    0x3dc07436, 0x3dbaf335,
-  0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
-    0x3d946801, 0x3d8ee5cf,
-  0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
-    0x3d68524c, 0x3d62ceeb,
-  0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
-    0x3d3c331f, 0x3d36ae8f,
-  0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
-    0x3d100a80, 0x3d0a84c3,
-  0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
-    0x3ce3d877, 0x3cde518d,
-  0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
-    0x3cb79d0a, 0x3cb214f4,
-  0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
-    0x3c8b5840, 0x3c85cefe,
-  0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
-    0x3c5f0a20, 0x3c597fb4,
-  0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
-    0x3c32b2b0, 0x3c2d271b,
-  0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
-    0x3c0651f8, 0x3c00c53a,
-  0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
-    0x3bd9e7fe, 0x3bd45a19,
-  0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
-    0x3bad74c9, 0x3ba7e5bd,
-  0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
-    0x3b80f861, 0x3b7b682e,
-  0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
-    0x3b5472cb, 0x3b4ee173,
-  0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
-    0x3b27e40f, 0x3b225193,
-  0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
-    0x3afb4c34, 0x3af5b894,
-  0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
-    0x3aceab40, 0x3ac9167e,
-  0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
-    0x3aa2013a, 0x3a9c6b57,
-  0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
-    0x3a754e2a, 0x3a6fb726,
-  0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
-    0x3a489216, 0x3a42f9f2,
-  0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
-    0x3a1bcd05, 0x3a1633c1,
-  0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
-    0x39eefefe, 0x39e9649c,
-  0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
-    0x39c22808, 0x39bc8c89,
-  0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
-    0x39954829, 0x398fab8e,
-  0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
-    0x39685f6a, 0x3962c1b2,
-  0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
-    0x393b6dd0, 0x3935cefd,
-  0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
-    0x390e7362, 0x3908d376,
-  0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
-    0x38e17028, 0x38dbcf23,
-  0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
-    0x38b46429, 0x38aec20b,
-  0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
-    0x38874f6b, 0x3881ac36,
-  0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
-    0x385a31f5, 0x38548daa,
-  0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
-    0x382d0bce, 0x3827666d,
-  0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
-    0x37ffdcfe, 0x37fa3688,
-  0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
-    0x37d2a58b, 0x37ccfe02,
-  0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
-    0x37a5657c, 0x379fbce0,
-  0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
-    0x37781cd9, 0x3772732a,
-  0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
-    0x374acba7, 0x374520e7,
-  0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
-    0x371d71ef, 0x3717c61f,
-  0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
-    0x36f00fb7, 0x36ea62d7,
-  0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
-    0x36c2a506, 0x36bcf718,
-  0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
-    0x369531e3, 0x368f82e7,
-  0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
-    0x3667b655, 0x3662064c,
-  0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
-    0x363a3264, 0x3634814f,
-  0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
-    0x360ca615, 0x3606f3f5,
-  0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
-    0x35df1171, 0x35d95e47,
-  0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
-    0x35b1747e, 0x35abc04b,
-  0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
-    0x3583cf44, 0x357e1a08,
-  0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
-    0x355621c9, 0x35506b85,
-  0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
-    0x35286c14, 0x3522b4c9,
-  0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
-    0x34faae2c, 0x34f4f5dc,
-  0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
-    0x34cce819, 0x34c72ec4,
-  0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
-    0x349f19e2, 0x34995f88,
-  0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
-    0x3471438d, 0x346b8830,
-  0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
-    0x34436521, 0x343da8c3,
-  0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
-    0x34157ea7, 0x340fc147,
-  0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
-    0x33e79024, 0x33e1d1c4,
-  0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
-    0x33b999a0, 0x33b3da40,
-  0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
-    0x338b9b22, 0x3385dac4,
-  0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
-    0x335d94b2, 0x3357d355,
-  0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
-    0x332f8655, 0x3329c3fb,
-  0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
-    0x33017014, 0x32fbacbe,
-  0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
-    0x32d351f5, 0x32cd8da4,
-  0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
-    0x32a52bff, 0x329f66b4,
-  0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
-    0x3276fe3a, 0x327137f6,
-  0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
-    0x3248c8ad, 0x32430170,
-  0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
-    0x321a8b5f, 0x3214c32a,
-  0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
-    0x31ec4657, 0x31e67d2b,
-  0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
-    0x31bdf99b, 0x31b82f7a,
-  0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
-    0x318fa535, 0x3189da1e,
-  0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
-    0x31614929, 0x315b7d1e,
-  0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
-    0x3132e580, 0x312d1882,
-  0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
-    0x31047a41, 0x30feac51,
-  0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
-    0x30d60772, 0x30d03891,
-  0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
-    0x30a78d1c, 0x30a1bd4a,
-  0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
-    0x30790b45, 0x30733a83,
-  0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
-    0x304a81f4, 0x3044b044,
-  0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
-    0x301bf131, 0x30161e93,
-  0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
-    0x2fed5902, 0x2fe78577,
-  0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
-    0x2fbeb970, 0x2fb8e4f9,
-  0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
-    0x2f901280, 0x2f8a3d1e,
-  0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
-    0x2f61643b, 0x2f5b8def,
-  0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
-    0x2f32aea8, 0x2f2cd772,
-  0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
-    0x2f03f1cd, 0x2efe19ae,
-  0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
-    0x2ed52db1, 0x2ecf54ac,
-  0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
-    0x2ea6625d, 0x2ea08871,
-  0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
-    0x2e778fd8, 0x2e71b506,
-  0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
-    0x2e48b628, 0x2e42da71,
-  0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
-    0x2e19d554, 0x2e13f8ba,
-  0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
-    0x2deaed65, 0x2de50fe8,
-  0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
-    0x2dbbfe61, 0x2db62001,
-  0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
-    0x2d8d084f, 0x2d87290f,
-  0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
-    0x2d5e0b38, 0x2d582b17,
-  0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
-    0x2d2f0721, 0x2d292620,
-  0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
-    0x2cfffc12, 0x2cfa1a33,
-  0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
-    0x2cd0ea13, 0x2ccb0756,
-  0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
-    0x2ca1d12a, 0x2c9bed91,
-  0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
-    0x2c72b160, 0x2c6ccceb,
-  0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
-    0x2c438abb, 0x2c3da56b,
-  0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
-    0x2c145d42, 0x2c0e7719,
-  0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
-    0x2be528fd, 0x2bdf41fb,
-  0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
-    0x2bb5edf4, 0x2bb00619,
-  0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
-    0x2b86ac2c, 0x2b80c37a,
-  0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
-    0x2b5763ae, 0x2b517a26,
-  0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
-    0x2b281482, 0x2b222a24,
-  0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
-    0x2af8bead, 0x2af2d37b,
-  0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
-    0x2ac96238, 0x2ac37633,
-  0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
-    0x2a99ff2a, 0x2a941252,
-  0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
-    0x2a6a958a, 0x2a64a7e0,
-  0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
-    0x2a3b2560, 0x2a3536e5,
-  0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
-    0x2a0baeb2, 0x2a05bf67,
-  0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
-    0x29dc3188, 0x29d6416f,
-  0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
-    0x29acadea, 0x29a6bd02,
-  0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
-    0x297d23df, 0x2977322a,
-  0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
-    0x294d936d, 0x2947a0ec,
-  0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
-    0x291dfc9d, 0x29180951,
-  0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
-    0x28ee5f76, 0x28e86b5f,
-  0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
-    0x28bebbff, 0x28b8c71f,
-  0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
-    0x288f123f, 0x28891c97,
-  0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
-    0x285f623f, 0x28596bce,
-  0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
-    0x282fac04, 0x2829b4cd,
-  0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
-    0x27ffef97, 0x27f9f79a,
-  0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
-    0x27d02cff, 0x27ca343d,
-  0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
-    0x27a06443, 0x279a6abd,
-  0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
-    0x2770956a, 0x276a9b21,
-  0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
-    0x2740c07d, 0x273ac572,
-  0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
-    0x2710e582, 0x270ae9b6,
-  0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
-    0x26e10480, 0x26db07f4,
-  0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
-    0x26b11d80, 0x26ab2034,
-  0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
-    0x26813088, 0x267b327e,
-  0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
-    0x26513da1, 0x264b3ed9,
-  0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
-    0x262144d0, 0x261b454c,
-  0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
-    0x25f1461e, 0x25eb45de,
-  0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
-    0x25c14192, 0x25bb4098,
-  0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
-    0x25913734, 0x258b3580,
-  0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
-    0x2561270b, 0x255b249e,
-  0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
-    0x2531111e, 0x252b0df9,
-  0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
-    0x2500f574, 0x24faf198,
-  0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
-    0x24d0d416, 0x24cacf84,
-  0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
-    0x24a0ad0b, 0x249aa7c4,
-  0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
-    0x24708059, 0x246a7a5e,
-  0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
-    0x24404e09, 0x243a475a,
-  0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
-    0x24101622, 0x240a0ec1,
-  0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
-    0x23dfd8ab, 0x23d9d098,
-  0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
-    0x23af95ac, 0x23a98ce8,
-  0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
-    0x237f4d2b, 0x237943b9,
-  0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
-    0x234eff32, 0x2348f511,
-  0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
-    0x231eabc7, 0x2318a0f8,
-  0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
-    0x22ee52f1, 0x22e84775,
-  0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
-    0x22bdf4b8, 0x22b7e890,
-  0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
-    0x228d9123, 0x22878451,
-  0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
-    0x225d283b, 0x22571abe,
-  0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
-    0x222cba06, 0x2226abe0,
-  0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
-    0x21fc468b, 0x21f637be,
-  0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
-    0x21cbcdd3, 0x21c5be5e,
-  0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
-    0x219b4fe5, 0x21953fca,
-  0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
-    0x216accc8, 0x2164bc08,
-  0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
-    0x213a4484, 0x2134331f,
-  0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
-    0x2109b720, 0x2103a518,
-  0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
-    0x20d924a4, 0x20d311f9,
-  0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
-    0x20a88d17, 0x20a279ca,
-  0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
-    0x2077f080, 0x2071dc93,
-  0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
-    0x20474ee8, 0x20413a5b,
-  0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
-    0x2016a856, 0x2010932a,
-  0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
-    0x1fe5fcd0, 0x1fdfe707,
-  0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
-    0x1fb54c60, 0x1faf35f9,
-  0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
-    0x1f84970b, 0x1f7e8009,
-  0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
-    0x1f53dcdb, 0x1f4dc53d,
-  0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
-    0x1f231dd5, 0x1f1d059e,
-  0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
-    0x1ef25a03, 0x1eec4132,
-  0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
-    0x1ec1916a, 0x1ebb7802,
-  0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
-    0x1e90c414, 0x1e8aaa14,
-  0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
-    0x1e5ff206, 0x1e59d770,
-  0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
-    0x1e2f1b4a, 0x1e29001e,
-  0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
-    0x1dfe3fe6, 0x1df82426,
-  0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
-    0x1dcd5fe2, 0x1dc7438e,
-  0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
-    0x1d9c7b45, 0x1d965e5f,
-  0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
-    0x1d6b9217, 0x1d6574a0,
-  0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
-    0x1d3aa460, 0x1d348658,
-  0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
-    0x1d09b227, 0x1d03938f,
-  0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
-    0x1cd8bb74, 0x1cd29c4d,
-  0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
-    0x1ca7c04d, 0x1ca1a099,
-  0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
-    0x1c76c0bc, 0x1c70a07b,
-  0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
-    0x1c45bcc7, 0x1c3f9bf9,
-  0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
-    0x1c14b475, 0x1c0e931d,
-  0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
-    0x1be3a7cf, 0x1bdd85ed,
-  0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
-    0x1bb296dc, 0x1bac7471,
-  0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
-    0x1b8181a4, 0x1b7b5eb0,
-  0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
-    0x1b50682e, 0x1b4a44b3,
-  0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
-    0x1b1f4a81, 0x1b192680,
-  0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
-    0x1aee28a6, 0x1ae8041f,
-  0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
-    0x1abd02a3, 0x1ab6dd98,
-  0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
-    0x1a8bd881, 0x1a85b2f3,
-  0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
-    0x1a5aaa47, 0x1a548436,
-  0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
-    0x1a2977fc, 0x1a23516a,
-  0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
-    0x19f841a9, 0x19f21a96,
-  0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
-    0x19c70754, 0x19c0dfc2,
-  0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
-    0x1995c906, 0x198fa0f5,
-  0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
-    0x196486c6, 0x195e5e37,
-  0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
-    0x1933409b, 0x192d178f,
-  0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
-    0x1901f68d, 0x18fbcd06,
-  0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
-    0x18d0a8a4, 0x18ca7ea2,
-  0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
-    0x189f56e8, 0x18992c6b,
-  0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
-    0x186e015f, 0x1867d66a,
-  0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
-    0x183ca812, 0x18367ca5,
-  0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
-    0x180b4b08, 0x18051f24,
-  0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
-    0x17d9ea49, 0x17d3bdee,
-  0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
-    0x17a885dc, 0x17a2590d,
-  0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
-    0x17771dc9, 0x1770f086,
-  0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
-    0x1745b218, 0x173f8461,
-  0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
-    0x171442d0, 0x170e14a7,
-  0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
-    0x16e2cff9, 0x16dca15f,
-  0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
-    0x16b1599b, 0x16ab2a90,
-  0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
-    0x167fdfbc, 0x1679b042,
-  0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
-    0x164e6266, 0x1648327d,
-  0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
-    0x161ce19e, 0x1616b148,
-  0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
-    0x15eb5d6e, 0x15e52cab,
-  0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
-    0x15b9d5dd, 0x15b3a4ae,
-  0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
-    0x15884af1, 0x15821958,
-  0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
-    0x1556bcb4, 0x15508ab1,
-  0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
-    0x15252b2c, 0x151ef8c0,
-  0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
-    0x14f39662, 0x14ed638e,
-  0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
-    0x14c1fe5c, 0x14bbcb22,
-  0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
-    0x14906323, 0x148a2f82,
-  0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
-    0x145ec4be, 0x145890b9,
-  0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
-    0x142d2335, 0x1426eecb,
-  0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
-    0x13fb7e8f, 0x13f549c3,
-  0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
-    0x13c9d6d4, 0x13c3a1a6,
-  0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
-    0x13982c0d, 0x1391f67d,
-  0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
-    0x13667e3f, 0x13604850,
-  0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
-    0x1334cd74, 0x132e9725,
-  0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
-    0x130319b3, 0x12fce305,
-  0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
-    0x12d16303, 0x12cb2bf8,
-  0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
-    0x129fa96c, 0x12997205,
-  0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
-    0x126decf5, 0x1267b533,
-  0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
-    0x123c2da8, 0x1235f58b,
-  0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
-    0x120a6b8a, 0x12043314,
-  0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
-    0x11d8a6a4, 0x11d26dd6,
-  0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
-    0x11a6defe, 0x11a0a5d8,
-  0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
-    0x1175149e, 0x116edb22,
-  0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
-    0x1143478e, 0x113d0dbc,
-  0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
-    0x111177d4, 0x110b3dad,
-  0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
-    0x10dfa578, 0x10d96afe,
-  0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
-    0x10add082, 0x10a795b5,
-  0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
-    0x107bf8fa, 0x1075bddb,
-  0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
-    0x104a1ee7, 0x1043e377,
-  0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
-    0x10184251, 0x10120691,
-  0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
-    0xfe6633f, 0xfe02730,
-  0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
-    0xfae455d,
-  0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
-    0xf7c611f,
-  0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
-    0xf4a7a7d,
-  0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
-    0xf189180,
-  0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
-    0xee6a62f,
-  0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
-    0xeb4b891,
-  0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
-    0xe82c8af,
-  0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
-    0xe50d690,
-  0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
-    0xe1ee23c,
-  0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
-    0xdecebba,
-  0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
-    0xdbaf313,
-  0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
-    0xd88f84d,
-  0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
-    0xd56fb71,
-  0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
-    0xd24fc87,
-  0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
-    0xcf2fb96,
-  0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
-    0xcc0f8a5,
-  0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
-    0xc8ef3bd,
-  0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
-    0xc5cece5,
-  0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
-    0xc2ae425,
-  0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
-    0xbf8d985,
-  0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
-    0xbc6cd0c,
-  0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
-    0xb94bec2,
-  0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
-    0xb62aeaf,
-  0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
-    0xb309cdb,
-  0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
-    0xafe894d,
-  0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
-    0xacc740c,
-  0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
-    0xa9a5d22,
-  0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
-    0xa684495,
-  0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
-    0xa362a6d,
-  0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
-    0xa040eb1,
-  0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
-    0x9d1f16b,
-  0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
-    0x99fd2a0,
-  0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
-    0x96db25a,
-  0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
-    0x93b90a0,
-  0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
-    0x9096d79,
-  0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
-    0x8d748ed,
-  0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
-    0x8a52304,
-  0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
-    0x872fbc6,
-  0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
-    0x840d33b,
-  0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
-    0x80ea969,
-  0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
-    0x7dc7e5a,
-  0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
-    0x7aa5214,
-  0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
-    0x77824a0,
-  0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
-    0x745f604,
-  0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
-    0x713c64a,
-  0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
-    0x6e19578,
-  0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
-    0x6af6396,
-  0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
-    0x67d30ad,
-  0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
-    0x64afcc3,
-  0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
-    0x618c7e1,
-  0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
-    0x5e6920e,
-  0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
-    0x5b45b53,
-  0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
-    0x58223b6,
-  0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
-    0x54feb3f,
-  0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
-    0x51db1f7,
-  0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
-    0x4eb77e5,
-  0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
-    0x4b93d11,
-  0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
-    0x4870182,
-  0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
-    0x454c541,
-  0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
-    0x4228854,
-  0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
-    0x3f04ac4,
-  0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
-    0x3be0c99,
-  0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
-    0x38bcdda,
-  0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
-    0x3598e8f,
-  0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
-    0x3274ec0,
-  0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
-    0x2f50e74,
-  0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
-    0x2c2cdb4,
-  0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
-    0x2908c87,
-  0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
-    0x25e4af4,
-  0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
-    0x22c0904,
-  0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
-    0x1f9c6be,
-  0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
-    0x1c7842a,
-  0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
-    0x1954150,
-  0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
-    0x162fe37,
-  0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
-    0x130bae7,
-  0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
-    0xfe7769,
-  0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
-    0xcc33c3,
-  0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
-    0x99effe,
-  0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
-    0x67ac21,
-  0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
-    0x356835,
-  0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
-
-};
-
-/**    
- * @brief  Initialization function for the Q31 DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure   
- * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure   
- * @param[in]     N          length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingQ31Table.gif    
- */
-
-arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
-    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  q31_t *pCosFactor[4] =
-    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
-    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT Function */
-  arm_rfft_init_q31(S->pRfft,  S->N, 0, 1);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
deleted file mode 100644
index 38131d5a..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_q15.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 Q15.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the Q15 DCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- *     
- * \par Input an output formats:    
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
- * Number of bits downscaled, depends on the size of the transform.    
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
- *    
- * \image html dct4FormatsQ15Table.gif    
- */
-
-void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer)
-{
-  uint32_t i;                                    /* Loop counter */
-  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
-  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
-  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
-  q15_t in;                                      /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = (uint32_t) S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------    
-  *  Step3: Multiply the FFT output with the weights.    
-  *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.13 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
-  arm_shift_q15(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = ((uint32_t) S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = ((uint32_t) S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = (uint32_t) S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------    
-  *  Step3: Multiply the FFT output with the weights.    
-  *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.13 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
-  arm_shift_q15(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter */
-  i = ((uint32_t) S->N - 1u);
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
deleted file mode 100644
index b8ec1518..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_q31.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 Q31.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the Q31 DCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- * \par Input an output formats:    
- * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,    
- * as the conversion from DCT2 to DCT4 involves one subtraction.    
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
- * Number of bits downscaled, depends on the size of the transform.    
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
- *    
- * \image html dct4FormatsQ31Table.gif    
- */
-
-void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer)
-{
-  uint16_t i;                                    /* Loop counter */
-  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
-  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
-  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
-  q31_t in;                                      /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
-  /*----------------------------------------------------------------------    
-   *  Step3: Multiply the FFT output with the weights.    
-   *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.29 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
-  arm_shift_q31(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = (S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = (S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
-  /*----------------------------------------------------------------------    
-   *  Step3: Multiply the FFT output with the weights.    
-   *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.29 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
-  arm_shift_q31(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* Initializing the loop counter */
-  i = (S->N - 1u);
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
deleted file mode 100644
index b72f8fd9..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_f32.c    
-*    
-* Description:	RFFT & RIFFT Floating point process function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-extern void arm_radix4_butterfly_f32(
-    float32_t * pSrc,
-    uint16_t fftLen,
-    float32_t * pCoef,
-    uint16_t twidCoefModifier);
-
-extern void arm_radix4_butterfly_inverse_f32(
-    float32_t * pSrc,
-    uint16_t fftLen,
-    float32_t * pCoef,
-    uint16_t twidCoefModifier,
-    float32_t onebyfftLen);
-
-extern void arm_bitreversal_f32(
-    float32_t * pSrc,
-    uint16_t fftSize,
-    uint16_t bitRevFactor,
-    uint16_t * pBitRevTab);
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/*--------------------------------------------------------------------    
- *		Internal functions prototypes    
- *--------------------------------------------------------------------*/
-
-void arm_split_rfft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier);
-void arm_split_rifft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier);
-
-/**    
- * @addtogroup RealFFT    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point RFFT/RIFFT.   
- * @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_f32 and will be removed
- * in the future.
- * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.   
- * @param[in]  *pSrc points to the input buffer.   
- * @param[out] *pDst points to the output buffer.   
- * @return none.   
- */
-
-void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst)
-{
-  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
-
-
-  /* Calculation of Real IFFT of input */
-  if(S->ifftFlagR == 1u)
-  {
-    /*  Real IFFT core process */
-    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
-
-    /* Complex radix-4 IFFT process */
-    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
-                                     S_CFFT->pTwiddle,
-                                     S_CFFT->twidCoefModifier,
-                                     S_CFFT->onebyfftLen);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-  }
-  else
-  {
-
-    /* Calculation of RFFT of input */
-
-    /* Complex radix-4 FFT process */
-    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
-                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-
-
-    /*  Real FFT core process */
-    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-  }
-
-}
-
-/**    
-   * @} end of RealFFT group    
-   */
-
-/**    
- * @brief  Core Real FFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  			length of FFT.    
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
- * @param[out]  *pDst 				points to the output buffer.    
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- */
-
-void arm_split_rfft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier)
-{
-  uint32_t i;                                    /* Loop Counter */
-  float32_t outR, outI;                          /* Temporary variables for output */
-  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
-  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
-  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
-  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
-
-  /* Init coefficient pointers */
-  pCoefA = &pATable[modifier * 2u];
-  pCoefB = &pBTable[modifier * 2u];
-
-  i = fftLen - 1u;
-
-  while(i > 0u)
-  {
-    /*    
-       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-    /* read pATable[2 * i] */
-    CoefA1 = *pCoefA++;
-    /* pATable[2 * i + 1] */
-    CoefA2 = *pCoefA;
-
-    /* pSrc[2 * i] * pATable[2 * i] */
-    outR = *pSrc1 * CoefA1;
-    /* pSrc[2 * i] * CoefA2 */
-    outI = *pSrc1++ * CoefA2;
-
-    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
-    outR -= (*pSrc1 + *pSrc2) * CoefA2;
-    /* pSrc[2 * i + 1] * CoefA1 */
-    outI += *pSrc1++ * CoefA1;
-
-    CoefB1 = *pCoefB;
-
-    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
-    outI -= *pSrc2-- * CoefB1;
-    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
-    outI -= *pSrc2 * CoefA2;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
-    outR += *pSrc2-- * CoefB1;
-
-    /* write output */
-    *pDst1++ = outR;
-    *pDst1++ = outI;
-
-    /* write complex conjugate output */
-    *pDst2-- = -outI;
-    *pDst2-- = outR;
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    i--;
-
-  }
-
-  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
-  pDst[(2u * fftLen) + 1u] = 0.0f;
-
-  pDst[0] = pSrc[0] + pSrc[1];
-  pDst[1] = 0.0f;
-
-}
-
-
-/**    
- * @brief  Core Real IFFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  			length of FFT.   
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
- * @param[out]  *pDst 				points to the output buffer.   
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.    
- * @return none.    
- */
-
-void arm_split_rifft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier)
-{
-  float32_t outR, outI;                          /* Temporary variables for output */
-  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
-  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
-  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
-
-  pCoefA = &pATable[0];
-  pCoefB = &pBTable[0];
-
-  while(fftLen > 0u)
-  {
-    /*    
-       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
-
-     */
-
-    CoefA1 = *pCoefA++;
-    CoefA2 = *pCoefA;
-
-    /* outR = (pSrc[2 * i] * CoefA1 */
-    outR = *pSrc1 * CoefA1;
-
-    /* - pSrc[2 * i] * CoefA2 */
-    outI = -(*pSrc1++) * CoefA2;
-
-    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
-    outR += (*pSrc1 + *pSrc2) * CoefA2;
-
-    /* pSrc[2 * i + 1] * CoefA1 */
-    outI += (*pSrc1++) * CoefA1;
-
-    CoefB1 = *pCoefB;
-
-    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
-    outI -= *pSrc2-- * CoefB1;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
-    outR += *pSrc2 * CoefB1;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
-    outI += *pSrc2-- * CoefA2;
-
-    /* write output */
-    *pDst++ = outR;
-    *pDst++ = outI;
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    /* Decrement loop count */
-    fftLen--;
-  }
-
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
deleted file mode 100644
index d4970b6b..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_rfft_f32.c
-*
-* Description:	RFFT & RIFFT Floating point process function
-*
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-void stage_rfft_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut)
-{
-   uint32_t  k;								   /* Loop Counter                     */
-   float32_t twR, twI;						   /* RFFT Twiddle coefficients        */
-   float32_t * pCoeff = S->pTwiddleRFFT;  /* Points to RFFT Twiddle factors   */
-   float32_t *pA = p;						   /* increasing pointer               */
-   float32_t *pB = p;						   /* decreasing pointer               */
-   float32_t xAR, xAI, xBR, xBI;				/* temporary variables              */
-   float32_t t1a, t1b;				         /* temporary variables              */
-   float32_t p0, p1, p2, p3;				   /* temporary variables              */
-
-
-   k = (S->Sint).fftLen - 1;					
-
-   /* Pack first and last sample of the frequency domain together */
-
-   xBR = pB[0];
-   xBI = pB[1];
-   xAR = pA[0];
-   xAI = pA[1];
-
-   twR = *pCoeff++ ;
-   twI = *pCoeff++ ;
-   
-   // U1 = XA(1) + XB(1); % It is real
-   t1a = xBR + xAR  ;
-   
-   // U2 = XB(1) - XA(1); % It is imaginary
-   t1b = xBI + xAI  ;
-
-   // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
-   // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
-   *pOut++ = 0.5f * ( t1a + t1b );
-   *pOut++ = 0.5f * ( t1a - t1b );
-
-   // XA(1) = 1/2*( U1 - imag(U2) +  i*( U1 +imag(U2) ));
-   pB  = p + 2*k;
-   pA += 2;
-
-   do
-   {
-      /*
-         function X = my_split_rfft(X, ifftFlag)
-         % X is a series of real numbers
-         L  = length(X);
-         XC = X(1:2:end) +i*X(2:2:end);
-         XA = fft(XC);
-         XB = conj(XA([1 end:-1:2]));
-         TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
-         for l = 2:L/2
-            XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
-         end
-         XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
-         X = XA;
-      */
-
-      xBI = pB[1];
-      xBR = pB[0];
-      xAR = pA[0];
-      xAI = pA[1];
-
-      twR = *pCoeff++;
-      twI = *pCoeff++;
-
-      t1a = xBR - xAR ;
-      t1b = xBI + xAI ;
-
-      // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
-      // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
-      p0 = twR * t1a;
-      p1 = twI * t1a;
-      p2 = twR * t1b;
-      p3 = twI * t1b;
-
-      *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
-      *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
-
-      pA += 2;
-      pB -= 2;
-      k--;
-   } while(k > 0u);
-}
-
-/* Prepares data for inverse cfft */
-void merge_rfft_f32(
-arm_rfft_fast_instance_f32 * S,
-float32_t * p, float32_t * pOut)
-{
-   uint32_t  k;								/* Loop Counter                     */
-   float32_t twR, twI;						/* RFFT Twiddle coefficients        */
-   float32_t *pCoeff = S->pTwiddleRFFT;		/* Points to RFFT Twiddle factors   */
-   float32_t *pA = p;						/* increasing pointer               */
-   float32_t *pB = p;						/* decreasing pointer               */
-   float32_t xAR, xAI, xBR, xBI;			/* temporary variables              */
-   float32_t t1a, t1b, r, s, t, u;			/* temporary variables              */
-
-   k = (S->Sint).fftLen - 1;					
-
-   xAR = pA[0];
-   xAI = pA[1];
-
-   pCoeff += 2 ;
-
-   *pOut++ = 0.5f * ( xAR + xAI );
-   *pOut++ = 0.5f * ( xAR - xAI );
-
-   pB  =  p + 2*k ;
-   pA +=  2	   ;
-
-   while(k > 0u)
-   {
-      /* G is half of the frequency complex spectrum */
-      //for k = 2:N
-      //    Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
-      xBI =   pB[1]    ;
-      xBR =   pB[0]    ;
-      xAR =  pA[0];
-      xAI =  pA[1];
-
-      twR = *pCoeff++;
-      twI = *pCoeff++;
-
-      t1a = xAR - xBR ;
-      t1b = xAI + xBI ;
-
-      r = twR * t1a;
-      s = twI * t1b;
-      t = twI * t1a;
-      u = twR * t1b;
-
-      // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
-      // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
-      *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
-      *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
-
-      pA += 2;
-      pB -= 2;
-      k--;
-   }
-
-}
-
-/**
-* @ingroup groupTransforms
-*/
-
-/**
- * @defgroup Fast Real FFT Functions
- *
- * \par
- * The CMSIS DSP library includes specialized algorithms for computing the
- * FFT of real data sequences.  The FFT is defined over complex data but
- * in many applications the input is real.  Real FFT algorithms take advantage
- * of the symmetry properties of the FFT and have a speed advantage over complex
- * algorithms of the same length.
- * \par
- * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
- * \par
- * The real length N forward FFT of a sequence is computed using the steps shown below.
- * \par
- * \image html RFFT.gif "Real Fast Fourier Transform"
- * \par
- * The real sequence is initially treated as if it were complex to perform a CFFT.
- * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
- * in complex format. Except the first complex number that contains the two real numbers
- * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
- * contains two real values packed.
- * \par
- * The input for the inverse RFFT should keep the same format as the output of the 
- * forward RFFT. A first processing stage pre-process the data to later perform an
- * inverse CFFT.
- * \par    
- * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"    
- * \par    
- * The algorithms for floating-point, Q15, and Q31 data are slightly different
- * and we describe each algorithm in turn.
- * \par Floating-point
- * The main functions are arm_rfft_fast_f32()
- * and arm_rfft_fast_init_f32().  The older functions
- * arm_rfft_f32() and arm_rfft_init_f32() have been
- * deprecated but are still documented.
- * \par
- * The FFT of a real N-point sequence has even symmetry in the frequency
- * domain.  The second half of the data equals the conjugate of the first half
- * flipped in frequency:
- * 
- *X[0] - real data
- *X[1] - complex data
- *X[2] - complex data
- *... 
- *X[fftLen/2-1] - complex data
- *X[fftLen/2] - real data
- *X[fftLen/2+1] - conjugate of X[fftLen/2-1]
- *X[fftLen/2+2] - conjugate of X[fftLen/2-2]
- *... 
- *X[fftLen-1] - conjugate of X[1]
- * 

- * Looking at the data, we see that we can uniquely represent the FFT using only
- * 
- *N/2+1 samples:
- *X[0] - real data
- *X[1] - complex data
- *X[2] - complex data
- *... 
- *X[fftLen/2-1] - complex data
- *X[fftLen/2] - real data
- * 

- * Looking more closely we see that the first and last samples are real valued.
- * They can be packed together and we can thus represent the FFT of an N-point
- * real sequence by N/2 complex values:
- * 
- *X[0],X[N/2] - packed real data: X[0] + jX[N/2]
- *X[1] - complex data
- *X[2] - complex data
- *... 
- *X[fftLen/2-1] - complex data
- * 

- * The real FFT functions pack the frequency domain data in this fashion.  The
- * forward transform outputs the data in this form and the inverse transform
- * expects input data in this form.  The function always performs the needed
- * bitreversal so that the input and output data is always in normal order.  The 
- * functions support lengths of [32, 64, 128, ..., 4096] samples.
- * \par
- * The forward and inverse real FFT functions apply the standard FFT scaling; no
- * scaling on the forward transform and 1/fftLen scaling on the inverse
- * transform.
- * \par Q15 and Q31
- * The real algorithms are defined in a similar manner and utilize N/2 complex
- * transforms behind the scenes.  
- * \par
- * The complex transforms used internally include scaling to prevent fixed-point
- * overflows.  The overall scaling equals 1/(fftLen/2).
- * \par
- * A separate instance structure must be defined for each transform used but 
- * twiddle factor and bit reversal tables can be reused.
- * \par
- * There is also an associated initialization function for each data type. 
- * The initialization function performs the following operations:
- * - Sets the values of the internal structure fields.   
- * - Initializes twiddle factor table and bit reversal table pointers.
- * - Initializes the internal complex FFT data structure.
- * \par   
- * Use of the initialization function is optional.   
- * However, if the initialization function is used, then the instance structure 
- * cannot be placed into a const data section. To place an instance structure 
- * into a const data section, the instance structure should be manually 
- * initialized as follows:
- * 
- *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
- *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
- * 

- * where fftLenReal is the length of the real transform;
- * fftLenBy2 length of  the internal complex transform.
- * ifftFlagR Selects forward (=0) or inverse (=1) transform.
- * bitReverseFlagR Selects bit reversed output (=0) or normal order
- * output (=1).
- * twidCoefRModifier stride modifier for the twiddle factor table.
- * The value is based on the FFT length;
- * pTwiddleARealpoints to the A array of twiddle coefficients; 
- * pTwiddleBRealpoints to the B array of twiddle coefficients;    
- * pCfft points to the CFFT Instance structure. The CFFT structure
- * must also be initialized.  Refer to arm_cfft_radix4_f32() for details regarding    
- * static initialization of the complex FFT instance structure.    
- */
-
-/**
-* @addtogroup RealFFT
-* @{
-*/
-
-/**
-* @brief Processing function for the floating-point real FFT.
-* @param[in]  *S              points to an arm_rfft_fast_instance_f32 structure.
-* @param[in]  *p              points to the input buffer.
-* @param[in]  *pOut           points to the output buffer.
-* @param[in]  ifftFlag        RFFT if flag is 0, RIFFT if flag is 1
-* @return none.
-*/
-
-void arm_rfft_fast_f32(
-arm_rfft_fast_instance_f32 * S,
-float32_t * p, float32_t * pOut,
-uint8_t ifftFlag)
-{
-   arm_cfft_instance_f32 * Sint = &(S->Sint);
-   Sint->fftLen = S->fftLenRFFT / 2;
-
-   /* Calculation of Real FFT */
-   if(ifftFlag)
-   {
-      /*  Real FFT compression */
-      merge_rfft_f32(S, p, pOut);
-
-      /* Complex radix-4 IFFT process */
-      arm_cfft_f32( Sint, pOut, ifftFlag, 1);
-   }
-   else
-   {
-      /* Calculation of RFFT of input */
-      arm_cfft_f32( Sint, p, ifftFlag, 1);
-   
-      /*  Real FFT extraction */
-      stage_rfft_f32(S, p, pOut);
-   }
-}
-
-/**    
-* @} end of RealFFT group    
-*/
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
deleted file mode 100644
index ba66980d..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_init_f32.c   
-*    
-* Description:	Split Radix Decimation in Frequency CFFT Floating point processing function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup RealFFT   
- * @{   
- */
-
-/**   
-* @brief  Initialization function for the floating-point real FFT.  
-* @param[in,out] *S             points to an arm_rfft_fast_instance_f32 structure.
-* @param[in]     fftLen         length of the Real Sequence.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter fftLen	Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-arm_status arm_rfft_fast_init_f32(
-  arm_rfft_fast_instance_f32 * S,
-  uint16_t fftLen)
-{
-  arm_cfft_instance_f32 * Sint;
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-  /*  Initialise the FFT length */
-  Sint = &(S->Sint);
-  Sint->fftLen = fftLen/2;
-  S->fftLenRFFT = fftLen;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (Sint->fftLen)
-  {
-  case 2048u:
-    /*  Initializations of structure parameters for 2048 point FFT */
-    /*  Initialise the bit reversal table length */
-    Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;
-    /*  Initialise the bit reversal table pointer */
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
-    /*  Initialise the Twiddle coefficient pointers */
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_2048;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_4096;
-    break;
-  case 1024u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_1024;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_2048;
-    break;
-  case 512u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_512;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_1024;
-    break;
-  case 256u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_256;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_512;
-    break;
-  case 128u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_128;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_256;
-    break;
-  case 64u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_64;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_128;
-    break;
-  case 32u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_32;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_64;
-    break;
-  case 16u:
-    Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;
-    Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
-		Sint->pTwiddle     = (float32_t *) twiddleCoef_16;
-		S->pTwiddleRFFT    = (float32_t *) twiddleCoef_rfft_32;
-    break;
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**   
- * @} end of RealFFT group   
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
deleted file mode 100644
index b9b50049..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
+++ /dev/null
@@ -1,8376 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_f32.c    
-*    
-* Description:	RFFT & RIFFT Floating point initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup RealFFT    
- * @{    
- */
-
-/**    
-* \par    
-* Generation of realCoefA array:    
-* \par    
-* 	n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-*/
-
-
-
-static const float32_t realCoefA[8192] = {
-  0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
-    -0.499999850988388f,
-  0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
-    -0.499998688697815f,
-  0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
-    -0.499996334314346f,
-  0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
-    -0.499992787837982f,
-  0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
-    -0.499988079071045f,
-  0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
-    -0.499982208013535f,
-  0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
-    -0.499975144863129f,
-  0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
-    -0.499966919422150f,
-  0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
-    -0.499957501888275f,
-  0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
-    -0.499946922063828f,
-  0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
-    -0.499935150146484f,
-  0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
-    -0.499922215938568f,
-  0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
-    -0.499908089637756f,
-  0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
-    -0.499892801046371f,
-  0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
-    -0.499876320362091f,
-  0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
-    -0.499858677387238f,
-  0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
-    -0.499839842319489f,
-  0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
-    -0.499819844961166f,
-  0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
-    -0.499798685312271f,
-  0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
-    -0.499776333570480f,
-  0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
-    -0.499752789735794f,
-  0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
-    -0.499728083610535f,
-  0.483129411935806f, -0.499715298414230f, 0.482746154069901f,
-    -0.499702215194702f,
-  0.482362866401672f, -0.499688833951950f, 0.481979638338089f,
-    -0.499675154685974f,
-  0.481596380472183f, -0.499661177396774f, 0.481213152408600f,
-    -0.499646931886673f,
-  0.480829954147339f, -0.499632388353348f, 0.480446726083755f,
-    -0.499617516994476f,
-  0.480063527822495f, -0.499602377414703f, 0.479680359363556f,
-    -0.499586939811707f,
-  0.479297190904617f, -0.499571204185486f, 0.478914022445679f,
-    -0.499555170536041f,
-  0.478530883789063f, -0.499538868665695f, 0.478147745132446f,
-    -0.499522238969803f,
-  0.477764606475830f, -0.499505341053009f, 0.477381497621536f,
-    -0.499488145112991f,
-  0.476998418569565f, -0.499470651149750f, 0.476615339517593f,
-    -0.499452859163284f,
-  0.476232260465622f, -0.499434769153595f, 0.475849211215973f,
-    -0.499416410923004f,
-  0.475466161966324f, -0.499397724866867f, 0.475083142518997f,
-    -0.499378770589828f,
-  0.474700123071671f, -0.499359518289566f, 0.474317133426666f,
-    -0.499339967966080f,
-  0.473934143781662f, -0.499320119619370f, 0.473551183938980f,
-    -0.499299973249435f,
-  0.473168224096298f, -0.499279528856277f, 0.472785294055939f,
-    -0.499258816242218f,
-  0.472402364015579f, -0.499237775802612f, 0.472019463777542f,
-    -0.499216467142105f,
-  0.471636593341827f, -0.499194860458374f, 0.471253722906113f,
-    -0.499172955751419f,
-  0.470870882272720f, -0.499150782823563f, 0.470488041639328f,
-    -0.499128282070160f,
-  0.470105201005936f, -0.499105513095856f, 0.469722419977188f,
-    -0.499082416296005f,
-  0.469339638948441f, -0.499059051275253f, 0.468956857919693f,
-    -0.499035388231277f,
-  0.468574106693268f, -0.499011427164078f, 0.468191385269165f,
-    -0.498987197875977f,
-  0.467808693647385f, -0.498962640762329f, 0.467426002025604f,
-    -0.498937815427780f,
-  0.467043310403824f, -0.498912662267685f, 0.466660678386688f,
-    -0.498887240886688f,
-  0.466278046369553f, -0.498861521482468f, 0.465895414352417f,
-    -0.498835533857346f,
-  0.465512841939926f, -0.498809218406677f, 0.465130269527435f,
-    -0.498782604932785f,
-  0.464747726917267f, -0.498755723237991f, 0.464365184307098f,
-    -0.498728543519974f,
-  0.463982671499252f, -0.498701065778732f, 0.463600188493729f,
-    -0.498673290014267f,
-  0.463217705488205f, -0.498645216226578f, 0.462835282087326f,
-    -0.498616874217987f,
-  0.462452858686447f, -0.498588204383850f, 0.462070435285568f,
-    -0.498559266328812f,
-  0.461688071489334f, -0.498530030250549f, 0.461305707693100f,
-    -0.498500496149063f,
-  0.460923373699188f, -0.498470664024353f, 0.460541069507599f,
-    -0.498440563678741f,
-  0.460158795118332f, -0.498410135507584f, 0.459776520729065f,
-    -0.498379439115524f,
-  0.459394276142120f, -0.498348444700241f, 0.459012061357498f,
-    -0.498317152261734f,
-  0.458629876375198f, -0.498285561800003f, 0.458247691392899f,
-    -0.498253703117371f,
-  0.457865566015244f, -0.498221516609192f, 0.457483440637589f,
-    -0.498189061880112f,
-  0.457101345062256f, -0.498156309127808f, 0.456719279289246f,
-    -0.498123258352280f,
-  0.456337243318558f, -0.498089909553528f, 0.455955207347870f,
-    -0.498056292533875f,
-  0.455573230981827f, -0.498022347688675f, 0.455191254615784f,
-    -0.497988134622574f,
-  0.454809308052063f, -0.497953623533249f, 0.454427421092987f,
-    -0.497918814420700f,
-  0.454045534133911f, -0.497883707284927f, 0.453663676977158f,
-    -0.497848302125931f,
-  0.453281819820404f, -0.497812628746033f, 0.452900022268295f,
-    -0.497776657342911f,
-  0.452518254518509f, -0.497740387916565f, 0.452136516571045f,
-    -0.497703820466995f,
-  0.451754778623581f, -0.497666954994202f, 0.451373100280762f,
-    -0.497629791498184f,
-  0.450991421937943f, -0.497592359781265f, 0.450609803199768f,
-    -0.497554630041122f,
-  0.450228184461594f, -0.497516602277756f, 0.449846625328064f,
-    -0.497478276491165f,
-  0.449465066194534f, -0.497439652681351f, 0.449083566665649f,
-    -0.497400760650635f,
-  0.448702067136765f, -0.497361570596695f, 0.448320597410202f,
-    -0.497322082519531f,
-  0.447939187288284f, -0.497282296419144f, 0.447557777166367f,
-    -0.497242212295532f,
-  0.447176426649094f, -0.497201830148697f, 0.446795076131821f,
-    -0.497161179780960f,
-  0.446413785219193f, -0.497120231389999f, 0.446032524108887f,
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-  0.469339638948441f, 0.499059051275253f, 0.469722419977188f,
-    0.499082416296005f,
-  0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
-    0.499128282070160f,
-  0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
-    0.499172955751419f,
-  0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
-    0.499216467142105f,
-  0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
-    0.499258816242218f,
-  0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
-    0.499299973249435f,
-  0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
-    0.499339967966080f,
-  0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
-    0.499378770589828f,
-  0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
-    0.499416410923004f,
-  0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
-    0.499452859163284f,
-  0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
-    0.499488145112991f,
-  0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
-    0.499522238969803f,
-  0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
-    0.499555170536041f,
-  0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
-    0.499586939811707f,
-  0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
-    0.499617516994476f,
-  0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
-    0.499646931886673f,
-  0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
-    0.499675154685974f,
-  0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
-    0.499702215194702f,
-  0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
-    0.499728083610535f,
-  0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
-    0.499752789735794f,
-  0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
-    0.499776333570480f,
-  0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
-    0.499798685312271f,
-  0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
-    0.499819844961166f,
-  0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
-    0.499839842319489f,
-  0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
-    0.499858677387238f,
-  0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
-    0.499876320362091f,
-  0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
-    0.499892801046371f,
-  0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
-    0.499908089637756f,
-  0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
-    0.499922215938568f,
-  0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
-    0.499935150146484f,
-  0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
-    0.499946922063828f,
-  0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
-    0.499957501888275f,
-  0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
-    0.499966919422150f,
-  0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
-    0.499975144863129f,
-  0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
-    0.499982208013535f,
-  0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
-    0.499988079071045f,
-  0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
-    0.499992787837982f,
-  0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
-    0.499996334314346f,
-  0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
-    0.499998688697815f,
-  0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
-    0.499999850988388f,
-};
-
-
-/**    
-* \par   
-* Generation of realCoefB array:    
-* \par   
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-*    
-*/
-static const float32_t realCoefB[8192] = {
-  0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
-    0.499999850988388f,
-  0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
-    0.499998688697815f,
-  0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
-    0.499996334314346f,
-  0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
-    0.499992787837982f,
-  0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
-    0.499988079071045f,
-  0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
-    0.499982208013535f,
-  0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
-    0.499975144863129f,
-  0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
-    0.499966919422150f,
-  0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
-    0.499957501888275f,
-  0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
-    0.499946922063828f,
-  0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
-    0.499935150146484f,
-  0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
-    0.499922215938568f,
-  0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
-    0.499908089637756f,
-  0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
-    0.499892801046371f,
-  0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
-    0.499876320362091f,
-  0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
-    0.499858677387238f,
-  0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
-    0.499839842319489f,
-  0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
-    0.499819844961166f,
-  0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
-    0.499798685312271f,
-  0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
-    0.499776333570480f,
-  0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
-    0.499752789735794f,
-  0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
-    0.499728083610535f,
-  0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
-    0.499702215194702f,
-  0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
-    0.499675154685974f,
-  0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
-    0.499646931886673f,
-  0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
-    0.499617516994476f,
-  0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
-    0.499586939811707f,
-  0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
-    0.499555170536041f,
-  0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
-    0.499522238969803f,
-  0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
-    0.499488145112991f,
-  0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
-    0.499452859163284f,
-  0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
-    0.499416410923004f,
-  0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
-    0.499378770589828f,
-  0.525299847126007f, 0.499359518289566f, 0.525682866573334f,
-    0.499339967966080f,
-  0.526065826416016f, 0.499320119619370f, 0.526448845863342f,
-    0.499299973249435f,
-  0.526831746101379f, 0.499279528856277f, 0.527214705944061f,
-    0.499258816242218f,
-  0.527597606182098f, 0.499237775802612f, 0.527980506420136f,
-    0.499216467142105f,
-  0.528363406658173f, 0.499194860458374f, 0.528746306896210f,
-    0.499172955751419f,
-  0.529129147529602f, 0.499150782823563f, 0.529511988162994f,
-    0.499128282070160f,
-  0.529894769191742f, 0.499105513095856f, 0.530277609825134f,
-    0.499082416296005f,
-  0.530660390853882f, 0.499059051275253f, 0.531043112277985f,
-    0.499035388231277f,
-  0.531425893306732f, 0.499011427164078f, 0.531808614730835f,
-    0.498987197875977f,
-  0.532191336154938f, 0.498962640762329f, 0.532573997974396f,
-    0.498937815427780f,
-  0.532956659793854f, 0.498912662267685f, 0.533339321613312f,
-    0.498887240886688f,
-  0.533721983432770f, 0.498861521482468f, 0.534104585647583f,
-    0.498835533857346f,
-  0.534487187862396f, 0.498809218406677f, 0.534869730472565f,
-    0.498782604932785f,
-  0.535252273082733f, 0.498755723237991f, 0.535634815692902f,
-    0.498728543519974f,
-  0.536017298698425f, 0.498701065778732f, 0.536399841308594f,
-    0.498673290014267f,
-  0.536782264709473f, 0.498645216226578f, 0.537164747714996f,
-    0.498616874217987f,
-  0.537547171115875f, 0.498588204383850f, 0.537929534912109f,
-    0.498559266328812f,
-  0.538311958312988f, 0.498530030250549f, 0.538694262504578f,
-    0.498500496149063f,
-  0.539076626300812f, 0.498470664024353f, 0.539458930492401f,
-    0.498440563678741f,
-  0.539841234683990f, 0.498410135507584f, 0.540223479270935f,
-    0.498379439115524f,
-  0.540605723857880f, 0.498348444700241f, 0.540987968444824f,
-    0.498317152261734f,
-  0.541370153427124f, 0.498285561800003f, 0.541752278804779f,
-    0.498253703117371f,
-  0.542134463787079f, 0.498221516609192f, 0.542516589164734f,
-    0.498189061880112f,
-  0.542898654937744f, 0.498156309127808f, 0.543280720710754f,
-    0.498123258352280f,
-  0.543662786483765f, 0.498089909553528f, 0.544044792652130f,
-    0.498056292533875f,
-  0.544426798820496f, 0.498022347688675f, 0.544808745384216f,
-    0.497988134622574f,
-  0.545190691947937f, 0.497953623533249f, 0.545572578907013f,
-    0.497918814420700f,
-  0.545954465866089f, 0.497883707284927f, 0.546336352825165f,
-    0.497848302125931f,
-  0.546718180179596f, 0.497812628746033f, 0.547099947929382f,
-    0.497776657342911f,
-  0.547481775283813f, 0.497740387916565f, 0.547863483428955f,
-    0.497703820466995f,
-  0.548245191574097f, 0.497666954994202f, 0.548626899719238f,
-    0.497629791498184f,
-  0.549008548259735f, 0.497592359781265f, 0.549390196800232f,
-    0.497554630041122f,
-  0.549771785736084f, 0.497516602277756f, 0.550153374671936f,
-    0.497478276491165f,
-  0.550534904003143f, 0.497439652681351f, 0.550916433334351f,
-    0.497400760650635f,
-  0.551297962665558f, 0.497361570596695f, 0.551679372787476f,
-    0.497322082519531f,
-  0.552060842514038f, 0.497282296419144f, 0.552442193031311f,
-    0.497242212295532f,
-  0.552823603153229f, 0.497201830148697f, 0.553204894065857f,
-    0.497161179780960f,
-  0.553586184978485f, 0.497120231389999f, 0.553967475891113f,
-    0.497078984975815f,
-  0.554348707199097f, 0.497037440538406f, 0.554729938507080f,
-    0.496995598077774f,
-  0.555111110210419f, 0.496953487396240f, 0.555492222309113f,
-    0.496911078691483f,
-  0.555873334407806f, 0.496868371963501f, 0.556254446506500f,
-    0.496825367212296f,
-  0.556635499000549f, 0.496782064437866f, 0.557016491889954f,
-    0.496738493442535f,
-  0.557397484779358f, 0.496694594621658f, 0.557778418064117f,
-    0.496650427579880f,
-  0.558159291744232f, 0.496605962514877f, 0.558540165424347f,
-    0.496561229228973f,
-  0.558921039104462f, 0.496516168117523f, 0.559301853179932f,
-    0.496470838785172f,
-  0.559682607650757f, 0.496425211429596f, 0.560063362121582f,
-    0.496379286050797f,
-  0.560444056987762f, 0.496333062648773f, 0.560824692249298f,
-    0.496286571025848f,
-  0.561205327510834f, 0.496239781379700f, 0.561585903167725f,
-    0.496192663908005f,
-  0.561966478824615f, 0.496145308017731f, 0.562346994876862f,
-    0.496097624301910f,
-  0.562727510929108f, 0.496049642562866f, 0.563107967376709f,
-    0.496001392602921f,
-  0.563488364219666f, 0.495952844619751f, 0.563868701457977f,
-    0.495903998613358f,
-  0.564249038696289f, 0.495854884386063f, 0.564629375934601f,
-    0.495805442333221f,
-  0.565009593963623f, 0.495755732059479f, 0.565389811992645f,
-    0.495705723762512f,
-  0.565770030021667f, 0.495655417442322f, 0.566150128841400f,
-    0.495604842901230f,
-  0.566530287265778f, 0.495553970336914f, 0.566910326480865f,
-    0.495502769947052f,
-  0.567290365695953f, 0.495451331138611f, 0.567670345306396f,
-    0.495399564504623f,
-  0.568050265312195f, 0.495347499847412f, 0.568430185317993f,
-    0.495295166969299f,
-  0.568810045719147f, 0.495242536067963f, 0.569189906120300f,
-    0.495189607143402f,
-  0.569569647312164f, 0.495136409997940f, 0.569949388504028f,
-    0.495082914829254f,
-  0.570329129695892f, 0.495029091835022f, 0.570708811283112f,
-    0.494975030422211f,
-  0.571088373661041f, 0.494920641183853f, 0.571467995643616f,
-    0.494865983724594f,
-  0.571847498416901f, 0.494810998439789f, 0.572227001190186f,
-    0.494755744934082f,
-  0.572606444358826f, 0.494700223207474f, 0.572985887527466f,
-    0.494644373655319f,
-  0.573365211486816f, 0.494588255882263f, 0.573744535446167f,
-    0.494531840085983f,
-  0.574123859405518f, 0.494475126266479f, 0.574503064155579f,
-    0.494418144226074f,
-  0.574882268905640f, 0.494360834360123f, 0.575261414051056f,
-    0.494303256273270f,
-  0.575640499591827f, 0.494245409965515f, 0.576019585132599f,
-    0.494187235832214f,
-  0.576398611068726f, 0.494128793478012f, 0.576777577400208f,
-    0.494070053100586f,
-  0.577156484127045f, 0.494011014699936f, 0.577535390853882f,
-    0.493951678276062f,
-  0.577914178371429f, 0.493892073631287f, 0.578292965888977f,
-    0.493832170963287f,
-  0.578671753406525f, 0.493771970272064f, 0.579050421714783f,
-    0.493711471557617f,
-  0.579429090023041f, 0.493650704622269f, 0.579807698726654f,
-    0.493589639663696f,
-  0.580186247825623f, 0.493528276681900f, 0.580564737319946f,
-    0.493466645479202f,
-  0.580943167209625f, 0.493404686450958f, 0.581321597099304f,
-    0.493342459201813f,
-  0.581699967384338f, 0.493279963731766f, 0.582078278064728f,
-    0.493217140436172f,
-  0.582456588745117f, 0.493154048919678f, 0.582834780216217f,
-    0.493090659379959f,
-  0.583212971687317f, 0.493026971817017f, 0.583591103553772f,
-    0.492963016033173f,
-  0.583969175815582f, 0.492898762226105f, 0.584347188472748f,
-    0.492834210395813f,
-  0.584725141525269f, 0.492769360542297f, 0.585103094577789f,
-    0.492704242467880f,
-  0.585480928421021f, 0.492638826370239f, 0.585858762264252f,
-    0.492573112249374f,
-  0.586236536502838f, 0.492507129907608f, 0.586614251136780f,
-    0.492440819740295f,
-  0.586991965770721f, 0.492374241352081f, 0.587369561195374f,
-    0.492307394742966f,
-  0.587747097015381f, 0.492240220308304f, 0.588124632835388f,
-    0.492172777652740f,
-  0.588502109050751f, 0.492105036973953f, 0.588879525661469f,
-    0.492037028074265f,
-  0.589256882667542f, 0.491968721151352f, 0.589634180068970f,
-    0.491900116205215f,
-  0.590011477470398f, 0.491831213235855f, 0.590388655662537f,
-    0.491762012243271f,
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-  0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
-    -0.499966919422150f,
-  0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
-    -0.499975144863129f,
-  0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
-    -0.499982208013535f,
-  0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
-    -0.499988079071045f,
-  0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
-    -0.499992787837982f,
-  0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
-    -0.499996334314346f,
-  0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
-    -0.499998688697815f,
-  0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
-    -0.499999850988388f,
-};
-
-
-
-/**    
-* @brief  Initialization function for the floating-point RFFT/RIFFT.   
-* @deprecated Do not use this function.  It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
-* in the future.
-* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.   
-* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.   
-* @param[in]     fftLenReal     length of the FFT.   
-* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    
-* This function also initializes Twiddle factor table.     
-*/
-
-arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag)
-{
-
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialize the Real FFT length */
-  S->fftLenReal = (uint16_t) fftLenReal;
-
-  /*  Initialize the Complex FFT length */
-  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
-
-  /*  Initialize the Twiddle coefficientA pointer */
-  S->pTwiddleAReal = (float32_t *) realCoefA;
-
-  /*  Initialize the Twiddle coefficientB pointer */
-  S->pTwiddleBReal = (float32_t *) realCoefB;
-
-  /*  Initialize the Flag for selection of RFFT or RIFFT */
-  S->ifftFlagR = (uint8_t) ifftFlagR;
-
-  /*  Initialize the Flag for calculation Bit reversal or not */
-  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLenReal)
-  {
-    /* Init table modifier value */
-  case 8192u:
-    S->twidCoefRModifier = 1u;
-    break;
-  case 2048u:
-    S->twidCoefRModifier = 4u;
-    break;
-  case 512u:
-    S->twidCoefRModifier = 16u;
-    break;
-  case 128u:
-    S->twidCoefRModifier = 64u;
-    break;
-  default:
-    /*  Reporting argument error if rfftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  /* Init Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  if(S->ifftFlagR)
-  {
-    /* Initializes the CIFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
-  }
-  else
-  {
-    /* Initializes the CFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
-  }
-
-  /* return the status of RFFT Init function */
-  return (status);
-
-}
-
-  /**    
-   * @} end of RealFFT group    
-   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
deleted file mode 100644
index 31b97b49..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
+++ /dev/null
@@ -1,2235 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_q15.c    
-*    
-* Description:	RFFT & RIFFT Q15 initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include "arm_const_structs.h"
-
-/**    
-* @ingroup groupTransforms    
-*/
-
-/**    
-* @addtogroup RealFFT    
-* @{    
-*/
-
-
-
-/**    
-* \par    
-* Generation fixed-point realCoefAQ15 array in Q15 format:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-* \par    
-* Convert to fixed point Q15 format    
-*       round(pATable[i] * pow(2, 15))    
-*/
-static const q15_t ALIGN4 realCoefAQ15[8192] = {
-    0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
-    0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
-    0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
-    0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
-    0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
-    0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
-    0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
-    0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
-    0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
-    0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
-    0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
-    0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
-    0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
-    0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
-    0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
-    0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
-    0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
-    0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
-    0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
-    0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
-    0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
-    0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
-    0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
-    0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
-    0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
-    0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
-    0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
-    0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
-    0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
-    0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
-    0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
-    0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
-    0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
-    0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
-    0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
-    0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
-    0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
-    0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
-    0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
-    0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
-    0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
-    0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
-    0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
-    0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
-    0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
-    0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
-    0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
-    0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
-    0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
-    0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
-    0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
-    0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
-    0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
-    0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
-    0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
-    0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
-    0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
-    0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
-    0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
-    0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
-    0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
-    0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
-    0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
-    0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
-    0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
-    0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
-    0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
-    0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
-    0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
-    0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
-    0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
-    0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
-    0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
-    0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
-    0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
-    0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
-    0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
-    0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
-    0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
-    0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
-    0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
-    0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
-    0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
-    0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
-    0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
-    0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
-    0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
-    0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
-    0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
-    0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
-    0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
-    0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
-    0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
-    0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
-    0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
-    0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
-    0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
-    0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
-    0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
-    0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
-    0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
-    0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
-    0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
-    0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
-    0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
-    0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
-    0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
-    0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
-    0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
-    0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
-    0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
-    0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
-    0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
-    0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
-    0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
-    0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
-    0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
-    0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
-    0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
-    0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
-    0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
-    0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
-    0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
-    0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
-    0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
-    0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
-    0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
-    0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
-    0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
-    0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
-    0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
-    0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
-    0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
-    0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
-    0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
-    0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
-    0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
-    0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
-    0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
-    0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
-    0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
-    0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
-    0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
-    0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
-    0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
-    0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
-    0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
-    0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
-    0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
-    0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
-    0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
-    0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
-    0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
-    0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
-    0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
-    0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
-    0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
-    0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
-    0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
-    0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
-    0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
-    0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
-    0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
-    0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
-    0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
-    0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
-    0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
-    0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
-    0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
-    0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
-    0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
-    0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
-    0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
-    0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
-    0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
-    0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
-    0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
-    0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
-    0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
-    0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
-    0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
-    0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
-    0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
-    0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
-    0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
-    0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
-    0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
-    0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
-    0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
-    0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
-    0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
-    0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
-    0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
-    0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
-    0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
-    0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
-    0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
-    0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
-    0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
-    0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
-    0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
-    0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
-    0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
-    0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
-    0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
-    0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
-    0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
-    0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
-    0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
-    0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
-    0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
-    0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
-    0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
-    0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
-    0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
-    0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
-    0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
-    0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
-    0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
-    0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
-    0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
-    0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
-    0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
-    0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
-    0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
-    0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
-    0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
-    0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
-    0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
-    0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
-    0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
-    0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
-    0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
-    0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
-    0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
-    0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
-    0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
-    0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
-    0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
-    0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
-    0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
-    0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
-    0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
-    0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
-    0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
-    0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
-    0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
-    0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
-    0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
-    0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
-    0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
-    0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
-    0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
-    0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
-    0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
-    0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
-    0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
-    0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
-    0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
-    0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
-    0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
-    0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
-    0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
-    0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
-    0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
-    0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
-    0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
-    0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
-    0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
-    0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
-    0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
-    0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
-    0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
-    0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
-    0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
-    0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
-    0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
-    0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
-    0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
-    0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
-    0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
-    0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
-    0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
-    0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
-    0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
-    0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
-    0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
-    0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
-    0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
-    0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
-    0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
-    0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
-    0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
-    0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
-    0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
-    0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
-    0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
-    0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
-    0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
-    0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
-    0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
-    0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
-    0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
-    0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
-    0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
-    0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
-    0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
-    0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
-    0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
-    0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
-    0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
-    0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
-    0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
-    0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
-    0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
-    0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
-    0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
-    0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
-    0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
-    0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
-    0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
-    0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
-    0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
-    0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
-    0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
-    0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
-    0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
-    0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
-    0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
-    0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
-    0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
-    0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
-    0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
-    0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
-    0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
-    0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
-    0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
-    0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
-    0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
-    0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
-    0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
-    0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
-    0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
-    0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
-    0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
-    0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
-    0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
-    0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
-    0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
-    0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
-    0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
-    0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
-    0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
-    0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
-    0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
-    0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
-    0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
-    0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
-    0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
-    0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
-    0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
-    0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
-    0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
-    0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
-    0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
-    0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
-    0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
-    0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
-    0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
-    0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
-    0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
-    0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
-    0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
-    0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
-    0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
-    0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
-    0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
-    0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
-    0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
-    0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
-    0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
-    0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
-    0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
-    0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
-    0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
-    0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
-    0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
-    0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
-    0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
-    0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
-    0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
-    0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
-    0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
-    0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
-    0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
-    0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
-    0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
-    0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
-    0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
-    0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
-    0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
-    0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
-    0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
-    0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
-    0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
-    0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
-    0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
-    0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
-    0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
-    0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
-    0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
-    0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
-    0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
-    0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
-    0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
-    0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
-    0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
-    0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
-    0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
-    0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
-    0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
-    0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
-    0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
-    0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
-    0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
-    0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
-    0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
-    0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
-    0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
-    0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
-    0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
-    0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
-    0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
-    0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
-    0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
-    0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
-    0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
-    0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
-    0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
-    0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
-    0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
-    0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
-    0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
-    0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
-    0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
-    0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
-    0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
-    0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
-    0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
-    0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
-    0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
-    0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
-    0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
-    0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
-    0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
-    0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
-    0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
-    0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
-    0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
-    0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
-    0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
-    0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
-    0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
-    0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
-    0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
-    0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
-    0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
-    0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
-    0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
-    0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
-    0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
-    0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
-    0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
-    0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
-    0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
-    0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
-    0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
-    0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
-    0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
-    0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
-    0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
-    0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
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-    0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
-    0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
-    0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
-    0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
-    0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
-    0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
-    0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
-    0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
-    0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
-    0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
-    0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
-    0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
-    0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
-    0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
-    0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
-    0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
-    0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
-};
-
-/**    
-* \par   
-* Generation of real_CoefB array:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
   
-* \par    
-* Convert to fixed point Q15 format    
-*       round(pBTable[i] * pow(2, 15))    
-*    
-*/
-static const q15_t ALIGN4 realCoefBQ15[8192] = {
-    0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
-    0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
-    0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
-    0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
-    0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
-    0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
-    0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
-    0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
-    0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
-    0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
-    0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
-    0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
-    0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
-    0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
-    0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
-    0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
-    0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
-    0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
-    0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
-    0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
-    0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
-    0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
-    0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
-    0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
-    0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
-    0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
-    0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
-    0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
-    0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
-    0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
-    0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
-    0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
-    0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
-    0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
-    0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
-    0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
-    0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
-    0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
-    0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
-    0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
-    0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
-    0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
-    0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
-    0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
-    0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
-    0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
-    0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
-    0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
-    0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
-    0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
-    0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
-    0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
-    0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
-    0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
-    0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
-    0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
-    0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
-    0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
-    0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
-    0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
-    0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
-    0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
-    0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
-    0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
-    0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
-    0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
-    0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
-    0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
-    0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
-    0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
-    0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
-    0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
-    0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
-    0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
-    0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
-    0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
-    0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
-    0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
-    0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
-    0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
-    0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
-    0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
-    0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
-    0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
-    0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
-    0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
-    0x50b1, 0x3dc9, 0x50bd, 0x3dc6, 0x50c9, 0x3dc2, 0x50d5, 0x3dbf,
-    0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
-    0x5112, 0x3daf, 0x511e, 0x3dab, 0x512a, 0x3da8, 0x5136, 0x3da4,
-    0x5142, 0x3da1, 0x514e, 0x3d9e, 0x515a, 0x3d9a, 0x5167, 0x3d97,
-    0x5173, 0x3d93, 0x517f, 0x3d90, 0x518b, 0x3d8d, 0x5197, 0x3d89,
-    0x51a3, 0x3d86, 0x51af, 0x3d82, 0x51bb, 0x3d7f, 0x51c7, 0x3d7b,
-    0x51d3, 0x3d78, 0x51df, 0x3d74, 0x51eb, 0x3d71, 0x51f7, 0x3d6d,
-    0x5204, 0x3d6a, 0x5210, 0x3d66, 0x521c, 0x3d63, 0x5228, 0x3d5f,
-    0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
-    0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
-    0x5294, 0x3d3f, 0x52a0, 0x3d3b, 0x52ac, 0x3d37, 0x52b8, 0x3d34,
-    0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
-    0x52f4, 0x3d21, 0x5300, 0x3d1d, 0x530c, 0x3d1a, 0x5318, 0x3d16,
-    0x5324, 0x3d12, 0x5330, 0x3d0e, 0x533c, 0x3d0b, 0x5348, 0x3d07,
-    0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
-    0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
-    0x53b4, 0x3ce4, 0x53c0, 0x3ce0, 0x53cc, 0x3cdd, 0x53d8, 0x3cd9,
-    0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
-    0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
-    0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
-    0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
-    0x54a2, 0x3c95, 0x54ae, 0x3c91, 0x54ba, 0x3c8d, 0x54c6, 0x3c89,
-    0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
-    0x5501, 0x3c74, 0x550d, 0x3c70, 0x5519, 0x3c6c, 0x5525, 0x3c68,
-    0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
-    0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
-    0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
-    0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
-    0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
-    0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
-    0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
-    0x567c, 0x3bec, 0x5687, 0x3be7, 0x5693, 0x3be3, 0x569f, 0x3bde,
-    0x56ab, 0x3bda, 0x56b6, 0x3bd6, 0x56c2, 0x3bd1, 0x56ce, 0x3bcd,
-    0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
-    0x5709, 0x3bb6, 0x5714, 0x3bb2, 0x5720, 0x3bad, 0x572c, 0x3ba9,
-    0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
-    0x5766, 0x3b92, 0x5772, 0x3b8d, 0x577e, 0x3b88, 0x5789, 0x3b84,
-    0x5795, 0x3b7f, 0x57a1, 0x3b7b, 0x57ac, 0x3b76, 0x57b8, 0x3b71,
-    0x57c4, 0x3b6d, 0x57cf, 0x3b68, 0x57db, 0x3b63, 0x57e7, 0x3b5f,
-    0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
-    0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
-    0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
-    0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
-    0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
-    0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
-    0x5909, 0x3ae6, 0x5914, 0x3ae2, 0x5920, 0x3add, 0x592c, 0x3ad8,
-    0x5937, 0x3ad3, 0x5943, 0x3ace, 0x594e, 0x3ac9, 0x595a, 0x3ac4,
-    0x5965, 0x3abf, 0x5971, 0x3aba, 0x597c, 0x3ab5, 0x5988, 0x3ab0,
-    0x5993, 0x3aab, 0x599f, 0x3aa6, 0x59aa, 0x3aa1, 0x59b6, 0x3a9c,
-    0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
-    0x59ef, 0x3a82, 0x59fb, 0x3a7d, 0x5a06, 0x3a78, 0x5a12, 0x3a73,
-    0x5a1d, 0x3a6e, 0x5a29, 0x3a69, 0x5a34, 0x3a64, 0x5a40, 0x3a5f,
-    0x5a4b, 0x3a59, 0x5a57, 0x3a54, 0x5a62, 0x3a4f, 0x5a6e, 0x3a4a,
-    0x5a79, 0x3a45, 0x5a84, 0x3a3f, 0x5a90, 0x3a3a, 0x5a9b, 0x3a35,
-    0x5aa7, 0x3a30, 0x5ab2, 0x3a2b, 0x5abe, 0x3a25, 0x5ac9, 0x3a20,
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-    0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
-    0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
-    0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
-    0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
-    0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
-    0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
-    0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
-    0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
-    0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
-    0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
-    0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
-    0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
-    0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
-    0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
-    0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
-    0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
-    0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
-    0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
-    0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
-    0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
-    0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
-    0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
-    0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
-    0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
-    0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
-    0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
-    0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
-    0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
-    0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
-    0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
-    0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
-    0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
-    0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
-    0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
-    0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
-    0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
-    0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
-    0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
-    0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
-};
-
-/**    
-* @brief  Initialization function for the Q15 RFFT/RIFFT.   
-* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.   
-* @param[in]      fftLenReal     length of the FFT.   
-* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    
-* This function also initializes Twiddle factor table.     
-*/
-arm_status arm_rfft_init_q15(
-    arm_rfft_instance_q15 * S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag)
-{
-    /*  Initialise the default arm status */
-    arm_status status = ARM_MATH_SUCCESS;
-
-    /*  Initialize the Real FFT length */
-    S->fftLenReal = (uint16_t) fftLenReal;
-
-    /*  Initialize the Twiddle coefficientA pointer */
-    S->pTwiddleAReal = (q15_t *) realCoefAQ15;
-
-    /*  Initialize the Twiddle coefficientB pointer */
-    S->pTwiddleBReal = (q15_t *) realCoefBQ15;
-
-    /*  Initialize the Flag for selection of RFFT or RIFFT */
-    S->ifftFlagR = (uint8_t) ifftFlagR;
-
-    /*  Initialize the Flag for calculation Bit reversal or not */
-    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-    /*  Initialization of coef modifier depending on the FFT length */
-    switch (S->fftLenReal)
-    {
-    case 8192u:
-        S->twidCoefRModifier = 1u;
-        S->pCfft = &arm_cfft_sR_q15_len4096;
-        break;
-    case 4096u:
-        S->twidCoefRModifier = 2u;
-        S->pCfft = &arm_cfft_sR_q15_len2048;
-        break;
-    case 2048u:
-        S->twidCoefRModifier = 4u;
-        S->pCfft = &arm_cfft_sR_q15_len1024;
-        break;
-    case 1024u:
-        S->twidCoefRModifier = 8u;
-        S->pCfft = &arm_cfft_sR_q15_len512;
-        break;
-    case 512u:
-        S->twidCoefRModifier = 16u;
-        S->pCfft = &arm_cfft_sR_q15_len256;
-        break;
-    case 256u:
-        S->twidCoefRModifier = 32u;
-        S->pCfft = &arm_cfft_sR_q15_len128;
-        break;
-    case 128u:
-        S->twidCoefRModifier = 64u;
-        S->pCfft = &arm_cfft_sR_q15_len64;
-        break;
-    case 64u:
-        S->twidCoefRModifier = 128u;
-        S->pCfft = &arm_cfft_sR_q15_len32;
-        break;
-    case 32u:
-        S->twidCoefRModifier = 256u;
-        S->pCfft = &arm_cfft_sR_q15_len16;
-        break;
-    default:
-        /*  Reporting argument error if rfftSize is not valid value */
-        status = ARM_MATH_ARGUMENT_ERROR;
-        break;
-    }
-
-    /* return the status of RFFT Init function */
-    return (status);
-}
-
-/**    
-* @} end of RealFFT group    
-*/
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
deleted file mode 100644
index 8ff254c0..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
+++ /dev/null
@@ -1,4285 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_q31.c    
-*    
-* Description:	RFFT & RIFFT Q31 initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-#include "arm_const_structs.h"
-
-/**    
-* @ingroup groupTransforms    
-*/
-
-/**    
-* @addtogroup RealFFT    
-* @{    
-*/
-
-/**    
-* \par    
-* Generation fixed-point realCoefAQ31 array in Q31 format:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-* }
    
-* \par    
-* Convert to fixed point Q31 format    
-*     round(pATable[i] * pow(2, 31))    
-*/
-
-
-static const q31_t realCoefAQ31[8192] = {
-    0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
-    0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
-    0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
-    0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
-    0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
-    0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
-    0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
-    0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
-    0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
-    0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
-    0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
-    0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
-    0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
-    0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
-    0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
-    0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
-    0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
-    0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
-    0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
-    0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
-    0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
-    0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
-    0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
-    0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
-    0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
-    0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
-    0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
-    0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
-    0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
-    0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
-    0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
-    0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
-    0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
-    0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
-    0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
-    0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
-    0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
-    0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
-    0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
-    0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
-    0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
-    0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
-    0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
-    0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
-    0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
-    0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
-    0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
-    0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
-    0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
-    0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
-    0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
-    0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
-    0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
-    0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
-    0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
-    0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
-    0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
-    0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
-    0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
-    0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
-    0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
-    0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
-    0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
-    0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
-    0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
-    0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
-    0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
-    0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
-    0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
-    0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
-    0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
-    0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
-    0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
-    0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
-    0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
-    0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
-    0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
-    0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
-    0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
-    0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
-    0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
-    0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
-    0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
-    0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
-    0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
-    0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
-    0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
-    0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
-    0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
-    0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
-    0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
-    0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
-    0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
-    0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
-    0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
-    0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
-    0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
-    0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
-    0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
-    0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
-    0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
-    0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
-    0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
-    0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
-    0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
-    0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
-    0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
-    0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
-    0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
-    0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
-    0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
-    0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
-    0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
-    0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
-    0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
-    0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
-    0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
-    0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
-    0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
-    0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
-    0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
-    0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
-    0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
-    0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
-    0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
-    0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
-    0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
-    0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
-    0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
-    0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
-    0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
-    0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
-    0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
-    0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
-    0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
-    0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
-    0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
-    0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
-    0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
-    0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
-    0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
-    0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
-    0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
-    0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
-    0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
-    0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
-    0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
-    0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
-    0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
-    0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
-    0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
-    0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
-    0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
-    0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
-    0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
-    0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
-    0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
-    0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
-    0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
-    0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
-    0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
-    0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
-    0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
-    0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
-    0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
-    0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
-    0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
-    0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
-    0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
-    0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
-    0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
-    0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
-    0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
-    0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
-    0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
-    0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
-    0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
-    0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
-    0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
-    0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
-    0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
-    0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
-    0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
-    0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
-    0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
-    0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
-    0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
-    0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
-    0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
-    0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
-    0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
-    0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
-    0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
-    0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
-    0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
-    0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
-    0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
-    0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
-    0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
-    0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
-    0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
-    0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
-    0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
-    0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
-    0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
-    0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
-    0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
-    0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
-    0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
-    0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
-    0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
-    0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
-    0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
-    0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
-    0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
-    0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
-    0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
-    0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
-    0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
-    0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
-    0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
-    0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
-    0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
-    0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
-    0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
-    0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
-    0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
-    0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
-    0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
-    0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
-    0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
-    0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
-    0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
-    0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
-    0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
-    0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
-    0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
-    0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
-    0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
-    0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
-    0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
-    0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
-    0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
-    0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
-    0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
-    0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
-    0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
-    0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
-    0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
-    0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
-    0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
-    0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
-    0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
-    0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
-    0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
-    0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
-    0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
-    0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
-    0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
-    0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
-    0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
-    0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
-    0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
-    0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
-    0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
-    0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
-    0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
-    0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
-    0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
-    0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
-    0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
-    0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
-    0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
-    0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
-    0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
-    0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
-    0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
-    0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
-    0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
-    0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
-    0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
-    0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
-    0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
-    0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
-    0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
-    0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
-    0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
-    0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
-    0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
-    0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
-    0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
-    0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
-    0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
-    0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
-    0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
-    0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
-    0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
-    0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
-    0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
-    0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
-    0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
-    0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
-    0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
-    0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
-    0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
-    0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
-    0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
-    0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
-    0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
-    0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
-    0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
-    0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
-    0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
-    0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
-    0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
-    0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
-    0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
-    0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
-    0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
-    0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
-    0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
-    0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
-    0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
-    0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
-    0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
-    0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
-    0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
-    0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
-    0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
-    0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
-    0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
-    0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
-    0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
-    0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
-    0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
-    0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
-    0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
-    0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
-    0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
-    0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
-    0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
-    0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
-    0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
-    0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
-    0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
-    0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
-    0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
-    0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
-    0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
-    0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
-    0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
-    0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
-    0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
-    0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
-    0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
-    0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
-    0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
-    0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
-    0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
-    0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
-    0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
-    0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
-    0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
-    0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
-    0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
-    0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
-    0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
-    0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
-    0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
-    0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
-    0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
-    0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
-    0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
-    0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
-    0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
-    0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
-    0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
-    0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
-    0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
-    0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
-    0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
-    0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
-    0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
-    0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
-    0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
-    0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
-    0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
-    0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
-    0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
-    0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
-    0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
-    0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
-    0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
-    0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
-    0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
-    0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
-    0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
-    0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
-    0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
-    0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
-    0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
-    0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
-    0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
-    0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
-    0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
-    0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
-    0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
-    0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
-    0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
-    0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
-    0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
-    0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
-    0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
-    0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
-    0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
-    0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
-    0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
-    0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
-    0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
-    0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
-    0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
-    0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
-    0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
-    0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
-    0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
-    0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
-    0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
-    0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
-    0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
-    0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
-    0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
-    0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
-    0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
-    0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
-    0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
-    0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
-    0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
-    0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
-    0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
-    0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
-    0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
-    0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
-    0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
-    0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
-    0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
-    0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
-    0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
-    0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
-    0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
-    0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
-    0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
-    0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
-    0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
-    0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
-    0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
-    0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
-    0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
-    0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
-    0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
-    0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
-    0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
-    0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
-    0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
-    0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
-    0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
-    0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
-    0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
-    0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
-    0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
-    0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
-    0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
-    0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
-    0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
-    0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
-    0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
-    0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
-    0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
-    0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
-    0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
-    0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
-    0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
-    0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
-    0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
-    0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
-    0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
-    0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
-    0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
-    0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
-    0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
-    0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
-    0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
-    0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
-    0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
-    0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
-    0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
-    0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
-    0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
-    0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
-    0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
-    0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
-    0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
-    0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
-    0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
-    0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
-    0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
-    0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
-    0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
-    0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
-    0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
-    0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
-    0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
-    0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
-    0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
-    0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
-    0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
-    0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
-    0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
-    0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
-    0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
-    0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
-    0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
-    0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
-    0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
-    0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
-    0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
-    0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
-    0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
-    0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
-    0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
-    0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
-    0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
-    0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
-    0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
-    0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
-    0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
-    0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
-    0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
-    0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
-    0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
-    0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
-    0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
-    0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
-    0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
-    0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
-    0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
-    0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
-    0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
-    0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
-    0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
-    0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
-    0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
-    0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
-    0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
-    0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
-    0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
-    0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
-    0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
-    0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
-    0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
-    0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
-    0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
-    0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
-    0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
-    0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
-    0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
-    0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
-    0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
-    0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
-    0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
-    0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
-    0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
-    0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
-    0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
-    0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
-    0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
-    0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
-    0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
-    0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
-    0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
-    0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
-    0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
-    0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
-    0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
-    0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
-    0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
-    0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
-    0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
-    0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
-    0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
-    0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
-    0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
-    0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
-    0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
-    0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
-    0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
-    0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
-    0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
-    0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
-    0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
-    0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
-    0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
-    0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
-    0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
-    0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
-    0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
-    0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
-    0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
-    0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
-    0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
-    0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
-    0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
-    0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
-    0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
-    0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
-    0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
-    0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
-    0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
-    0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
-    0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
-    0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
-    0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
-    0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
-    0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
-    0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
-    0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
-    0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
-    0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
-    0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
-    0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
-    0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
-    0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
-    0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
-    0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
-    0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
-    0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
-    0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
-    0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
-    0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
-    0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
-    0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
-    0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
-    0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
-    0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
-    0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
-    0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
-    0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
-    0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
-    0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
-    0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
-    0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
-    0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
-    0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
-    0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
-    0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
-    0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
-    0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
-    0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
-    0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
-    0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
-    0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
-    0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
-    0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
-    0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
-    0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
-    0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
-    0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
-    0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
-    0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
-    0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
-    0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
-    0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
-    0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
-    0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
-    0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
-    0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
-    0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
-    0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
-    0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
-    0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
-    0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
-    0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
-    0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
-    0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
-    0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
-    0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
-    0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
-    0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
-    0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
-    0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
-    0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
-    0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
-    0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
-    0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
-    0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
-    0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
-    0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
-    0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
-    0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
-    0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
-    0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
-    0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
-    0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
-    0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
-    0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
-    0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
-    0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
-    0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
-    0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
-    0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
-    0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
-    0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
-    0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
-    0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
-    0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
-    0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
-    0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
-    0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
-    0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
-    0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
-    0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
-    0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
-    0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
-    0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
-    0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
-    0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
-    0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
-    0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
-    0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
-    0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
-    0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
-    0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
-    0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
-    0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
-    0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
-    0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
-    0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
-    0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
-    0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
-    0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
-    0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
-    0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
-    0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
-    0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
-    0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
-    0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
-    0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
-    0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
-    0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
-    0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
-    0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
-    0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
-    0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
-    0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
-    0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
-    0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
-    0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
-    0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
-    0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
-    0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
-    0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
-    0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
-    0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
-    0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
-    0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
-    0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
-    0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
-    0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
-    0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
-    0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
-    0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
-    0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
-    0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
-    0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
-    0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
-    0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
-    0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
-    0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
-    0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
-    0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
-    0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
-    0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
-    0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
-    0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
-    0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
-    0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
-    0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
-    0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
-    0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
-    0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
-    0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
-    0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
-    0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
-    0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
-    0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
-    0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
-    0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
-    0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
-    0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
-    0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
-    0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
-    0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
-    0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
-    0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
-    0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
-    0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
-    0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
-    0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
-    0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
-    0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
-    0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
-    0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
-    0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
-    0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
-    0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
-    0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
-    0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
-    0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
-    0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
-    0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
-    0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
-    0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
-    0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
-    0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
-    0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
-    0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
-    0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
-    0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
-    0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
-    0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
-    0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
-    0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
-    0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
-    0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
-    0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
-    0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
-    0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
-    0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
-    0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
-    0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
-    0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
-    0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
-    0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
-    0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
-    0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
-    0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
-    0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
-    0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
-    0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
-    0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
-    0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
-    0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
-    0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
-    0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
-    0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
-    0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
-    0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
-    0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
-    0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
-    0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
-    0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
-    0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
-    0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
-    0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
-    0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
-    0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
-    0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
-    0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
-    0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
-    0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
-    0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
-    0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
-    0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
-    0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
-    0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
-    0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
-    0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
-    0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
-    0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
-    0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
-    0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
-    0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
-    0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
-    0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
-    0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
-    0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
-    0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
-    0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
-    0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
-    0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
-    0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
-    0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
-    0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
-    0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
-    0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
-    0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
-    0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
-    0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
-    0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
-    0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
-    0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
-    0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
-    0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
-    0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
-    0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
-    0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
-    0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
-    0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
-    0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
-    0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
-    0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
-    0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
-    0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
-    0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
-    0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
-    0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
-    0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
-    0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
-    0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
-    0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
-    0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
-    0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
-    0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
-    0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
-    0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
-    0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
-    0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
-    0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
-    0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
-    0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
-    0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
-    0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
-    0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
-    0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
-    0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
-    0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
-    0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
-    0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
-    0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
-    0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
-    0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
-    0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
-    0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
-    0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
-    0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
-    0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
-    0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
-    0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
-    0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
-    0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
-    0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
-    0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
-    0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
-    0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
-    0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
-    0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
-    0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
-    0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
-    0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
-    0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
-    0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
-    0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
-    0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
-    0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
-    0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
-    0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
-    0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
-    0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
-    0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
-    0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
-    0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
-    0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
-    0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
-    0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
-    0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
-    0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
-    0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
-    0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
-    0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
-    0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
-    0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
-    0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
-    0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
-    0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
-    0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
-    0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
-    0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
-    0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
-    0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
-    0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
-    0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
-    0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
-    0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
-    0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
-    0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
-    0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
-    0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
-    0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
-    0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
-    0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
-    0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
-    0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
-    0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
-    0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
-    0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
-    0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
-    0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
-    0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
-    0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
-    0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
-    0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
-    0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
-    0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
-    0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
-    0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
-    0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
-    0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
-    0x13bd3, 0xff36f170, 0x11594, 0xff438234,
-    0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
-    0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
-    0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
-    0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
-    0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
-    0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
-    0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
-    0x0, 0x0, 0x13c, 0xc90fe,
-    0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
-    0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
-    0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
-    0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
-    0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
-    0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
-    0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
-    0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
-    0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
-    0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
-    0x25519, 0x1147271, 0x28c9c, 0x12102f4,
-    0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
-    0x341f4, 0x146b438, 0x38356, 0x153448c,
-    0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
-    0x45648, 0x178f536, 0x4a188, 0x1858552,
-    0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
-    0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
-    0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
-    0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
-    0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
-    0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
-    0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
-    0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
-    0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
-    0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
-    0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
-    0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
-    0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
-    0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
-    0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
-    0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
-    0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
-    0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
-    0x164757, 0x3562038, 0x16f047, 0x362acc5,
-    0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
-    0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
-    0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
-    0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
-    0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
-    0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
-    0x2064ab, 0x405c361, 0x213018, 0x4124dee,
-    0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
-    0x23a124, 0x437eca4, 0x24766a, 0x444768d,
-    0x254e27, 0x451004d, 0x262859, 0x45d89e2,
-    0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
-    0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
-    0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
-    0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
-    0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
-    0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
-    0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
-    0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
-    0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
-    0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
-    0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
-    0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
-    0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
-    0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
-    0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
-    0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
-    0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
-    0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
-    0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
-    0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
-    0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
-    0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
-    0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
-    0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
-    0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
-    0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
-    0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
-    0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
-    0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
-    0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
-    0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
-    0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
-    0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
-    0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
-    0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
-    0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
-    0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
-    0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
-    0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
-    0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
-    0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
-    0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
-    0x91b01d, 0x884104b, 0x935d64, 0x8908483,
-    0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
-    0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
-    0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
-    0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
-    0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
-    0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
-    0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
-    0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
-    0xb15502, 0x9640837, 0xb32e42, 0x9707635,
-    0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
-    0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
-    0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
-    0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
-    0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
-    0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
-    0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
-    0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
-    0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
-    0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
-    0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
-    0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
-    0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
-    0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
-    0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
-    0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
-    0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
-    0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
-    0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
-    0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
-    0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
-    0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
-    0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
-    0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
-    0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
-    0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
-    0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
-    0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
-    0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
-    0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
-    0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
-    0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
-    0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
-    0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
-    0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
-    0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
-    0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
-    0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
-    0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
-    0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
-    0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
-    0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
-    0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
-    0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
-    0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
-    0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
-    0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
-    0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
-    0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
-    0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
-    0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
-    0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
-    0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
-    0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
-    0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
-    0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
-    0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
-    0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
-    0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
-    0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
-    0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
-    0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
-    0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
-    0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
-    0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
-    0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
-    0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
-    0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
-    0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
-    0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
-    0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
-    0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
-    0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
-    0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
-    0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
-    0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
-    0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
-    0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
-    0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
-    0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
-    0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
-    0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
-    0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
-    0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
-    0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
-    0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
-    0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
-    0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
-    0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
-    0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
-    0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
-    0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
-    0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
-    0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
-    0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
-    0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
-    0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
-    0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
-    0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
-    0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
-    0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
-    0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
-    0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
-    0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
-    0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
-    0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
-    0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
-    0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
-    0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
-    0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
-    0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
-    0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
-    0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
-    0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
-    0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
-    0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
-    0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
-    0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
-    0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
-    0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
-    0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
-    0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
-    0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
-    0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
-    0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
-    0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
-    0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
-    0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
-    0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
-    0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
-    0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
-    0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
-    0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
-    0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
-    0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
-    0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
-    0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
-    0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
-    0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
-    0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
-    0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
-    0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
-    0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
-    0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
-    0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
-    0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
-    0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
-    0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
-    0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
-    0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
-    0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
-    0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
-    0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
-    0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
-    0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
-    0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
-    0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
-    0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
-    0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
-    0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
-    0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
-    0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
-    0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
-    0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
-    0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
-    0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
-    0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
-    0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
-    0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
-    0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
-    0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
-    0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
-    0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
-    0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
-    0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
-    0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
-    0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
-    0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
-    0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
-    0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
-    0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
-    0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
-    0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
-    0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
-    0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
-    0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
-    0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
-    0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
-    0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
-    0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
-    0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
-    0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
-    0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
-    0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
-    0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
-    0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
-    0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
-    0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
-    0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
-    0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
-    0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
-    0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
-    0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
-    0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
-    0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
-    0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
-    0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
-    0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
-    0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
-    0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
-    0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
-    0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
-    0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
-    0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
-    0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
-    0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
-    0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
-    0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
-    0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
-    0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
-    0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
-    0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
-    0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
-    0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
-    0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
-    0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
-    0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
-    0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
-    0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
-    0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
-    0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
-    0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
-    0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
-    0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
-    0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
-    0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
-    0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
-    0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
-    0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
-    0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
-    0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
-    0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
-    0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
-    0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
-    0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
-    0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
-    0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
-    0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
-    0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
-    0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
-    0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
-    0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
-    0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
-    0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
-    0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
-    0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
-    0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
-    0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
-    0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
-    0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
-    0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
-    0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
-    0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
-    0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
-    0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
-    0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
-    0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
-    0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
-    0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
-    0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
-    0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
-    0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
-    0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
-    0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
-    0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
-    0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
-    0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
-    0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
-    0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
-    0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
-    0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
-    0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
-    0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
-    0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
-    0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
-    0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
-    0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
-    0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
-    0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
-    0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
-    0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
-    0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
-    0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
-    0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
-    0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
-    0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
-    0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
-    0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
-    0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
-    0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
-    0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
-    0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
-    0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
-    0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
-    0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
-    0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
-    0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
-    0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
-    0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
-    0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
-    0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
-    0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
-    0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
-    0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
-    0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
-    0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
-    0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
-    0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
-    0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
-    0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
-    0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
-    0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
-    0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
-    0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
-    0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
-    0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
-    0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
-    0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
-    0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
-    0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
-    0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
-    0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
-    0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
-    0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
-    0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
-    0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
-    0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
-    0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
-    0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
-    0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
-    0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
-    0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
-    0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
-    0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
-    0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
-    0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
-    0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
-    0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
-    0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
-    0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
-    0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
-    0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
-    0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
-    0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
-    0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
-    0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
-    0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
-    0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
-    0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
-    0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
-    0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
-    0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
-    0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
-    0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
-    0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
-    0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
-    0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
-    0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
-    0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
-    0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
-    0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
-    0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
-    0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
-    0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
-    0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
-    0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
-    0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
-    0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
-    0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
-    0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
-    0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
-    0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
-    0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
-    0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
-    0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
-    0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
-    0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
-    0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
-    0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
-    0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
-    0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
-    0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
-    0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
-    0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
-    0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
-    0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
-    0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
-    0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
-    0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
-    0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
-    0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
-    0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
-    0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
-    0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
-    0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
-    0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
-    0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
-    0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
-    0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
-    0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
-    0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
-    0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
-    0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
-    0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
-    0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
-    0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
-    0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
-    0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
-    0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
-    0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
-    0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
-    0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
-    0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
-    0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
-    0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
-    0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
-    0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
-    0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
-    0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
-    0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
-    0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
-    0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
-    0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
-    0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
-    0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
-    0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
-    0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
-    0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
-    0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
-    0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
-    0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
-    0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
-    0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
-    0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
-    0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
-    0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
-    0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
-    0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
-    0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
-    0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
-    0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
-    0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
-    0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
-    0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
-    0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
-    0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
-    0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
-    0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
-    0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
-    0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
-    0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
-    0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
-    0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
-    0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
-    0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
-    0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
-    0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
-    0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
-    0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
-    0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
-    0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
-    0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
-    0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
-    0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
-    0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
-    0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
-    0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
-    0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
-    0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
-    0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
-    0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
-    0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
-    0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
-    0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
-    0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
-    0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
-    0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
-    0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
-    0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
-    0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
-    0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
-    0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
-    0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
-    0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
-    0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
-    0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
-    0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
-    0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
-    0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
-    0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
-    0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
-    0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
-    0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
-    0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
-    0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
-    0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
-    0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
-    0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
-    0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
-    0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
-    0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
-    0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
-    0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
-    0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
-    0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
-    0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
-    0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
-    0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
-    0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
-    0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
-    0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
-    0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
-    0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
-    0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
-    0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
-    0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
-    0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
-    0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
-    0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
-    0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
-    0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
-    0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
-    0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
-    0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
-    0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
-    0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
-    0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
-    0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
-    0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
-    0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
-    0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
-    0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
-    0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
-    0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
-    0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
-    0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
-    0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
-    0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
-    0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
-    0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
-    0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
-    0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
-    0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
-    0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
-    0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
-    0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
-    0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
-    0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
-    0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
-    0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
-    0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
-    0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
-    0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
-    0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
-    0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
-    0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
-    0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
-    0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
-    0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
-    0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
-    0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
-    0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
-    0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
-    0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
-    0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
-    0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
-    0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
-    0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
-    0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
-    0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
-    0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
-    0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
-    0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
-    0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
-    0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
-    0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
-    0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
-    0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
-    0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
-    0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
-    0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
-    0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
-    0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
-    0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
-    0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
-    0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
-    0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
-    0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
-    0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
-    0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
-    0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
-    0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
-    0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
-    0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
-    0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
-    0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
-    0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
-    0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
-    0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
-    0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
-    0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
-    0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
-    0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
-    0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
-    0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
-    0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
-    0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
-    0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
-    0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
-    0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
-    0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
-    0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
-    0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
-    0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
-    0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
-    0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
-    0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
-    0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
-    0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
-    0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
-    0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
-    0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
-    0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
-    0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
-    0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
-    0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
-    0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
-    0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
-    0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
-    0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
-    0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
-    0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
-    0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
-    0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
-    0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
-    0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
-    0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
-    0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
-    0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
-    0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
-    0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
-    0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
-    0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
-    0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
-    0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
-    0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
-    0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
-    0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
-    0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
-    0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
-    0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
-    0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
-    0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
-    0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
-    0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
-    0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
-    0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
-    0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
-    0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
-    0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
-    0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
-    0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
-    0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
-    0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
-    0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
-    0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
-    0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
-    0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
-    0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
-    0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
-    0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
-    0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
-    0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
-    0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
-    0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
-    0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
-    0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
-    0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
-    0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
-    0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
-    0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
-    0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
-    0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
-    0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
-    0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
-    0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
-    0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
-    0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
-    0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
-    0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
-    0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
-    0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
-    0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
-    0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
-    0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
-    0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
-    0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
-    0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
-    0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
-    0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
-    0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
-    0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
-    0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
-    0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
-    0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
-    0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
-    0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
-    0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
-    0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
-    0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
-    0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
-    0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
-    0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
-    0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
-    0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
-    0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
-    0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
-    0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
-    0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
-    0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
-    0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
-    0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
-    0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
-    0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
-    0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
-    0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
-    0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
-    0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
-    0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
-    0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
-    0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
-    0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
-    0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
-    0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
-    0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
-    0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
-    0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
-    0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
-    0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
-    0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
-    0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
-    0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
-    0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
-    0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
-    0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
-    0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
-    0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
-    0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
-    0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
-    0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
-    0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
-    0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
-    0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
-    0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
-    0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
-    0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
-    0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
-    0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
-    0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
-    0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
-    0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
-    0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
-    0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
-    0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
-    0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
-    0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
-    0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
-    0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
-    0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
-    0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
-    0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
-    0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
-    0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
-    0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
-    0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
-    0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
-    0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
-    0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
-    0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
-    0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
-    0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
-    0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
-    0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
-    0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
-    0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
-    0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
-    0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
-    0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
-    0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
-    0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
-    0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
-    0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
-    0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
-    0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
-    0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
-    0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
-    0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
-    0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
-    0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
-    0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
-    0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
-    0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
-    0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
-    0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
-    0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
-    0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
-    0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
-    0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
-    0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
-    0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
-    0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
-    0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
-    0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
-    0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
-    0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
-    0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
-    0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
-    0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
-    0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
-    0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
-    0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
-    0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
-    0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
-    0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
-    0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
-    0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
-    0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
-    0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
-    0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
-    0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
-    0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
-    0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
-    0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
-    0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
-    0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
-    0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
-    0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
-    0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
-    0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
-    0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
-    0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
-    0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
-    0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
-    0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
-    0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
-    0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
-    0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
-    0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
-    0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
-    0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
-    0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
-    0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
-    0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
-    0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
-    0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
-    0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
-    0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
-    0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
-    0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
-    0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
-    0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
-    0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
-    0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
-    0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
-    0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
-    0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
-    0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
-    0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
-    0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
-    0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
-    0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
-    0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
-    0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
-    0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
-    0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
-    0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
-    0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
-    0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
-    0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
-    0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
-    0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
-    0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
-    0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
-    0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
-    0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
-    0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
-    0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
-    0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
-    0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
-    0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
-    0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
-    0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
-    0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
-    0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
-    0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
-    0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
-    0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
-    0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
-    0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
-    0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
-    0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
-    0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
-    0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
-    0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
-    0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
-    0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
-    0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
-    0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
-    0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
-    0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
-    0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
-    0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
-    0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
-    0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
-    0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
-    0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
-    0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
-};
-
-
-/**    
-* \par   
-* Generation of realCoefBQ31 array:    
-* \par    
-*  n = 4096        
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-* } 
    
-* \par    
-* Convert to fixed point Q31 format    
-*     round(pBTable[i] * pow(2, 31))    
-*    
-*/
-
-static const q31_t realCoefBQ31[8192] = {
-    0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
-    0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
-    0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
-    0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
-    0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
-    0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
-    0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
-    0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
-    0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
-    0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
-    0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
-    0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
-    0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
-    0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
-    0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
-    0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
-    0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
-    0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
-    0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
-    0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
-    0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
-    0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
-    0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
-    0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
-    0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
-    0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
-    0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
-    0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
-    0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
-    0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
-    0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
-    0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
-    0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
-    0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
-    0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
-    0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
-    0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
-    0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
-    0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
-    0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
-    0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
-    0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
-    0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
-    0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
-    0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
-    0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
-    0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
-    0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
-    0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
-    0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
-    0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
-    0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
-    0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
-    0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
-    0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
-    0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
-    0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
-    0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
-    0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
-    0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
-    0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
-    0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
-    0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
-    0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
-    0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
-    0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
-    0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
-    0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
-    0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
-    0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
-    0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
-    0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
-    0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
-    0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
-    0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
-    0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
-    0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
-    0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
-    0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
-    0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
-    0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
-    0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
-    0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
-    0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
-    0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
-    0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
-    0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
-    0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
-    0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
-    0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
-    0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
-    0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
-    0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
-    0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
-    0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
-    0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
-    0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
-    0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
-    0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
-    0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
-    0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
-    0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
-    0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
-    0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
-    0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
-    0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
-    0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
-    0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
-    0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
-    0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
-    0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
-    0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
-    0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
-    0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
-    0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
-    0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
-    0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
-    0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
-    0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
-    0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
-    0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
-    0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
-    0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
-    0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
-    0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
-    0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
-    0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
-    0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
-    0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
-    0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
-    0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
-    0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
-    0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
-    0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
-    0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
-    0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
-    0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
-    0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
-    0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
-    0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
-    0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
-    0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
-    0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
-    0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
-    0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
-    0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
-    0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
-    0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
-    0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
-    0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
-    0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
-    0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
-    0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
-    0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
-    0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
-    0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
-    0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
-    0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
-    0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
-    0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
-    0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
-    0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
-    0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
-    0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
-    0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
-    0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
-    0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
-    0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
-    0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
-    0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
-    0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
-    0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
-    0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
-    0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
-    0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
-    0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
-    0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
-    0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
-    0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
-    0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
-    0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
-    0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
-    0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
-    0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
-    0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
-    0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
-    0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
-    0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
-    0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
-    0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
-    0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
-    0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
-    0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
-    0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
-    0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
-    0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
-    0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
-    0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
-    0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
-    0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
-    0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
-    0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
-    0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
-    0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
-    0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
-    0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
-    0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
-    0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
-    0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
-    0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
-    0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
-    0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
-    0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
-    0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
-    0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
-    0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
-    0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
-    0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
-    0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
-    0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
-    0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
-    0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
-    0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
-    0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
-    0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
-    0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
-    0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
-    0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
-    0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
-    0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
-    0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
-    0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
-    0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
-    0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
-    0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
-    0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
-    0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
-    0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
-    0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
-    0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
-    0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
-    0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
-    0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
-    0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
-    0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
-    0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
-    0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
-    0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
-    0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
-    0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
-    0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
-    0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
-    0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
-    0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
-    0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
-    0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
-    0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
-    0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
-    0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
-    0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
-    0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
-    0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
-    0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
-    0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
-    0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
-    0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
-    0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
-    0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
-    0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
-    0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
-    0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
-    0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
-    0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
-    0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
-    0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
-    0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
-    0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
-    0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
-    0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
-    0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
-    0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
-    0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
-    0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
-    0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
-    0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
-    0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
-    0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
-    0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
-    0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
-    0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
-    0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
-    0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
-    0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
-    0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
-    0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
-    0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
-    0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
-    0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
-    0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
-    0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
-    0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
-    0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
-    0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
-    0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
-    0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
-    0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
-    0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
-    0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
-    0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
-    0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
-    0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
-    0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
-    0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
-    0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
-    0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
-    0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
-    0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
-    0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
-    0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
-    0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
-    0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
-    0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
-    0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
-    0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
-    0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
-    0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
-    0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
-    0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
-    0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
-    0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
-    0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
-    0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
-    0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
-    0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
-    0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
-    0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
-    0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
-    0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
-    0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
-    0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
-    0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
-    0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
-    0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
-    0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
-    0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
-    0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
-    0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
-    0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
-    0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
-    0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
-    0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
-    0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
-    0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
-    0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
-    0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
-    0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
-    0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
-    0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
-    0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
-    0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
-    0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
-    0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
-    0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
-    0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
-    0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
-    0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
-    0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
-    0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
-    0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
-    0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
-    0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
-    0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
-    0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
-    0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
-    0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
-    0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
-    0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
-    0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
-    0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
-    0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
-    0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
-    0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
-    0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
-    0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
-    0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
-    0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
-    0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
-    0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
-    0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
-    0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
-    0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
-    0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
-    0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
-    0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
-    0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
-    0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
-    0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
-    0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
-    0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
-    0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
-    0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
-    0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
-    0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
-    0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
-    0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
-    0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
-    0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
-    0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
-    0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
-    0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
-    0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
-    0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
-    0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
-    0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
-    0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
-    0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
-    0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
-    0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
-    0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
-    0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
-    0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
-    0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
-    0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
-    0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
-    0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
-    0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
-    0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
-    0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
-    0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
-    0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
-    0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
-    0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
-    0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
-    0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
-    0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
-    0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
-    0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
-    0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
-    0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
-    0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
-    0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
-    0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
-    0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
-    0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
-    0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
-    0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
-    0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
-    0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
-    0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
-    0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
-    0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
-    0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
-    0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
-    0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
-    0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
-    0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
-    0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
-    0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
-    0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
-    0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
-    0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
-    0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
-    0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
-    0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
-    0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
-    0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
-    0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
-    0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
-    0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
-    0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
-    0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
-    0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
-    0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
-    0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
-    0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
-    0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
-    0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
-    0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
-    0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
-    0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
-    0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
-    0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
-    0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
-    0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
-    0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
-    0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
-    0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
-    0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
-    0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
-    0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
-    0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
-    0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
-    0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
-    0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
-    0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
-    0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
-    0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
-    0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
-    0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
-    0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
-    0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
-    0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
-    0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
-    0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
-    0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
-    0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
-    0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
-    0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
-    0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
-    0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
-    0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
-    0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
-    0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
-    0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
-    0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
-    0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
-    0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
-    0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
-    0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
-    0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
-    0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
-    0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
-    0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
-    0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
-    0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
-    0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
-    0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
-    0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
-    0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
-    0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
-    0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
-    0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
-    0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
-    0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
-    0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
-    0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
-    0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
-    0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
-    0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
-    0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
-    0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
-    0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
-    0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
-    0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
-    0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
-    0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
-    0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
-    0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
-    0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
-    0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
-    0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
-    0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
-    0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
-    0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
-    0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
-    0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
-    0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
-    0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
-    0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
-    0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
-    0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
-    0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
-    0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
-    0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
-    0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
-    0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
-    0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
-    0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
-    0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
-    0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
-    0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
-    0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
-    0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
-    0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
-    0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
-    0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
-    0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
-    0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
-    0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
-    0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
-    0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
-    0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
-    0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
-    0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
-    0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
-    0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
-    0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
-    0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
-    0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
-    0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
-    0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
-    0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
-    0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
-    0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
-    0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
-    0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
-    0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
-    0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
-    0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
-    0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
-    0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
-    0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
-    0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
-    0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
-    0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
-    0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
-    0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
-    0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
-    0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
-    0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
-    0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
-    0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
-    0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
-    0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
-    0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
-    0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
-    0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
-    0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
-    0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
-    0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
-    0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
-    0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
-    0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
-    0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
-    0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
-    0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
-    0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
-    0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
-    0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
-    0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
-    0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
-    0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
-    0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
-    0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
-    0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
-    0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
-    0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
-    0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
-    0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
-    0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
-    0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
-    0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
-    0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
-    0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
-    0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
-    0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
-    0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
-    0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
-    0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
-    0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
-    0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
-    0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
-    0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
-    0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
-    0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
-    0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
-    0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
-    0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
-    0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
-    0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
-    0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
-    0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
-    0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
-    0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
-    0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
-    0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
-    0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
-    0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
-    0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
-    0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
-    0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
-    0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
-    0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
-    0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
-    0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
-    0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
-    0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
-    0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
-    0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
-    0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
-    0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
-    0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
-    0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
-    0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
-    0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
-    0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
-    0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
-    0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
-    0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
-    0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
-    0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
-    0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
-    0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
-    0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
-    0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
-    0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
-    0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
-    0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
-    0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
-    0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
-    0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
-    0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
-    0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
-    0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
-    0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
-    0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
-    0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
-    0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
-    0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
-    0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
-    0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
-    0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
-    0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
-    0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
-    0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
-    0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
-    0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
-    0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
-    0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
-    0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
-    0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
-    0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
-    0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
-    0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
-    0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
-    0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
-    0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
-    0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
-    0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
-    0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
-    0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
-    0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
-    0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
-    0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
-    0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
-    0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
-    0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
-    0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
-    0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
-    0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
-    0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
-    0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
-    0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
-    0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
-    0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
-    0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
-    0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
-    0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
-    0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
-    0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
-    0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
-    0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
-    0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
-    0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
-    0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
-    0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
-    0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
-    0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
-    0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
-    0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
-    0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
-    0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
-    0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
-    0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
-    0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
-    0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
-    0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
-    0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
-    0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
-    0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
-    0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
-    0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
-    0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
-    0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
-    0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
-    0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
-    0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
-    0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
-    0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
-    0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
-    0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
-    0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
-    0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
-    0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
-    0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
-    0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
-    0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
-    0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
-    0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
-    0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
-    0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
-    0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
-    0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
-    0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
-    0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
-    0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
-    0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
-    0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
-    0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
-    0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
-    0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
-    0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
-    0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
-    0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
-    0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
-    0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
-    0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
-    0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
-    0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
-    0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
-    0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
-    0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
-    0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
-    0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
-    0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
-    0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
-    0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
-    0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
-    0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
-    0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
-    0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
-    0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
-    0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
-    0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
-    0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
-    0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
-    0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
-    0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
-    0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
-    0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
-    0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
-    0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
-    0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
-    0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
-    0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
-    0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
-    0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
-    0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
-    0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
-    0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
-    0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
-    0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
-    0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
-    0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
-    0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
-    0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
-    0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
-    0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
-    0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
-    0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
-    0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
-    0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
-    0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
-    0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
-    0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
-    0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
-    0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
-    0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
-    0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
-    0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
-    0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
-    0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
-    0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
-    0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
-    0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
-    0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
-    0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
-    0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
-    0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
-    0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
-    0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
-    0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
-    0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
-    0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
-    0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
-    0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
-    0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
-    0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
-    0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
-    0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
-    0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
-    0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
-    0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
-    0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
-    0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
-    0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
-    0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
-    0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
-    0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
-    0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
-    0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
-    0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
-    0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
-    0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
-    0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
-    0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
-    0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
-    0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
-    0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
-    0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
-    0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
-    0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
-    0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
-    0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
-    0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
-    0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
-    0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
-    0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
-    0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
-    0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
-    0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
-    0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
-    0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
-    0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
-    0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
-    0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
-    0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
-    0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
-    0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
-    0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
-    0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
-    0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
-    0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
-    0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
-    0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
-    0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
-    0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
-    0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
-    0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
-    0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
-    0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
-    0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
-    0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
-    0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
-    0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
-    0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
-    0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
-    0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
-    0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
-    0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
-    0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
-    0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
-    0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
-    0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
-    0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
-    0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
-    0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
-    0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
-    0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
-    0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
-    0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
-    0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
-    0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
-    0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
-    0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
-    0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
-    0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
-    0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
-    0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
-    0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
-    0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
-    0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
-    0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
-    0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
-    0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
-    0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
-    0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
-    0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
-    0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
-    0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
-    0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
-    0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
-    0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
-    0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
-    0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
-    0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
-    0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
-    0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
-    0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
-    0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
-    0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
-    0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
-    0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
-    0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
-    0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
-    0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
-    0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
-    0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
-    0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
-    0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
-    0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
-    0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
-    0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
-    0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
-    0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
-    0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
-    0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
-    0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
-    0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
-    0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
-    0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
-    0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
-    0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
-    0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
-    0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
-    0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
-    0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
-    0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
-    0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
-    0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
-    0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
-    0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
-    0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
-    0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
-    0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
-    0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
-    0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
-    0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
-    0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
-    0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
-    0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
-    0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
-    0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
-    0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
-    0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
-    0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
-    0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
-    0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
-    0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
-    0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
-    0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
-    0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
-    0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
-    0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
-    0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
-    0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
-    0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
-    0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
-    0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
-    0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
-    0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
-    0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
-    0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
-    0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
-    0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
-    0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
-    0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
-    0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
-    0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
-    0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
-    0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
-    0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
-    0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
-    0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
-    0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
-    0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
-    0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
-    0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
-    0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
-    0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
-    0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
-    0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
-    0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
-    0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
-    0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
-    0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
-    0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
-    0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
-    0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
-    0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
-    0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
-    0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
-    0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
-    0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
-    0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
-    0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
-    0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
-    0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
-    0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
-    0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
-    0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
-    0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
-    0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
-    0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
-    0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
-    0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
-    0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
-    0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
-    0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
-    0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
-    0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
-    0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
-    0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
-    0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
-    0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
-    0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
-    0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
-    0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
-    0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
-    0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
-    0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
-    0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
-    0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
-    0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
-    0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
-    0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
-    0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
-    0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
-    0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
-    0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
-    0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
-    0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
-    0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
-    0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
-    0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
-    0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
-    0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
-    0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
-    0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
-    0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
-    0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
-    0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
-    0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
-    0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
-    0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
-    0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
-    0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
-    0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
-    0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
-    0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
-    0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
-    0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
-    0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
-    0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
-    0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
-    0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
-    0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
-    0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
-    0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
-    0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
-    0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
-    0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
-    0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
-    0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
-    0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
-    0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
-    0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
-    0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
-    0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
-    0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
-    0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
-    0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
-    0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
-    0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
-    0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
-    0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
-    0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
-    0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
-    0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
-    0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
-    0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
-    0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
-    0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
-    0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
-    0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
-    0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
-    0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
-    0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
-    0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
-    0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
-    0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
-    0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
-    0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
-    0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
-    0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
-    0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
-    0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
-    0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
-    0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
-    0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
-    0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
-    0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
-    0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
-    0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
-    0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
-    0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
-    0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
-    0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
-    0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
-    0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
-    0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
-    0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
-    0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
-    0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
-    0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
-    0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
-    0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
-    0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
-    0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
-    0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
-    0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
-    0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
-    0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
-    0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
-    0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
-    0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
-    0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
-    0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
-    0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
-    0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
-    0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
-    0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
-    0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
-    0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
-    0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
-    0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
-    0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
-    0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
-    0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
-    0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
-    0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
-    0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
-    0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
-    0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
-    0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
-    0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
-    0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
-    0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
-    0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
-    0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
-    0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
-    0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
-    0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
-    0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
-    0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
-    0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
-    0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
-    0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
-    0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
-    0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
-    0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
-    0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
-    0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
-    0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
-    0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
-    0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
-    0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
-    0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
-    0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
-    0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
-    0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
-    0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
-    0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
-    0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
-    0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
-    0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
-    0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
-    0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
-    0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
-    0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
-    0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
-    0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
-    0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
-    0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
-    0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
-    0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
-    0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
-    0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
-    0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
-    0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
-    0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
-    0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
-    0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
-    0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
-    0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
-    0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
-    0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
-    0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
-    0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
-    0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
-    0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
-    0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
-    0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
-    0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
-    0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
-    0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
-    0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
-    0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
-    0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
-    0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
-    0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
-    0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
-    0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
-    0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
-    0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
-    0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
-    0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
-    0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
-    0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
-    0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
-    0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
-    0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
-    0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
-    0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
-    0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
-    0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
-    0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
-    0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
-    0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
-    0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
-    0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
-    0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
-    0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
-    0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
-    0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
-    0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
-    0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
-    0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
-    0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
-    0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
-    0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
-    0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
-    0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
-    0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
-    0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
-    0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
-    0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
-    0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
-    0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
-    0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
-    0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
-    0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
-    0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
-    0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
-    0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
-    0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
-    0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
-    0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
-    0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
-    0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
-    0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
-    0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
-    0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
-    0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
-    0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
-    0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
-    0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
-    0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
-    0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
-    0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
-    0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
-    0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
-    0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
-    0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
-    0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
-    0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
-    0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
-    0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
-    0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
-    0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
-    0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
-    0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
-    0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
-    0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
-    0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
-    0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
-    0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
-    0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
-    0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
-    0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
-    0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
-    0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
-    0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
-    0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
-    0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
-    0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
-    0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
-    0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
-    0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
-    0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
-    0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
-    0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
-    0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
-    0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
-    0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
-    0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
-    0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
-    0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
-    0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
-    0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
-    0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
-    0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
-    0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
-    0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
-    0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
-    0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
-    0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
-    0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
-    0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
-    0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
-    0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
-    0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
-    0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
-    0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
-    0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
-    0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
-    0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
-    0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
-    0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
-    0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
-    0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
-    0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
-    0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
-    0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
-    0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
-    0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
-    0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
-    0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
-    0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
-    0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
-    0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
-    0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
-    0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
-    0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
-    0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
-    0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
-    0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
-    0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
-    0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
-    0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
-    0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
-    0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
-    0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
-    0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
-    0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
-    0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
-    0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
-    0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
-    0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
-    0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
-    0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
-    0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
-    0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
-    0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
-    0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
-    0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
-    0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
-    0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
-    0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
-    0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
-    0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
-    0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
-    0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
-    0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
-    0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
-    0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
-    0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
-    0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
-    0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
-    0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
-    0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
-    0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
-    0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
-    0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
-    0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
-    0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
-    0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
-    0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
-    0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
-    0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
-    0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
-    0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
-    0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
-    0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
-    0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
-    0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
-    0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
-    0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
-    0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
-    0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
-    0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
-    0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
-    0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
-    0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
-    0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
-    0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
-    0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
-    0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
-    0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
-    0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
-    0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
-    0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
-    0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
-    0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
-    0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
-    0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
-    0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
-    0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
-    0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
-    0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
-    0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
-    0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
-    0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
-    0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
-    0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
-    0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
-    0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
-    0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
-    0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
-    0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
-    0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
-    0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
-    0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
-    0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
-    0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
-    0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
-    0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
-    0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
-    0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
-    0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
-    0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
-    0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
-    0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
-    0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
-    0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
-    0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
-    0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
-    0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
-    0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
-    0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
-    0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
-    0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
-    0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
-    0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
-    0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
-    0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
-    0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
-    0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
-    0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
-    0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
-    0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
-    0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
-    0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
-    0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
-    0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
-    0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
-    0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
-    0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
-    0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
-    0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
-    0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
-    0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
-    0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
-    0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
-    0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
-    0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
-    0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
-    0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
-    0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
-    0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
-    0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
-    0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
-    0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
-    0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
-    0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
-    0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
-    0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
-    0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
-    0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
-    0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
-    0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
-    0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
-    0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
-    0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
-    0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
-    0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
-    0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
-    0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
-    0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
-    0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
-    0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
-    0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
-    0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
-    0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
-    0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
-    0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
-    0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
-    0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
-    0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
-    0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
-    0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
-    0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
-    0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
-    0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
-    0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
-    0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
-    0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
-    0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
-    0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
-    0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
-    0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
-    0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
-    0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
-    0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
-    0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
-    0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
-    0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
-    0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
-    0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
-    0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
-    0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
-    0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
-    0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
-    0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
-    0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
-    0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
-    0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
-    0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
-    0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
-    0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
-    0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
-    0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
-    0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
-    0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
-    0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
-    0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
-    0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
-    0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
-    0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
-    0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
-    0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
-    0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
-    0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
-    0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
-    0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
-    0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
-    0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
-    0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
-    0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
-    0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
-    0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
-    0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
-    0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
-    0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
-    0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
-    0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
-    0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
-    0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
-    0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
-    0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
-    0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
-    0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
-    0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
-    0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
-    0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
-    0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
-    0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
-    0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
-    0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
-    0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
-    0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
-    0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
-    0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
-    0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
-    0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
-    0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
-    0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
-    0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
-    0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
-    0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
-    0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
-    0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
-    0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
-    0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
-    0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
-    0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
-    0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
-    0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
-    0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
-    0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
-    0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
-    0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
-    0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
-    0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
-    0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
-    0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
-    0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
-    0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
-    0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
-    0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
-    0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
-    0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
-    0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
-    0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
-    0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
-    0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
-    0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
-    0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
-    0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
-    0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
-    0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
-    0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
-    0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
-    0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
-    0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
-    0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
-    0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
-    0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
-    0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
-    0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
-    0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
-    0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
-    0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
-    0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
-    0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
-    0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
-    0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
-    0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
-    0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
-    0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
-    0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
-    0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
-    0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
-    0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
-    0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
-    0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
-    0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
-    0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
-    0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
-    0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
-    0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
-    0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
-    0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
-    0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
-    0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
-    0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
-    0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
-    0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
-    0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
-    0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
-    0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
-    0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
-    0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
-    0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
-    0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
-    0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
-    0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
-    0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
-    0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
-    0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
-    0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
-    0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
-    0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
-    0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
-    0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
-    0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
-    0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
-    0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
-    0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
-    0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
-    0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
-    0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
-    0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
-    0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
-    0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
-    0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
-    0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
-    0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
-    0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
-    0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
-    0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
-    0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
-    0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
-    0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
-    0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
-    0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
-    0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
-    0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
-    0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
-    0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
-    0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
-    0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
-    0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
-    0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
-    0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
-    0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
-    0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
-    0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
-    0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
-    0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
-    0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
-    0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
-    0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
-    0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
-    0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
-    0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
-    0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
-    0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
-    0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
-    0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
-    0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
-    0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
-    0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
-    0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
-    0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
-    0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
-    0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
-    0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
-    0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
-    0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
-    0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
-    0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
-    0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
-    0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
-    0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
-    0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
-    0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
-    0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
-    0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
-    0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
-    0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
-    0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
-    0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
-    0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
-    0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
-    0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
-    0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
-    0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
-    0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
-    0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
-    0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
-    0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
-    0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
-    0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
-    0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
-    0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
-    0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
-    0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
-    0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
-    0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
-    0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
-    0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
-    0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
-    0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
-    0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
-    0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
-    0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
-    0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
-    0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
-    0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
-    0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
-    0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
-    0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
-    0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
-    0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
-    0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
-    0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
-    0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
-    0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
-    0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
-    0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
-    0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
-    0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
-    0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
-    0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
-    0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
-    0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
-    0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
-    0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
-    0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
-    0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
-    0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
-    0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
-    0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
-    0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
-    0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
-    0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
-    0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
-    0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
-    0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
-    0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
-    0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
-    0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
-    0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
-    0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
-    0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
-    0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
-    0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
-    0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
-    0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
-    0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
-    0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
-    0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
-    0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
-    0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
-    0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
-    0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
-    0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
-    0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
-    0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
-    0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
-    0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
-    0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
-    0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
-    0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
-    0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
-    0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
-    0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
-    0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
-    0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
-    0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
-    0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
-    0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
-    0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
-    0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
-    0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
-    0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
-    0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
-    0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
-    0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
-    0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
-    0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
-    0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
-    0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
-    0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
-    0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
-    0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
-    0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
-    0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
-    0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
-    0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
-    0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
-    0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
-    0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
-    0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
-    0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
-    0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
-    0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
-    0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
-    0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
-    0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
-    0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
-    0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
-    0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
-    0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
-    0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
-    0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
-    0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
-    0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
-    0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
-    0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
-    0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
-    0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
-    0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
-    0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
-    0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
-    0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
-    0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
-    0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
-    0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
-    0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
-    0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
-    0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
-    0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
-    0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
-    0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
-    0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
-    0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
-    0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
-    0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
-    0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
-    0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
-    0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
-    0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
-    0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
-    0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
-    0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
-    0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
-    0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
-    0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
-    0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
-    0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
-    0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
-    0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
-    0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
-    0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
-    0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
-    0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
-    0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
-    0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
-    0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
-    0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
-    0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
-    0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
-    0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
-    0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
-    0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
-    0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
-    0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
-    0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
-    0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
-    0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
-    0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
-    0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
-    0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
-    0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
-    0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
-    0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
-    0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
-    0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
-    0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
-    0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
-    0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
-    0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
-    0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
-    0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
-    0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
-    0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
-    0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
-    0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
-    0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
-    0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
-    0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
-    0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
-    0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
-    0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
-    0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
-    0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
-    0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
-    0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
-    0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
-    0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
-    0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
-    0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
-    0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
-    0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
-    0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
-    0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
-    0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
-    0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
-    0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
-    0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
-    0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
-    0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
-    0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
-    0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
-    0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
-    0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
-};
-
-/**    
-* @brief  Initialization function for the Q31 RFFT/RIFFT.   
-* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.   
-* @param[in]      fftLenReal     length of the FFT.   
-* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    7
-* This function also initializes Twiddle factor table.    
-*/
-
-arm_status arm_rfft_init_q31(
-    arm_rfft_instance_q31 * S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag)
-{
-    /*  Initialise the default arm status */
-    arm_status status = ARM_MATH_SUCCESS;
-
-    /*  Initialize the Real FFT length */
-    S->fftLenReal = (uint16_t) fftLenReal;
-
-    /*  Initialize the Twiddle coefficientA pointer */
-    S->pTwiddleAReal = (q31_t *) realCoefAQ31;
-
-    /*  Initialize the Twiddle coefficientB pointer */
-    S->pTwiddleBReal = (q31_t *) realCoefBQ31;
-
-    /*  Initialize the Flag for selection of RFFT or RIFFT */
-    S->ifftFlagR = (uint8_t) ifftFlagR;
-
-    /*  Initialize the Flag for calculation Bit reversal or not */
-    S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-    /*  Initialization of coef modifier depending on the FFT length */
-    switch (S->fftLenReal)
-    {
-    case 8192u:
-        S->twidCoefRModifier = 1u;
-        S->pCfft = &arm_cfft_sR_q31_len4096;
-        break;
-    case 4096u:
-        S->twidCoefRModifier = 2u;
-        S->pCfft = &arm_cfft_sR_q31_len2048;
-        break;
-    case 2048u:
-        S->twidCoefRModifier = 4u;
-        S->pCfft = &arm_cfft_sR_q31_len1024;
-        break;
-    case 1024u:
-        S->twidCoefRModifier = 8u;
-        S->pCfft = &arm_cfft_sR_q31_len512;
-        break;
-    case 512u:
-        S->twidCoefRModifier = 16u;
-        S->pCfft = &arm_cfft_sR_q31_len256;
-        break;
-    case 256u:
-        S->twidCoefRModifier = 32u;
-        S->pCfft = &arm_cfft_sR_q31_len128;
-        break;
-    case 128u:
-        S->twidCoefRModifier = 64u;
-        S->pCfft = &arm_cfft_sR_q31_len64;
-        break;
-    case 64u:
-        S->twidCoefRModifier = 128u;
-        S->pCfft = &arm_cfft_sR_q31_len32;
-        break;
-    case 32u:
-        S->twidCoefRModifier = 256u;
-        S->pCfft = &arm_cfft_sR_q31_len16;
-        break;
-    default:
-        /*  Reporting argument error if rfftSize is not valid value */
-        status = ARM_MATH_ARGUMENT_ERROR;
-        break;
-    }
-
-    /* return the status of RFFT Init function */
-    return (status);
-}
-
-/**    
-* @} end of RealFFT group    
-*/
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
deleted file mode 100644
index 6e76b9c2..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_q15.c    
-*    
-* Description:	RFFT & RIFFT Q15 process function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.     
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/*--------------------------------------------------------------------    
-*		Internal functions prototypes    
---------------------------------------------------------------------*/
-
-void arm_split_rfft_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    q15_t * pATable,
-    q15_t * pBTable,
-    q15_t * pDst,
-    uint32_t modifier);
-
-void arm_split_rifft_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    q15_t * pATable,
-    q15_t * pBTable,
-    q15_t * pDst,
-    uint32_t modifier);
-
-/**    
-* @addtogroup RealFFT    
-* @{    
-*/
-
-/**    
-* @brief Processing function for the Q15 RFFT/RIFFT.   
-* @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.   
-* @param[in]  *pSrc points to the input buffer.   
-* @param[out] *pDst points to the output buffer.   
-* @return none.   
-*    
-* \par Input an output formats:   
-* \par    
-* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.    
-* Hence the output format is different for different RFFT sizes.    
-* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
-* \par    
-* \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"    
-* \par    
-* \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"    
-*/
-
-void arm_rfft_q15(
-    const arm_rfft_instance_q15 * S,
-    q15_t * pSrc,
-    q15_t * pDst)
-{
-    const arm_cfft_instance_q15 *S_CFFT = S->pCfft;
-    uint32_t i;
-    uint32_t L2 = S->fftLenReal >> 1;
-
-    /* Calculation of RIFFT of input */
-    if(S->ifftFlagR == 1u)
-    {
-        /*  Real IFFT core process */
-        arm_split_rifft_q15(pSrc, L2, S->pTwiddleAReal,
-                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-        
-        /* Complex IFFT process */
-        arm_cfft_q15(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
-        
-        for(i=0;ifftLenReal;i++)
-        {
-            pDst[i] = pDst[i] << 1;
-        }
-    }
-    else
-    {
-        /* Calculation of RFFT of input */
-        
-        /* Complex FFT process */
-        arm_cfft_q15(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
-
-        /*  Real FFT core process */
-        arm_split_rfft_q15(pSrc, L2, S->pTwiddleAReal,
-                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-    }
-}
-
-/**    
-* @} end of RealFFT group    
-*/
-
-/**    
-* @brief  Core Real FFT process    
-* @param  *pSrc 				points to the input buffer.   
-* @param  fftLen  				length of FFT.   
-* @param  *pATable 			points to the A twiddle Coef buffer.    
-* @param  *pBTable 			points to the B twiddle Coef buffer.   
-* @param  *pDst 				points to the output buffer.   
-* @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.    
-* The function implements a Real FFT    
-*/
-
-void arm_split_rfft_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    q15_t * pATable,
-    q15_t * pBTable,
-    q15_t * pDst,
-    uint32_t modifier)
-{
-    uint32_t i;                                    /* Loop Counter */
-    q31_t outR, outI;                              /* Temporary variables for output */
-    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-    q15_t *pSrc1, *pSrc2;
-#ifndef ARM_MATH_CM0_FAMILY
-    q15_t *pD1, *pD2;
-#endif
-
-    //  pSrc[2u * fftLen] = pSrc[0]; 
-    //  pSrc[(2u * fftLen) + 1u] = pSrc[1]; 
-
-    pCoefA = &pATable[modifier * 2u];
-    pCoefB = &pBTable[modifier * 2u];
-
-    pSrc1 = &pSrc[2];
-    pSrc2 = &pSrc[(2u * fftLen) - 2u];
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-    i = 1u;
-    pD1 = pDst + 2;
-    pD2 = pDst + (4u * fftLen) - 2;
-
-    for(i = fftLen - 1; i > 0; i--)
-    {
-        /*    
-        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-        */
-
-        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
-        outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
-
-#else
-
-        /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
-        outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
-        outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 16u;
-
-        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
-#else
-
-        outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
-        outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
-
-        /* write output */
-        *pD1++ = (q15_t) outR;
-        *pD1++ = outI >> 16u;
-
-        /* write complex conjugate output */
-        pD2[0] = (q15_t) outR;
-        pD2[1] = -(outI >> 16u);
-        pD2 -= 2;
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (2u * modifier);
-        pCoefA = pCoefA + (2u * modifier);
-    }
-
-    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
-    pDst[(2u * fftLen) + 1u] = 0;
-
-    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
-    pDst[1] = 0;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-    i = 1u;
-
-    while(i < fftLen)
-    {
-        /*    
-        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-        */
-
-        outR = *pSrc1 * *pCoefA;
-        outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
-        outR = outR + (*pSrc2 * *pCoefB);
-        outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16;
-
-
-        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
-        */
-
-        outI = *pSrc2 * *(pCoefB + 1);
-        outI = outI - (*(pSrc2 + 1) * *pCoefB);
-        outI = outI + (*(pSrc1 + 1) * *pCoefA);
-        outI = outI + (*pSrc1 * *(pCoefA + 1));
-
-        /* update input pointers */
-        pSrc1 += 2u;
-        pSrc2 -= 2u;
-
-        /* write output */
-        pDst[2u * i] = (q15_t) outR;
-        pDst[(2u * i) + 1u] = outI >> 16u;
-
-        /* write complex conjugate output */
-        pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
-        pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 16u);
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (2u * modifier);
-        pCoefA = pCoefA + (2u * modifier);
-
-        i++;
-    }
-
-    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
-    pDst[(2u * fftLen) + 1u] = 0;
-
-    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
-    pDst[1] = 0;
-
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-}
-
-
-/**    
-* @brief  Core Real IFFT process    
-* @param[in]   *pSrc 				points to the input buffer.    
-* @param[in]   fftLen  		    length of FFT.   
-* @param[in]   *pATable 			points to the twiddle Coef A buffer.   
-* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
-* @param[out]  *pDst 				points to the output buffer.   
-* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.    
-* The function implements a Real IFFT    
-*/
-void arm_split_rifft_q15(
-    q15_t * pSrc,
-    uint32_t fftLen,
-    q15_t * pATable,
-    q15_t * pBTable,
-    q15_t * pDst,
-    uint32_t modifier)
-{
-    uint32_t i;                                    /* Loop Counter */
-    q31_t outR, outI;                              /* Temporary variables for output */
-    q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-    q15_t *pSrc1, *pSrc2;
-    q15_t *pDst1 = &pDst[0];
-
-    pCoefA = &pATable[0];
-    pCoefB = &pBTable[0];
-
-    pSrc1 = &pSrc[0];
-    pSrc2 = &pSrc[2u * fftLen];
-
-#ifndef ARM_MATH_CM0_FAMILY
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-    i = fftLen;
-
-    while(i > 0u)
-    {
-        /*    
-        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
-        */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
-        outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
-
-#else
-
-        /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +  
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
-        outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i] */
-        outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 16u;
-
-        /*    
-        -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-        outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
-        /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
-
-#else
-
-        outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-        /* write output */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 16u), 16);
-
-#else
-
-        *__SIMD32(pDst1)++ = __PKHBT((outI >> 16u), outR, 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (2u * modifier);
-        pCoefA = pCoefA + (2u * modifier);
-
-        i--;
-    }
-#else
-    /* Run the below code for Cortex-M0 */
-    i = fftLen;
-
-    while(i > 0u)
-    {
-        /*    
-        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-        */
-
-        outR = *pSrc2 * *pCoefB;
-        outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
-        outR = outR + (*pSrc1 * *pCoefA);
-        outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16;
-
-        /*   
-        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
-        */
-
-        outI = *(pSrc1 + 1) * *pCoefA;
-        outI = outI - (*pSrc1 * *(pCoefA + 1));
-        outI = outI - (*pSrc2 * *(pCoefB + 1));
-        outI = outI - (*(pSrc2 + 1) * *(pCoefB));
-
-        /* update input pointers */
-        pSrc1 += 2u;
-        pSrc2 -= 2u;
-
-        /* write output */
-        *pDst1++ = (q15_t) outR;
-        *pDst1++ = (q15_t) (outI >> 16);
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (2u * modifier);
-        pCoefA = pCoefA + (2u * modifier);
-
-        i--;
-    }
-#endif /* #ifndef ARM_MATH_CM0_FAMILY */
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
deleted file mode 100644
index 71bba217..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
-*    
-* $Date:        19. March 2015 
-* $Revision: 	V.1.4.5  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_q31.c    
-*    
-* Description:	RFFT & RIFFT Q31 process function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Redistribution and use in source and binary forms, with or without 
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the 
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/*--------------------------------------------------------------------    
-*		Internal functions prototypes    
---------------------------------------------------------------------*/
-
-void arm_split_rfft_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pATable,
-    q31_t * pBTable,
-    q31_t * pDst,
-    uint32_t modifier);
-
-void arm_split_rifft_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pATable,
-    q31_t * pBTable,
-    q31_t * pDst,
-    uint32_t modifier);
-
-/**    
-* @addtogroup RealFFT    
-* @{    
-*/
-
-/**    
-* @brief Processing function for the Q31 RFFT/RIFFT.   
-* @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.   
-* @param[in]  *pSrc points to the input buffer.   
-* @param[out] *pDst points to the output buffer.   
-* @return none.   
-*    
-* \par Input an output formats:   
-* \par    
-* Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
-* Hence the output format is different for different RFFT sizes.    
-* The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
-* \par    
-* \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"    
-*    
-* \par    
-* \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"    
-*/
-void arm_rfft_q31(
-    const arm_rfft_instance_q31 * S,
-    q31_t * pSrc,
-    q31_t * pDst)
-{
-    const arm_cfft_instance_q31 *S_CFFT = S->pCfft;
-    uint32_t i;
-    uint32_t L2 = S->fftLenReal >> 1;
-
-    /* Calculation of RIFFT of input */
-    if(S->ifftFlagR == 1u)
-    {
-        /*  Real IFFT core process */
-        arm_split_rifft_q31(pSrc, L2, S->pTwiddleAReal,
-                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-        
-        /* Complex IFFT process */
-        arm_cfft_q31(S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR);
-        
-        for(i=0;ifftLenReal;i++)
-        {
-            pDst[i] = pDst[i] << 1;
-        }
-    }
-    else
-    {
-        /* Calculation of RFFT of input */
-        
-        /* Complex FFT process */
-        arm_cfft_q31(S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR);
-
-        /*  Real FFT core process */
-        arm_split_rfft_q31(pSrc, L2, S->pTwiddleAReal,
-                            S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-    }
-}
-
-/**    
-* @} end of RealFFT group    
-*/
-
-/**    
-* @brief  Core Real FFT process    
-* @param[in]   *pSrc 				points to the input buffer.    
-* @param[in]   fftLen  			    length of FFT.   
-* @param[in]   *pATable 			points to the twiddle Coef A buffer.    
-* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
-* @param[out]  *pDst 				points to the output buffer.    
-* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.    
-*/
-void arm_split_rfft_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pATable,
-    q31_t * pBTable,
-    q31_t * pDst,
-    uint32_t modifier)
-{
-    uint32_t i;                                    /* Loop Counter */
-    q31_t outR, outI;                              /* Temporary variables for output */
-    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
-    q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
-    q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
-
-    /* Init coefficient pointers */
-    pCoefA = &pATable[modifier * 2u];
-    pCoefB = &pBTable[modifier * 2u];
-
-    i = fftLen - 1u;
-
-    while(i > 0u)
-    {
-        /*    
-        outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-        + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-        pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-        */
-
-        /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-        CoefA1 = *pCoefA++;
-        CoefA2 = *pCoefA;
-
-        /* outR = (pSrc[2 * i] * pATable[2 * i] */    
-        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
-
-        /* outI = pIn[2 * i] * pATable[2 * i + 1] */
-        mult_32x32_keep32_R(outI, *pIn1++, CoefA2);
-
-        /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
-        multSub_32x32_keep32_R(outR, *pIn1, CoefA2);
-
-        /* (pIn[2 * i + 1] * pATable[2 * i] */
-        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
-
-        /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
-        multSub_32x32_keep32_R(outR, *pIn2, CoefA2);
-        CoefB1 = *pCoefB;
-
-        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
-        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
-
-        /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
-        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
-
-        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-        multSub_32x32_keep32_R(outI, *pIn2--, CoefA2);
-
-        /* write output */
-        *pOut1++ = outR;
-        *pOut1++ = outI;
-
-        /* write complex conjugate output */
-        *pOut2-- = -outI;
-        *pOut2-- = outR;
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (modifier * 2u);
-        pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-        i--;
-    }
-    pDst[2u * fftLen] = (pSrc[0] - pSrc[1]) >> 1;
-    pDst[(2u * fftLen) + 1u] = 0;
-
-    pDst[0] = (pSrc[0] + pSrc[1]) >> 1;
-    pDst[1] = 0;
-}
-
-/**    
-* @brief  Core Real IFFT process    
-* @param[in]   *pSrc 				points to the input buffer.   
-* @param[in]   fftLen  			    length of FFT.    
-* @param[in]   *pATable 			points to the twiddle Coef A buffer.   
-* @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
-* @param[out]  *pDst 				points to the output buffer.   
-* @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
-* @return none.    
-*/
-void arm_split_rifft_q31(
-    q31_t * pSrc,
-    uint32_t fftLen,
-    q31_t * pATable,
-    q31_t * pBTable,
-    q31_t * pDst,
-    uint32_t modifier)
-{
-    q31_t outR, outI;                              /* Temporary variables for output */
-    q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-    q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
-    q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
-
-    pCoefA = &pATable[0];
-    pCoefB = &pBTable[0];
-
-    while(fftLen > 0u)
-    {
-        /*    
-        outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-        pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-        outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-        pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-        pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
-        */
-        CoefA1 = *pCoefA++;
-        CoefA2 = *pCoefA;
-
-        /* outR = (pIn[2 * i] * pATable[2 * i] */
-        mult_32x32_keep32_R(outR, *pIn1, CoefA1);
-
-        /* - pIn[2 * i] * pATable[2 * i + 1] */
-        mult_32x32_keep32_R(outI, *pIn1++, -CoefA2);
-        
-        /* pIn[2 * i + 1] * pATable[2 * i + 1] */
-        multAcc_32x32_keep32_R(outR, *pIn1, CoefA2);
-
-        /* pIn[2 * i + 1] * pATable[2 * i] */
-        multAcc_32x32_keep32_R(outI, *pIn1++, CoefA1);
-
-        /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
-        multAcc_32x32_keep32_R(outR, *pIn2, CoefA2);
-        CoefB1 = *pCoefB;
-
-        /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
-        multSub_32x32_keep32_R(outI, *pIn2--, CoefB1);
-
-        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
-        multAcc_32x32_keep32_R(outR, *pIn2, CoefB1);
-
-        /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-        multAcc_32x32_keep32_R(outI, *pIn2--, CoefA2);
-
-        /* write output */
-        *pDst++ = outR;
-        *pDst++ = outI;
-
-        /* update coefficient pointer */
-        pCoefB = pCoefB + (modifier * 2u);
-        pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-        /* Decrement loop count */
-        fftLen--;
-    }
-}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h
index cc72a55c..cdc64d1a 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h
@@ -2,45 +2,28 @@
   ******************************************************************************
   * @file    stm32f205xx.h
   * @author  MCD Application Team
-  * @version V2.1.0
-  * @date    09-October-2015
   * @brief   CMSIS STM32F205xx Device Peripheral Access Layer Header File. 
+  *
   *          This file contains :  
   *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
+  *           - Peripherals registers declarations and bits definition
   *           - Macros to access peripheral’s registers hardware
   *
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
-/** @addtogroup CMSIS
+/** @addtogroup CMSIS_Device
   * @{
   */
 
@@ -55,7 +38,6 @@
  extern "C" {
 #endif /* __cplusplus */
   
-
 /** @addtogroup Configuration_section_for_CMSIS
   * @{
   */
@@ -63,10 +45,10 @@
 /**
   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
   */
-#define __CM3_REV                 0x0200  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F2XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
 
 /**
   * @}
@@ -84,6 +66,7 @@ typedef enum
 {
 /******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Hard Fault Interrupt                                            */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
@@ -168,7 +151,7 @@ typedef enum
   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  HASH_RNG_IRQn               = 80      /*!< Hash and Rng global interrupt                                     */
+   RNG_IRQn                   = 80      /*!< Rng global interrupt                                     */
 } IRQn_Type;
 
 /**
@@ -483,7 +466,6 @@ typedef struct
   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
 } I2C_TypeDef;
 
 /** 
@@ -696,7 +678,6 @@ typedef struct
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 
-
 /** 
   * @brief RNG
   */
@@ -715,24 +696,24 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
+  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
+  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
+  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
 }
 USB_OTG_GlobalTypeDef;
 
@@ -743,26 +724,26 @@ USB_OTG_GlobalTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
+  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
+  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
+  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
+  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
+  __IO uint32_t DIEPMSK;      /*!< dev IN Endpoint Mask        Address offset : 0x810 */
+  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
+  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
+  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
+  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
+  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
+  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
+  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
+  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
+  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
+  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
+  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
+  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
+  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
+  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
+  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
 }
 USB_OTG_DeviceTypeDef;
 
@@ -772,14 +753,14 @@ USB_OTG_DeviceTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
+  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
+  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
+  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
+  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
+  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
+  __IO uint32_t DTXFSTS;        /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
+  uint32_t Reserved18;          /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 }
 USB_OTG_INEndpointTypeDef;
 
@@ -835,17 +816,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x080FFFFF) /*!< FLASH end address                                                          */
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -854,114 +837,121 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
 
 /*!< AHB2 peripherals */
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
 
 /*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000UL
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
-
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+/*******************  Device electronic signature  ***************/
+#define UID_BASE             0x1FFF7A10UL        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE       0x1FFF7A22UL        /*!< FLASH Size register base address */
 
 /**
   * @}
@@ -994,15 +984,18 @@ USB_OTG_HostChannelTypeDef;
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
 #define USART1              ((USART_TypeDef *) USART1_BASE)
 #define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
 #define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
@@ -1039,7 +1032,7 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)  
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
@@ -1073,360 +1066,593 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
-/** @addtogroup CMSIS
+/** @addtogroup CMSIS_Device
   * @{
   */
 
@@ -55,7 +38,6 @@
  extern "C" {
 #endif /* __cplusplus */
   
-
 /** @addtogroup Configuration_section_for_CMSIS
   * @{
   */
@@ -63,10 +45,10 @@
 /**
   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
   */
-#define __CM3_REV                 0x0200  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F2XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
 
 /**
   * @}
@@ -84,6 +66,7 @@ typedef enum
 {
 /******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Hard Fault Interrupt                                            */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
@@ -171,7 +154,7 @@ typedef enum
   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  HASH_RNG_IRQn               = 80      /*!< Hash and Rng global interrupt                                     */
+   RNG_IRQn                   = 80      /*!< Rng global interrupt                                     */
 } IRQn_Type;
 
 /**
@@ -393,7 +376,8 @@ typedef struct
   uint32_t      RESERVED0[2];
   __IO uint32_t MACRWUFFR;             /*   11 */
   __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
   __IO uint32_t MACSR;                 /*   15 */
   __IO uint32_t MACIMR;
   __IO uint32_t MACA0HR;
@@ -578,7 +562,6 @@ typedef struct
   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
 } I2C_TypeDef;
 
 /** 
@@ -809,24 +792,24 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
+  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
+  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
+  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
 }
 USB_OTG_GlobalTypeDef;
 
@@ -837,26 +820,26 @@ USB_OTG_GlobalTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
+  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
+  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
+  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
+  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
+  __IO uint32_t DIEPMSK;      /*!< dev IN Endpoint Mask        Address offset : 0x810 */
+  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
+  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
+  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
+  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
+  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
+  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
+  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
+  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
+  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
+  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
+  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
+  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
+  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
+  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
+  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
 }
 USB_OTG_DeviceTypeDef;
 
@@ -866,14 +849,14 @@ USB_OTG_DeviceTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
+  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
+  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
+  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
+  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
+  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
+  __IO uint32_t DTXFSTS;        /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
+  uint32_t Reserved18;          /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 }
 USB_OTG_INEndpointTypeDef;
 
@@ -900,12 +883,12 @@ USB_OTG_OUTEndpointTypeDef;
 typedef struct 
 {
   __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
+  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;           /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
 }
 USB_OTG_HostTypeDef;
 
@@ -929,17 +912,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x080FFFFF) /*!< FLASH end address                                                          */
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -948,120 +933,127 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
 #define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
 
 /*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
 
 /*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000UL
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
-
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+/*******************  Device electronic signature  ***************/
+#define UID_BASE             0x1FFF7A10UL        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE       0x1FFF7A22UL        /*!< FLASH Size register base address */
 
 /**
   * @}
@@ -1094,15 +1086,18 @@ USB_OTG_HostChannelTypeDef;
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
 #define USART1              ((USART_TypeDef *) USART1_BASE)
 #define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
 #define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
@@ -1175,360 +1170,593 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
-/** @addtogroup CMSIS
+/** @addtogroup CMSIS_Device
   * @{
   */
 
@@ -55,7 +38,6 @@
  extern "C" {
 #endif /* __cplusplus */
   
-
 /** @addtogroup Configuration_section_for_CMSIS
   * @{
   */
@@ -63,10 +45,10 @@
 /**
   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
   */
-#define __CM3_REV                 0x0200  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F2XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
 
 /**
   * @}
@@ -84,6 +66,7 @@ typedef enum
 {
 /******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Hard Fault Interrupt                                            */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
@@ -484,7 +467,6 @@ typedef struct
   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
 } I2C_TypeDef;
 
 /** 
@@ -697,6 +679,7 @@ typedef struct
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 
+
 /** 
   * @brief Crypto Processor
   */
@@ -705,7 +688,7 @@ typedef struct
 {
   __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
   __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
-  __IO uint32_t DR;     /*!< CRYP data input register,                         Address offset: 0x08 */
+  __IO uint32_t DIN;    /*!< CRYP data input register,                                 Address offset: 0x08 */
   __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
   __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
   __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
@@ -759,24 +742,24 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
+  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
+  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
+  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
 }
 USB_OTG_GlobalTypeDef;
 
@@ -787,26 +770,26 @@ USB_OTG_GlobalTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
+  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
+  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
+  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
+  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
+  __IO uint32_t DIEPMSK;      /*!< dev IN Endpoint Mask        Address offset : 0x810 */
+  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
+  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
+  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
+  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
+  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
+  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
+  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
+  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
+  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
+  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
+  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
+  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
+  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
+  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
+  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
 }
 USB_OTG_DeviceTypeDef;
 
@@ -816,14 +799,14 @@ USB_OTG_DeviceTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
+  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
+  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
+  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
+  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
+  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
+  __IO uint32_t DTXFSTS;        /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
+  uint32_t Reserved18;          /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 }
 USB_OTG_INEndpointTypeDef;
 
@@ -850,12 +833,12 @@ USB_OTG_OUTEndpointTypeDef;
 typedef struct 
 {
   __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
+  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;           /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
 }
 USB_OTG_HostTypeDef;
 
@@ -879,18 +862,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x080FFFFF) /*!< FLASH end address                                                          */
-
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -899,117 +883,123 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
 
 /*!< AHB2 peripherals */
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000UL)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
 
 /*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000UL
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
-
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+/*******************  Device electronic signature  ***************/
+#define UID_BASE             0x1FFF7A10UL        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE       0x1FFF7A22UL        /*!< FLASH Size register base address */
 
 /**
   * @}
@@ -1042,15 +1032,18 @@ USB_OTG_HostChannelTypeDef;
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
 #define USART1              ((USART_TypeDef *) USART1_BASE)
 #define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
 #define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
@@ -1090,7 +1083,6 @@ USB_OTG_HostChannelTypeDef;
 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
 #define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
@@ -1124,360 +1116,593 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
-/** @addtogroup CMSIS
+/** @addtogroup CMSIS_Device
   * @{
   */
 
@@ -55,7 +38,6 @@
  extern "C" {
 #endif /* __cplusplus */
   
-
 /** @addtogroup Configuration_section_for_CMSIS
   * @{
   */
@@ -63,10 +45,10 @@
 /**
   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
   */
-#define __CM3_REV                 0x0200  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1       /*!< STM32F2XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
 
 /**
   * @}
@@ -84,6 +66,7 @@ typedef enum
 {
 /******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Hard Fault Interrupt                                            */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
@@ -394,7 +377,8 @@ typedef struct
   uint32_t      RESERVED0[2];
   __IO uint32_t MACRWUFFR;             /*   11 */
   __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1[2];
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
   __IO uint32_t MACSR;                 /*   15 */
   __IO uint32_t MACIMR;
   __IO uint32_t MACA0HR;
@@ -579,7 +563,6 @@ typedef struct
   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
 } I2C_TypeDef;
 
 /** 
@@ -792,6 +775,7 @@ typedef struct
   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 } WWDG_TypeDef;
 
+
 /** 
   * @brief Crypto Processor
   */
@@ -800,7 +784,7 @@ typedef struct
 {
   __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
   __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
-  __IO uint32_t DR;     /*!< CRYP data input register,                         Address offset: 0x08 */
+  __IO uint32_t DIN;    /*!< CRYP data input register,                                 Address offset: 0x08 */
   __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
   __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
   __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
@@ -854,24 +838,24 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t GOTGCTL;      /*!<  USB_OTG Control and Status Register    000h*/
-  __IO uint32_t GOTGINT;      /*!<  USB_OTG Interrupt Register             004h*/
-  __IO uint32_t GAHBCFG;      /*!<  Core AHB Configuration Register    008h*/
-  __IO uint32_t GUSBCFG;      /*!<  Core USB Configuration Register    00Ch*/
-  __IO uint32_t GRSTCTL;      /*!<  Core Reset Register                010h*/
-  __IO uint32_t GINTSTS;      /*!<  Core Interrupt Register            014h*/
-  __IO uint32_t GINTMSK;      /*!<  Core Interrupt Mask Register       018h*/
-  __IO uint32_t GRXSTSR;      /*!<  Receive Sts Q Read Register        01Ch*/
-  __IO uint32_t GRXSTSP;      /*!<  Receive Sts Q Read & POP Register  020h*/
-  __IO uint32_t GRXFSIZ;      /* Receive FIFO Size Register         024h*/
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register 028h*/
-  __IO uint32_t HNPTXSTS;     /*!<  Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
-  uint32_t Reserved30[2];     /* Reserved                           030h*/
-  __IO uint32_t GCCFG;        /* General Purpose IO Register        038h*/
-  __IO uint32_t CID;          /* User ID Register                   03Ch*/
-  uint32_t  Reserved40[48];   /* Reserved                      040h-0FFh*/
-  __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg     100h*/
-  __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
+  uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
+  __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
+  __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
+  uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
 }
 USB_OTG_GlobalTypeDef;
 
@@ -882,26 +866,26 @@ USB_OTG_GlobalTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DCFG;         /* dev Configuration Register   800h*/
-  __IO uint32_t DCTL;         /* dev Control Register         804h*/
-  __IO uint32_t DSTS;         /* dev Status Register (RO)     808h*/
-  uint32_t Reserved0C;           /* Reserved                     80Ch*/
-  __IO uint32_t DIEPMSK;   /* dev IN Endpoint Mask         810h*/
-  __IO uint32_t DOEPMSK;  /* dev OUT Endpoint Mask        814h*/
-  __IO uint32_t DAINT;     /* dev All Endpoints Itr Reg    818h*/
-  __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask   81Ch*/
-  uint32_t  Reserved20;          /* Reserved                     820h*/
-  uint32_t Reserved9;       /* Reserved                     824h*/
-  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
-  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
-  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
-  __IO uint32_t DIEPEMPMSK; /* dev empty msk             834h*/
-  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
-  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
-  uint32_t Reserved40;      /* dedicated EP mask           840h*/
-  __IO uint32_t DINEP1MSK;  /* dedicated EP mask           844h*/
-  uint32_t  Reserved44[15];      /* Reserved                 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK; /* dedicated EP msk            884h*/   
+  __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
+  __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
+  __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
+  uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
+  __IO uint32_t DIEPMSK;      /*!< dev IN Endpoint Mask        Address offset : 0x810 */
+  __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
+  __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
+  __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
+  uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
+  uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
+  __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
+  __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
+  __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
+  __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
+  __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
+  __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */  
+  uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
+  __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
+  uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
+  __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */   
 }
 USB_OTG_DeviceTypeDef;
 
@@ -911,14 +895,14 @@ USB_OTG_DeviceTypeDef;
   */
 typedef struct 
 {
-  __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;             /* Reserved                       900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;             /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;             /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+  __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
+  uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
+  __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
+  uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
+  __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
+  __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
+  __IO uint32_t DTXFSTS;        /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
+  uint32_t Reserved18;          /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 }
 USB_OTG_INEndpointTypeDef;
 
@@ -945,12 +929,12 @@ USB_OTG_OUTEndpointTypeDef;
 typedef struct 
 {
   __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
-  __IO uint32_t HFIR;      /* Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;         /* Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;                   /* Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;   /* Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;   /* Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;   /* Host All Channels Interrupt Mask 418h*/
+  __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;           /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
 }
 USB_OTG_HostTypeDef;
 
@@ -974,17 +958,19 @@ USB_OTG_HostChannelTypeDef;
 /** 
   * @brief Peripheral_memory_map
   */
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */
-#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             ((uint32_t)0x080FFFFF) /*!< FLASH end address                                                          */
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
+#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
 
 /* Legacy defines */
 #define SRAM_BASE             SRAM1_BASE
@@ -993,123 +979,129 @@ USB_OTG_HostChannelTypeDef;
 
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
 
 /*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
 
 /*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
 
 /*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
 #define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
 
 /*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
-#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
-#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
-#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000UL)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
 
 /*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
 
 /* Debug MCU registers base address */
-#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+#define DBGMCU_BASE           0xE0042000UL
 
 /*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               ((uint32_t )0x40040000)
-#define USB_OTG_FS_PERIPH_BASE               ((uint32_t )0x50000000)
-
-#define USB_OTG_GLOBAL_BASE                  ((uint32_t )0x000)
-#define USB_OTG_DEVICE_BASE                  ((uint32_t )0x800)
-#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t )0x900)
-#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t )0xB00)
-#define USB_OTG_EP_REG_SIZE                  ((uint32_t )0x20)
-#define USB_OTG_HOST_BASE                    ((uint32_t )0x400)
-#define USB_OTG_HOST_PORT_BASE               ((uint32_t )0x440)
-#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t )0x500)
-#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t )0x20)
-#define USB_OTG_PCGCCTL_BASE                 ((uint32_t )0xE00)
-#define USB_OTG_FIFO_BASE                    ((uint32_t )0x1000)
-#define USB_OTG_FIFO_SIZE                    ((uint32_t )0x1000)
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+/*******************  Device electronic signature  ***************/
+#define UID_BASE             0x1FFF7A10UL        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE       0x1FFF7A22UL        /*!< FLASH Size register base address */
 
 /**
   * @}
@@ -1142,15 +1134,18 @@ USB_OTG_HostChannelTypeDef;
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
 #define USART1              ((USART_TypeDef *) USART1_BASE)
 #define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
 #define SPI1                ((SPI_TypeDef *) SPI1_BASE) 
 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
@@ -1192,7 +1187,6 @@ USB_OTG_HostChannelTypeDef;
 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
 #define HASH                ((HASH_TypeDef *) HASH_BASE)
-#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
@@ -1226,360 +1220,593 @@ USB_OTG_HostChannelTypeDef;
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)       /*!
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -99,17 +81,17 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.1.0
-  */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32F2xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-                                             
+  * @brief CMSIS Device version number V2.2.2
+  */
+#define __STM32F2xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F2xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32F2xx_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+#define __STM32F2xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F2xx_CMSIS_VERSION        ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F2xx_CMSIS_VERSION))
+
 /**
   * @}
   */
@@ -139,21 +121,21 @@
   */ 
 typedef enum 
 {
-  RESET = 0, 
+  RESET = 0U, 
   SET = !RESET
 } FlagStatus, ITStatus;
 
 typedef enum 
 {
-  DISABLE = 0, 
+  DISABLE = 0U, 
   ENABLE = !DISABLE
 } FunctionalState;
 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
 typedef enum 
 {
-  ERROR = 0, 
-  SUCCESS = !ERROR
+  SUCCESS = 0U,
+  ERROR = !SUCCESS
 } ErrorStatus;
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h
index 16f8e86e..ac0d6518 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    system_stm32f2xx.h
   * @author  MCD Application Team
-  * @version V2.1.0
-  * @date    09-October-2015
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.       
-******************************************************************************
+  * @brief   CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
+  ****************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
+  ******************************************************************************
+  */
 
 /** @addtogroup CMSIS
   * @{
@@ -75,6 +57,8 @@
   */
 extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
 
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s
index b17214ed..418feaf7 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s
@@ -1,8 +1,6 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f205xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F205xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,31 +11,18 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;******************************************************************************
+;* @attention
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; 
-;*******************************************************************************
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s
index 1dd59f9e..82e8ba04 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f207xx.s
@@ -1,8 +1,6 @@
-******************* (C) COPYRIGHT 2015 STMicroelectronics ********************
+******************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f207xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F207xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,31 +11,18 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;******************************************************************************
+;* @attention
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; 
-;*******************************************************************************
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f215xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f215xx.s
index fcdfec8e..bc5c95d4 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f215xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f215xx.s
@@ -1,8 +1,6 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f215xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F215xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,31 +11,18 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;******************************************************************************
+;* @attention
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; 
-;*******************************************************************************
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f217xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f217xx.s
index a65b707d..58aa783e 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f217xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f217xx.s
@@ -1,8 +1,6 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f217xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F217xx devices vector table for MDK-ARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,31 +11,18 @@
 ;*                      After Reset the CortexM3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-; 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;******************************************************************************
+;* @attention
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; 
-;*******************************************************************************
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f205xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f205xx.s
index 5e534225..3eb1691f 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f205xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f205xx.s
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32f205xx.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      09-October-2015
   * @brief     STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -16,29 +14,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s
index c5ec0e0c..b34aa820 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32f207xx.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      09-October-2015
   * @brief     STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -16,29 +14,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s
index 67917624..c51829ad 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32f215xx.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      09-October-2015
   * @brief     STM32F215xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -16,29 +14,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s
index 3f024dc9..a9ceb28d 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32f217xx.s
   * @author    MCD Application Team
-  * @version   V2.1.0
-  * @date      09-October-2015
   * @brief     STM32F217xx Devices vector table for Atollic TrueSTUDIO toolchain. 
   *            This module performs:
   *                - Set the initial SP
@@ -16,29 +14,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s
index 45d25523..f60726d1 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f205xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,30 +11,17 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;*******************************************************************************
+;* @attention
+;*
+;* 
© Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.

+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
 ;*******************************************************************************
 ;
 ;
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s
index 483a496e..e72150d1 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f207xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,30 +11,17 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;*******************************************************************************
+;* @attention
+;*
+;* 
© Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.

+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
 ;*******************************************************************************
 ;
 ;
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s
index ffa4af4c..4d9ab95d 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f215xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,30 +11,17 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;*******************************************************************************
+;* @attention
+;*
+;* 
© Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.

+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
 ;*******************************************************************************
 ;
 ;
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s
index aa05aeee..dbfeb077 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32f217xx.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 09-October-2015
 ;* Description        : STM32F20x/21x devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -13,30 +11,17 @@
 ;*                        calls main()).
 ;*                      After Reset the Cortex-M3 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
+;*******************************************************************************
+;* @attention
+;*
+;* 
© Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.

+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
 ;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
 ;*******************************************************************************
 ;
 ;
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
index acd46803..3c2a20b0 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f2xx.c
   * @author  MCD Application Team
-  * @version V2.1.0
-  * @date    09-October-2015
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *             
   *   This file provides two functions and one global variable to be called from 
@@ -23,29 +21,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -65,7 +47,7 @@
 #include "stm32f2xx.h"
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
@@ -123,9 +105,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 12000000;
+  uint32_t SystemCoreClock = 16000000;
   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
+  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 /**
   * @}
   */
@@ -211,10 +193,10 @@ void SystemInit(void)
   *             16 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.   
   *    
-  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
   *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_common_tables.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_common_tables.h
deleted file mode 100644
index 039cc3d6..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_common_tables.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
-*
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-//extern const q31_t realCoefAQ31[1024];
-//extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_const_structs.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_const_structs.h
deleted file mode 100644
index 726d06eb..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_const_structs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
-*
-* Description:	This file has constant structs that are initialized for
-*              user convenience.  For example, some can be given as
-*              arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_math.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_math.h
deleted file mode 100644
index e4b2f62e..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7556 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-*
-* $Date:        19. March 2015
-* $Revision: 	V.1.4.5
-*
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_math.h
-*
-* Description:	Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the Lib folder.
-   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
-   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
-   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
-   *
-   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file  arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
-   *
-   * 

-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   * 
-   * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   * 
-   * 

-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * 

- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size numRows X numCols
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * 
- *     pData[i*numCols + j]
- * 

- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
- * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- * 

- * where nRows specifies the number of rows, nColumns
- * specifies the number of columns, and pData points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * 
- *     ARM_MATH_SIZE_MISMATCH
- * 

- * Otherwise the functions return
- * 
- *     ARM_MATH_SUCCESS
- * 

- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * 
- *     ARM_MATH_MATRIX_CHECK
- * 

- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return ARM_MATH_SUCCESS.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-  #include "core_cm7.h"
-#elif defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-  #elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-  #define ARM_MATH_CM0_FAMILY
-#else
-  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#ifndef PI
-#define PI					3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SIZE  256
-#define TABLE_SPACING_Q31	   0x400000
-#define TABLE_SPACING_Q15	   0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if defined __CC_ARM
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED __attribute__((unused))
-#elif defined __ICCARM__
-  #define __SIMD32_TYPE int32_t __packed
-  #define CMSIS_UNUSED
-#elif defined __GNUC__
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED __attribute__((unused))
-#elif defined __CSMC__			/* Cosmic */
-  #define __SIMD32_TYPE int32_t
-  #define CMSIS_UNUSED
-#elif defined __TASKING__
-  #define __SIMD32_TYPE __unaligned int32_t
-  #define CMSIS_UNUSED
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-
-#define __SIMD64(addr)  (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  static __INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  static __INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  static __INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  static __INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  static __INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-//#define __CLZ __clz
-//#endif
-
-//note: function can be removed when all toolchain support __CLZ for Cortex-M0
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data);
-
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-
-  }
-
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  static __INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 1;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 1;
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-      tempVal = 0x7FFFFFFF - tempVal;
-      /*      1.31 with exp 1 */
-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  static __INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 17;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 17;
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-    {
-      tempVal = (q15_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFF - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0_FAMILY)
-
-  static __INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if(x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if(x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if(x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum =
-      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
-                                                                0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (q15_t) x;
-    s = (q15_t) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSDX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
-                     ((q15_t) (x >> 16) * (q15_t) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUADX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
-                     ((q15_t) (x >> 16) * (q15_t) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLAD(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
-            ((q15_t) x * (q15_t) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLADX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
-            ((q15_t) x * (q15_t) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLSDX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
-            ((q15_t) x * (q15_t) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALD(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
-            ((q15_t) x * (q15_t) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALDX(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
-      ((q15_t) x * (q15_t) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUAD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SXTB16(
-  q31_t x)
-  {
-
-    return ((((x << 24) >> 24) & 0x0000FFFF) |
-            (((x << 8) >> 8) & 0xFFFF0000));
-  }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * numTaps is not a supported value.
-   */
-
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f64;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point, complex, matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15, complex,  matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Q31, complex, matrix multiplication.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_cmplx_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
-   * or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
-   * or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
-   * or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @param[in]		 *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;                /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q15;
-
-void arm_cfft_q15( 
-    const arm_cfft_instance_q15 * S, 
-    q15_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
-
-  /**
-   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_q31;
-
-void arm_cfft_q31( 
-    const arm_cfft_instance_q31 * S, 
-    q31_t * p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
-  
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;                        /**< length of the real sequence */
-	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-	arm_rfft_fast_instance_f32 * S,
-	uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-    /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * blockSize is not a multiple of M.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * blockSize is not a multiple of M.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * blockSize is not a multiple of M.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length numTaps is not a multiple of the interpolation factor L.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length numTaps is not a multiple of the interpolation factor L.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length numTaps is not a multiple of the interpolation factor L.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f64;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_stereo_df2T_f32(
-  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f64(
-  const arm_biquad_cascade_df2T_instance_f64 * S,
-  float64_t * pSrc,
-  float64_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_stereo_df2T_init_f32(
-  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f64(
-  arm_biquad_cascade_df2T_instance_f64 * S,
-  uint8_t numStages,
-  float64_t * pCoeffs,
-  float64_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cos output.
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cosine output.
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * S points to an instance of the PID control data structure.  in
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  

-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  static __INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-
-  static __INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  static __INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
-
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f64(
-  const arm_matrix_instance_f64 * src,
-  arm_matrix_instance_f64 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
-   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
-   * When Ialpha is superposed with Ia as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
-   * can be calculated using only Ia and Ib.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where Ia and Ib are the instantaneous stator phases and
-   * pIalpha and pIbeta are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate a
-   * @param[in]       Ib       input three-phase coordinate b
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  static __INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta =
-      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate a
-   * @param[in]       Ib       input three-phase coordinate b
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where pIa and pIb are the instantaneous stator phases and
-   * Ialpha and Ibeta are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate a
-   * @param[out]      *pIb    points to output three-phase coordinate b
-   * @return none.
-   */
-
-
-  static __INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate a
-   * @param[out]      *pIb    points to output three-phase coordinate b
-   * @return none.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where Ialpha and Ibeta are the stator vector components,
-   * pId and pIq are rotor vector components and cosVal and sinVal are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  static __INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where pIalpha and pIbeta are the stator vector components,
-   * Id and Iq are rotor vector components and cosVal and sinVal are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  static __INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * Scaling and Overflow Behavior:
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * 

-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * S points to an instance of the Linear Interpolate function data structure.
-   * x is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  static __INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if(i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 + i * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-
-    }
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (y >> 20);
-    }
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  static __INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-
-    if(index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (y >> 20u);
-
-    }
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-  float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-  q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-  float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   * 

-   * where x1 is the current estimate,
-   * x0 is the previous estimate, and
-   * f'(x0) is the derivative of f() evaluated at x0.
-   * For the square root function, the algorithm reduces to:
-   * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * 

-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * in is negative value and returns zero output for negative values.
-   */
-
-  static __INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if(in >= 0.0f)
-    {
-
-//      #if __FPU_USED
-#if (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * in is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * in is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  static __INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return none.
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * Algorithm
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * 

-   *
-   * \par
-   * where numRows specifies the number of rows in the table;
-   * numCols specifies the number of columns in the table;
-   * and pData points to an array of size numRows*numCols values.
-   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
-   *
-   * \par
-   * Let (x, y) specify the desired interpolation point.  Then define:
-   * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * 

-   * \par
-   * The interpolated output point is computed as:
-   * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * 

-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-
-  static __INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
-       || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-   
-
-//SMMLAR
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMLSR
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMULR
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-//SMMLA
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMLS
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM ) //Keil
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_ENTER \
-         _Pragma ("push")         \
-         _Pragma ("O1")
-    #else
-      #define LOW_OPTIMIZATION_ENTER 
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_EXIT \
-         _Pragma ("pop")
-    #else
-      #define LOW_OPTIMIZATION_EXIT  
-    #endif
-
-//Enter low optimization region - place directly above function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__) //IAR
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define LOW_OPTIMIZATION_ENTER \
-         _Pragma ("optimize=low")
-    #else
-      #define LOW_OPTIMIZATION_ENTER   
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-  #define LOW_OPTIMIZATION_EXIT
-
-//Enter low optimization region - place directly above function definition
-    #ifdef ARM_MATH_CM4
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-         _Pragma ("optimize=low")
-    #else
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
-    #endif
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
-
-  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
-
-  #define LOW_OPTIMIZATION_EXIT
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__CSMC__)		// Cosmic
-
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__TASKING__)		// TASKING
-
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0.h
index cf2b5d66..f929bba0 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_cm0.h
  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM0_H_GENERIC
 #define __CORE_CM0_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,74 +55,49 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex_M0
+/**
+  \ingroup Cortex_M0
   @{
  */
 
+#include "cmsis_version.h"
+ 
 /*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#endif
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0
+#define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -138,15 +105,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -166,17 +133,17 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
+    #define __CM0_REV               0x0000U
     #warning "__CM0_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
+    #define __NVIC_PRIO_BITS          2U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -190,12 +157,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group Cortex_M0 */
 
@@ -209,325 +181,364 @@
   - Core SCB Register
   - Core SysTick Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/* Memory mapping of Cortex-M0 Hardware */
+/* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 
 
 /*@} */
@@ -541,179 +552,377 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
 
-    \param [in]      IRQn  Interrupt number.
 
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
 
-    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
 
-    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
 
-    The function sets the priority of an interrupt.
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
 
-    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
 
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-/** \brief  Get Interrupt Priority
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
 
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
 
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
-
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
 
-    The function initiates a system reset request to reset the MCU.
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
 
-/** \brief  System Tick Configuration
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0plus.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0plus.h
index 123cb400..424011ac 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0plus.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm0plus.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_cm0plus.h
  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM0PLUS_H_GENERIC
 #define __CORE_CM0PLUS_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,74 +55,49 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex-M0+
+/**
+  \ingroup Cortex-M0+
   @{
  */
 
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0
+#define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -138,15 +105,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -166,27 +133,27 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
+    #define __CM0PLUS_REV             0x0000U
     #warning "__CM0PLUS_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
+    #define __VTOR_PRESENT            0U
     #warning "__VTOR_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
+    #define __NVIC_PRIO_BITS          2U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -200,12 +167,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group Cortex-M0+ */
 
@@ -220,428 +192,471 @@
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
 #else
-       uint32_t RESERVED0;
+        uint32_t RESERVED0;
 #endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
-#if (__VTOR_PRESENT == 1)
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 #endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
   @{
  */
 
-/* Memory mapping of Cortex-M0+ Hardware */
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 /*@} */
@@ -655,179 +670,393 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
 
-    \param [in]      IRQn  Interrupt number.
 
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
 
-    The function sets the pending bit of an external interrupt.
 
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
 
-    The function clears the pending bit of an external interrupt.
 
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-    The function sets the priority of an interrupt.
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
 
-    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
 
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 
-/** \brief  Get Interrupt Priority
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
 
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
 
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
-  }
 }
 
 
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
+/* ##########################  MPU functions  #################################### */
 
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
 
-/** \brief  System Tick Configuration
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm3.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm3.h
index 092ee23d..74bff64b 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm3.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm3.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_cm3.h
  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,74 +55,49 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex_M3
+/**
+  \ingroup Cortex_M3
   @{
  */
 
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
+#include "cmsis_version.h"
 
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#endif
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0
+#define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -138,15 +105,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -166,22 +133,22 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
+    #define __CM3_REV               0x0200U
     #warning "__CM3_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -195,12 +162,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group Cortex_M3 */
 
@@ -216,1101 +188,1219 @@
   - Core Debug Register
   - Core MPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 }  NVIC_Type;
 
 /* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 #else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 #endif
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
 
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 
 /* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 #else
-       uint32_t RESERVED1[1];
+        uint32_t RESERVED1[1U];
 #endif
 } SCnSCB_Type;
 
 /* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
 
 /* Auxiliary Control Register Definitions */
 
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
 
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
 
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
 {
-  __O  union
+  __OM  union
   {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
 /* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
 
 /* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
 
 /* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
 
 /* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 } DWT_Type;
 
 /* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
 
 /* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
 
 /* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
 
 /* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 
 /* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
 
 /* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
 
 /* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
 
 /* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
 
 /*@}*/ /* end of group CMSIS_DWT */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
   @{
  */
 
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
 {
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 
 /* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
 
 /* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
 
 /* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
 
 /* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 
 /* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
   @{
  */
 
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
 {
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
 
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 /*@} */
@@ -1325,187 +1415,273 @@ typedef struct
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/** \brief  Set Priority Grouping
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
 
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field.
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
 
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
   }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  else
+  {
+    return(0U);
   }
 }
 
 
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
 
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
   }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
 
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1523,19 +1699,18 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
 }
 
 
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
@@ -1549,11 +1724,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
 
-    The function initiates a system reset request to reset the MCU.
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1561,40 +1767,76 @@ __STATIC_INLINE void NVIC_SystemReset(void)
                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
+/* ##########################  MPU functions  #################################### */
 
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
 
-/** \brief  System Tick Configuration
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
@@ -1612,49 +1854,52 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-    \param [in]     ch  Character to transmit.
 
-    \returns            Character to transmit.
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
   }
   return (ch);
 }
 
 
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1663,19 +1908,22 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
 }
 
 
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
   }
 }
 
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm4.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm4.h
index 9749c27d..7d568735 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm4.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm4.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_cm4.h
  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM4_H_GENERIC
 #define __CORE_CM4_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,131 +55,112 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex_M4
+/**
+  \ingroup Cortex_M4
   @{
  */
 
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
+#include "cmsis_version.h"
 
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#endif
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
 */
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
-#elif defined ( __TMS470__ )
+#elif defined ( __TI_ARM__ )
   #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
-#include                  /* Compiler specific SIMD Intrinsics               */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -207,27 +180,27 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
+    #define __CM4_REV               0x0000U
     #warning "__CM4_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
+    #define __FPU_PRESENT             0U
     #warning "__FPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -241,12 +214,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group Cortex_M4 */
 
@@ -263,1220 +241,1341 @@
   - Core MPU Register
   - Core FPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
 
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
 #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
 
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 }  NVIC_Type;
 
 /* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
 
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 
 /* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 } SCnSCB_Type;
 
 /* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
 
 /* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
 
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
 
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
 
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
 
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
 {
-  __O  union
+  __OM  union
   {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
 /* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
 
 /* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
 
 /* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
 
 /* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 } DWT_Type;
 
 /* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
 
 /* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
 
 /* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
 
 /* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 
 /* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
 
 /* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
 
 /* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
 
 /* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
 
 /*@}*/ /* end of group CMSIS_DWT */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
   @{
  */
 
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
 {
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 
 /* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
 
 /* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
 
 /* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
 
 /* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 
 /* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
-#endif
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
 
 
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
   @{
  */
 
-/** \brief  Structure type to access the Floating Point Unit (FPU).
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
 } FPU_Type;
 
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
 
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
 
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
 
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
 
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
 
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
 
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
 
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
 
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
 
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
 
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
 
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
 
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
 
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
 
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
 
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
 
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
 
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
 
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
 
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
 
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
 
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
 
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
 
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
 
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
 
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
 
 /*@} end of group CMSIS_FPU */
-#endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
   @{
  */
 
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
 {
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
 
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
   @{
  */
 
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
 
 /*@} */
 
@@ -1490,187 +1589,276 @@ typedef struct
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/** \brief  Set Priority Grouping
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
 
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
 
-    \param [in]      PriorityGroup  Priority grouping field.
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
 
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
   }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  else
+  {
+    return(0U);
   }
 }
 
 
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
 
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
   }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
 
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1688,19 +1876,18 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
 }
 
 
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
@@ -1714,11 +1901,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
 
-    The function initiates a system reset request to reset the MCU.
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1726,40 +1944,87 @@ __STATIC_INLINE void NVIC_SystemReset(void)
                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
+/* ##########################  MPU functions  #################################### */
 
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
 
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
 
-/** \brief  System Tick Configuration
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
@@ -1777,49 +2042,52 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
 
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
   }
   return (ch);
 }
 
 
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1828,19 +2096,22 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
 }
 
 
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
   }
 }
 
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm7.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm7.h
index 842e323f..a14dc623 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm7.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cm7.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_cm7.h
  * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_CM7_H_GENERIC
 #define __CORE_CM7_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,131 +55,112 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup Cortex_M7
+/**
+  \ingroup Cortex_M7
   @{
  */
 
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
+#include "cmsis_version.h"
 
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
 
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
 */
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
-#elif defined ( __TMS470__ )
+#elif defined ( __TI_ARM__ )
   #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
 #elif defined ( __TASKING__ )
   #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
     #else
       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
+      #define __FPU_USED       0U
     #endif
   #else
-    #define __FPU_USED         0
+    #define __FPU_USED         0U
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
-#include                  /* Compiler specific SIMD Intrinsics               */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -207,42 +180,42 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM7_REV
-    #define __CM7_REV               0x0000
+    #define __CM7_REV               0x0000U
     #warning "__CM7_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
+    #define __FPU_PRESENT             0U
     #warning "__FPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0
+    #define __ICACHE_PRESENT          0U
     #warning "__ICACHE_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0
+    #define __DCACHE_PRESENT          0U
     #warning "__DCACHE_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0
+    #define __DTCM_PRESENT            0U
     #warning "__DTCM_PRESENT        not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -256,12 +229,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group Cortex_M7 */
 
@@ -278,1392 +256,1534 @@
   - Core MPU Register
   - Core FPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
 
-#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
 #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
 
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 }  NVIC_Type;
 
 /* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[1];
-  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
-  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
-  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
-  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-       uint32_t RESERVED3[93];
-  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
-       uint32_t RESERVED4[15];
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
-       uint32_t RESERVED5[1];
-  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
-       uint32_t RESERVED6[1];
-  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
-  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
-  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
-  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
-  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
-  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
-  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
-  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
-       uint32_t RESERVED7[6];
-  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
-  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
-  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
-  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
-  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
-       uint32_t RESERVED8[1];
-  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
 #define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
 
-#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
 #define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
 
-#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
 #define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
 
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
 
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 
 /* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
 
-/* Cache Level ID register */
-#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
 #define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
 
-#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
 
-/* Cache Type register */
-#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
 #define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
 
-#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
 #define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
 
-#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
 #define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
 
-#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
 #define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
 
-#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
 #define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
 
-/* Cache Size ID Register */
-#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
 
-#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
 
-#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
 
-#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
 
-#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
 #define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
 
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
 #define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
 
-#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
 #define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
 
-/* Cache Size Selection Register */
-#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
 #define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
 
-#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
 #define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
 
-/* SCB Software Triggered Interrupt Register */
-#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
 #define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
 
-/* Instruction Tightly-Coupled Memory Control Register*/
-#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
 #define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
 
-#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
 #define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
 
-#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
 #define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
 
-#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
 #define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
 
-/* Data Tightly-Coupled Memory Control Registers */
-#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
 #define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
 
-#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
 #define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
 
-#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
 #define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
 
-#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
 #define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
 
-/* AHBP Control Register */
-#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
 #define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
 
-#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
 #define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
 
-/* L1 Cache Control Register */
-#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
 #define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
 
-#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
 #define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
 
-#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
 #define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
 
-/* AHBS control register */
-#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
 #define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
 
-#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
 #define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
 
-#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
 #define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
 
-/* Auxiliary Bus Fault Status Register */
-#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
 #define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
 
-#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
 #define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
 
-#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
 #define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
 
-#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
 #define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
 
-#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
 #define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
 
-#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
 #define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 } SCnSCB_Type;
 
 /* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
 
 /* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
 
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
 #define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
 
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
 #define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
 
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
 
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
 {
-  __O  union
+  __OM  union
   {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
 /* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
 
 /* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
 
 /* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
 
 /* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-       uint32_t RESERVED3[981];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
 } DWT_Type;
 
 /* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
 
 /* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
 
 /* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
 
 /* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 
 /* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
 
 /* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
 
 /* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
 
 /* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
 
 /*@}*/ /* end of group CMSIS_DWT */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
   @{
  */
 
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
 {
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 
 /* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
 
 /* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
 
 /* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
 
 /* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 
 /* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
-#endif
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
 
 
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
   @{
  */
 
-/** \brief  Structure type to access the Floating Point Unit (FPU).
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
 } FPU_Type;
 
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
 
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
 
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
 
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
 
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
 
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
 
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
 
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
 
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
 
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
 
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
 
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
 
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
 
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
 
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
 
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
 
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
 
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
 
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
 
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
 
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
 
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
 
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
 
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
 
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
 
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
 
-/* Media and FP Feature Register 2 */
+/* Media and FP Feature Register 2 Definitions */
 
 /*@} end of group CMSIS_FPU */
-#endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
   @{
  */
 
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
 {
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
 
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
 
 /*@} */
 
@@ -1677,187 +1797,276 @@ typedef struct
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/** \brief  Set Priority Grouping
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
 
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field.
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
   SCB->AIRCR =  reg_value;
 }
 
 
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
-  if((int32_t)IRQn < 0) {
-    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
   }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  else
+  {
+    return(0U);
   }
 }
 
 
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
 
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
   }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
 
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1875,19 +2084,18 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
 }
 
 
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
@@ -1901,11 +2109,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
 
-    The function initiates a system reset request to reset the MCU.
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1913,22 +2152,34 @@ __STATIC_INLINE void NVIC_SystemReset(void)
                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
 
 /* ##########################  FPU functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_FpuFunctions FPU Functions
-    \brief      Function that provides FPU type.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
  */
 
 /**
-  \fn          uint32_t SCB_GetFPUType(void)
-  \brief       get FPU type
+  \brief   get FPU type
+  \details returns the FPU type
   \returns
    - \b  0: No FPU
    - \b  1: Single precision FPU
@@ -1939,12 +2190,17 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
   uint32_t mvfr0;
 
   mvfr0 = SCB->MVFR0;
-  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
-    return 2UL;           // Double + Single precision FPU
-  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
-    return 1UL;           // Single precision FPU
-  } else {
-    return 0UL;           // No FPU
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
   }
 }
 
@@ -1954,59 +2210,61 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
 
 
 /* ##########################  Cache functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_CacheFunctions Cache Functions
-    \brief      Functions that configure Instruction and Data cache.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
  */
 
 /* Cache Size ID Register Macros */
 #define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
 #define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
-
 
-/** \brief Enable I-Cache
 
-    The function turns on I-Cache
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
   */
 __STATIC_INLINE void SCB_EnableICache (void)
 {
-  #if (__ICACHE_PRESENT == 1)
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
     __DSB();
     __ISB();
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
     __DSB();
     __ISB();
   #endif
 }
 
 
-/** \brief Disable I-Cache
-
-    The function turns off I-Cache
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
   */
 __STATIC_INLINE void SCB_DisableICache (void)
 {
-  #if (__ICACHE_PRESENT == 1)
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
     __DSB();
     __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache
-    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
     __DSB();
     __ISB();
   #endif
 }
 
 
-/** \brief Invalidate I-Cache
-
-    The function invalidates I-Cache
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
   */
 __STATIC_INLINE void SCB_InvalidateICache (void)
 {
-  #if (__ICACHE_PRESENT == 1)
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
     __DSB();
     __ISB();
     SCB->ICIALLU = 0UL;
@@ -2016,35 +2274,37 @@ __STATIC_INLINE void SCB_InvalidateICache (void)
 }
 
 
-/** \brief Enable D-Cache
-
-    The function turns on D-Cache
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
   */
 __STATIC_INLINE void SCB_EnableDCache (void)
 {
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
 
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
     __DSB();
 
-    do {                                   // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
     __DSB();
 
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
 
     __DSB();
     __ISB();
@@ -2052,35 +2312,37 @@ __STATIC_INLINE void SCB_EnableDCache (void)
 }
 
 
-/** \brief Disable D-Cache
-
-    The function turns off D-Cache
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
   */
 __STATIC_INLINE void SCB_DisableDCache (void)
 {
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
 
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
     __DSB();
 
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache
-
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
 
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
 
     __DSB();
     __ISB();
@@ -2088,32 +2350,34 @@ __STATIC_INLINE void SCB_DisableDCache (void)
 }
 
 
-/** \brief Invalidate D-Cache
-
-    The function invalidates D-Cache
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
   */
 __STATIC_INLINE void SCB_InvalidateDCache (void)
 {
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
 
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
     __DSB();
 
-    do {                                    // invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
 
     __DSB();
     __ISB();
@@ -2121,32 +2385,34 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
 }
 
 
-/** \brief Clean D-Cache
-
-    The function cleans D-Cache
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
   */
 __STATIC_INLINE void SCB_CleanDCache (void)
 {
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
-
-    __DSB();
-
-    do {                                    // clean D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCSW = sw;
-            } while(tmpways--);
-        } while(sets--);
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
 
     __DSB();
     __ISB();
@@ -2154,32 +2420,34 @@ __STATIC_INLINE void SCB_CleanDCache (void)
 }
 
 
-/** \brief Clean & Invalidate D-Cache
-
-    The function cleans and Invalidates D-Cache
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
   */
 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
 {
-  #if (__DCACHE_PRESENT == 1)
-    uint32_t ccsidr, sshift, wshift, sw;
-    uint32_t sets, ways;
-
-    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
-    ccsidr  = SCB->CCSIDR;
-    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
-    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
-    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
-    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
 
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
     __DSB();
 
-    do {                                    // clean & invalidate D-Cache
-         uint32_t tmpways = ways;
-         do {
-              sw = ((tmpways << wshift) | (sets << sshift));
-              SCB->DCCISW = sw;
-            } while(tmpways--);
-        } while(sets--);
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
 
     __DSB();
     __ISB();
@@ -2188,24 +2456,24 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
 
 
 /**
-  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Invalidate by address
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 {
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
     uint32_t op_addr = (uint32_t)addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
     __DSB();
 
     while (op_size > 0) {
       SCB->DCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
     }
 
     __DSB();
@@ -2215,24 +2483,24 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize
 
 
 /**
-  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean by address
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
 {
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
     uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
     __DSB();
 
     while (op_size > 0) {
       SCB->DCCMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
     }
 
     __DSB();
@@ -2242,24 +2510,24 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
 
 
 /**
-  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
-  \brief       D-Cache Clean and Invalidate by address
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 {
-  #if (__DCACHE_PRESENT == 1)
-    int32_t  op_size = dsize;
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
     uint32_t op_addr = (uint32_t) addr;
-    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
     __DSB();
 
     while (op_size > 0) {
       SCB->DCCIMVAC = op_addr;
-      op_addr +=          linesize;
-      op_size -= (int32_t)linesize;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
     }
 
     __DSB();
@@ -2273,32 +2541,32 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t
 
 
 /* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
@@ -2316,49 +2584,52 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-/** \brief  ITM Send Character
 
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
   }
   return (ch);
 }
 
 
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -2367,19 +2638,22 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
 }
 
 
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
   }
 }
 
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmFunc.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmFunc.h
deleted file mode 100644
index b6ad0a4c..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmFunc.h
+++ /dev/null
@@ -1,664 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-    or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Set Base Priority with condition
-
-    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-	or the new value increases the BASEPRI priority level.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include 
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include 
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include 
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmInstr.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmInstr.h
deleted file mode 100644
index fca425c5..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmInstr.h
+++ /dev/null
@@ -1,916 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0)
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-  return(result);
-}
-#endif
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
-
-  result = value;                      // r will be reversed bits of v; first get LSB of v
-  for (value >>= 1; value; value >>= 1)
-  {
-    result <<= 1;
-    result |= value & 1;
-    s--;
-  }
-  result <<= s;                       // shift when v's highest bits are zero
-#endif
-  return(result);
-}
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit.
-    The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include 
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include 
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include 
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmSimd.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmSimd.h
deleted file mode 100644
index 7b8e37ff..00000000
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_cmSimd.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmSimd.h
- * @brief    CMSIS Cortex-M SIMD Header File
- * @version  V4.10
- * @date     18. March 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include 
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include 
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include 
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc000.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc000.h
index 44cb0274..9b67c92f 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc000.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc000.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_sc000.h
  * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_SC000_H_GENERIC
 #define __CORE_SC000_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,74 +55,49 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup SC000
+/**
+  \ingroup SC000
   @{
  */
 
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
+#include "cmsis_version.h"
 
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#endif
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0
+#define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -138,15 +105,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -166,22 +133,22 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __SC000_REV
-    #define __SC000_REV             0x0000
+    #define __SC000_REV             0x0000U
     #warning "__SC000_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
+    #define __NVIC_PRIO_BITS          2U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -195,12 +162,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group SC000 */
 
@@ -215,443 +187,486 @@
   - Core SysTick Register
   - Core MPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED0[1];
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-       uint32_t RESERVED1[154];
-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 } SCnSCB_Type;
 
 /* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
   @{
  */
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
   @{
  */
 
-/* Memory mapping of SC000 Hardware */
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 /*@} */
@@ -665,179 +680,322 @@ typedef struct
   - Core SysTick Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
 
-    \note The priority cannot be set for every core interrupt.
 
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if((int32_t)(IRQn) < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else {
+  if ((int32_t)(IRQn) >= 0)
+  {
     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
   }
 }
 
 
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if((int32_t)(IRQn) < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
   }
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
 
-    The function initiates a system reset request to reset the MCU.
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                  SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                        /* wait until reset */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
 
-/** \brief  System Tick Configuration
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc300.h b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc300.h
index 7e40672a..3e8a4710 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc300.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/Include/core_sc300.h
@@ -1,52 +1,44 @@
 /**************************************************************************//**
  * @file     core_sc300.h
  * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V4.10
- * @date     18. March 2015
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
- * @note
+ * SPDX-License-Identifier: Apache-2.0
  *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
 #endif
 
 #ifndef __CORE_SC300_H_GENERIC
 #define __CORE_SC300_H_GENERIC
 
+#include 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
   CMSIS violates the following MISRA-C:2004 rules:
 
    \li Required Rule 8.5, object/function definition in header file.

@@ -63,74 +55,49 @@
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
-/** \ingroup SC3000
+/**
+  \ingroup SC3000
   @{
  */
 
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
+#include "cmsis_version.h"
 
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 
-#endif
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
 
 /** __FPU_USED indicates whether an FPU is used or not.
     This core does not support an FPU at all
 */
-#define __FPU_USED       0
+#define __FPU_USED       0U
 
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
 #elif defined ( __TASKING__ )
@@ -138,15 +105,15 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
+
 #endif
 
-#include                       /* standard types definitions                      */
-#include                 /* Core Instruction Access                         */
-#include                  /* Core Function Access                            */
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
 
 #ifdef __cplusplus
 }
@@ -166,22 +133,22 @@
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __SC300_REV
-    #define __SC300_REV               0x0000
+    #define __SC300_REV               0x0000U
     #warning "__SC300_REV not defined in device header file; using default!"
   #endif
 
   #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
+    #define __MPU_PRESENT             0U
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif
 
   #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
+    #define __NVIC_PRIO_BITS          3U
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif
 
   #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
+    #define __Vendor_SysTickConfig    0U
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif
@@ -195,12 +162,17 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group SC300 */
 
@@ -216,1083 +188,1199 @@
   - Core Debug Register
   - Core MPU Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 
 /* APSR Register Definitions */
-#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 
-#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 
-#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 
-#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 
-#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
 
 
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 
 /* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
 typedef union
 {
   struct
   {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 
 /* xPSR Register Definitions */
-#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 
-#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 
-#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 
-#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 
-#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
 
-#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
 
-#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 
-#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 
 
-/** \brief  Union type to access the Control Registers (CONTROL).
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
  */
 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 
 /* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 
-#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
 
 /*@} end of group CMSIS_CORE */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
 typedef struct
 {
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
 }  NVIC_Type;
 
 /* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_NVIC */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+/**
+  \brief  Structure type to access the System Control Block (SCB).
  */
 typedef struct
 {
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-       uint32_t RESERVED1[129];
-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
 } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
 
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
 
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
 
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
 
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
 
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
 
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
 
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
 
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
 
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
 
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
 
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
 
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
 
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
 
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
 
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
 
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
 
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
 
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
 
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
 
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
 
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
 
 /* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
 
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
 
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
 
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
 
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
 
 /*@} end of group CMSIS_SCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
   @{
  */
 
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
  */
 typedef struct
 {
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-       uint32_t RESERVED1[1];
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
 } SCnSCB_Type;
 
 /* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
 
 /*@} end of group CMSIS_SCnotSCB */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+/**
+  \brief  Structure type to access the System Timer (SysTick).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
   @{
  */
 
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
  */
 typedef struct
 {
-  __O  union
+  __OM  union
   {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
 } ITM_Type;
 
 /* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
 #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
 
 /* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
 
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
 
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
 
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
 
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
 
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
 
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
 
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
 
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
 
 /* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
 
 /* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
 
 /* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
 
 /* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
 
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
 
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
 
 /*@}*/ /* end of group CMSIS_ITM */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
   @{
  */
 
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
  */
 typedef struct
 {
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
 } DWT_Type;
 
 /* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
 
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
 
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
 
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
 
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
 
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
 
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
 
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
 
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
 
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
 
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
 
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
 
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
 
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
 
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
 
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
 
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
 
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
 
 /* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
 
 /* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
 
 /* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
 
 /* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
 
 /* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
 
 /* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
 
 /* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
 
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
 
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
 
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
 
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
 
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
 
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
 
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
 
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
 
 /*@}*/ /* end of group CMSIS_DWT */
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
   @{
  */
 
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
  */
 typedef struct
 {
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
 } TPI_Type;
 
 /* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
 
 /* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
 
 /* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
 
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
 
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
 
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
 
 /* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
 
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
 
 /* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
 
 /* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
 
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
 
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
 
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
 
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
 
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
 
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
 
 /* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
 
 /* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
 
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
 
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
 
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
 
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
 
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
 
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
 
 /* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
 
 /* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
 
 /* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
 
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
 
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
 
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
 
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
 
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
 
 /* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
 
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
 /*@}*/ /* end of group CMSIS_TPI */
 
 
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
   @{
  */
 
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
  */
 typedef struct
 {
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
 } MPU_Type;
 
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
 
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
 
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
 
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
 
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
 
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
 
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
 
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
 
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
 
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
 
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
 
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
 
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
 
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
 
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
 
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
 
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
 
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
 
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
 
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
 
 /*@} end of group CMSIS_MPU */
 #endif
 
 
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
   @{
  */
 
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
  */
 typedef struct
 {
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
 } CoreDebug_Type;
 
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
 
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
 
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
 
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
 
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
 
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
 
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
 
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
 
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
 
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
 
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
 
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
 
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
 
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
 
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
 
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
 
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
 
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
 
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
 
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
 
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
 
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
 
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
 
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
 
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
 
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
 
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
 
 /*@} end of group CMSIS_CoreDebug */
 
 
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
   @{
  */
 
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
 #endif
 
 /*@} */
@@ -1307,187 +1395,274 @@ typedef struct
   - Core Debug Functions
   - Core Register Access Functions
  ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
 
 
 /* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
  */
 
-/** \brief  Set Priority Grouping
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
 
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 
-    \param [in]      PriorityGroup  Priority grouping field.
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
  */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 
   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
   reg_value  =  (reg_value                                   |
                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }
 
 
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
 {
   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 }
 
 
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
 }
 
 
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
 }
 
 
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
-  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
-  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
 }
 
 
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
 {
-  if((int32_t)IRQn < 0) {
-    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
   }
-  else {
-    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  else
+  {
+    return(0U);
   }
 }
 
 
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
 
 
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if((int32_t)IRQn < 0) {
-    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
   }
-  else {
-    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
   }
 }
 
 
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
@@ -1505,19 +1680,18 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
 }
 
 
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
  */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
@@ -1531,11 +1705,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
 }
 
 
-/** \brief  System Reset
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
 
-    The function initiates a system reset request to reset the MCU.
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */
@@ -1543,40 +1748,69 @@ __STATIC_INLINE void NVIC_SystemReset(void)
                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
   __DSB();                                                          /* Ensure completion of memory access */
-  while(1) { __NOP(); }                                             /* wait until reset */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
 }
 
 /*@} end of CMSIS_Core_NVICFunctions */
 
 
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
   @{
  */
 
-#if (__Vendor_SysTickConfig == 0)
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
 
-/** \brief  System Tick Configuration
+/*@} end of CMSIS_Core_FpuFunctions */
 
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
 
-    \param [in]  ticks  Number of ticks between two interrupts.
 
-    \return          0  Function succeeded.
-    \return          1  Function failed.
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
 
-    \note     When the variable __Vendor_SysTickConfig is set to 1, then the
-    function SysTick_Config is not included. In this case, the file device.h
-    must contain a vendor-specific implementation of this function.
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
  */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
 
   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
@@ -1594,49 +1828,52 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 
 
 /* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
   @{
  */
 
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
 
-    \param [in]     ch  Character to transmit.
 
-    \returns            Character to transmit.
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
  */
 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
   {
-    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
-    ITM->PORT[0].u8 = (uint8_t)ch;
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
   }
   return (ch);
 }
 
 
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1645,19 +1882,22 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
 }
 
 
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
   }
 }
 
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3b_math.lib b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3b_math.lib
index 3db65b8e..1a8f571b 100644
Binary files a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3b_math.lib and b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3b_math.lib differ
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3l_math.lib b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3l_math.lib
index 3ae530e8..52677b78 100644
Binary files a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3l_math.lib and b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/ARM/arm_cortexM3l_math.lib differ
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/GCC/libarm_cortexM3l_math.a b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/GCC/libarm_cortexM3l_math.a
index cf1f80cb..12c644a4 100644
Binary files a/STM32CubeMX/2020c/Drivers/CMSIS/Lib/GCC/libarm_cortexM3l_math.a and b/STM32CubeMX/2020c/Drivers/CMSIS/Lib/GCC/libarm_cortexM3l_math.a differ
diff --git a/STM32CubeMX/2020c/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/STM32CubeMX/2020c/Drivers/CMSIS/RTOS/Template/cmsis_os.h
index 02930af3..30068d35 100644
--- a/STM32CubeMX/2020c/Drivers/CMSIS/RTOS/Template/cmsis_os.h
+++ b/STM32CubeMX/2020c/Drivers/CMSIS/RTOS/Template/cmsis_os.h
@@ -24,30 +24,21 @@
  *    Removed: osSignalGet 
  *----------------------------------------------------------------------------
  *
- * Copyright (c) 2013 ARM LIMITED
- * All rights reserved.
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *  - Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *  - Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *  - Neither the name of ARM  nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without
- *    specific prior written permission.
+ * Copyright (c) 2013-2017 ARM LIMITED
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *---------------------------------------------------------------------------*/
  
  
@@ -336,14 +327,14 @@ osPriority osThreadGetPriority (osThreadId thread_id);
 //  ==== Generic Wait Functions ====
  
 /// Wait for Timeout (Time Delay).
-/// \param[in]     millisec      time delay value
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
 /// \return status code that indicates the execution status of the function.
 osStatus osDelay (uint32_t millisec);
  
 #if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
  
 /// Wait for Signal, Message, Mail, or Timeout.
-/// \param[in] millisec          timeout value or 0 in case of no time-out
+/// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return event that contains signal, message, or mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
 osEvent osWait (uint32_t millisec);
@@ -383,7 +374,7 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void
  
 /// Start or restart a timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
-/// \param[in]     millisec      time delay value of the timer.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
@@ -419,7 +410,7 @@ int32_t osSignalClear (osThreadId thread_id, int32_t signals);
  
 /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
 /// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return event flag information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
 osEvent osSignalWait (int32_t signals, uint32_t millisec);
@@ -454,7 +445,7 @@ osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
  
 /// Wait until a Mutex becomes available.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
 osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
@@ -504,7 +495,7 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t
  
 /// Wait until a Semaphore token becomes available.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return number of available tokens, or -1 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
 int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
@@ -614,14 +605,14 @@ osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId threa
 /// Put a Message to a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     info          message information.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
 osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
  
 /// Get a Message or Wait for a Message from a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return event information that includes status code.
 /// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
 osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
@@ -664,14 +655,14 @@ osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
  
 /// Allocate a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
  
 /// Allocate a memory block from a mail and set memory block to zero.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
@@ -685,7 +676,7 @@ osStatus osMailPut (osMailQId queue_id, void *mail);
  
 /// Get a mail from a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
-/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return event that contains mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
 osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 80b0551c..52c9d6c5 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -2,43 +2,25 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants 
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
 
 #ifdef __cplusplus
  extern "C" {
@@ -60,7 +42,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -92,10 +74,10 @@
 #define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
 #define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
 #define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
 #define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
 #define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
 #define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
@@ -103,6 +85,7 @@
 #define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
 #define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
 
 #define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
 #define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
@@ -110,25 +93,28 @@
 #define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
 #define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
 #define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
   * @{
-  */ 
-  
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
 
 /**
   * @}
-  */   
-   
+  */
+
 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
   * @{
   */
-  
 #define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
 #define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
 #define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
@@ -138,11 +124,89 @@
 #define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
 #if defined(STM32F373xC) || defined(STM32F378xx)
 #define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
 #define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
 #endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
 /**
   * @}
   */
@@ -150,7 +214,7 @@
 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 #define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
 #define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
 
@@ -165,13 +229,23 @@
 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
 #define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
 
+#if defined(STM32G4)
+#define DAC_CHIPCONNECT_DISABLE       (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
+#define DAC_CHIPCONNECT_ENABLE        (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
 /**
   * @}
   */
@@ -179,28 +253,120 @@
 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
   * @{
   */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
 #define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
 #define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    
-  
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
 #define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
 #define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-  
-  
-  
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#endif /* STM32L4 */
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#endif /* STM32H7 */
+
 /**
   * @}
   */
@@ -208,7 +374,7 @@
 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 #define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
 #define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
 #define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
@@ -280,14 +446,47 @@
 #define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
 #define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
 #define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
+#endif
+
 /**
   * @}
   */
-  
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
@@ -297,20 +496,27 @@
 #define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
 #define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
 #define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
 /**
   * @}
   */
-  
+
 
 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
   * @{
   */
-#if defined(STM32L4) || defined(STM32F7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#else
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
 #define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
 #define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
 #define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
@@ -323,7 +529,7 @@
 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 #define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
 #define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
 /**
@@ -351,30 +557,40 @@
 #define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
 #endif
 
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+#endif
+
 #define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1) 
- #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     
- #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     
- #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     
- #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
 #endif /* STM32L1 */
 
-#if defined(STM32F3) 
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
  #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
  #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
  #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F3 */
+#endif /* STM32F0 || STM32F3 || STM32F1 */
 
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
 /**
   * @}
   */
@@ -391,7 +607,7 @@
 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-   
+
 #define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
 #define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
 #define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
@@ -400,6 +616,125 @@
 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
 #define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
 #define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
 /**
   * @}
   */
@@ -415,6 +750,14 @@
 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
 /**
   * @}
   */
@@ -456,7 +799,7 @@
 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
 
 /* The following 3 definition have also been present in a temporary version of lptim.h */
 /* They need to be renamed also to the right name, just in case */
@@ -471,6 +814,11 @@
 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
   * @{
   */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
 #define NAND_AddressTypedef             NAND_AddressTypeDef
 
 #define __ARRAY_ADDRESS                 ARRAY_ADDRESS
@@ -481,7 +829,7 @@
 /**
   * @}
   */
-   
+
 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -505,11 +853,11 @@
 #define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
 #define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
 #define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-                                              
+
 #define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
 #define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
 #define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
 
 #define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
 #define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
@@ -518,14 +866,20 @@
 #define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
 
 #define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
 
 #define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-                                                                      
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          
-                                                        
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
 /**
   * @}
   */
@@ -534,6 +888,18 @@
   * @{
   */
 #define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+  #define I2S_IT_TXE               I2S_IT_TXP
+  #define I2S_IT_RXNE              I2S_IT_RXP
+
+  #define I2S_FLAG_TXE             I2S_FLAG_TXP
+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
 /**
   * @}
   */
@@ -543,18 +909,18 @@
   */
 
 /* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA                
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       
-#define CF_CARD_HEAD                  ATA_CARD_HEAD           
-#define CF_STATUS_CMD                 ATA_STATUS_CMD          
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
 #define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
 
 /* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
 #define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
 #define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
 #define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
@@ -567,31 +933,27 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 #define FORMAT_BIN                  RTC_FORMAT_BIN
 #define FORMAT_BCD                  RTC_FORMAT_BCD
 
 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
 
 #define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
 #define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
 
@@ -599,15 +961,15 @@
 #define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
 #define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
 
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
 
 /**
   * @}
   */
 
-  
+
 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -628,8 +990,8 @@
   * @}
   */
 
-  
-  /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
   * @{
   */
 #define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
@@ -646,8 +1008,8 @@
 /**
   * @}
   */
-  
-  /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
   * @{
   */
 #define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
@@ -659,16 +1021,31 @@
 #define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
 #define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
 
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+ #define SPI_IT_TXE                      SPI_IT_TXP
+ #define SPI_IT_RXNE                     SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
   * @{
   */
 #define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
 #define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-  
+
 #define TIM_DMABase_CR1                  TIM_DMABASE_CR1
 #define TIM_DMABase_CR2                  TIM_DMABASE_CR2
 #define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
@@ -726,6 +1103,33 @@
 #define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
 #define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
 
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
 /**
   * @}
   */
@@ -760,6 +1164,8 @@
 #define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
 #define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
 
+#define __DIV_LPUART                    UART_DIV_LPUART
+
 #define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
 #define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
 
@@ -767,7 +1173,7 @@
   * @}
   */
 
-  
+
 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -800,14 +1206,14 @@
 #define CAN_IT_RQCP2                CAN_IT_TME
 #define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
 #define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
 
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -821,26 +1227,101 @@
 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 
-#define ETH_MMCCR              ((uint32_t)0x00000100)  
-#define ETH_MMCRIR             ((uint32_t)0x00000104)  
-#define ETH_MMCTIR             ((uint32_t)0x00000108)  
-#define ETH_MMCRIMR            ((uint32_t)0x0000010C)  
-#define ETH_MMCTIMR            ((uint32_t)0x00000110)  
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014C)  
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150)  
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168)  
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194)  
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198)  
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4) 
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
 
 /**
   * @}
   */
 
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
   * @{
   */
-  
+
 /**
   * @}
   */
@@ -853,11 +1334,11 @@
 #define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
 /**
   * @}
-  */  
+  */
 
 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
   * @{
-  */ 
+  */
 #define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
 #define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
 #define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
@@ -867,12 +1348,12 @@
 
 /*HASH Algorithm Selection*/
 
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1 
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
 #define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
 #define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
 #define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
 
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH 
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
 #define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
 
 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
@@ -880,7 +1361,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
   * @{
   */
@@ -893,7 +1374,10 @@
 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
 /**
@@ -918,10 +1402,34 @@
 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
   * @{
   */
-#define HAL_I2CEx_AnalogFilter_Config      HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config     HAL_I2CEx_ConfigDigitalFilter
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
 
 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
  /**
   * @}
   */
@@ -956,6 +1464,8 @@
 
 #define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
 #define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
 
 #define DBP_BitNumber                                 DBP_BIT_NUMBER
 #define PVDE_BitNumber                                PVDE_BIT_NUMBER
@@ -969,17 +1479,17 @@
 #define BRE_BitNumber                                 BRE_BIT_NUMBER
 
 #define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
- 
+
  /**
   * @}
-  */  
-  
+  */
+
 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
   * @{
   */
 #define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback         
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback   
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
 /**
   * @}
   */
@@ -990,7 +1500,7 @@
 #define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
 /**
   * @}
-  */  
+  */
 
 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
   * @{
@@ -999,31 +1509,42 @@
 #define HAL_TIM_DMAError                                TIM_DMAError
 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */
 /**
   * @}
   */
-   
+
 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
   * @{
-  */ 
+  */
 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
   * @{
-  */ 
+  */
 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
 /**
   * @}
-  */  
-   
-  
-   /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
   * @{
   */
-  
+
 /**
   * @}
   */
@@ -1038,8 +1559,8 @@
 #define AES_FLAG_CCF                   CRYP_FLAG_CCF
 /**
   * @}
-  */  
-  
+  */
+
 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -1048,7 +1569,7 @@
 #define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
 #define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
 #define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
 #define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
 #define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
 #define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
@@ -1056,6 +1577,7 @@
 #define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
 #define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
 #define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
 
 #define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
 #define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
@@ -1067,7 +1589,7 @@
   * @}
   */
 
-   
+
 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -1137,7 +1659,6 @@
 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 #define __HAL_ADC_JSQR                                   ADC_JSQR
 
 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
@@ -1164,7 +1685,7 @@
 /**
   * @}
   */
-   
+
 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -1209,10 +1730,17 @@
 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#if defined(STM32H7)
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
@@ -1237,7 +1765,7 @@
 #define COMP_START                                       __HAL_COMP_ENABLE
 #define COMP_STOP                                        __HAL_COMP_DISABLE
 #define COMP_LOCK                                        __HAL_COMP_LOCK
-   
+
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -1395,10 +1923,28 @@
 
 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
 
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
 /**
   * @}
   */
 
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -1406,7 +1952,7 @@
 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
                           ((WAVE) == DAC_WAVE_NOISE)|| \
                           ((WAVE) == DAC_WAVE_TRIANGLE))
-  
+
 /**
   * @}
   */
@@ -1425,14 +1971,18 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+
 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
@@ -1448,14 +1998,18 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+
 #define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
 #define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
 
+#if defined(STM32H7)
+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
 /**
   * @}
   */
@@ -1463,7 +2017,7 @@
 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+
 #define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
 #define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
 
@@ -1472,7 +2026,7 @@
 #define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
 #define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
 
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE                  
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
 
 
 /**
@@ -1501,8 +2055,8 @@
 /**
   * @}
   */
-  
-  
+
+
 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -1567,7 +2121,7 @@
 #if defined (STM32F4)
 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()   
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
 #else
@@ -1575,37 +2129,37 @@
 #define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
 #define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
 #define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG 
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
 #endif /* STM32F4 */
-/**   
+/**
   * @}
-  */  
-  
-  
+  */
+
+
 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
   * @{
   */
-  
+
 #define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
 #define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
 
 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1622,7 +2176,7 @@
 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -1850,6 +2404,21 @@
 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2038,26 +2607,26 @@
 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
 #define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
 #define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
 #define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
@@ -2066,12 +2635,28 @@
 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
 #define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
 #define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
 #define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
@@ -2100,111 +2685,111 @@
 #define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
 #define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
 #define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE  
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
 #define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE  
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
 #define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE  
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
 #define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE  
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
 #define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
 #define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
 #define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE  
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
 #define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
 #define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
 #define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
 #define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
 #define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE  
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
 #define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
 #define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
 #define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
 #define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
 #define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE  
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
 #define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
 #define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
 #define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
 #define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
 #define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE  
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
 #define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
 #define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
 #define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
 #define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE  
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
 #define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE  
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
 #define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE  
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
 #define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE  
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
 #define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE  
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
 #define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE  
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
 #define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE  
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
 #define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
 #define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
 #define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE  
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
 #define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE  
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
 #define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
 #define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
 #define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
 #define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
 #define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE  
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
 #define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
 #define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
 #define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
 #define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
 #define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE  
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
 #define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
 #define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
 #define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
 #define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
 #define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE  
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
 #define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
 #define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
 #define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
 #define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
 #define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE  
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
 #define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
 #define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
 #define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
 #define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE  
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
 #define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE  
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
 #define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
 #define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
 #define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
 #define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
 #define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE  
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
 #define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
 #define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
 #define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
 #define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
 #define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE  
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
 #define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
 #define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
 #define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
 #define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
 #define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE  
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
 #define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
 #define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
 #define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
 #define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
 #define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
@@ -2212,29 +2797,28 @@
 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
 #define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET  
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
 #define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
 #define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE  
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
 #define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
 #define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE  
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
 #define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
 #define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
 #define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE  
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
 #define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
 #define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
 #define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE  
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
 #define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
 #define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
 #define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
@@ -2250,8 +2834,6 @@
 #define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
 #define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
 #define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
 #define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
@@ -2273,8 +2855,6 @@
 #define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
 #define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
 #define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
 #define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
@@ -2409,6 +2989,15 @@
 #define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
 #define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
 
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
 #if defined(STM32F4)
 #define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
 #define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
@@ -2438,14 +3027,38 @@
 #define SdioClockSelection                 Sdmmc1ClockSelection
 #define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
 #define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE	
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
 #endif
 
 #if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
 #define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
 #endif
 
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
 
@@ -2459,10 +3072,22 @@
 
 #define RCC_IT_HSI14                RCC_IT_HSI14RDY
 
-#if defined(STM32L0)
-#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
-#define RCC_IT_CSS                 RCC_IT_CSSHSE
-#endif
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
 
 #define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
 #define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
@@ -2487,7 +3112,12 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
+#else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
 
 #define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
 #define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
@@ -2556,6 +3186,46 @@
 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
 
 #define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
 /**
   * @}
   */
@@ -2563,17 +3233,19 @@
 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
   * @{
   */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)                                       
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
 
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
+#else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
 #define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
 #define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
 
@@ -2609,7 +3281,7 @@
 #define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
 #define IS_TAMPER                                 IS_RTC_TAMPER
 #define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER 
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
 #define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
 #define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
 #define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
@@ -2634,26 +3306,26 @@
 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
 
-#if defined(STM32F4)
+#if defined(STM32F4) || defined(STM32F2)
 #define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION  
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND   
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT     
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED   
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE      
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE     
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE  
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL  
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT   
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT  
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG    
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG  
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT      
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT    
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS	       
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT	       
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
 #define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
 /* alias CMSIS */
 #define  SDMMC1_IRQn                SDIO_IRQn
@@ -2662,8 +3334,8 @@
 
 #if defined(STM32F7) || defined(STM32L4)
 #define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY    
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED  
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
 #define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
 #define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
 #define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
@@ -2685,6 +3357,25 @@
 #define  SDIO_IRQn                  SDMMC1_IRQn
 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
 #endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
 /**
   * @}
   */
@@ -2703,7 +3394,7 @@
 #define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
 #define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
 
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE                  
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
 
 /**
   * @}
@@ -2735,7 +3426,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -2747,8 +3438,8 @@
 
 #define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
 
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE                  
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE                  
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
 
 /**
   * @}
@@ -2845,31 +3536,7 @@
 #define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
 
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                      ((SELECTION) == TIM_TS_ITR1) || \
-                                                      ((SELECTION) == TIM_TS_ITR2) || \
-                                                      ((SELECTION) == TIM_TS_ITR3))
-
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                       ((CHANNEL) == TIM_CHANNEL_2))
-
-#define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
-                                     ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-
-#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
-                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))  
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
 /**
   * @}
   */
@@ -2877,7 +3544,7 @@
 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+
 #define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
 #define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
 #define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
@@ -2886,7 +3553,7 @@
 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
 
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE 
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
 #define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
 #define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
 /**
@@ -2897,6 +3564,7 @@
   * @{
   */
 #define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
 /**
   * @}
   */
@@ -2909,23 +3577,60 @@
 #define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
 #define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
 #define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY              
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL    
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL       
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL           
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL       
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL               
-#define IS_SAI_BLOCK_MONO_STREO_MODE     IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
 
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
 /**
   * @}
   */
 
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif
+/**
+  * @}
+  */
 
 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+
 /**
   * @}
   */
@@ -2934,7 +3639,7 @@
 }
 #endif
 
-#endif /* ___STM32_HAL_LEGACY */
+#endif /* STM32_HAL_LEGACY */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
index a81f7637..1fa049d3 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
@@ -2,39 +2,21 @@
   ******************************************************************************
   * @file    stm32f2xx_hal.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_H
@@ -57,6 +39,29 @@
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup HAL_Exported_Macros HAL Exported Macros
   * @{
@@ -137,6 +142,16 @@
   * @}
   */
 
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup HAL_Exported_Functions
   * @{
@@ -150,6 +165,17 @@ HAL_StatusTypeDef HAL_DeInit(void);
 void HAL_MspInit(void);
 void HAL_MspDeInit(void);
 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+  * @}
+  */
+
+ /* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
 /**
   * @}
   */
@@ -161,6 +187,9 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
 void HAL_IncTick(void);
 void HAL_Delay(__IO uint32_t Delay);
 uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
 void HAL_SuspendTick(void);
 void HAL_ResumeTick(void);
 uint32_t HAL_GetHalVersion(void);
@@ -174,6 +203,9 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
 void HAL_DBGMCU_DisableDBGStandbyMode(void);
 void HAL_EnableCompensationCell(void);
 void HAL_DisableCompensationCell(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h
index a6712a5d..b5b524ce 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -172,34 +154,38 @@ typedef struct
   * @brief  HAL ADC state machine: ADC states definition (bitfields)
   */ 
 /* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET             0x00000000U    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             0x00000001U    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     0x00000002U    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           0x00000004U    /*!< TimeOut occurrence */
 
 /* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL    0x00000010U    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      0x00000020U    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         0x00000040U    /*!< DMA error occurrence */
 
 /* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOC           0x00000200U    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           0x00000400U    /*!< Overrun occurrence */
 
 /* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_EOC           0x00002000U    /*!< Conversion data available on group injected */
 
 /* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD1              0x00010000U    /*!< Out-of-window occurrence of analog watchdog 1 */
 
 /** 
   * @brief  ADC handle Structure definition
   */ 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
 typedef struct
+#endif
 {
   ADC_TypeDef                   *Instance;                   /*!< Register base address */
 
@@ -214,7 +200,39 @@ typedef struct
   __IO uint32_t                 State;                       /*!< ADC communication state */
 
   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 }ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x05U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x06U   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -227,11 +245,14 @@ typedef struct
 /** @defgroup ADC_Error_Code ADC Error Code
   * @{
   */
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
+#define HAL_ADC_ERROR_NONE        0x00U   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    0x01U   /*!< ADC IP internal error: if problem of clocking, 
                                                           enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
+#define HAL_ADC_ERROR_OVR         0x02U   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         0x04U   /*!< DMA transfer error                                    */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -240,7 +261,7 @@ typedef struct
 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
   * @{
   */ 
-#define ADC_CLOCK_SYNC_PCLK_DIV2    ((uint32_t)0x00000000)
+#define ADC_CLOCK_SYNC_PCLK_DIV2    0x00000000U
 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
@@ -251,7 +272,7 @@ typedef struct
 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
   * @{
   */ 
-#define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000)
+#define ADC_TWOSAMPLINGDELAY_5CYCLES    0x00000000U
 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@@ -274,7 +295,7 @@ typedef struct
 /** @defgroup ADC_Resolution ADC Resolution
   * @{
   */ 
-#define ADC_RESOLUTION_12B  ((uint32_t)0x00000000)
+#define ADC_RESOLUTION_12B  0x00000000U
 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
@@ -285,7 +306,7 @@ typedef struct
 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
   * @{
   */ 
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           0x00000000U
 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
@@ -298,7 +319,7 @@ typedef struct
   */
 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
 /*       compatibility with other STM32 devices.                              */
-#define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONV_T1_CC1    0x00000000U
 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -314,7 +335,7 @@ typedef struct
 #define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 #define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1)
+#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)
 /**
   * @}
   */ 
@@ -322,7 +343,7 @@ typedef struct
 /** @defgroup ADC_Data_align ADC Data Align
   * @{
   */ 
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT      0x00000000U
 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
 /**
   * @}
@@ -331,7 +352,7 @@ typedef struct
 /** @defgroup ADC_channels  ADC Common Channels
   * @{
   */ 
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000)
+#define ADC_CHANNEL_0           0x00000000U
 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@@ -360,7 +381,7 @@ typedef struct
 /** @defgroup ADC_sampling_times  ADC Sampling Times
   * @{
   */ 
-#define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_3CYCLES    0x00000000U
 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@@ -375,9 +396,9 @@ typedef struct
   /** @defgroup ADC_EOCSelection ADC EOC Selection
   * @{
   */ 
-#define ADC_EOC_SEQ_CONV              ((uint32_t)0x00000000)
-#define ADC_EOC_SINGLE_CONV           ((uint32_t)0x00000001)
-#define ADC_EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002)  /*!< reserved for future use */
+#define ADC_EOC_SEQ_CONV              0x00000000U
+#define ADC_EOC_SINGLE_CONV           0x00000001U
+#define ADC_EOC_SINGLE_SEQ_CONV       0x00000002U  /*!< reserved for future use */
 /**
   * @}
   */ 
@@ -400,7 +421,7 @@ typedef struct
 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE               0x00000000U
 /**
   * @}
   */ 
@@ -432,9 +453,9 @@ typedef struct
 /** @defgroup ADC_channels_type ADC Channels Type
   * @{
   */ 
-#define ADC_ALL_CHANNELS      ((uint32_t)0x00000001)
-#define ADC_REGULAR_CHANNELS  ((uint32_t)0x00000002) /*!< reserved for future use */
-#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
+#define ADC_ALL_CHANNELS      0x00000001U
+#define ADC_REGULAR_CHANNELS  0x00000002U /*!< reserved for future use */
+#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
 /**
   * @}
   */
@@ -449,60 +470,70 @@ typedef struct
   */
 
 /** @brief Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
+     (__HANDLE__)->MspInitCallback = NULL;                                     \
+     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
+    } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
 
 /**
   * @brief  Enable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
 
 /**
   * @brief  Disable the ADC peripheral.
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
 
 /**
   * @brief  Enable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC Interrupt.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ ADC Interrupt.
   * @retval None
   */
 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the ADC end of conversion interrupt.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: ADC interrupt.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ ADC interrupt.
   * @retval None
   */
 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
 
 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __INTERRUPT__ specifies the ADC interrupt source to check.
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Clear the ADC's pending flags.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __FLAG__ ADC flag.
   * @retval None
   */
 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
 
 /**
   * @brief  Get the selected ADC's flag status.
-  * @param  __HANDLE__: specifies the ADC Handle.
-  * @param  __FLAG__: ADC flag.
+  * @param  __HANDLE__ specifies the ADC Handle.
+  * @param  __FLAG__ ADC flag.
   * @retval None
   */
 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
@@ -527,6 +558,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -591,11 +628,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /* Delay for ADC stabilization time.                                        */
 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
 /* Unit: us                                                                 */
-#define ADC_STAB_DELAY_US               ((uint32_t) 3)
+#define ADC_STAB_DELAY_US               3U
 /* Delay for temperature sensor stabilization time.                         */
 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
 /* Unit: us                                                                 */
-#define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
+#define ADC_TEMPSENSOR_DELAY_US        10U
 /**
   * @}
   */
@@ -610,7 +647,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
   * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
 #define ADC_IS_ENABLE(__HANDLE__)                                              \
@@ -620,7 +657,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /**
   * @brief Test if conversion trigger of regular group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
@@ -629,7 +666,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /**
   * @brief Test if conversion trigger of injected group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
@@ -646,7 +683,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
   * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
@@ -723,102 +760,102 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
 
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
-   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
-    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
+    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
+    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= 0x00FFU)) || \
+    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= 0x003FU)))
 
 /**
   * @brief  Set ADC Regular channel sequence length.
-  * @param  _NbrOfConversion_: Regular channel sequence length. 
+  * @param  _NbrOfConversion_ Regular channel sequence length. 
   * @retval None
   */
-#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
+#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U)
 
 /**
   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.  
+  * @param  _SAMPLETIME_ Sample time parameter.
+  * @param  _CHANNELNB_ Channel number.  
   * @retval None
   */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
 
 /**
   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param  _SAMPLETIME_: Sample time parameter.
-  * @param  _CHANNELNB_: Channel number.  
+  * @param  _SAMPLETIME_ Sample time parameter.
+  * @param  _CHANNELNB_ Channel number.  
   * @retval None
   */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 1 and 6.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
   * @retval None
   */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 7 and 12.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
   * @retval None
   */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
 
 /**
   * @brief  Set the selected regular channel rank for rank between 13 and 16.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number.    
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number.    
   * @retval None
   */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
 
 /**
   * @brief  Enable ADC continuous conversion mode.
-  * @param  _CONTINUOUS_MODE_: Continuous mode.
+  * @param  _CONTINUOUS_MODE_ Continuous mode.
   * @retval None
   */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
+#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
 
 /**
   * @brief  Configures the number of discontinuous conversions for the regular group channels.
-  * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
+  * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
   * @retval None
   */
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
+#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
 
 /**
   * @brief  Enable ADC scan mode.
-  * @param  _SCANCONV_MODE_: Scan conversion mode.
+  * @param  _SCANCONV_MODE_ Scan conversion mode.
   * @retval None
   */
-#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
+#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
 
 /**
   * @brief  Enable the ADC end of conversion selection.
-  * @param  _EOCSelection_MODE_: End of conversion selection mode.
+  * @param  _EOCSelection_MODE_ End of conversion selection mode.
   * @retval None
   */
-#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
+#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
 
 /**
   * @brief  Enable the ADC DMA continuous request.
-  * @param  _DMAContReq_MODE_: DMA continuous request mode.
+  * @param  _DMAContReq_MODE_ DMA continuous request mode.
   * @retval None
   */
-#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
+#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
 
 /**
   * @brief Return resolution bits in CR1 register.
-  * @param __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h
index 6d046320..b0b11fc2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h
@@ -1,36 +1,18 @@
 /**
   ******************************************************************************
-  * @file    stm32f2xx_hal_adc.h
+  * @file    stm32f2xx_hal_adc_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   Header file of ADC HAL module.
+  * @brief   Header file of ADC HAL extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -126,9 +108,6 @@ typedef struct
                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
 }ADC_InjectionConfTypeDef; 
-/**
-  * @}
-  */
 
 /** 
   * @brief ADC Configuration multi-mode structure definition  
@@ -155,7 +134,7 @@ typedef struct
 /** @defgroup ADCEx_Common_mode ADC Common Mode
   * @{
   */ 
-#define ADC_MODE_INDEPENDENT                  ((uint32_t)0x00000000)      
+#define ADC_MODE_INDEPENDENT                  0x00000000U      
 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)
 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)
 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@@ -175,7 +154,7 @@ typedef struct
 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
   * @{
   */ 
-#define ADC_DMAACCESSMODE_DISABLED  ((uint32_t)0x00000000)     /*!< DMA mode disabled */
+#define ADC_DMAACCESSMODE_DISABLED  0x00000000U     /*!< DMA mode disabled */
 #define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
 #define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
 #define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@@ -186,7 +165,7 @@ typedef struct
 /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
   * @{
   */ 
-#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           0x00000000U
 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
@@ -197,7 +176,7 @@ typedef struct
 /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
   * @{
   */ 
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           0x00000000U
 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)
 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)
 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@@ -213,7 +192,7 @@ typedef struct
 #define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)
-#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1)
+#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1U)
 /**
   * @}
   */ 
@@ -221,10 +200,10 @@ typedef struct
 /** @defgroup ADCEx_injected_rank ADC Injected Rank
   * @{
   */ 
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
+#define ADC_INJECTED_RANK_1    0x00000001U
+#define ADC_INJECTED_RANK_2    0x00000002U
+#define ADC_INJECTED_RANK_3    0x00000003U
+#define ADC_INJECTED_RANK_4    0x00000004U
 /**
   * @}
   */
@@ -338,17 +317,17 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \
                                         ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
                                         ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
 
 /**
   * @brief  Set the selected injected Channel rank.
-  * @param  _CHANNELNB_: Channel number.
-  * @param  _RANKNB_: Rank number. 
-  * @param  _JSQR_JL_: Sequence length.     
+  * @param  _CHANNELNB_ Channel number.
+  * @param  _RANKNB_ Rank number. 
+  * @param  _JSQR_JL_ Sequence length.
   * @retval None
   */
-#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
+#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h
index 318803a3..16176ae0 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CAN_H
-#define __STM32F2xx_HAL_CAN_H
+#ifndef STM32F2xx_HAL_CAN_H
+#define STM32F2xx_HAL_CAN_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -50,6 +32,7 @@
   * @{
   */
 
+#if defined (CAN1)
 /** @addtogroup CAN
   * @{
   */
@@ -58,63 +41,60 @@
 /** @defgroup CAN_Exported_Types CAN Exported Types
   * @{
   */
-
 /**
   * @brief  HAL State structures definition
   */
 typedef enum
 {
-  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
-  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
-  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
+  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
+  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
+  HAL_CAN_STATE_LISTENING         = 0x02U,  /*!< CAN receive process is ongoing      */
+  HAL_CAN_STATE_SLEEP_PENDING     = 0x03U,  /*!< CAN sleep request is pending        */
+  HAL_CAN_STATE_SLEEP_ACTIVE      = 0x04U,  /*!< CAN sleep mode is active            */
+  HAL_CAN_STATE_ERROR             = 0x05U   /*!< CAN error state                     */
 
-}HAL_CAN_StateTypeDef;
+} HAL_CAN_StateTypeDef;
 
 /**
   * @brief  CAN init structure definition
   */
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
-                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  uint32_t Prescaler;                  /*!< Specifies the length of a time quantum.
+                                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+  uint32_t Mode;                       /*!< Specifies the CAN operating mode.
+                                            This parameter can be a value of @ref CAN_operating_mode */
 
-  uint32_t Mode;       /*!< Specifies the CAN operating mode.
-                            This parameter can be a value of @ref CAN_operating_mode */
+  uint32_t SyncJumpWidth;              /*!< Specifies the maximum number of time quanta the CAN hardware
+                                            is allowed to lengthen or shorten a bit to perform resynchronization.
+                                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
 
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
-                            the CAN hardware is allowed to lengthen or
-                            shorten a bit to perform resynchronization.
-                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
+  uint32_t TimeSeg1;                   /*!< Specifies the number of time quanta in Bit Segment 1.
+                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
 
-  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+  uint32_t TimeSeg2;                   /*!< Specifies the number of time quanta in Bit Segment 2.
+                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
 
-  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
-                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  FunctionalState TimeTriggeredMode;   /*!< Enable or disable the time triggered communication mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
-                            This parameter can be set to ENABLE or DISABLE. */
+  FunctionalState AutoBusOff;          /*!< Enable or disable the automatic bus-off management.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
-                            This parameter can be set to ENABLE or DISABLE */
+  FunctionalState AutoWakeUp;          /*!< Enable or disable the automatic wake-up mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
-                            This parameter can be set to ENABLE or DISABLE */
+  FunctionalState AutoRetransmission;  /*!< Enable or disable the non-automatic retransmission mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
-                            This parameter can be set to ENABLE or DISABLE */
+  FunctionalState ReceiveFifoLocked;   /*!< Enable or disable the Receive FIFO Locked mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
-                            This parameter can be set to ENABLE or DISABLE */
+  FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+                                            This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
-                            This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
+} CAN_InitTypeDef;
 
 /**
   * @brief  CAN filter configuration structure definition
@@ -123,27 +103,30 @@ typedef struct
 {
   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
                                        configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
                                        configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
                                        according to the mode (MSBs for a 32-bit configuration,
                                        first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
                                        according to the mode (LSBs for a 32-bit configuration,
                                        second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
                                        This parameter can be a value of @ref CAN_filter_FIFO */
 
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+  uint32_t FilterBank;            /*!< Specifies the filter bank which will be initialized.
+                                       For single CAN instance(14 dedicated filter banks),
+                                       this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+                                       For dual CAN instances(28 filter banks shared),
+                                       this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
 
   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
                                        This parameter can be a value of @ref CAN_filter_mode */
@@ -152,112 +135,182 @@ typedef struct
                                        This parameter can be a value of @ref CAN_filter_scale */
 
   uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be set to ENABLE or DISABLE. */
+                                       This parameter can be a value of @ref CAN_filter_activation */
 
-  uint32_t BankNumber;            /*!< Select the start slave bank filter.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+  uint32_t SlaveStartFilterBank;  /*!< Select the start filter bank for the slave CAN instance.
+                                       For single CAN instances, this parameter is meaningless.
+                                       For dual CAN instances, all filter banks with lower index are assigned to master
+                                       CAN instance, whereas all filter banks with greater index are assigned to slave
+                                       CAN instance.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
 
-}CAN_FilterConfTypeDef;
+} CAN_FilterTypeDef;
 
 /**
-  * @brief  CAN Tx message structure definition
+  * @brief  CAN Tx message header structure definition
   */
 typedef struct
 {
   uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
 
   uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
 
   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_Identifier_Type */
+                          This parameter can be a value of @ref CAN_identifier_type */
 
   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
                           This parameter can be a value of @ref CAN_remote_transmission_request */
 
   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint8_t Data[8];   /*!< Contains the data to be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+  FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+                          of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+                          @note: Time Triggered Communication Mode must be enabled.
+                          @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+                          This parameter can be set to ENABLE or DISABLE. */
 
-}CanTxMsgTypeDef;
+} CAN_TxHeaderTypeDef;
 
 /**
-  * @brief  CAN Rx message structure definition
+  * @brief  CAN Rx message header structure definition
   */
 typedef struct
 {
-  uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
-  uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
 
-  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
-                             This parameter can be a value of @ref CAN_Identifier_Type */
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
 
-  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
-                             This parameter can be a value of @ref CAN_remote_transmission_request */
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
 
-  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */
 
-  uint8_t Data[8];      /*!< Contains the data to be received.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+  uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+                          @note: Time Triggered Communication Mode must be enabled.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
 
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
-                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+  uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 
-}CanRxMsgTypeDef;
+} CAN_RxHeaderTypeDef;
 
 /**
   * @brief  CAN handle Structure definition
   */
-typedef struct
+typedef struct __CAN_HandleTypeDef
 {
-  CAN_TypeDef                 *Instance;  /*!< Register base address          */
+  CAN_TypeDef                 *Instance;                 /*!< Register base address */
+
+  CAN_InitTypeDef             Init;                      /*!< CAN required parameters */
 
-  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
+  __IO HAL_CAN_StateTypeDef   State;                     /*!< CAN communication state */
 
-  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
+  __IO uint32_t               ErrorCode;                 /*!< CAN Error code.
+                                                              This parameter can be a value of @ref CAN_Error_Code */
 
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback    */
+  void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback    */
+  void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback    */
+  void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 0 abort callback       */
+  void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 1 abort callback       */
+  void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 2 abort callback       */
+  void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback    */
+  void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 0 full callback           */
+  void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback    */
+  void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 1 full callback           */
+  void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Sleep callback                    */
+  void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Wake Up from Rx msg callback      */
+  void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Error callback                    */
 
-  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
+  void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan);           /*!< CAN Msp Init callback                 */
+  void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan);         /*!< CAN Msp DeInit callback               */
 
-  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+} CAN_HandleTypeDef;
 
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL CAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID       = 0x00U,    /*!< CAN Tx Mailbox 0 complete callback ID         */
+  HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID       = 0x01U,    /*!< CAN Tx Mailbox 1 complete callback ID         */
+  HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID       = 0x02U,    /*!< CAN Tx Mailbox 2 complete callback ID         */
+  HAL_CAN_TX_MAILBOX0_ABORT_CB_ID          = 0x03U,    /*!< CAN Tx Mailbox 0 abort callback ID            */
+  HAL_CAN_TX_MAILBOX1_ABORT_CB_ID          = 0x04U,    /*!< CAN Tx Mailbox 1 abort callback ID            */
+  HAL_CAN_TX_MAILBOX2_ABORT_CB_ID          = 0x05U,    /*!< CAN Tx Mailbox 2 abort callback ID            */
+  HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID       = 0x06U,    /*!< CAN Rx FIFO 0 message pending callback ID     */
+  HAL_CAN_RX_FIFO0_FULL_CB_ID              = 0x07U,    /*!< CAN Rx FIFO 0 full callback ID                */
+  HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID       = 0x08U,    /*!< CAN Rx FIFO 1 message pending callback ID     */
+  HAL_CAN_RX_FIFO1_FULL_CB_ID              = 0x09U,    /*!< CAN Rx FIFO 1 full callback ID                */
+  HAL_CAN_SLEEP_CB_ID                      = 0x0AU,    /*!< CAN Sleep callback ID                         */
+  HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID         = 0x0BU,    /*!< CAN Wake Up fropm Rx msg callback ID          */
+  HAL_CAN_ERROR_CB_ID                      = 0x0CU,    /*!< CAN Error callback ID                         */
+
+  HAL_CAN_MSPINIT_CB_ID                    = 0x0DU,    /*!< CAN MspInit callback ID                       */
+  HAL_CAN_MSPDEINIT_CB_ID                  = 0x0EU,    /*!< CAN MspDeInit callback ID                     */
+
+} HAL_CAN_CallbackIDTypeDef;
 
-}CAN_HandleTypeDef;
+/**
+  * @brief  HAL CAN Callback pointer definition
+  */
+typedef  void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function   */
 
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup CAN_Exported_Constants CAN Exported Constants
   * @{
   */
 
-/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
+/** @defgroup CAN_Error_Code CAN Error Code
   * @{
   */
-#define   HAL_CAN_ERROR_NONE      0x00    /*!< No error             */
-#define   HAL_CAN_ERROR_EWG       0x01    /*!< EWG error            */
-#define   HAL_CAN_ERROR_EPV       0x02    /*!< EPV error            */
-#define   HAL_CAN_ERROR_BOF       0x04    /*!< BOF error            */
-#define   HAL_CAN_ERROR_STF       0x08    /*!< Stuff error          */
-#define   HAL_CAN_ERROR_FOR       0x10    /*!< Form error           */
-#define   HAL_CAN_ERROR_ACK       0x20    /*!< Acknowledgment error */
-#define   HAL_CAN_ERROR_BR        0x40    /*!< Bit recessive        */
-#define   HAL_CAN_ERROR_BD        0x80    /*!< LEC dominant         */
-#define   HAL_CAN_ERROR_CRC       0x100   /*!< LEC transfer error   */
+#define HAL_CAN_ERROR_NONE            (0x00000000U)  /*!< No error                                             */
+#define HAL_CAN_ERROR_EWG             (0x00000001U)  /*!< Protocol Error Warning                               */
+#define HAL_CAN_ERROR_EPV             (0x00000002U)  /*!< Error Passive                                        */
+#define HAL_CAN_ERROR_BOF             (0x00000004U)  /*!< Bus-off error                                        */
+#define HAL_CAN_ERROR_STF             (0x00000008U)  /*!< Stuff error                                          */
+#define HAL_CAN_ERROR_FOR             (0x00000010U)  /*!< Form error                                           */
+#define HAL_CAN_ERROR_ACK             (0x00000020U)  /*!< Acknowledgment error                                 */
+#define HAL_CAN_ERROR_BR              (0x00000040U)  /*!< Bit recessive error                                  */
+#define HAL_CAN_ERROR_BD              (0x00000080U)  /*!< Bit dominant error                                   */
+#define HAL_CAN_ERROR_CRC             (0x00000100U)  /*!< CRC error                                            */
+#define HAL_CAN_ERROR_RX_FOV0         (0x00000200U)  /*!< Rx FIFO0 overrun error                               */
+#define HAL_CAN_ERROR_RX_FOV1         (0x00000400U)  /*!< Rx FIFO1 overrun error                               */
+#define HAL_CAN_ERROR_TX_ALST0        (0x00000800U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0        (0x00001000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */
+#define HAL_CAN_ERROR_TX_ALST1        (0x00002000U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1        (0x00004000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */
+#define HAL_CAN_ERROR_TX_ALST2        (0x00008000U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2        (0x00010000U)  /*!< TxMailbox 1 transmit failure due to tranmit error    */
+#define HAL_CAN_ERROR_TIMEOUT         (0x00020000U)  /*!< Timeout error                                        */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U)  /*!< Peripheral not initialized                           */
+#define HAL_CAN_ERROR_NOT_READY       (0x00080000U)  /*!< Peripheral not ready                                 */
+#define HAL_CAN_ERROR_NOT_STARTED     (0x00100000U)  /*!< Peripheral not started                               */
+#define HAL_CAN_ERROR_PARAM           (0x00200000U)  /*!< Parameter error                                      */
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error                               */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+#define HAL_CAN_ERROR_INTERNAL        (0x00800000U)  /*!< Internal error                                       */
+
 /**
   * @}
   */
@@ -265,8 +318,8 @@ typedef struct
 /** @defgroup CAN_InitStatus CAN InitStatus
   * @{
   */
-#define CAN_INITSTATUS_FAILED       ((uint8_t)0x00)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      ((uint8_t)0x01)  /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK     */
 /**
   * @}
   */
@@ -274,7 +327,7 @@ typedef struct
 /** @defgroup CAN_operating_mode CAN Operating Mode
   * @{
   */
-#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
+#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */
 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
@@ -282,10 +335,11 @@ typedef struct
   * @}
   */
 
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
   * @{
   */
-#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
+#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */
 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
@@ -293,10 +347,10 @@ typedef struct
   * @}
   */
 
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
   * @{
   */
-#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
+#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */
 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
@@ -316,10 +370,10 @@ typedef struct
   * @}
   */
 
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
   * @{
   */
-#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
+#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */
 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
@@ -331,11 +385,11 @@ typedef struct
   * @}
   */
 
-/** @defgroup CAN_filter_mode  CAN Filter Mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
   * @{
   */
-#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
+#define CAN_FILTERMODE_IDMASK       (0x00000000U)  /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST       (0x00000001U)  /*!< Identifier list mode */
 /**
   * @}
   */
@@ -343,8 +397,17 @@ typedef struct
 /** @defgroup CAN_filter_scale CAN Filter Scale
   * @{
   */
-#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
+#define CAN_FILTERSCALE_16BIT       (0x00000000U)  /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT       (0x00000001U)  /*!< One 32-bit filter  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_activation CAN Filter Activation
+  * @{
+  */
+#define CAN_FILTER_DISABLE          (0x00000000U)  /*!< Disable filter */
+#define CAN_FILTER_ENABLE           (0x00000001U)  /*!< Enable filter  */
 /**
   * @}
   */
@@ -352,17 +415,17 @@ typedef struct
 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
   * @{
   */
-#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_FILTER_FIFO0            (0x00000000U)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1            (0x00000001U)  /*!< Filter FIFO 1 assignment for filter x */
 /**
   * @}
   */
 
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
+/** @defgroup CAN_identifier_type CAN Identifier Type
   * @{
   */
-#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
-#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define CAN_ID_STD                  (0x00000000U)  /*!< Standard Id */
+#define CAN_ID_EXT                  (0x00000004U)  /*!< Extended Id */
 /**
   * @}
   */
@@ -370,95 +433,100 @@ typedef struct
 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
   * @{
   */
-#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
-#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame   */
+#define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */
 /**
   * @}
   */
 
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
   * @{
   */
-#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
+#define CAN_RX_FIFO0                (0x00000000U)  /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1                (0x00000001U)  /*!< CAN receive FIFO 1 */
 /**
   * @}
   */
 
-/** @defgroup CAN_flags CAN Flags
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
   * @{
   */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
-   CAN_GetFlagStatus() function.  */
+#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
+#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
+#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
+/**
+  * @}
+  */
 
+/** @defgroup CAN_flags CAN Flags
+  * @{
+  */
 /* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
-#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_RQCP0              (0x00000500U)  /*!< Request complete MailBox 0 flag   */
+#define CAN_FLAG_TXOK0              (0x00000501U)  /*!< Transmission OK MailBox 0 flag    */
+#define CAN_FLAG_ALST0              (0x00000502U)  /*!< Arbitration Lost MailBox 0 flag   */
+#define CAN_FLAG_TERR0              (0x00000503U)  /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1              (0x00000508U)  /*!< Request complete MailBox1 flag    */
+#define CAN_FLAG_TXOK1              (0x00000509U)  /*!< Transmission OK MailBox 1 flag    */
+#define CAN_FLAG_ALST1              (0x0000050AU)  /*!< Arbitration Lost MailBox 1 flag   */
+#define CAN_FLAG_TERR1              (0x0000050BU)  /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2              (0x00000510U)  /*!< Request complete MailBox2 flag    */
+#define CAN_FLAG_TXOK2              (0x00000511U)  /*!< Transmission OK MailBox 2 flag    */
+#define CAN_FLAG_ALST2              (0x00000512U)  /*!< Arbitration Lost MailBox 2 flag   */
+#define CAN_FLAG_TERR2              (0x00000513U)  /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0               (0x0000051AU)  /*!< Transmit mailbox 0 empty flag     */
+#define CAN_FLAG_TME1               (0x0000051BU)  /*!< Transmit mailbox 1 empty flag     */
+#define CAN_FLAG_TME2               (0x0000051CU)  /*!< Transmit mailbox 2 empty flag     */
+#define CAN_FLAG_LOW0               (0x0000051DU)  /*!< Lowest priority mailbox 0 flag    */
+#define CAN_FLAG_LOW1               (0x0000051EU)  /*!< Lowest priority mailbox 1 flag    */
+#define CAN_FLAG_LOW2               (0x0000051FU)  /*!< Lowest priority mailbox 2 flag    */
 
 /* Receive Flags */
-#define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
-#define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
-#define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
+#define CAN_FLAG_FF0                (0x00000203U)  /*!< RX FIFO 0 Full flag               */
+#define CAN_FLAG_FOV0               (0x00000204U)  /*!< RX FIFO 0 Overrun flag            */
+#define CAN_FLAG_FF1                (0x00000403U)  /*!< RX FIFO 1 Full flag               */
+#define CAN_FLAG_FOV1               (0x00000404U)  /*!< RX FIFO 1 Overrun flag            */
 
 /* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
-#define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
-         In this case the SLAK bit can be polled.*/
+#define CAN_FLAG_INAK               (0x00000100U)  /*!< Initialization acknowledge flag   */
+#define CAN_FLAG_SLAK               (0x00000101U)  /*!< Sleep acknowledge flag            */
+#define CAN_FLAG_ERRI               (0x00000102U)  /*!< Error flag                        */
+#define CAN_FLAG_WKU                (0x00000103U)  /*!< Wake up interrupt flag            */
+#define CAN_FLAG_SLAKI              (0x00000104U)  /*!< Sleep acknowledge interrupt flag  */
 
 /* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
+#define CAN_FLAG_EWG                (0x00000300U)  /*!< Error warning flag                */
+#define CAN_FLAG_EPV                (0x00000301U)  /*!< Error passive flag                */
+#define CAN_FLAG_BOF                (0x00000302U)  /*!< Bus-Off flag                      */
 /**
   * @}
   */
 
+
 /** @defgroup CAN_Interrupts CAN Interrupts
   * @{
   */
-#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY     ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
 
 /* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL        ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
+#define CAN_IT_RX_FIFO0_OVERRUN     ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL        ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
+#define CAN_IT_RX_FIFO1_OVERRUN     ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
 
 /* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
-#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
+#define CAN_IT_WAKEUP               ((uint32_t)CAN_IER_WKUIE)   /*!< Wake-up interrupt                */
+#define CAN_IT_SLEEP_ACK            ((uint32_t)CAN_IER_SLKIE)   /*!< Sleep acknowledge interrupt      */
 
 /* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
-#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
-#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
-#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
-  * @{
-  */
-#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
+#define CAN_IT_ERROR_WARNING        ((uint32_t)CAN_IER_EWGIE)   /*!< Error warning interrupt          */
+#define CAN_IT_ERROR_PASSIVE        ((uint32_t)CAN_IER_EPVIE)   /*!< Error passive interrupt          */
+#define CAN_IT_BUSOFF               ((uint32_t)CAN_IER_BOFIE)   /*!< Bus-off interrupt                */
+#define CAN_IT_LAST_ERROR_CODE      ((uint32_t)CAN_IER_LECIE)   /*!< Last error code interrupt        */
+#define CAN_IT_ERROR                ((uint32_t)CAN_IER_ERRIE)   /*!< Error Interrupt                  */
 /**
   * @}
   */
@@ -467,217 +535,212 @@ typedef struct
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup CAN_Exported_Macros CAN Exported Macros
   * @{
   */
 
-/** @brief Reset CAN handle state
-  * @param  __HANDLE__: specifies the CAN Handle.
+/** @brief  Reset CAN handle state
+  * @param  __HANDLE__ CAN handle.
   * @retval None
   */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{                                              \
+                                                     (__HANDLE__)->State = HAL_CAN_STATE_RESET;   \
+                                                     (__HANDLE__)->MspInitCallback = NULL;        \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \
+                                                   } while(0)
+#else
 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt sources to enable.
+  *           This parameter can be any combination of @arg CAN_Interrupts
   * @retval None
   */
 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt sources to disable.
+  *           This parameter can be any combination of @arg CAN_Interrupts
   * @retval None
   */
 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 
-/**
-  * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval The number of pending message.
+/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
+  *           This parameter can be a value of @arg CAN_Interrupts
+  * @retval The state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
 
 /** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of @arg CAN_flags
+  * @retval The state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+  ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
 
 /** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
-  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
-  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
-  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
-  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
-  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
-  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
-  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
-  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
-  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKU: Wake up Flag
-  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
-  *            @arg CAN_FLAG_EWG: Error Warning Flag
-  *            @arg CAN_FLAG_EPV: Error Passive Flag
-  *            @arg CAN_FLAG_BOF: Bus-Off Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  *            @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+  *            @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+  *            @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+  *            @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+  *            @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+  *            @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+  *            @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+  *            @arg CAN_FLAG_FF0:   RX FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0:  RX FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FF1:   RX FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1:  RX FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKUI:  Wake up Interrupt Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+  * @retval None
   */
 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? (((__HANDLE__)->Instance->MSR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->ESR) = ~((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
-  *             @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
-  *             @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+  ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
 
 /**
-  * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval The new status of transmission  (TRUE or FALSE).
-  */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+ * @}
+ */
 
-/**
-  * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
-  * @retval None
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+  * @{
   */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
 
-/**
-  * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
-  * @retval None
-  */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
 
-/**
-  * @brief  Enable or disable the DBG Freeze for CAN.
-  * @param  __HANDLE__: CAN Handle
-  * @param  __NEWSTATE__: new state of the CAN peripheral.
-  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *          during debug. Reception FIFOs can still be accessed/controlled normally)
-  *          or DISABLE (CAN is working during debug).
-  * @retval None
-  */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
 
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
 /**
-  * @}
-  */
+ * @}
+ */
 
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
-  * @{
-  */
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
 
-/** @addtogroup CAN_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
 /**
-  * @}
-  */
+ * @}
+ */
 
-/** @addtogroup CAN_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ *  @brief    Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ *  @brief    Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
 /**
-  * @}
-  */
+ * @}
+ */
 
-/** @addtogroup CAN_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
 /**
-  * @}
-  */
+ * @}
+ */
 
 /**
-  * @}
-  */
+ * @}
+ */
 
 /* Private types -------------------------------------------------------------*/
 /** @defgroup CAN_Private_Types CAN Private Types
@@ -695,66 +758,82 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup CAN_Private_Constants CAN Private Constants
   * @{
   */
-#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK  ((uint32_t)0x000000FF)
+#define CAN_FLAG_MASK  (0x000000FFU)
 /**
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/
+/* Private Macros -----------------------------------------------------------*/
 /** @defgroup CAN_Private_Macros CAN Private Macros
   * @{
   */
+
 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
                            ((MODE) == CAN_MODE_LOOPBACK)|| \
                            ((MODE) == CAN_MODE_SILENT) || \
                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+                         ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+                         ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+                         ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+                         ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+                         ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+                         ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+                         ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+                         ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+                         ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+                         ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
                                   ((MODE) == CAN_FILTERMODE_IDLIST))
 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+                                              ((ACTIVATION) == CAN_FILTER_ENABLE))
 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
                                   ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)
 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
                                 ((IDTYPE) == CAN_ID_EXT))
 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY     | CAN_IT_RX_FIFO0_MSG_PENDING      | \
+                                CAN_IT_RX_FIFO0_FULL        | CAN_IT_RX_FIFO0_OVERRUN          | \
+                                CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL             | \
+                                CAN_IT_RX_FIFO1_OVERRUN     | CAN_IT_WAKEUP                    | \
+                                CAN_IT_SLEEP_ACK            | CAN_IT_ERROR_WARNING             | \
+                                CAN_IT_ERROR_PASSIVE        | CAN_IT_BUSOFF                    | \
+                                CAN_IT_LAST_ERROR_CODE      | CAN_IT_ERROR))
 
 /**
   * @}
   */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
-  * @{
-  */
+/* End of private macros -----------------------------------------------------*/
 
 /**
   * @}
   */
 
 
-/**
-  * @}
-  */
-
+#endif /* CAN1 */
 /**
   * @}
   */
@@ -763,7 +842,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 }
 #endif
 
-#endif /* __STM32F2xx_CAN_H */
+#endif /* STM32F2xx_HAL_CAN_H */
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h
index 5905a932..c26dc66d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h
@@ -2,40 +2,22 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_conf_template.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   HAL configuration template file. 
   *          This file should be copied to the application folder and renamed
   *          to stm32f2xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CONF_H
@@ -52,41 +34,43 @@
 /**
   * @brief This is the list of modules to be used in the HAL driver 
   */
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED  
-#define HAL_CAN_MODULE_ENABLED  
-#define HAL_CRC_MODULE_ENABLED  
-#define HAL_CRYP_MODULE_ENABLED  
-#define HAL_DAC_MODULE_ENABLED  
-#define HAL_DCMI_MODULE_ENABLED 
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
 #define HAL_DMA_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED 
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
 #define HAL_NAND_MODULE_ENABLED
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_PCCARD_MODULE_ENABLED
 #define HAL_SRAM_MODULE_ENABLED
-#define HAL_HASH_MODULE_ENABLED  
+#define HAL_HASH_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED   
-#define HAL_IWDG_MODULE_ENABLED 
-#define HAL_PWR_MODULE_ENABLED   
-#define HAL_RCC_MODULE_ENABLED 
-#define HAL_RNG_MODULE_ENABLED   
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
 #define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED  
-#define HAL_SPI_MODULE_ENABLED   
-#define HAL_TIM_MODULE_ENABLED   
-#define HAL_UART_MODULE_ENABLED 
-#define HAL_USART_MODULE_ENABLED 
-#define HAL_IRDA_MODULE_ENABLED 
-#define HAL_SMARTCARD_MODULE_ENABLED 
-#define HAL_WWDG_MODULE_ENABLED  
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
 #define HAL_PCD_MODULE_ENABLED
 #define HAL_HCD_MODULE_ENABLED
-
+#define HAL_MMC_MODULE_ENABLED
 
 /* ########################## HSE/HSI Values adaptation ##################### */
 /**
@@ -95,11 +79,11 @@
   *        (when HSE is used as system clock source, directly or through the PLL).  
   */
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE                    25000000U       /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT               100U       /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -108,31 +92,35 @@
   *        (when HSI is used as system clock source, directly or through the PLL). 
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE                    16000000U       /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
 #if !defined  (LSI_VALUE) 
- #define LSI_VALUE  ((uint32_t)32000)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
+ #define LSI_VALUE                        32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                                 /*!< Value of the Internal Low Speed oscillator in Hz
+                                                            The real value may vary depending on the variations
+                                                            in voltage and temperature.*/
 /**
   * @brief External Low Speed oscillator (LSE) value.
   */
 #if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+ #define LSE_VALUE                        32768U       /*!< Value of the External Low Speed oscillator in Hz */
 #endif /* LSE_VALUE */
 
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT              5000U       /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
 /**
   * @brief External clock source for I2S peripheral
   *        This value is used by the I2S HAL module to compute the I2S clock source 
   *        frequency, this source is inserted directly through I2S_CKIN pad. 
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+  #define EXTERNAL_CLOCK_VALUE       12288000U        /*!< Value of the Internal oscillator in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -142,54 +130,81 @@
 /**
   * @brief This is the HAL system configuration section
   */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     1
-#define  DATA_CACHE_ENABLE            1
+#define  VDD_VALUE                      3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY              0x0FU /*!< tick interrupt priority */
+#define  USE_RTOS                          0U
+#define  PREFETCH_ENABLE                   1U
+#define  INSTRUCTION_CACHE_ENABLE          1U
+#define  DATA_CACHE_ENABLE                 1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
 
 /* ########################## Assert Selection ############################## */
 /**
   * @brief Uncomment the line below to expanse the "assert_param" macro in the 
   *        HAL drivers code
   */
-/* #define USE_FULL_ASSERT    1 */
+/* #define USE_FULL_ASSERT    1U */
 
 /* ################## Ethernet peripheral configuration ##################### */
 
 /* Section 1 : Ethernet peripheral configuration */
 
 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
+#define MAC_ADDR0                         2U
+#define MAC_ADDR1                         0U
+#define MAC_ADDR2                         0U
+#define MAC_ADDR3                         0U
+#define MAC_ADDR4                         0U
+#define MAC_ADDR5                         0U
 
 /* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)4)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+#define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                       4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                       4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
 
 /* Section 2: PHY configuration section */
 
 /* DP83848 PHY Address*/ 
-#define DP83848_PHY_ADDRESS             0x01
+#define DP83848_PHY_ADDRESS             0x01U
 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+#define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+#define PHY_CONFIG_DELAY                0x00000FFFU
 
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
 
 /* Section 3: Common PHY Registers */
 
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
  
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
@@ -208,9 +223,9 @@
   
 /* Section 4: Extended PHY Registers */
 
-#define PHY_SR                          ((uint16_t)0x10)    /*!< PHY status register Offset                      */
-#define PHY_MICR                        ((uint16_t)0x11)    /*!< MII Interrupt Control Register                  */
-#define PHY_MISR                        ((uint16_t)0x12)    /*!< MII Interrupt Status and Misc. Control Register */
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
  
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
@@ -222,6 +237,15 @@
 #define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
 #define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
 
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
 /* Includes ------------------------------------------------------------------*/
 /**
   * @brief Include module's header file 
@@ -235,6 +259,10 @@
   #include "stm32f2xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
 
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f2xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f2xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
@@ -251,6 +279,10 @@
   #include "stm32f2xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
 
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f2xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
 #ifdef HAL_CRC_MODULE_ENABLED
   #include "stm32f2xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
@@ -358,22 +390,25 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f2xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f2xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
+  * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
   *         line number of the call that failed. 
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
   void assert_failed(uint8_t* file, uint32_t line);
 #else
-  #define assert_param(expr) ((void)0)
+  #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
 
 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h
index 82eff8ec..8502ef1a 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CORTEX_H
@@ -58,7 +40,7 @@
   * @{
   */
 
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
   * @brief  MPU Region initialization structure 
   * @{
@@ -105,25 +87,25 @@ typedef struct
 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
   * @{
   */
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+                                                      0 bits for subpriority */
 /**
   * @}
   */
 
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 
   * @{
   */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
 
 /**
   * @}
@@ -133,10 +115,11 @@ typedef struct
 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
   * @{
   */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
+#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
+#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
 /**
   * @}
   */
@@ -201,44 +184,44 @@ typedef struct
   */
 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06) 
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07) 
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08) 
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B) 
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C) 
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D) 
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E) 
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F) 
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13) 
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14) 
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15) 
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16) 
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D) 
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E) 
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-/**                                
+/**
   * @}
   */
    
 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
   * @{
   */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01) 
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05) 
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
 /**
   * @}
@@ -247,11 +230,11 @@ typedef struct
 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
   * @{
   */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01) 
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04) 
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
@@ -266,29 +249,6 @@ typedef struct
 
 
 /* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/** @brief Configures the SysTick clock source.
-  * @param __CLKSRC__: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__)                             \
-                            do {                                               \
-                                 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK)   \
-                                  {                                            \
-                                    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;   \
-                                  }                                            \
-                                 else                                          \
-                                    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;  \
-                                } while(0)
-/**
-  * @}
-  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup CORTEX_Exported_Functions
@@ -296,8 +256,8 @@ typedef struct
   */
   
 /** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
+  * @{
+  */
 /* Initialization and de-initialization functions *****************************/
 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
@@ -310,12 +270,9 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
   */
 
 /** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
+  * @{
+  */
 /* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
 uint32_t HAL_NVIC_GetPriorityGrouping(void);
 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
@@ -325,6 +282,12 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
 void HAL_SYSTICK_IRQHandler(void);
 void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
 /**
   * @}
   */
@@ -333,7 +296,7 @@ void HAL_SYSTICK_Callback(void);
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
@@ -346,16 +309,16 @@ void HAL_SYSTICK_Callback(void);
                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
 
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
 
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
 
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
 
 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
 
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
                                      ((STATE) == MPU_REGION_DISABLE))
 
@@ -425,52 +388,9 @@ void HAL_SYSTICK_Callback(void);
 
 /**                                                                          
   * @}                                                                  
-  */                                                                            
-                                                                                   
-/* Private functions ---------------------------------------------------------*/   
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
-  * @brief    CORTEX private  functions 
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disables the MPU
-  * @retval None
   */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU */
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
-  * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged access to the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
 
-/**
-  * @}
-  */
+/* Private functions ---------------------------------------------------------*/
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h
index 6089497a..40b6a60b 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CRC_H
-#define __STM32F2xx_HAL_CRC_H
+#ifndef STM32F2xx_HAL_CRC_H
+#define STM32F2xx_HAL_CRC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -50,8 +32,7 @@
   * @{
   */
 
-/** @defgroup CRC CRC
-  * @brief CRC HAL module driver
+/** @addtogroup CRC
   * @{
   */
 
@@ -60,95 +41,110 @@
   * @{
   */
 
-/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition 
-  * @{
+/**
+  * @brief  CRC HAL State Structure definition
   */
 typedef enum
 {
-  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
-
-}HAL_CRC_StateTypeDef;
-/** 
-  * @}
-  */
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+} HAL_CRC_StateTypeDef;
 
-/** @defgroup CRC_Exported_Types_Group2 CRC Handle Structure definition   
-  * @{
-  */ 
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
 typedef struct
 {
-  CRC_TypeDef                 *Instance;  /*!< Register base address   */
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
 
-  HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
 
-  __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
 
-}CRC_HandleTypeDef;
-/** 
+} CRC_HandleTypeDef;
+/**
   * @}
   */
 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
 /**
   * @}
-  */ 
+  */
 
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup CRC_Exported_Macros CRC Exported Macros
   * @{
   */
 
-/** @brief Resets CRC handle state
-  * @param  __HANDLE__: CRC handle
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__ CRC handle.
   * @retval None
   */
 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
 
 /**
-  * @brief  Resets CRC Data Register.
-  * @param  __HANDLE__: CRC handle
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__ CRC handle
   * @retval None
   */
 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
 
 /**
-  * @brief Stores a 8-bit data in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @brief Store data in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__  Value to be stored in the ID register
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
   * @retval None
   */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) 
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
 
 /**
-  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @retval 8-bit value of the ID register 
+  * @brief Return the data stored in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval Value of the ID register
   */
 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
 /**
   * @}
-  */ 
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros CRC Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup CRC_Exported_Functions CRC Exported Functions
   * @{
   */
 
+/* Initialization and de-initialization functions  ****************************/
 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
 void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
 void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
 /**
   * @}
-  */ 
+  */
 
+/* Peripheral Control functions ***********************************************/
 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
@@ -156,94 +152,33 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
 /**
   * @}
-  */ 
+  */
 
+/* Peripheral State and Error functions ***************************************/
 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
 /**
   * @}
-  */ 
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRC_Private_Types CRC Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRC_Private_Defines CRC Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Variables CRC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Constants CRC Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRC_Private_Macros CRC Private Macros
-  * @{
   */
 
 /**
   * @}
   */
 
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
-  * @{
-  */
-
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
-  * @{
-  */
-
 /**
   * @}
   */
 
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_CRC_H */
+#endif /* STM32F2xx_HAL_CRC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h
index 6ad71357..8d09e5c4 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */ 
@@ -40,10 +22,11 @@
 #define __STM32F2xx_HAL_CRYP_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-#if defined(STM32F215xx) || defined(STM32F217xx)
+#if defined(CRYP)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
@@ -51,7 +34,8 @@
   * @{
   */
 
-/** @addtogroup CRYP
+/** @defgroup CRYP CRYP
+  * @brief CRYP HAL module driver.
   * @{
   */
 
@@ -61,281 +45,315 @@
   * @{
   */
 
-/** @defgroup CRYP_Exported_Types_Group1 CRYP Configuration Structure definition
-  * @{
+/**
+  * @brief CRYP Init Structure definition
   */
 
 typedef struct
 {
-  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                             This parameter can be a value of @ref CRYP CRYP_Data_Type */
+  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                                        This parameter can be a value of @ref CRYP_Data_Type */
+  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+                                            This parameter can be a value of @ref CRYP_Key_Size */
+  uint32_t* pKey;                      /*!< The key used for encryption/decryption */
+  uint32_t* pInitVect;                 /*!< The initialization vector used also as initialization
+                                         counter in CTR mode */
+  uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC*/
+ 
+  uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+}CRYP_ConfigTypeDef;
+
+
+/**
+  * @brief  CRYP State Structure definition
+  */
+
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02U  /*!< CRYP BUSY, internal processing is ongoing  */
+}HAL_CRYP_STATETypeDef;
+
+
+/**
+  * @brief  CRYP handle Structure definition
+  */
+
+typedef struct __CRYP_HandleTypeDef
+{
+
+      CRYP_TypeDef                      *Instance;            /*!< CRYP registers base address */
+
+      CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
+
+      uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+      uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+      
+      __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
 
-  uint32_t KeySize;     /*!< Used only in AES mode only : 128, 192 or 256 bit key length. 
-                             This parameter can be a value of @ref CRYP CRYP_Key_Size */
+      __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
 
-  uint8_t* pKey;        /*!< The key used for encryption/decryption */
+      uint16_t                          Size;           /*!< length of input data in word */
 
-  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
-                             counter in CTR mode */
+      uint32_t                          Phase;            /*!< CRYP peripheral phase */
 
-  uint8_t IVSize;       /*!< The size of initialization vector. 
-                             This parameter (called nonce size in CCM) is used only 
-                             in AES-128/192/256 encryption/decryption CCM mode */
+      DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
 
-  uint8_t TagSize;      /*!< The size of returned authentication TAG. 
-                             This parameter is used only in AES-128/192/256 
-                             encryption/decryption CCM mode */
+      DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
 
-  uint8_t* Header;      /*!< The header used in GCM and CCM modes */
+      HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
 
-  uint32_t HeaderSize;  /*!< The size of header buffer in bytes */
+      __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
 
-  uint8_t* pScratch;    /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
-                             This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
-}CRYP_InitTypeDef;
+      __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
 
-/** 
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+ void (*InCpltCallback)    (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback  */
+ void (*OutCpltCallback)   (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
+ void (*ErrorCallback)     (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
+
+ void (* MspInitCallback)  (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback  */
+ void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback  */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+}CRYP_HandleTypeDef;
+
+
+/**
   * @}
   */
 
-/** @defgroup CRYP_Exported_Types_Group2 CRYP State structures definition
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
+  * @brief  HAL CRYP Callback ID enumeration definition
   * @{
   */
-    
-
 typedef enum
 {
-  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
-  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
-  HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */
-}HAL_CRYP_STATETypeDef;
+  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x01U,    /*!< CRYP Input FIFO transfer completed callback ID */
+  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x02U,    /*!< CRYP Output FIFO transfer completed callback ID */
+  HAL_CRYP_ERROR_CB_ID             = 0x03U,    /*!< CRYP Error callback ID           */
 
-/** 
+  HAL_CRYP_MSPINIT_CB_ID        = 0x04U,    /*!< CRYP MspInit callback ID         */
+  HAL_CRYP_MSPDEINIT_CB_ID      = 0x05U     /*!< CRYP MspDeInit callback ID       */
+
+}HAL_CRYP_CallbackIDTypeDef;
+/**
   * @}
   */
-  
-/** @defgroup CRYP_Exported_Types_Group3 CRYP phase structures definition
+
+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
+  * @brief  HAL CRYP Callback pointer definition
   * @{
   */
-    
 
-typedef enum
-{
-  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
-  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
-  HAL_CRYP_PHASE_FINAL             = 0x03     /*!< CRYP peripheral is in final phase
-                                                   This is relevant only with CCM and GCM modes */
-}HAL_PhaseTypeDef;
+typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp);   /*!< pointer to a common CRYP callback function */
 
-/** 
+/**
   * @}
   */
-  
-/** @defgroup CRYP_Exported_Types_Group4 CRYP handle Structure definition
-  * @{
-  */
-  
-typedef struct
-{
-      CRYP_TypeDef             *Instance;        /*!< CRYP registers base address */
-
-      CRYP_InitTypeDef         Init;             /*!< CRYP required parameters */
 
-      uint8_t                  *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 
-      uint8_t                  *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
 
-      __IO uint16_t            CrypInCount;      /*!< Counter of input data */
+/** @defgroup CRYP_Error_Definition   CRYP Error Definition
+  * @{
+  */
+#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
+#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
+#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
+#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
+#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 
-      __IO uint16_t            CrypOutCount;     /*!< Counter of outputted data */
+/**
+  * @}
+  */
 
-      HAL_StatusTypeDef        Status;           /*!< CRYP peripheral status */
 
-      HAL_PhaseTypeDef         Phase;            /*!< CRYP peripheral phase */
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+  * @{
+  */
 
-      DMA_HandleTypeDef        *hdmain;          /*!< CRYP In DMA handle parameters */
+#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is word */
 
-      DMA_HandleTypeDef        *hdmaout;         /*!< CRYP Out DMA handle parameters */
+/**
+  * @}
+  */
 
-      HAL_LockTypeDef          Lock;             /*!< CRYP locking object */
+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
+  * @{
+  */
 
-   __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
-}CRYP_HandleTypeDef;
+#define CRYP_DES_ECB     CRYP_CR_ALGOMODE_DES_ECB
+#define CRYP_DES_CBC     CRYP_CR_ALGOMODE_DES_CBC
+#define CRYP_TDES_ECB    CRYP_CR_ALGOMODE_TDES_ECB
+#define CRYP_TDES_CBC    CRYP_CR_ALGOMODE_TDES_CBC
+#define CRYP_AES_ECB     CRYP_CR_ALGOMODE_AES_ECB
+#define CRYP_AES_CBC     CRYP_CR_ALGOMODE_AES_CBC
+#define CRYP_AES_CTR     CRYP_CR_ALGOMODE_AES_CTR
 
-/** 
+/**
   * @}
   */
 
-/** 
-  * @}
-  */
-    
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+/** @defgroup CRYP_Key_Size CRYP Key Size
   * @{
   */
 
-/** @defgroup CRYP_Exported_Constants_Group1 CRYP CRYP_Key_Size
-  * @{
-  */
-#define CRYP_KEYSIZE_128B         ((uint32_t)0x00000000)
+#define CRYP_KEYSIZE_128B         0x00000000U
 #define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0
 #define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1
-/**                                
+
+/**
   * @}
   */
 
-/** @defgroup CRYP_Exported_Constants_Group2 CRYP CRYP_Data_Type
+/** @defgroup CRYP_Data_Type CRYP Data Type
   * @{
   */
-#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
+
+#define CRYP_DATATYPE_32B         0x00000000U
 #define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
 #define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
 #define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
-/**                                
-  * @}
-  */
 
-/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
-  * @{
-  */
-#define CRYP_CR_ALGOMODE_DIRECTION         ((uint32_t)0x0008003C)
-#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT  ((uint32_t)0x00000000)
-#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT  ((uint32_t)0x00000004)
-#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT  ((uint32_t)0x00000008)
-#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT  ((uint32_t)0x0000000C)
-#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT   ((uint32_t)0x00000010)
-#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT   ((uint32_t)0x00000014)
-#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT   ((uint32_t)0x00000018)
-#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT   ((uint32_t)0x0000001C)
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT   ((uint32_t)0x00000020)
-#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT   ((uint32_t)0x00000024)
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT   ((uint32_t)0x00000028)
-#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT   ((uint32_t)0x0000002C)
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT   ((uint32_t)0x00000030)
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT   ((uint32_t)0x00000034)
 /**
   * @}
   */
-  
-/** @defgroup CRYP_Exported_Constants_Group4 CRYP CRYP_Interrupt
+
+/** @defgroup CRYP_Interrupt  CRYP Interrupt
   * @{
   */
-#define CRYP_IT_INI               ((uint32_t)CRYP_IMSCR_INIM)   /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI              ((uint32_t)CRYP_IMSCR_OUTIM)  /*!< Output FIFO Interrupt */
+
+#define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< Input FIFO Interrupt */
+#define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< Output FIFO Interrupt */
+
 /**
   * @}
   */
 
-/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
+/** @defgroup CRYP_Flags CRYP Flags
   * @{
   */
-#define CRYP_FLAG_BUSY   ((uint32_t)0x00000010)  /*!< The CRYP core is currently 
-                                                     processing a block of data 
-                                                     or a key preparation (for 
-                                                     AES decryption). */
-#define CRYP_FLAG_IFEM   ((uint32_t)0x00000001)  /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF   ((uint32_t)0x00000002)  /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE   ((uint32_t)0x00000004)  /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU   ((uint32_t)0x00000008)  /*!< Output FIFO is Full */
-#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002)  /*!< Output FIFO service raw 
-                                                      interrupt status */
-#define CRYP_FLAG_INRIS  ((uint32_t)0x01000001)  /*!< Input FIFO service raw 
-                                                      interrupt status */
+
+/* Flags in the SR register */
+#define CRYP_FLAG_IFEM    CRYP_SR_IFEM  /*!< Input FIFO is empty */
+#define CRYP_FLAG_IFNF    CRYP_SR_IFNF  /*!< Input FIFO is not Full */
+#define CRYP_FLAG_OFNE    CRYP_SR_OFNE  /*!< Output FIFO is not empty */
+#define CRYP_FLAG_OFFU    CRYP_SR_OFFU  /*!< Output FIFO is Full */
+#define CRYP_FLAG_BUSY    CRYP_SR_BUSY  /*!< The CRYP core is currently processing a block of data
+                                             or a key preparation (for AES decryption). */
+/* Flags in the RISR register */
+#define CRYP_FLAG_OUTRIS  0x01000002U  /*!< Output FIFO service raw interrupt status */
+#define CRYP_FLAG_INRIS   0x01000001U  /*!< Input FIFO service raw interrupt status*/
+
 /**
   * @}
   */
 
+
 /**
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup CRYP_Exported_Macros CRYP Exported Macros
   * @{
   */
-  
+
 /** @brief Reset CRYP handle state
-  * @param  __HANDLE__: specifies the CRYP handle.
+  * @param  __HANDLE__ specifies the CRYP handle.
   * @retval None
   */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                     }while(0)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enable/Disable the CRYP peripheral.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @retval None
   */
+
 #define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)
 #define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)
 
-/**
-  * @brief  Flush the data FIFO.
-  * @param  __HANDLE__: specifies the CRYP handle.
-  * @retval None
-  */
-#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
-
-/**
-  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
-  * @param  __HANDLE__: specifies the CRYP handle.
-  * @param  MODE: The algorithm mode.
-  * @retval None
-  */
-#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE)  ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
-
-/** @brief  Check whether the specified CRYP flag is set or not.
-  * @param  __HANDLE__: specifies the CRYP handle.
+/** @brief  Check whether the specified CRYP status flag is set or not.
   * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data 
-  *                                 or a key preparation (for AES decryption). 
+  *         This parameter can be one of the following values for CRYP:
+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+  *                                 or a key preparation (for AES decryption).
   *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
   *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
   *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
   *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
   *            @arg CRYP_FLAG_OFFU: Output FIFO is full
   *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @retval The state of __FLAG__ (TRUE or FALSE).
   */
+#define CRYP_FLAG_MASK  0x0000001FU
 
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
                                                  ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
 
 /** @brief  Check whether the specified CRYP interrupt is set or not.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: specifies the interrupt to check.
-  *         This parameter can be one of the following values:
-  *            @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
-  *            @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  *         This parameter can be one of the following values for CRYP:
+  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
+  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
   */
+
 #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Enable the CRYP interrupt.
   * @param  __HANDLE__: specifies the CRYP handle.
   * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values for CRYP:
+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
   * @retval None
   */
+
 #define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the CRYP interrupt.
   * @param  __HANDLE__: specifies the CRYP handle.
-  * @param  __INTERRUPT__: CRYP interrupt.
+  * @param  __INTERRUPT__: CRYP Interrupt.
+  *         This parameter can be one of the following values for CRYP:
+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
   * @retval None
   */
+
 #define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
 
 /**
   * @}
-  */ 
-  
-
-
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
@@ -344,170 +362,126 @@ typedef struct
 
 /** @addtogroup CRYP_Exported_Functions_Group1
   * @{
-  */    
+  */
 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup CRYP_Exported_Functions_Group2
   * @{
-  */  
-/* AES encryption/decryption using polling  ***********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt  *********************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA  ***************************************/
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
-  * @}
-  */ 
+  */
 
-/** @addtogroup CRYP_Exported_Functions_Group3
-  * @{
-  */  
-/* DES encryption/decryption using polling  ***********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-
-/* DES encryption/decryption using interrupt  *********************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* DES encryption/decryption using DMA  ***************************************/
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/**
-  * @}
-  */ 
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
 
-/** @addtogroup CRYP_Exported_Functions_Group4
-  * @{
-  */  
-/* TDES encryption/decryption using polling  **********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* TDES encryption/decryption using interrupt  ********************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* TDES encryption/decryption using DMA  **************************************/
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
 /**
   * @}
-  */ 
+  */
+
 
-/** @addtogroup CRYP_Exported_Functions_Group5
+/** @addtogroup CRYP_Exported_Functions_Group3
   * @{
-  */  
+  */
+/* Interrupt Handler functions  **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
 void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup CRYP_Exported_Functions_Group6
-  * @{
-  */  
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup CRYP_Exported_Functions_Group7
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros   CRYP Private Macros
   * @{
-  */  
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
   */
 
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Types CRYP Private Types
+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
   * @{
   */
 
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB)   || \
+                                   ((ALGORITHM)  == CRYP_DES_CBC)   || \
+                                   ((ALGORITHM)  == CRYP_TDES_ECB)  || \
+                                   ((ALGORITHM)  == CRYP_TDES_CBC)  || \
+                                   ((ALGORITHM)  == CRYP_AES_ECB)   || \
+                                   ((ALGORITHM)  == CRYP_AES_CBC)   || \
+                                   ((ALGORITHM)  == CRYP_AES_CTR))
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
+                                 ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
+                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \
+                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
+                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \
+                                   ((DATATYPE) == CRYP_DATATYPE_1B))
+
 /**
   * @}
-  */ 
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
-  * @{
   */
 
 /**
   * @}
-  */ 
+  */
+
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup CRYP_Private_Constants CRYP Private Constants
   * @{
   */
-#define CRYP_FLAG_MASK  ((uint32_t)0x0000001F)
+
 /**
   * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
+  */
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
   * @{
   */
 
-#define IS_CRYP_KEYSIZE(__KEYSIZE__)  (((__KEYSIZE__) == CRYP_KEYSIZE_128B)  || \
-                                       ((__KEYSIZE__) == CRYP_KEYSIZE_192B)  || \
-                                       ((__KEYSIZE__) == CRYP_KEYSIZE_256B))
-
+/**
+  * @}
+  */
 
-#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
-                                        ((__DATATYPE__) == CRYP_DATATYPE_16B) || \
-                                        ((__DATATYPE__) == CRYP_DATATYPE_8B)  || \
-                                        ((__DATATYPE__) == CRYP_DATATYPE_1B))  
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+  * @{
+  */
 
+/**
+  * @}
+  */
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
+  * @{
+  */
 
- /**
+/**
   * @}
-  */ 
-  
+  */
+
 /* Private functions ---------------------------------------------------------*/
 /** @defgroup CRYP_Private_Functions CRYP Private Functions
   * @{
@@ -516,17 +490,18 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
 /**
   * @}
   */
-     
-#endif /* STM32F215xx || STM32F217xx */
+
 
 /**
   * @}
-  */ 
+  */
+
 
+#endif /* CRYP */
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h
index e4cc175e..0d2f5461 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h
@@ -2,79 +2,69 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DAC_H
-#define __STM32F2xx_HAL_DAC_H
+#ifndef STM32F2xx_HAL_DAC_H
+#define STM32F2xx_HAL_DAC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_hal_def.h"
+
+#if defined(DAC)
+
 /** @addtogroup DAC
   * @{
   */
 
 /* Exported types ------------------------------------------------------------*/
+
 /** @defgroup DAC_Exported_Types DAC Exported Types
   * @{
   */
 
-/** 
-  * @brief HAL State structures definition
+/**
+  * @brief  HAL State structures definition
   */
 typedef enum
 {
-  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief DAC handle Structure definition
+  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
+
+} HAL_DAC_StateTypeDef;
+
+/**
+  * @brief  DAC handle Structure definition
   */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
 typedef struct
+#endif
 {
   DAC_TypeDef                 *Instance;     /*!< Register base address             */
 
@@ -88,24 +78,67 @@ typedef struct
 
   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
 
-}DAC_HandleTypeDef;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
+
+  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
+  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
-/** 
-  * @brief DAC Configuration regular Channel structure definition
+} DAC_HandleTypeDef;
+
+
+/**
+  * @brief   DAC Configuration regular Channel structure definition
   */
 typedef struct
 {
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DAC_trigger_selection */
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+
+} DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DAC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
+  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
+  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
+  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
+  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
+  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
+  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
+  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
+  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
+  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
+  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
+} HAL_DAC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DAC Callback pointer definition
+  */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-}DAC_ChannelConfTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup DAC_Exported_Constants DAC Exported Constants
   * @{
   */
@@ -113,75 +146,82 @@ typedef struct
 /** @defgroup DAC_Error_Code DAC Error Code
   * @{
   */
-#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup DAC_trigger_selection DAC Trigger Selection
+/** @defgroup DAC_trigger_selection DAC trigger selection
   * @{
   */
+#define DAC_TRIGGER_NONE                0x00000000U                                                      /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO             (DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO             (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO             (                                                   DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO             (                                  DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE            (DAC_CR_TSEL1                                     | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
 
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
 /**
   * @}
   */
 
-/** @defgroup DAC_output_buffer  DAC Output Buffer
+/** @defgroup DAC_output_buffer DAC output buffer
   * @{
   */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
+#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_CR_BOFF1)
+
 /**
   * @}
   */
 
-/** @defgroup DAC_Channel_selection DAC Channel Selection
+/** @defgroup DAC_Channel_selection DAC Channel selection
   * @{
   */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+#define DAC_CHANNEL_1                      0x00000000U
+#define DAC_CHANNEL_2                      0x00000010U
 /**
   * @}
   */
 
-/** @defgroup DAC_data_alignment DAC Data Alignment
+/** @defgroup DAC_data_alignment DAC data alignment
   * @{
   */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
+#define DAC_ALIGN_12B_R                    0x00000000U
+#define DAC_ALIGN_12B_L                    0x00000004U
+#define DAC_ALIGN_8B_R                     0x00000008U
+
 /**
   * @}
   */
 
-/** @defgroup DAC_flags_definition DAC Flags Definition
+/** @defgroup DAC_flags_definition DAC flags definition
   * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
+  */
+#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
+
 /**
   * @}
   */
 
-/** @defgroup DAC_IT_definition DAC IT Definition
+/** @defgroup DAC_IT_definition  DAC IT definition
   * @{
-  */ 
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
+  */
+#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
+
 /**
   * @}
   */
@@ -191,47 +231,82 @@ typedef struct
   */
 
 /* Exported macro ------------------------------------------------------------*/
+
 /** @defgroup DAC_Exported_Macros DAC Exported Macros
   * @{
   */
 
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
+/** @brief Reset DAC handle state.
+  * @param  __HANDLE__ specifies the DAC handle.
   * @retval None
   */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
+                                                     } while(0)
+#else
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/** @brief Enable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __DAC_Channel__ specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Disable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __DAC_Channel__ specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Set DHR12R1 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
 
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
+/** @brief  Set DHR12R2 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
 
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
+/** @brief  Set DHR12RD alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
 
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+/** @brief Enable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
   * @retval None
   */
 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
 
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+/** @brief Disable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
   * @retval None
   */
 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
 
-/** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
-  * @param __HANDLE__: DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__ DAC handle
+  * @param __INTERRUPT__ DAC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -240,150 +315,134 @@ typedef struct
 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to get.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
   * @retval None
   */
 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
-  *            @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
   * @retval None
   */
 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
 /**
   * @}
   */
 
-/* Include DAC HAL Extension module */
-#include "stm32f2xx_hal_dac_ex.h"   
+/* Private macro -------------------------------------------------------------*/
 
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DAC_Exported_Functions
+/** @defgroup DAC_Private_Macros DAC Private Macros
   * @{
   */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                 ((CHANNEL) == DAC_CHANNEL_2))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
 
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
 /**
   * @}
   */
 
-/** @addtogroup DAC_Exported_Functions_Group2
+/* Include DAC HAL Extended module */
+#include "stm32f2xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
   * @{
   */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/**
-  * @}
-  */
 
-/** @addtogroup DAC_Exported_Functions_Group3
+/** @addtogroup DAC_Exported_Functions_Group1
   * @{
   */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
 /**
   * @}
   */
 
-/** @addtogroup DAC_Exported_Functions_Group4
+/** @addtogroup DAC_Exported_Functions_Group2
   * @{
   */
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
 
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-/**
-  * @}
-  */
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                               pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_Private_Constants DAC Private Constants
+
+/** @addtogroup DAC_Exported_Functions_Group3
   * @{
   */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
 
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
 /**
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_Private_Macros DAC Private Macros
+/** @addtogroup DAC_Exported_Functions_Group4
   * @{
   */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-/** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
-
-/** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
 
-/** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
-  * @retval None
+/**
+  * @}
   */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
 
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
 /** @defgroup DAC_Private_Functions DAC Private Functions
   * @{
   */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
@@ -392,14 +451,18 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
   * @}
   */
 
+#endif /* DAC */
+
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /*__STM32F2xx_HAL_DAC_H */
+
+#endif /*STM32F2xx_HAL_DAC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h
index dbbad816..08c2adcd 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h
@@ -1,119 +1,83 @@
 /**
   ******************************************************************************
-  * @file    stm32f2xx_hal_dac.h
+  * @file    stm32f2xx_hal_dac_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   Header file of DAC HAL Extension module.
+  * @brief   Header file of DAC HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DAC_EX_H
-#define __STM32F2xx_HAL_DAC_EX_H
+#ifndef STM32F2xx_HAL_DAC_EX_H
+#define STM32F2xx_HAL_DAC_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_hal_def.h"
+
+#if defined(DAC)
+
 /** @addtogroup DACEx
   * @{
   */
 
 /* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Constants DAC Exported Constants
-  * @{
-  */
 
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
 /**
-  * @}
+  * @brief  HAL State structures definition
   */
 
-/**
-  * @}
-  */
+/* Exported constants --------------------------------------------------------*/
 
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DACEx_Exported_Functions
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
   * @{
   */
 
-/** @addtogroup DACEx_Exported_Functions_Group1
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
   * @{
   */
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+#define DAC_LFSRUNMASK_BIT0                0x00000000U                                                         /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000U                                                         /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
 
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
 /**
   * @}
   */
@@ -121,21 +85,26 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
 /**
   * @}
   */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Constants DAC Private Constants
-  * @{
-  */
 
-/**
-  * @}
-  */
+/* Exported macro ------------------------------------------------------------*/
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DACEx_Private_Macros DAC Private Macros
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
   * @{
   */
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+
 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -160,18 +129,52 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
 
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DAC Private Functions
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Private_Functions
   * @{
   */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
 /**
   * @}
   */
@@ -183,11 +186,17 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
-  
+
+#endif /* DAC */
+
+/**
+  * @}
+  */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /*__STM32F2xx_HAL_DAC_EX_H */
+#endif /*STM32F2xx_HAL_DAC_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h
index 2adce5bf..b6ab036e 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h
@@ -2,51 +2,33 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dcmi.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of DCMI HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DCMI_H
-#define __STM32F2xx_HAL_DCMI_H
+#ifndef STM32F2xx_HAL_DCMI_H
+#define STM32F2xx_HAL_DCMI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-#if defined(STM32F207xx) || defined(STM32F217xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
+#if defined (DCMI)
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -55,35 +37,49 @@
 /** @addtogroup DCMI DCMI
   * @brief DCMI HAL module driver
   * @{
-  */  
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Types DCMI Exported Types
   * @{
   */
-/** 
-  * @brief DCMI Error source
+/**
+  * @brief  HAL DCMI State structures definition
   */
 typedef enum
-{ 
-  DCMI_ERROR_SYNC = 1,     /*!< Synchronisation error */
-  DCMI_OVERRUN   = 2,      /*!< DCMI Overrun */
-}DCMI_ErrorTypeDef;
+{
+  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */
+  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */
+  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */
+  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
+} HAL_DCMI_StateTypeDef;
 
-/** 
-  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
-  */ 
+/**
+  * @brief   DCMIEx Embedded Synchronisation CODE Init structure definition
+  */
 typedef struct
 {
   uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
-}DCMI_CodesInitTypeDef;
+} DCMI_CodesInitTypeDef;
 
-/** 
+/**
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+} DCMI_SyncUnmaskTypeDef;
+/**
   * @brief   DCMI Init structure definition
-  */ 
+  */
 typedef struct
 {
   uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.
@@ -104,29 +100,17 @@ typedef struct
   uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
                                              This parameter can be a value of @ref DCMI_Extended_Data_Mode   */
 
-  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the frame start delimiter.                */
+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the
+                                             line/frame end delimiter */
 
-  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.                                
+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.
                                              This parameter can be a value of @ref DCMI_MODE_JPEG            */
+} DCMI_InitTypeDef;
 
-}DCMI_InitTypeDef;
-
-/** 
-  * @brief  HAL DCMI State structures definition
-  */ 
-typedef enum
-{
-  HAL_DCMI_STATE_RESET             = 0x00,  /*!< DCMI not yet initialized or disabled  */
-  HAL_DCMI_STATE_READY             = 0x01,  /*!< DCMI initialized and ready for use    */
-  HAL_DCMI_STATE_BUSY              = 0x02,  /*!< DCMI internal processing is ongoing   */
-  HAL_DCMI_STATE_TIMEOUT           = 0x03,  /*!< DCMI timeout state                    */
-  HAL_DCMI_STATE_ERROR             = 0x04   /*!< DCMI error state                      */
-}HAL_DCMI_StateTypeDef;
-
-/** 
+/**
   * @brief  DCMI handle Structure definition
   */
-typedef struct
+typedef struct __DCMI_HandleTypeDef
 {
   DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */
 
@@ -147,13 +131,37 @@ typedef struct
   DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */
 
   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Frame Event Callback */
+  void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Vsync Event Callback */
+  void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Line Event Callback  */
+  void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi);            /*!< DCMI Error Callback       */
+  void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);          /*!< DCMI Msp Init callback    */
+  void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Msp DeInit callback  */
+#endif  /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+} DCMI_HandleTypeDef;
+
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+typedef enum
+{
+  HAL_DCMI_FRAME_EVENT_CB_ID    = 0x00U,    /*!< DCMI Frame Event Callback ID */
+  HAL_DCMI_VSYNC_EVENT_CB_ID    = 0x01U,    /*!< DCMI Vsync Event Callback ID */
+  HAL_DCMI_LINE_EVENT_CB_ID     = 0x02U,    /*!< DCMI Line Event Callback ID  */
+  HAL_DCMI_ERROR_CB_ID          = 0x03U,    /*!< DCMI Error Callback ID       */
+  HAL_DCMI_MSPINIT_CB_ID        = 0x04U,    /*!< DCMI MspInit callback ID     */
+  HAL_DCMI_MSPDEINIT_CB_ID      = 0x05U     /*!< DCMI MspDeInit callback ID   */
+
+} HAL_DCMI_CallbackIDTypeDef;
+
+typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
 
-}DCMI_HandleTypeDef;
 /**
   * @}
   */
-
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
   * @{
   */
@@ -161,18 +169,22 @@ typedef struct
 /** @defgroup DCMI_Error_Code DCMI Error Code
   * @{
   */
-#define HAL_DCMI_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
-#define HAL_DCMI_ERROR_OVF       ((uint32_t)0x00000001)    /*!< Overflow error        */
-#define HAL_DCMI_ERROR_SYNC      ((uint32_t)0x00000002)    /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
+#define HAL_DCMI_ERROR_NONE             ((uint32_t)0x00000000U)  /*!< No error              */
+#define HAL_DCMI_ERROR_OVR              ((uint32_t)0x00000001U)  /*!< Overrun error         */
+#define HAL_DCMI_ERROR_SYNC             ((uint32_t)0x00000002U)  /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT          ((uint32_t)0x00000020U)  /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA              ((uint32_t)0x00000040U)  /*!< DMA error             */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)  /*!< Invalid callback error */
+#endif
 /**
   * @}
   */
 
 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
   * @{
-  */ 
-#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000)  /*!< The received data are transferred continuously 
+  */
+#define DCMI_MODE_CONTINUOUS           ((uint32_t)0x00000000U)  /*!< The received data are transferred continuously 
                                                                     into the destination memory through the DMA             */
 #define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of 
                                                                     frame and then transfers a single frame through the DMA */
@@ -182,8 +194,8 @@ typedef struct
 
 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
   * @{
-  */ 
-#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000)   /*!< Hardware synchronization data capture (frame/line start/stop)
+  */
+#define DCMI_SYNCHRO_HARDWARE        ((uint32_t)0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)
                                                                    is synchronized with the HSYNC/VSYNC signals                  */
 #define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with 
                                                                    synchronization codes embedded in the data flow               */
@@ -195,17 +207,17 @@ typedef struct
 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
   * @{
   */
-#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000)      /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPOLARITY_FALLING    ((uint32_t)0x00000000U)      /*!< Pixel clock active on Falling edge */
 #define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */
 
 /**
   * @}
   */
- 
+
 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
   * @{
   */
-#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Vertical synchronization active Low  */
+#define DCMI_VSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Vertical synchronization active Low  */
 #define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */
 
 /**
@@ -214,8 +226,8 @@ typedef struct
 
 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
   * @{
-  */ 
-#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000)     /*!< Horizontal synchronization active Low  */
+  */
+#define DCMI_HSPOLARITY_LOW     ((uint32_t)0x00000000U)     /*!< Horizontal synchronization active Low  */
 #define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */
 
 /**
@@ -225,7 +237,7 @@ typedef struct
 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
   * @{
   */
-#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000)    /*!< Mode JPEG Disabled  */
+#define DCMI_JPEG_DISABLE   ((uint32_t)0x00000000U)    /*!< Mode JPEG Disabled  */
 #define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */
 
 /**
@@ -235,7 +247,7 @@ typedef struct
 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
   * @{
   */
-#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000)      /*!< All frames are captured        */
+#define DCMI_CR_ALL_FRAME            ((uint32_t)0x00000000U)      /*!< All frames are captured        */
 #define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */
 #define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */
 
@@ -246,7 +258,7 @@ typedef struct
 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
   * @{
   */
-#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000)                       /*!< Interface captures 8-bit data on every pixel clock  */
+#define DCMI_EXTEND_DATA_8B     ((uint32_t)0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */
 #define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */
 #define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */
@@ -258,7 +270,7 @@ typedef struct
 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
   * @{
   */
-#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFF)  /*!< Window coordinate */
+#define DCMI_WINDOW_COORDINATE    ((uint32_t)0x3FFFU)  /*!< Window coordinate */
 
 /**
   * @}
@@ -266,8 +278,8 @@ typedef struct
 
 /** @defgroup DCMI_Window_Height DCMI Window Height
   * @{
-  */ 
-#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFF)  /*!< Window Height */
+  */
+#define DCMI_WINDOW_HEIGHT    ((uint32_t)0x1FFFU)  /*!< Window Height */
 
 /**
   * @}
@@ -276,11 +288,11 @@ typedef struct
 /** @defgroup DCMI_interrupt_sources  DCMI interrupt sources
   * @{
   */
-#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)
-#define DCMI_IT_OVF      ((uint32_t)DCMI_IER_OVF_IE)
-#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)
-#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)
-#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)
+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */
+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */
+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */
+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */
+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */
 /**
   * @}
   */
@@ -289,82 +301,94 @@ typedef struct
   * @{
   */
 
-/** 
+/**
   * @brief   DCMI SR register
-  */ 
-#define DCMI_FLAG_HSYNC     ((uint32_t)0x2001)
-#define DCMI_FLAG_VSYNC     ((uint32_t)0x2002)
-#define DCMI_FLAG_FNE       ((uint32_t)0x2004)
-/** 
-  * @brief   DCMI RISR register  
-  */ 
-#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RISR_FRAME_RIS)
-#define DCMI_FLAG_OVFRI      ((uint32_t)DCMI_RISR_OVF_RIS)
-#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RISR_ERR_RIS)
-#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RISR_VSYNC_RIS)
-#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RISR_LINE_RIS)
-/** 
-  * @brief   DCMI MISR register  
-  */ 
-#define DCMI_FLAG_FRAMEMI    ((uint32_t)0x1001)
-#define DCMI_FLAG_OVFMI      ((uint32_t)0x1002)
-#define DCMI_FLAG_ERRMI      ((uint32_t)0x1004)
-#define DCMI_FLAG_VSYNCMI    ((uint32_t)0x1008)
-#define DCMI_FLAG_LINEMI     ((uint32_t)0x1010)
+  */
+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */
+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */
+/**
+  * @brief   DCMI RIS register
+  */
+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */
+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */
+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */
+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */
+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */
+/**
+  * @brief   DCMI MIS register
+  */
+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */
+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */
+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */
+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */
+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
- 
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
   * @{
   */
-  
+
 /** @brief Reset DCMI handle state
-  * @param  __HANDLE__: specifies the DCMI handle.
+  * @param  __HANDLE__ specifies the DCMI handle.
   * @retval None
   */
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
+                                                     (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
+                                                     (__HANDLE__)->MspInitCallback = NULL;      \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                   } while(0)
 
 /**
   * @brief  Enable the DCMI.
-  * @param  __HANDLE__: DCMI handle
+  * @param  __HANDLE__ DCMI handle
   * @retval None
   */
 #define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
 
 /**
   * @brief  Disable the DCMI.
-  * @param  __HANDLE__: DCMI handle
+  * @param  __HANDLE__ DCMI handle
   * @retval None
   */
 #define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
 
 /* Interrupt & Flag management */
 /**
-  * @brief  Get the DCMI pending flags.
-  * @param  __HANDLE__: DCMI handle
-  * @param  __FLAG__: Get the specified flag.
-  *         This parameter can be any combination of the following values:
+  * @brief  Get the DCMI pending flag.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __FLAG__ Get the specified flag.
+  *         This parameter can be one of the following values (no combination allowed)
+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
+  *            @arg DCMI_FLAG_FNE: FIFO empty flag
   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
-  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
+  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask
   *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
   *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
   *            @arg DCMI_FLAG_LINERI: Line flag mask
+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
   * @retval The state of FLAG.
   */
 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
-((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
- (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
 
 /**
   * @brief  Clear the DCMI pending flags.
-  * @param  __HANDLE__: DCMI handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __FLAG__ specifies the flag to clear.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
   *            @arg DCMI_FLAG_OVFRI: Overflow flag mask
@@ -377,8 +401,8 @@ typedef struct
 
 /**
   * @brief  Enable the specified DCMI interrupts.
-  * @param  __HANDLE__:    DCMI handle
-  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  * @param  __HANDLE__    DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -391,8 +415,8 @@ typedef struct
 
 /**
   * @brief  Disable the specified DCMI interrupts.
-  * @param  __HANDLE__: DCMI handle
-  * @param  __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. 
+  * @param  __HANDLE__ DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
   *         This parameter can be any combination of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -405,8 +429,8 @@ typedef struct
 
 /**
   * @brief  Check whether the specified DCMI interrupt has occurred or not.
-  * @param  __HANDLE__: DCMI handle
-  * @param  __INTERRUPT__: specifies the DCMI interrupt source to check.
+  * @param  __HANDLE__ DCMI handle
+  * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
   *            @arg DCMI_IT_OVF: Overflow interrupt mask
@@ -420,32 +444,38 @@ typedef struct
 /**
   * @}
   */
-      
+
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup DCMI_Exported_Functions
+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
   * @{
   */
 
-/** @addtogroup DCMI_Exported_Functions_Group1 
+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
  * @{
  */
- 
 /* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
-void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
-void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
 /**
   * @}
   */
-  
-/** @addtogroup DCMI_Exported_Functions_Group2 
+
+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
  * @{
  */
- 
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
 void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
 void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
 void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
@@ -454,19 +484,21 @@ void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
 /**
   * @}
   */
-  
-/** @addtogroup DCMI_Exported_Functions_Group3 
+
+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
  * @{
  */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef     HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
-HAL_StatusTypeDef     HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef     HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
+
 /**
   * @}
   */
-  
-/** @addtogroup DCMI_Exported_Functions_Group4 
+
+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
  * @{
  */
 /* Peripheral State functions *************************************************/
@@ -482,38 +514,46 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/   
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DCMI_Private_Constants DCMI Private Constants
+  * @{
+  */
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /** @defgroup DCMI_Private_Macros DCMI Private Macros
   * @{
   */
 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
                                    ((MODE) == DCMI_MODE_SNAPSHOT))
-                                                                                                
+
 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
                               ((MODE) == DCMI_SYNCHRO_EMBEDDED))
-                              
+
 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
                                       ((POLARITY) == DCMI_PCKPOLARITY_RISING))
-                                      
+
 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
                                      ((POLARITY) == DCMI_VSPOLARITY_HIGH))
-                                     
+
 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
                                      ((POLARITY) == DCMI_HSPOLARITY_HIGH))
-                                     
+
 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
                                      ((JPEG_MODE) == DCMI_JPEG_ENABLE))
-                                     
+
 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \
                                     ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
                                     ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
-                                    
+
 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \
                                     ((DATA) == DCMI_EXTEND_DATA_10B) || \
                                     ((DATA) == DCMI_EXTEND_DATA_12B) || \
                                     ((DATA) == DCMI_EXTEND_DATA_14B))
-                                    
+
 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
 
 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
@@ -526,26 +566,23 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
   * @{
   */
-  
+
 /**
   * @}
   */
-      
-#endif /* STM32F207xx || STM32F217xx */
-
 
 /**
   * @}
   */
-    
 /**
   * @}
-  */ 
+  */
+#endif /* DCMI */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_DCMI_H */
+#endif /* STM32F2xx_HAL_DCMI_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h
index 8b64c5e1..d9af9845 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h
@@ -2,36 +2,18 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -47,7 +29,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx.h"
 #include "Legacy/stm32_hal_legacy.h"
-#include 
+#include 
 
 /* Exported types ------------------------------------------------------------*/
 
@@ -56,10 +38,10 @@
   */  
 typedef enum 
 {
-  HAL_OK       = 0x00,
-  HAL_ERROR    = 0x01,
-  HAL_BUSY     = 0x02,
-  HAL_TIMEOUT  = 0x03
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
 } HAL_StatusTypeDef;
 
 /** 
@@ -67,26 +49,27 @@ typedef enum
   */
 typedef enum 
 {
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01  
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U  
 } HAL_LockTypeDef;
 
 /* Exported macro ------------------------------------------------------------*/
-#define HAL_MAX_DELAY      0xFFFFFFFF
 
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
 
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)               \
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
                         do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
-                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \
-                          } while(0)
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0U)
 
-#define UNUSED(x) ((void)(x))
-							  
 /** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @param  __HANDLE__ specifies the Peripheral Handle.
   * @note  This macro can be used for the following purpose: 
   *          - When the Handle is declared as local variable; before passing it as parameter
   *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
@@ -100,11 +83,11 @@ typedef enum
   *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
   * @retval None
   */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
 
-#if (USE_RTOS == 1)
+#if (USE_RTOS == 1U)
   /* Reserved for future use */
-  #error " USE_RTOS should be 0 in the current HAL release "
+  #error "USE_RTOS should be 0 in the current HAL release"
 #else
   #define __HAL_LOCK(__HANDLE__)                                           \
                                 do{                                        \
@@ -116,15 +99,15 @@ typedef enum
                                     {                                      \
                                        (__HANDLE__)->Lock = HAL_LOCKED;    \
                                     }                                      \
-                                  }while (0)
+                                  }while (0U)
 
   #define __HAL_UNLOCK(__HANDLE__)                                          \
                                   do{                                       \
                                       (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0)
+                                    }while (0U)
 #endif /* USE_RTOS */
 
-#if  defined ( __GNUC__ )
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
   #ifndef __weak
     #define __weak   __attribute__((weak))
   #endif /* __weak */
@@ -133,11 +116,11 @@ typedef enum
   #endif /* __packed */
 #endif /* __GNUC__ */
 
-  
+
 /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
   #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
+    #define __ALIGN_END    __attribute__ ((aligned (4U)))
   #endif /* __ALIGN_END */
   #ifndef __ALIGN_BEGIN  
     #define __ALIGN_BEGIN
@@ -148,7 +131,7 @@ typedef enum
   #endif /* __ALIGN_END */
   #ifndef __ALIGN_BEGIN      
     #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)  
+      #define __ALIGN_BEGIN    __align(4U)
     #elif defined (__ICCARM__)    /* IAR Compiler */
       #define __ALIGN_BEGIN 
     #endif /* __CC_ARM */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h
index e8bf0999..5c3bc2dc 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_DMA_H
@@ -120,17 +102,12 @@ typedef struct
   */
 typedef enum
 {
-  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
-  HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
-  HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
-  HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
-  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
-  HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
 }HAL_DMA_StateTypeDef;
 
 /** 
@@ -138,10 +115,24 @@ typedef enum
   */
 typedef enum
 {
-  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
 }HAL_DMA_LevelCompleteTypeDef;
 
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
 /** 
   * @brief  DMA handle Structure definition
   */
@@ -155,21 +146,26 @@ typedef struct __DMA_HandleTypeDef
 
   __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 
-  void                       *Parent;                                                      /*!< Parent object state                    */  
+  void                       *Parent;                                                      /*!< Parent object state                    */ 
 
   void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 
   void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 
   void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
-
+  
+  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
+  
   void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
+  
+  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer Abort callback            */  
 
- __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                         */
-
+ __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                          */
+  
  uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
 
- uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */ 
+ uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */
+ 
 }DMA_HandleTypeDef;
 
 /**
@@ -187,11 +183,14 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA Error Code 
   * @{
   */ 
-#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
-#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
-#define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
-#define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
-#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
+#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
+#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
+#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
+#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
+#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
+#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
+#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */ 
+#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */     
 /**
   * @}
   */
@@ -200,14 +199,14 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA channel selection 
   * @{
   */ 
-#define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
+#define DMA_CHANNEL_0        0x00000000U  /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1        0x02000000U  /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2        0x04000000U  /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3        0x06000000U  /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4        0x08000000U  /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5        0x0A000000U  /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6        0x0C000000U  /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7        0x0E000000U  /*!< DMA Channel 7 */
 /**
   * @}
   */
@@ -216,19 +215,19 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA data transfer direction 
   * @{
   */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY         0x00000000U      /*!< Peripheral to memory direction */
 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
 /**
   * @}
-  */  
+  */
         
 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
   * @brief    DMA peripheral incremented mode 
   * @{
   */ 
 #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
+#define DMA_PINC_DISABLE       0x00000000U     /*!< Peripheral increment mode disable */
 /**
   * @}
   */ 
@@ -238,7 +237,7 @@ typedef struct __DMA_HandleTypeDef
   * @{
   */ 
 #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
+#define DMA_MINC_DISABLE        0x00000000U     /*!< Memory increment mode disable */
 /**
   * @}
   */
@@ -247,7 +246,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA peripheral data size 
   * @{
   */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_BYTE          0x00000000U        /*!< Peripheral data alignment: Byte     */
 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
 /**
@@ -258,7 +257,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA memory data size 
   * @{ 
   */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_BYTE          0x00000000U        /*!< Memory data alignment: Byte     */
 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
 /**
@@ -269,7 +268,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA mode 
   * @{
   */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_NORMAL         0x00000000U       /*!< Normal mode                  */
 #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
 #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
 /**
@@ -280,7 +279,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA priority levels 
   * @{
   */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
+#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level: Low       */
 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
@@ -292,7 +291,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA FIFO direct mode
   * @{
   */
-#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
+#define DMA_FIFOMODE_DISABLE        0x00000000U       /*!< FIFO mode disable */
 #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
 /**
   * @}
@@ -302,7 +301,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA FIFO level 
   * @{
   */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U       /*!< FIFO threshold 1 quart full configuration  */
 #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
 #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
@@ -314,7 +313,7 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA memory burst 
   * @{
   */ 
-#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)  
+#define DMA_MBURST_SINGLE       0x00000000U
 #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  
 #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  
 #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  
@@ -326,10 +325,10 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA peripheral burst 
   * @{
   */ 
-#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)  
-#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)  
-#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)  
-#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)  
+#define DMA_PBURST_SINGLE       0x00000000U
+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)
 /**
   * @}
   */
@@ -342,7 +341,7 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
 #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
 #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE                         ((uint32_t)0x00000080)
+#define DMA_IT_FE                         0x00000080U
 /**
   * @}
   */
@@ -351,26 +350,26 @@ typedef struct __DMA_HandleTypeDef
   * @brief    DMA flag definitions 
   * @{
   */ 
-#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
-#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
-#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
-#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
-#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
-#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
-#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
-#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
-#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
-#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
-#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
-#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
-#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
-#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
-#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
-#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
-#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
-#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
-#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
-#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
+#define DMA_FLAG_FEIF0_4                    0x00000001U
+#define DMA_FLAG_DMEIF0_4                   0x00000004U
+#define DMA_FLAG_TEIF0_4                    0x00000008U
+#define DMA_FLAG_HTIF0_4                    0x00000010U
+#define DMA_FLAG_TCIF0_4                    0x00000020U
+#define DMA_FLAG_FEIF1_5                    0x00000040U
+#define DMA_FLAG_DMEIF1_5                   0x00000100U
+#define DMA_FLAG_TEIF1_5                    0x00000200U
+#define DMA_FLAG_HTIF1_5                    0x00000400U
+#define DMA_FLAG_TCIF1_5                    0x00000800U
+#define DMA_FLAG_FEIF2_6                    0x00010000U
+#define DMA_FLAG_DMEIF2_6                   0x00040000U
+#define DMA_FLAG_TEIF2_6                    0x00080000U
+#define DMA_FLAG_HTIF2_6                    0x00100000U
+#define DMA_FLAG_TCIF2_6                    0x00200000U
+#define DMA_FLAG_FEIF3_7                    0x00400000U
+#define DMA_FLAG_DMEIF3_7                   0x01000000U
+#define DMA_FLAG_TEIF3_7                    0x02000000U
+#define DMA_FLAG_HTIF3_7                    0x04000000U
+#define DMA_FLAG_TCIF3_7                    0x08000000U
 /**
   * @}
   */
@@ -382,14 +381,14 @@ typedef struct __DMA_HandleTypeDef
 /* Exported macro ------------------------------------------------------------*/
 
 /** @brief Reset DMA handle state
-  * @param  __HANDLE__: specifies the DMA handle.
+  * @param  __HANDLE__ specifies the DMA handle.
   * @retval None
   */
 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 
 /**
   * @brief  Return the current DMA Stream FIFO filled level.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The FIFO filling state.
   *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
   *                                              and not empty.
@@ -403,14 +402,14 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Enable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
 
 /**
   * @brief  Disable the specified DMA Stream.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
@@ -419,7 +418,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -439,7 +438,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -459,7 +458,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -479,7 +478,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream FIFO error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified FIFO error flag index.
   */
 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
@@ -499,7 +498,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Return the current DMA Stream direct mode error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified direct mode error flag index.
   */
 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
@@ -519,8 +518,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Get the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -537,8 +536,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Clear the DMA Stream pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
   *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -555,8 +554,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Enable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *        This parameter can be any combination of the following values:
   *           @arg DMA_IT_TC: Transfer complete interrupt mask.
   *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -570,8 +569,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Disable the specified DMA Stream interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *         This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -585,8 +584,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg DMA_IT_TC: Transfer complete interrupt mask.
   *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -601,8 +600,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Writes the number of data units to be transferred on the DMA Stream.
-  * @param  __HANDLE__: DMA handle
-  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) 
+  * @param  __HANDLE__ DMA handle
+  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
   *          Number of data items depends only on the Peripheral data format.
   *            
   * @note   If Peripheral data format is Bytes: number of data units is equal 
@@ -620,7 +619,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   *   
   * @retval The number of remaining data units in the current DMA Stream transfer.
   */
@@ -654,8 +653,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
 /**
   * @}
   */ 
@@ -699,7 +703,7 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
 
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
 
 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
                                             ((STATE) == DMA_PINC_DISABLE))
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h
index 1f8a9689..e633c564 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -65,9 +47,8 @@
   */ 
 typedef enum
 {
-  MEMORY0      = 0x00,    /*!< Memory 0     */
-  MEMORY1      = 0x01,    /*!< Memory 1     */
-
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U     /*!< Memory 1     */
 }HAL_DMA_MemoryTypeDef;
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h
index 810f2d5f..4c2932f8 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h
@@ -2,63 +2,46 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_eth.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of ETH HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_ETH_H
 #define __STM32F2xx_HAL_ETH_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-#if defined(STM32F207xx) || defined(STM32F217xx)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
+#if defined (ETH)
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup ETH
   * @{
-  */ 
-  
+  */
+
 /** @defgroup ETH_Private_Macros ETH Private Macros
   * @{
   */
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
                                      ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
@@ -122,7 +105,7 @@
 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
 #define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
                                         ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
@@ -137,7 +120,7 @@
                                           ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
                                                 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
                                          ((ADDRESS) == ETH_MAC_ADDRESS1) || \
                                          ((ADDRESS) == ETH_MAC_ADDRESS2) || \
@@ -243,7 +226,7 @@
                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
                                          ((FLAG) == ETH_DMARXDESC_AFM) || \
                                          ((FLAG) == ETH_DMARXDESC_ES) || \
@@ -266,7 +249,7 @@
                                           ((BUFFER) == ETH_DMARXDESC_BUFFER2))
 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
                                    ((FLAG) == ETH_PMT_FLAG_MPR))
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
                                    ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
                                    ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
@@ -278,14 +261,14 @@
                                    ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
                                    ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
                                    ((FLAG) == ETH_DMA_FLAG_T))
-#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFD87) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFD87U) == 0x00U) && ((IT) != 0x00U))
 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
                                ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
                                ((IT) == ETH_MAC_IT_PMT))
 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
                                    ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
                                    ((FLAG) == ETH_MAC_FLAG_PMT))
-#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
                                ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
                                ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
@@ -297,8 +280,8 @@
                                ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
                                            ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
-#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
-                           ((IT) != 0x00))
+#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFF) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
+                           ((IT) != 0x00U))
 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
                                ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
                                ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
@@ -314,76 +297,76 @@
   * @{
   */
 /* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+#define ETH_REG_WRITE_DELAY 0x00000001U
 
 /* ETHERNET Errors */
-#define  ETH_SUCCESS            ((uint32_t)0)
-#define  ETH_ERROR              ((uint32_t)1)
+#define  ETH_SUCCESS            0U
+#define  ETH_ERROR              1U
 
 /* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         ((uint32_t)3)
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT         3U
 
 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16U
 
 /* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           ((uint32_t)16)
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16U
 
 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           ((uint32_t)16)
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16U
 
 /* ETHERNET DMA Rx descriptors Frame length Shift */
-#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            ((uint32_t)16)
+#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            16U
 
 /* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40)  /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44)  /* ETHERNET MAC address low offset */
+#define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + 0x40U)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + 0x44U)  /* ETHERNET MAC address low offset */
 
 /* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
+#define ETH_MACMIIAR_CR_MASK    0xFFFFFFE3U
 
 /* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
+#define ETH_MACCR_CLEAR_MASK    0xFF20810FU
 
 /* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+#define ETH_MACFCR_CLEAR_MASK   0x0000FF41U
 
 /* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+#define ETH_DMAOMR_CLEAR_MASK   0xF8DE3F23U
 
 /* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH      8
+#define ETH_WAKEUP_REGISTER_LENGTH      8U
 
 /* ETHERNET Missed frames counter Shift */
-#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
- /**
-  * @}
-  */
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U
+/**
+ * @}
+ */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup ETH_Exported_Types ETH Exported Types
   * @{
   */
 
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
-  HAL_ETH_STATE_RESET             = 0x00,    /*!< Peripheral not yet Initialized or disabled         */
-  HAL_ETH_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_ETH_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_ETH_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_ETH_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_ETH_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_ETH_STATE_BUSY_WR           = 0x42,    /*!< Write process is ongoing                           */
-  HAL_ETH_STATE_BUSY_RD           = 0x82,    /*!< Read process is ongoing                            */
-  HAL_ETH_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_ETH_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                       */
-}HAL_ETH_StateTypeDef;
-
-/** 
-  * @brief  ETH Init Structure definition  
+  HAL_ETH_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
+  HAL_ETH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_ETH_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_ETH_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing               */
+  HAL_ETH_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing                  */
+  HAL_ETH_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_ETH_STATE_BUSY_WR           = 0x42U,    /*!< Write process is ongoing                           */
+  HAL_ETH_STATE_BUSY_RD           = 0x82U,    /*!< Read process is ongoing                            */
+  HAL_ETH_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                      */
+  HAL_ETH_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
+} HAL_ETH_StateTypeDef;
+
+/**
+  * @brief  ETH Init Structure definition
   */
 
 typedef struct
@@ -398,34 +381,34 @@ typedef struct
 
   uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
-  
+
   uint16_t             PhyAddress;                /*!< Ethernet PHY address.
                                                            This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-  
+
   uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-  
+
   uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
                                                            This parameter can be a value of @ref ETH_Rx_Mode */
-  
-  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software. 
+
+  uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software.
                                                          This parameter can be a value of @ref ETH_Checksum_Mode */
-  
-  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface. 
+
+  uint32_t             MediaInterface    ;               /*!< Selects the media-independent interface or the reduced media-independent interface.
                                                          This parameter can be a value of @ref ETH_Media_Interface */
 
 } ETH_InitTypeDef;
 
 
- /** 
-  * @brief  ETH MAC Configuration Structure definition  
-  */
+/**
+ * @brief  ETH MAC Configuration Structure definition
+ */
 
 typedef struct
 {
   uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
                                                            When disabled, the MAC can receive up to 16384 bytes.
-                                                           This parameter can be a value of @ref ETH_Watchdog */  
+                                                           This parameter can be a value of @ref ETH_Watchdog */
 
   uint32_t             Jabber;                    /*!< Selects or not Jabber timer
                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
@@ -433,7 +416,7 @@ typedef struct
                                                            This parameter can be a value of @ref ETH_Jabber */
 
   uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
-                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
+                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */
 
   uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
                                                            This parameter can be a value of @ref ETH_Carrier_Sense */
@@ -441,70 +424,70 @@ typedef struct
   uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
                                                            in Half-Duplex mode.
-                                                           This parameter can be a value of @ref ETH_Receive_Own */  
+                                                           This parameter can be a value of @ref ETH_Receive_Own */
 
   uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
-                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
+                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */
 
   uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
-                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
+                                                           This parameter can be a value of @ref ETH_Checksum_Offload */
 
   uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
                                                            when a collision occurs (Half-Duplex mode).
                                                            This parameter can be a value of @ref ETH_Retry_Transmission */
 
   uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
-                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
+                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
 
   uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
                                                            This parameter can be a value of @ref ETH_Back_Off_Limit */
 
   uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
-                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
+                                                           This parameter can be a value of @ref ETH_Deferral_Check */
 
   uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
-                                                           This parameter can be a value of @ref ETH_Receive_All */   
+                                                           This parameter can be a value of @ref ETH_Receive_All */
 
-  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.                                                           
-                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
+  uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.
+                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */
 
-  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
-                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
+  uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */
 
   uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
                                                            This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
 
   uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
-                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
+                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */
 
   uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
                                                            This parameter can be a value of @ref ETH_Promiscuous_Mode */
 
   uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
-                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
+                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
 
   uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
-                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
+                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
 
   uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
 
   uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
-                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */    
+                                                           This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF  */
 
-  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 
+  uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
 
   uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
-                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
+                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
 
   uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
                                                            automatic retransmission of PAUSE Frame.
                                                            This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-                                                           
+
   uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
                                                            unicast address and unique multicast address).
-                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
+                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
 
   uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
                                                            disable its transmitter for a specified time (Pause Time)
@@ -512,34 +495,34 @@ typedef struct
 
   uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
                                                            or the MAC back-pressure operation (Half-Duplex mode)
-                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
+                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */
 
   uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
                                                            comparison and filtering.
-                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
+                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
 
   uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
 
 } ETH_MACInitTypeDef;
 
 
-/** 
-  * @brief  ETH DMA Configuration Structure definition  
+/**
+  * @brief  ETH DMA Configuration Structure definition
   */
 
 typedef struct
 {
- uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
-                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+  uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
 
   uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
-                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */
 
   uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
-                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */
 
   uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
-                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */
 
   uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
                                                              This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
@@ -563,95 +546,130 @@ typedef struct
 
   uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
                                                              This parameter can be a value of @ref ETH_Fixed_Burst */
-                       
+
   uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
-                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
 
   uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
                                                              This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-  
+
   uint32_t             EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format.
                                                              This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
 
   uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
-                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */                                                             
+                                                             This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
 
   uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
-                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */
 } ETH_DMAInitTypeDef;
 
 
-/** 
+/**
   * @brief  ETH DMA Descriptors data structure definition
-  */ 
+  */
 
-typedef struct  
+typedef struct
 {
   __IO uint32_t   Status;           /*!< Status */
-  
+
   uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
-  
+
   uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
-  
+
   uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
-  
+
   /*!< Enhanced ETHERNET DMA PTP Descriptors */
   uint32_t   ExtendedStatus;        /*!< Extended status for PTP receive descriptor */
-  
+
   uint32_t   Reserved1;             /*!< Reserved */
-  
+
   uint32_t   TimeStampLow;          /*!< Time Stamp Low value for transmit and receive */
-  
+
   uint32_t   TimeStampHigh;         /*!< Time Stamp High value for transmit and receive */
 
 } ETH_DMADescTypeDef;
 
 
-/** 
+/**
   * @brief  Received Frame Informations structure definition
-  */ 
-typedef struct  
+  */
+typedef struct
 {
   ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
-  
+
   ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
-  
+
   uint32_t  SegCount;                    /*!< Segment count */
-  
+
   uint32_t length;                       /*!< Frame length */
-  
+
   uint32_t buffer;                       /*!< Frame buffer */
 
 } ETH_DMARxFrameInfos;
 
 
-/** 
-  * @brief  ETH Handle Structure definition  
+/**
+  * @brief  ETH Handle Structure definition
   */
-  
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 {
   ETH_TypeDef                *Instance;     /*!< Register base address       */
-  
+
   ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
-  
+
   uint32_t                   LinkStatus;    /*!< Ethernet link status        */
-  
+
   ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
-  
+
   ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
-  
+
   ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
-  
+
   __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
-  
+
   HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
 
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Tx Complete Callback   */
+  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback   */
+  void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth);          /*!< DMA Error Callback      */
+  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp Init callback       */
+  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);         /*!< ETH Msp DeInit callback     */
+
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
 } ETH_HandleTypeDef;
 
- /**
-  * @}
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ETH Callback ID enumeration definition
   */
+typedef enum
+{
+  HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID            */
+  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID          */
+  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID        */
+  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID        */
+  HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID          */
+
+} HAL_ETH_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ETH Callback pointer definition
+  */
+typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup ETH_Exported_Constants ETH Exported Constants
@@ -660,72 +678,72 @@ typedef struct
 
 /** @defgroup ETH_Buffers_setting ETH Buffers setting
   * @{
-  */ 
-#define ETH_MAX_PACKET_SIZE    ((uint32_t)1524)    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER               ((uint32_t)14)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC                   ((uint32_t)4)    /*!< Ethernet CRC */
-#define ETH_EXTRA                 ((uint32_t)2)    /*!< Extra bytes in some cases */   
-#define ETH_VLAN_TAG                  ((uint32_t)4)    /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD          ((uint32_t)46)    /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD        ((uint32_t)1500)    /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD    ((uint32_t)9000)    /*!< Jumbo frame payload size */      
+  */
+#define ETH_MAX_PACKET_SIZE    1524U    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4U    /*!< Ethernet CRC */
+#define ETH_EXTRA                 2U    /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG                  4U    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD          46U    /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD        1500U    /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD    9000U    /*!< Jumbo frame payload size */
 
- /* Ethernet driver receive buffers are organized in a chained linked-list, when
-    an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
-    to the driver receive buffers memory.
+/* Ethernet driver receive buffers are organized in a chained linked-list, when
+   an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+   to the driver receive buffers memory.
 
-    Depending on the size of the received ethernet packet and the size of 
-    each ethernet driver receive buffer, the received packet can take one or more
-    ethernet driver receive buffer. 
+   Depending on the size of the received ethernet packet and the size of
+   each ethernet driver receive buffer, the received packet can take one or more
+   ethernet driver receive buffer.
 
-    In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 
-    and the total count of the driver receive buffers ETH_RXBUFNB.
+   In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+   and the total count of the driver receive buffers ETH_RXBUFNB.
 
-    The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 
-    example, they can be reconfigured in the application layer to fit the application 
-    needs */ 
+   The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+   example, they can be reconfigured in the application layer to fit the application
+   needs */
 
 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
    packet */
 #ifndef ETH_RX_BUF_SIZE
- #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE 
+#define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
 #endif
 
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
 #ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB             ((uint32_t)5     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_RXBUFNB             5U     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
 #endif
 
 
- /* Ethernet driver transmit buffers are organized in a chained linked-list, when
-    an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 
-    driver transmit buffers memory to the TxFIFO.
+/* Ethernet driver transmit buffers are organized in a chained linked-list, when
+   an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+   driver transmit buffers memory to the TxFIFO.
 
-    Depending on the size of the Ethernet packet to be transmitted and the size of 
-    each ethernet driver transmit buffer, the packet to be transmitted can take 
-    one or more ethernet driver transmit buffer. 
+   Depending on the size of the Ethernet packet to be transmitted and the size of
+   each ethernet driver transmit buffer, the packet to be transmitted can take
+   one or more ethernet driver transmit buffer.
 
-    In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 
-    and the total count of the driver transmit buffers ETH_TXBUFNB.
+   In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+   and the total count of the driver transmit buffers ETH_TXBUFNB.
 
-    The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 
-    example, they can be reconfigured in the application layer to fit the application 
-    needs */ 
+   The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+   example, they can be reconfigured in the application layer to fit the application
+   needs */
 
 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
    packet */
-#ifndef ETH_TX_BUF_SIZE 
- #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
+#ifndef ETH_TX_BUF_SIZE
+#define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
 #endif
 
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
 #ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB             ((uint32_t)5      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_TXBUFNB             5U      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
 #endif
 
- /**
-  * @}
-  */
+/**
+ * @}
+ */
 
 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
   * @{
@@ -744,70 +762,70 @@ typedef struct
   -----------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
-  */ 
-#define ETH_DMATXDESC_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
-#define ETH_DMATXDESC_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
-#define ETH_DMATXDESC_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
-#define ETH_DMATXDESC_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
-#define ETH_DMATXDESC_CIC_IPV4HEADER          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
-#define ETH_DMATXDESC_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
-#define ETH_DMATXDESC_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
-#define ETH_DMATXDESC_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
-
-/** 
+  */
+#define ETH_DMATXDESC_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC                      0x40000000U  /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS                      0x20000000U  /*!< Last Segment */
+#define ETH_DMATXDESC_FS                      0x10000000U  /*!< First Segment */
+#define ETH_DMATXDESC_DC                      0x08000000U  /*!< Disable CRC */
+#define ETH_DMATXDESC_DP                      0x04000000U  /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE                    0x02000000U  /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC                     0x00C00000U  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS              0x00000000U  /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U  /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER                     0x00200000U  /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH                     0x00100000U  /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS                    0x00020000U  /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE                     0x00010000U  /*!< IP Header Error */
+#define ETH_DMATXDESC_ES                      0x00008000U  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT                      0x00004000U  /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF                      0x00002000U  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE                     0x00001000U  /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF                      0x00000080U  /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC                      0x00000078U  /*!< Collision Count */
+#define ETH_DMATXDESC_ED                      0x00000004U  /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF                      0x00000002U  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB                      0x00000001U  /*!< Deferred Bit */
+
+/**
   * @brief  Bit definition of TDES1 register
-  */ 
-#define ETH_DMATXDESC_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
+  */
+#define ETH_DMATXDESC_TBS2  0x1FFF0000U  /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1  0x00001FFFU  /*!< Transmit Buffer1 Size */
 
-/** 
+/**
   * @brief  Bit definition of TDES2 register
-  */ 
-#define ETH_DMATXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+  */
+#define ETH_DMATXDESC_B1AP  0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
 
-/** 
+/**
   * @brief  Bit definition of TDES3 register
-  */ 
-#define ETH_DMATXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+  */
+#define ETH_DMATXDESC_B2AP  0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
 
-  /*---------------------------------------------------------------------------------------------
-  TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
-  -----------------------------------------------------------------------------------------------
-  TDES7 |                         Transmit Time Stamp High [31:0]                                |
-  ----------------------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------------------------
+TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
+-----------------------------------------------------------------------------------------------
+TDES7 |                         Transmit Time Stamp High [31:0]                                |
+----------------------------------------------------------------------------------------------*/
 
 /* Bit definition of TDES6 register */
- #define ETH_DMAPTPTXDESC_TTSL  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp Low */
+#define ETH_DMAPTPTXDESC_TTSL  0xFFFFFFFFU  /* Transmit Time Stamp Low */
 
 /* Bit definition of TDES7 register */
- #define ETH_DMAPTPTXDESC_TTSH  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stamp High */
+#define ETH_DMAPTPTXDESC_TTSH  0xFFFFFFFFU  /* Transmit Time Stamp High */
 
 /**
   * @}
-  */ 
+  */
 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
   * @{
   */
@@ -825,47 +843,47 @@ typedef struct
   ---------------------------------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
-  */ 
-#define ETH_DMARXDESC_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
-#define ETH_DMARXDESC_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
-#define ETH_DMARXDESC_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
-#define ETH_DMARXDESC_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE          ((uint32_t)0x00004000)  /*!< Descriptor error: no more descriptors for receive frame  */
-#define ETH_DMARXDESC_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
-#define ETH_DMARXDESC_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
-#define ETH_DMARXDESC_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
-#define ETH_DMARXDESC_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
-#define ETH_DMARXDESC_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
-#define ETH_DMARXDESC_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
-#define ETH_DMARXDESC_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
-#define ETH_DMARXDESC_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
-#define ETH_DMARXDESC_CE          ((uint32_t)0x00000002)  /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/** 
+  */
+#define ETH_DMARXDESC_OWN         0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARXDESC_AFM         0x40000000U  /*!< DA Filter Fail for the rx frame  */
+#define ETH_DMARXDESC_FL          0x3FFF0000U  /*!< Receive descriptor frame length  */
+#define ETH_DMARXDESC_ES          0x00008000U  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE          0x00004000U  /*!< Descriptor error: no more descriptors for receive frame  */
+#define ETH_DMARXDESC_SAF         0x00002000U  /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE          0x00001000U  /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE          0x00000800U  /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN        0x00000400U  /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS          0x00000200U  /*!< First descriptor of the frame  */
+#define ETH_DMARXDESC_LS          0x00000100U  /*!< Last descriptor of the frame  */
+#define ETH_DMARXDESC_IPV4HCE     0x00000080U  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
+#define ETH_DMARXDESC_LC          0x00000040U  /*!< Late collision occurred during reception   */
+#define ETH_DMARXDESC_FT          0x00000020U  /*!< Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARXDESC_RWT         0x00000010U  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARXDESC_RE          0x00000008U  /*!< Receive error: error reported by MII interface  */
+#define ETH_DMARXDESC_DBE         0x00000004U  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARXDESC_CE          0x00000002U  /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE      0x00000001U  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
   * @brief  Bit definition of RDES1 register
-  */ 
-#define ETH_DMARXDESC_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
-
-/** 
-  * @brief  Bit definition of RDES2 register  
-  */ 
-#define ETH_DMARXDESC_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
-
-/** 
-  * @brief  Bit definition of RDES3 register  
-  */ 
-#define ETH_DMARXDESC_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+  */
+#define ETH_DMARXDESC_DIC   0x80000000U  /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2  0x1FFF0000U  /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER   0x00008000U  /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH   0x00004000U  /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1  0x00001FFFU  /*!< Receive Buffer1 Size */
+
+/**
+  * @brief  Bit definition of RDES2 register
+  */
+#define ETH_DMARXDESC_B1AP  0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
+
+/**
+  * @brief  Bit definition of RDES3 register
+  */
+#define ETH_DMARXDESC_B2AP  0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
 
 /*---------------------------------------------------------------------------------------------------------------------
   RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
@@ -878,181 +896,181 @@ typedef struct
   --------------------------------------------------------------------------------------------------------------------*/
 
 /* Bit definition of RDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV     ((uint32_t)0x00002000)  /* PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT    ((uint32_t)0x00001000)  /* PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT    ((uint32_t)0x00000F00)  /* PTP Message Type */
-  #define ETH_DMAPTPRXDESC_PTPMT_SYNC                      ((uint32_t)0x00000100)  /* SYNC message (all clock types) */
-  #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  ((uint32_t)0x00000200)  /* FollowUp message (all clock types) */ 
-  #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  ((uint32_t)0x00000300)  /* DelayReq message (all clock types) */ 
-  #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 ((uint32_t)0x00000400)  /* DelayResp message (all clock types) */ 
-  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        ((uint32_t)0x00000500)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 
-  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          ((uint32_t)0x00000600)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ 
-  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           
-#define ETH_DMAPTPRXDESC_IPV6PR   ((uint32_t)0x00000080)  /* IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4PR   ((uint32_t)0x00000040)  /* IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCB  ((uint32_t)0x00000020)  /* IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPE  ((uint32_t)0x00000010)  /* IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHE  ((uint32_t)0x00000008)  /* IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT  ((uint32_t)0x00000007)  /* IP Payload Type */
-  #define ETH_DMAPTPRXDESC_IPPT_UDP                 ((uint32_t)0x00000001)  /* UDP payload encapsulated in the IP datagram */
-  #define ETH_DMAPTPRXDESC_IPPT_TCP                 ((uint32_t)0x00000002)  /* TCP payload encapsulated in the IP datagram */ 
-  #define ETH_DMAPTPRXDESC_IPPT_ICMP                ((uint32_t)0x00000003)  /* ICMP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_PTPV     0x00002000U  /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT    0x00001000U  /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT    0x00000F00U  /* PTP Message Type */
+#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      0x00000100U  /* SYNC message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  0x00000200U  /* FollowUp message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  0x00000300U  /* DelayReq message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 0x00000400U  /* DelayResp message (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        0x00000500U  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          0x00000600U  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR   0x00000080U  /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR   0x00000040U  /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB  0x00000020U  /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE  0x00000010U  /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE  0x00000008U  /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT  0x00000007U  /* IP Payload Type */
+#define ETH_DMAPTPRXDESC_IPPT_UDP                 0x00000001U  /* UDP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_TCP                 0x00000002U  /* TCP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_ICMP                0x00000003U  /* ICMP payload encapsulated in the IP datagram */
 
 /* Bit definition of RDES6 register */
-#define ETH_DMAPTPRXDESC_RTSL  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp Low */
+#define ETH_DMAPTPRXDESC_RTSL  0xFFFFFFFFU  /* Receive Time Stamp Low */
 
 /* Bit definition of RDES7 register */
-#define ETH_DMAPTPRXDESC_RTSH  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stamp High */
+#define ETH_DMAPTPRXDESC_RTSH  0xFFFFFFFFU  /* Receive Time Stamp High */
 /**
   * @}
   */
- /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 
-  * @{
-  */ 
-#define ETH_AUTONEGOTIATION_ENABLE     ((uint32_t)0x00000001)
-#define ETH_AUTONEGOTIATION_DISABLE    ((uint32_t)0x00000000)
+/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE     0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE    0x00000000U
 
 /**
   * @}
   */
-/** @defgroup ETH_Speed ETH Speed 
+/** @defgroup ETH_Speed ETH Speed
   * @{
-  */ 
-#define ETH_SPEED_10M        ((uint32_t)0x00000000)
-#define ETH_SPEED_100M       ((uint32_t)0x00004000)
+  */
+#define ETH_SPEED_10M        0x00000000U
+#define ETH_SPEED_100M       0x00004000U
 
 /**
   * @}
   */
 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
   * @{
-  */ 
-#define ETH_MODE_FULLDUPLEX       ((uint32_t)0x00000800)
-#define ETH_MODE_HALFDUPLEX       ((uint32_t)0x00000000)
+  */
+#define ETH_MODE_FULLDUPLEX       0x00000800U
+#define ETH_MODE_HALFDUPLEX       0x00000000U
 /**
   * @}
   */
 /** @defgroup ETH_Rx_Mode ETH Rx Mode
   * @{
-  */ 
-#define ETH_RXPOLLING_MODE      ((uint32_t)0x00000000)
-#define ETH_RXINTERRUPT_MODE    ((uint32_t)0x00000001)
+  */
+#define ETH_RXPOLLING_MODE      0x00000000U
+#define ETH_RXINTERRUPT_MODE    0x00000001U
 /**
   * @}
   */
 
 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
   * @{
-  */ 
-#define ETH_CHECKSUM_BY_HARDWARE      ((uint32_t)0x00000000)
-#define ETH_CHECKSUM_BY_SOFTWARE      ((uint32_t)0x00000001)
+  */
+#define ETH_CHECKSUM_BY_HARDWARE      0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE      0x00000001U
 /**
   * @}
   */
 
 /** @defgroup ETH_Media_Interface ETH Media Interface
   * @{
-  */ 
-#define ETH_MEDIA_INTERFACE_MII       ((uint32_t)0x00000000)
+  */
+#define ETH_MEDIA_INTERFACE_MII       0x00000000U
 #define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
 /**
   * @}
   */
 
-/** @defgroup ETH_Watchdog ETH Watchdog 
+/** @defgroup ETH_Watchdog ETH Watchdog
   * @{
-  */ 
-#define ETH_WATCHDOG_ENABLE       ((uint32_t)0x00000000)
-#define ETH_WATCHDOG_DISABLE      ((uint32_t)0x00800000)
+  */
+#define ETH_WATCHDOG_ENABLE       0x00000000U
+#define ETH_WATCHDOG_DISABLE      0x00800000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Jabber ETH Jabber
   * @{
-  */ 
-#define ETH_JABBER_ENABLE    ((uint32_t)0x00000000)
-#define ETH_JABBER_DISABLE   ((uint32_t)0x00400000)
+  */
+#define ETH_JABBER_ENABLE    0x00000000U
+#define ETH_JABBER_DISABLE   0x00400000U
 /**
   * @}
   */
 
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
   * @{
-  */ 
-#define ETH_INTERFRAMEGAP_96BIT   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
+  */
+#define ETH_INTERFRAMEGAP_96BIT   0x00000000U  /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT   0x00020000U  /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT   0x00040000U  /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT   0x00060000U  /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT   0x00080000U  /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT   0x000A0000U  /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT   0x000C0000U  /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT   0x000E0000U  /*!< minimum IFG between frames during transmission is 40Bit */
 /**
   * @}
   */
 
 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
   * @{
-  */ 
-#define ETH_CARRIERSENCE_ENABLE   ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE  ((uint32_t)0x00010000)
+  */
+#define ETH_CARRIERSENCE_ENABLE   0x00000000U
+#define ETH_CARRIERSENCE_DISABLE  0x00010000U
 /**
   * @}
   */
 
-/** @defgroup ETH_Receive_Own ETH Receive Own 
+/** @defgroup ETH_Receive_Own ETH Receive Own
   * @{
-  */ 
-#define ETH_RECEIVEOWN_ENABLE     ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE    ((uint32_t)0x00002000)
+  */
+#define ETH_RECEIVEOWN_ENABLE     0x00000000U
+#define ETH_RECEIVEOWN_DISABLE    0x00002000U
 /**
   * @}
   */
 
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
   * @{
-  */ 
-#define ETH_LOOPBACKMODE_ENABLE        ((uint32_t)0x00001000)
-#define ETH_LOOPBACKMODE_DISABLE       ((uint32_t)0x00000000)
+  */
+#define ETH_LOOPBACKMODE_ENABLE        0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE       0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
   * @{
-  */ 
-#define ETH_CHECKSUMOFFLAOD_ENABLE     ((uint32_t)0x00000400)
-#define ETH_CHECKSUMOFFLAOD_DISABLE    ((uint32_t)0x00000000)
+  */
+#define ETH_CHECKSUMOFFLAOD_ENABLE     0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
   * @{
-  */ 
-#define ETH_RETRYTRANSMISSION_ENABLE   ((uint32_t)0x00000000)
-#define ETH_RETRYTRANSMISSION_DISABLE  ((uint32_t)0x00000200)
+  */
+#define ETH_RETRYTRANSMISSION_ENABLE   0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE  0x00000200U
 /**
   * @}
   */
 
 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
   * @{
-  */ 
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     ((uint32_t)0x00000080)
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    ((uint32_t)0x00000000)
+  */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
   * @{
-  */ 
-#define ETH_BACKOFFLIMIT_10  ((uint32_t)0x00000000)
-#define ETH_BACKOFFLIMIT_8   ((uint32_t)0x00000020)
-#define ETH_BACKOFFLIMIT_4   ((uint32_t)0x00000040)
-#define ETH_BACKOFFLIMIT_1   ((uint32_t)0x00000060)
+  */
+#define ETH_BACKOFFLIMIT_10  0x00000000U
+#define ETH_BACKOFFLIMIT_8   0x00000020U
+#define ETH_BACKOFFLIMIT_4   0x00000040U
+#define ETH_BACKOFFLIMIT_1   0x00000060U
 /**
   * @}
   */
@@ -1060,423 +1078,389 @@ typedef struct
 /** @defgroup ETH_Deferral_Check ETH Deferral Check
   * @{
   */
-#define ETH_DEFFERRALCHECK_ENABLE       ((uint32_t)0x00000010)
-#define ETH_DEFFERRALCHECK_DISABLE      ((uint32_t)0x00000000)
+#define ETH_DEFFERRALCHECK_ENABLE       0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE      0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Receive_All ETH Receive All
   * @{
-  */ 
-#define ETH_RECEIVEALL_ENABLE     ((uint32_t)0x80000000)
-#define ETH_RECEIVEAll_DISABLE    ((uint32_t)0x00000000)
+  */
+#define ETH_RECEIVEALL_ENABLE     0x80000000U
+#define ETH_RECEIVEAll_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
   * @{
-  */ 
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       ((uint32_t)0x00000200)
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      ((uint32_t)0x00000300)
-#define ETH_SOURCEADDRFILTER_DISABLE             ((uint32_t)0x00000000)
+  */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE             0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
   * @{
-  */ 
-#define ETH_PASSCONTROLFRAMES_BLOCKALL                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+  */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL                0x00000040U  /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL              0x00000080U  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U  /*!< MAC forwards control frames that pass the Address Filter. */
 /**
   * @}
   */
 
 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
   * @{
-  */ 
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     ((uint32_t)0x00000000)
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    ((uint32_t)0x00000020)
+  */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    0x00000020U
 /**
   * @}
   */
 
 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
   * @{
-  */ 
-#define ETH_DESTINATIONADDRFILTER_NORMAL    ((uint32_t)0x00000000)
-#define ETH_DESTINATIONADDRFILTER_INVERSE   ((uint32_t)0x00000008)
+  */
+#define ETH_DESTINATIONADDRFILTER_NORMAL    0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE   0x00000008U
 /**
   * @}
   */
 
 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
   * @{
-  */ 
-#define ETH_PROMISCUOUS_MODE_ENABLE     ((uint32_t)0x00000001)
-#define ETH_PROMISCUOUS_MODE_DISABLE    ((uint32_t)0x00000000)
+  */
+#define ETH_PROMISCUOUS_MODE_ENABLE     0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
   * @{
-  */ 
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    ((uint32_t)0x00000404)
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           ((uint32_t)0x00000004)
-#define ETH_MULTICASTFRAMESFILTER_PERFECT             ((uint32_t)0x00000000)
-#define ETH_MULTICASTFRAMESFILTER_NONE                ((uint32_t)0x00000010)
+  */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT             0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE                0x00000010U
 /**
   * @}
   */
 
 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
   * @{
-  */ 
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE        ((uint32_t)0x00000002)
-#define ETH_UNICASTFRAMESFILTER_PERFECT          ((uint32_t)0x00000000)
+  */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE        0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT          0x00000000U
 /**
   * @}
   */
 
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
   * @{
-  */ 
-#define ETH_ZEROQUANTAPAUSE_ENABLE     ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE    ((uint32_t)0x00000080)
+  */
+#define ETH_ZEROQUANTAPAUSE_ENABLE     0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE    0x00000080U
 /**
   * @}
   */
 
 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
   * @{
-  */ 
-#define ETH_PAUSELOWTHRESHOLD_MINUS4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
+  */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4        0x00000000U  /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28       0x00000010U  /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144      0x00000020U  /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256      0x00000030U  /*!< Pause time minus 256 slot times */
 /**
   * @}
   */
 
 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
   * @{
-  */ 
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  ((uint32_t)0x00000008)
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
+  */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
   * @{
-  */ 
-#define ETH_RECEIVEFLOWCONTROL_ENABLE       ((uint32_t)0x00000004)
-#define ETH_RECEIVEFLOWCONTROL_DISABLE      ((uint32_t)0x00000000)
+  */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE       0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE      0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
   * @{
-  */ 
-#define ETH_TRANSMITFLOWCONTROL_ENABLE      ((uint32_t)0x00000002)
-#define ETH_TRANSMITFLOWCONTROL_DISABLE     ((uint32_t)0x00000000)
+  */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE      0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE     0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
   * @{
-  */ 
-#define ETH_VLANTAGCOMPARISON_12BIT    ((uint32_t)0x00010000)
-#define ETH_VLANTAGCOMPARISON_16BIT    ((uint32_t)0x00000000)
+  */
+#define ETH_VLANTAGCOMPARISON_12BIT    0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_MAC_addresses ETH MAC addresses
   * @{
-  */ 
-#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008)
-#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010)
-#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018)
+  */
+#define ETH_MAC_ADDRESS0     0x00000000U
+#define ETH_MAC_ADDRESS1     0x00000008U
+#define ETH_MAC_ADDRESS2     0x00000010U
+#define ETH_MAC_ADDRESS3     0x00000018U
 /**
   * @}
   */
 
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
   * @{
-  */ 
-#define ETH_MAC_ADDRESSFILTER_SA       ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESSFILTER_DA       ((uint32_t)0x00000008)
+  */
+#define ETH_MAC_ADDRESSFILTER_SA       0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA       0x00000008U
 /**
   * @}
   */
 
 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
   * @{
-  */ 
-#define ETH_MAC_ADDRESSMASK_BYTE6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
-  * @{
-  */ 
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
+  */
+#define ETH_MAC_ADDRESSMASK_BYTE6      0x20000000U  /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5      0x10000000U  /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4      0x08000000U  /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3      0x04000000U  /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2      0x02000000U  /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1      0x01000000U  /*!< Mask MAC Address low reg bits [70] */
 /**
   * @}
   */
 
 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
   * @{
-  */ 
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   ((uint32_t)0x00000000)
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  ((uint32_t)0x04000000)
+  */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   0x00000000U
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  0x04000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
   * @{
-  */ 
-#define ETH_RECEIVESTOREFORWARD_ENABLE      ((uint32_t)0x02000000)
-#define ETH_RECEIVESTOREFORWARD_DISABLE     ((uint32_t)0x00000000)
+  */
+#define ETH_RECEIVESTOREFORWARD_ENABLE      0x02000000U
+#define ETH_RECEIVESTOREFORWARD_DISABLE     0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
   * @{
-  */ 
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE       ((uint32_t)0x00000000)
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE      ((uint32_t)0x01000000)
+  */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE       0x00000000U
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE      0x01000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
   * @{
-  */ 
-#define ETH_TRANSMITSTOREFORWARD_ENABLE     ((uint32_t)0x00200000)
-#define ETH_TRANSMITSTOREFORWARD_DISABLE    ((uint32_t)0x00000000)
+  */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE     0x00200000U
+#define ETH_TRANSMITSTOREFORWARD_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
   * @{
-  */ 
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+  */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     0x00000000U  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    0x00004000U  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    0x00008000U  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    0x0000C000U  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     0x00010000U  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     0x00014000U  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     0x00018000U  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     0x0001C000U  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
 /**
   * @}
   */
 
 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
   * @{
-  */ 
-#define ETH_FORWARDERRORFRAMES_ENABLE       ((uint32_t)0x00000080)
-#define ETH_FORWARDERRORFRAMES_DISABLE      ((uint32_t)0x00000000)
+  */
+#define ETH_FORWARDERRORFRAMES_ENABLE       0x00000080U
+#define ETH_FORWARDERRORFRAMES_DISABLE      0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
   * @{
-  */ 
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   ((uint32_t)0x00000040)
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  ((uint32_t)0x00000000)     
+  */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   0x00000040U
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
   * @{
-  */ 
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+  */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      0x00000000U  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      0x00000008U  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      0x00000010U  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     0x00000018U  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
 /**
   * @}
   */
 
 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
   * @{
-  */ 
-#define ETH_SECONDFRAMEOPERARTE_ENABLE       ((uint32_t)0x00000004)
-#define ETH_SECONDFRAMEOPERARTE_DISABLE      ((uint32_t)0x00000000)  
+  */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE       0x00000004U
+#define ETH_SECONDFRAMEOPERARTE_DISABLE      0x00000000U
 /**
   * @}
   */
 
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
   * @{
-  */ 
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE      ((uint32_t)0x02000000)
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE     ((uint32_t)0x00000000) 
+  */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE      0x02000000U
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE     0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
   * @{
-  */ 
-#define ETH_FIXEDBURST_ENABLE     ((uint32_t)0x00010000)
-#define ETH_FIXEDBURST_DISABLE    ((uint32_t)0x00000000) 
+  */
+#define ETH_FIXEDBURST_ENABLE     0x00010000U
+#define ETH_FIXEDBURST_DISABLE    0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
   * @{
-  */ 
-#define ETH_RXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+  */
+#define ETH_RXDMABURSTLENGTH_1BEAT          0x00020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT          0x00040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT          0x00080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT          0x00100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT         0x00200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT         0x00400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    0x01020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    0x01040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   0x01080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   0x01100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   0x01200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  0x01400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
 /**
   * @}
   */
 
 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
   * @{
-  */ 
-#define ETH_TXDMABURSTLENGTH_1BEAT          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+  */
+#define ETH_TXDMABURSTLENGTH_1BEAT          0x00000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT          0x00000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT          0x00000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT          0x00000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT         0x00001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT         0x00002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    0x01000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    0x01000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   0x01000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   0x01000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   0x01001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  0x01002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
   * @{
-  */  
-#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              ((uint32_t)0x00000080)
-#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             ((uint32_t)0x00000000)
+  */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE              0x00000080U
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE             0x00000000U
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
   * @{
-  */ 
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX             ((uint32_t)0x00000002)
+  */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   0x00000000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   0x00004000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   0x00008000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   0x0000C000U
+#define ETH_DMAARBITRATION_RXPRIORTX             0x00000002U
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
   * @{
-  */ 
-#define ETH_DMATXDESC_LASTSEGMENTS      ((uint32_t)0x40000000)  /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT      ((uint32_t)0x20000000)  /*!< First Segment */
+  */
+#define ETH_DMATXDESC_LASTSEGMENTS      0x40000000U  /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT      0x20000000U  /*!< First Segment */
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
   * @{
-  */ 
-#define ETH_DMATXDESC_CHECKSUMBYPASS             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+  */
+#define ETH_DMATXDESC_CHECKSUMBYPASS             0x00000000U   /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         0x00400000U   /*!< IPv4 header checksum insertion  */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  0x00800000U   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     0x00C00000U   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
 /**
   * @}
   */
 
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
   * @{
-  */ 
-#define ETH_DMARXDESC_BUFFER1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
+  */
+#define ETH_DMARXDESC_BUFFER1     0x00000000U  /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2     0x00000001U  /*!< DMA Rx Desc Buffer2 */
 /**
   * @}
   */
 
 /** @defgroup ETH_PMT_Flags ETH PMT Flags
   * @{
-  */ 
-#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
+  */
+#define ETH_PMT_FLAG_WUFFRPR      0x80000000U  /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR         0x00000040U  /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          0x00000020U  /*!< Magic Packet Received */
 /**
   * @}
   */
 
 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
   * @{
-  */ 
-#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
+  */
+#define ETH_MMC_IT_TGF       0x00200000U  /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    0x00008000U  /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     0x00004000U  /*!< When Tx good single col counter reaches half the maximum value */
 /**
   * @}
   */
@@ -1484,114 +1468,114 @@ typedef struct
 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
   * @{
   */
-#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
+#define ETH_MMC_IT_RGUF      0x10020000U  /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      0x10000040U  /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      0x10000020U  /*!< When Rx crc error counter reaches half the maximum value */
 /**
   * @}
   */
 
 /** @defgroup ETH_MAC_Flags ETH MAC Flags
   * @{
-  */ 
-#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
-#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
+  */
+#define ETH_MAC_FLAG_TST     0x00000200U  /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    0x00000040U  /*!< MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    0x00000020U  /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC     0x00000010U  /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     0x00000008U  /*!< PMT flag (on MAC) */
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Flags ETH DMA Flags
   * @{
-  */ 
-#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR    ((uint32_t)0x01000000)  /*!< Error bits 0-write transfer, 1-read transfer */
-#define ETH_DMA_FLAG_ACCESSERROR       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
-#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
+  */
+#define ETH_DMA_FLAG_TST               0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               0x10000000U  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               0x08000000U  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR    0x01000000U  /*!< Error bits 0-write transfer, 1-read transfer */
+#define ETH_DMA_FLAG_ACCESSERROR       0x02000000U  /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               0x00010000U  /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               0x00008000U  /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                0x00004000U  /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE               0x00002000U  /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                0x00000400U  /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT               0x00000200U  /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               0x00000100U  /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               0x00000080U  /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 0x00000040U  /*!< Receive flag */
+#define ETH_DMA_FLAG_TU                0x00000020U  /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO                0x00000010U  /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT               0x00000008U  /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               0x00000004U  /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               0x00000002U  /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 0x00000001U  /*!< Transmit flag */
 /**
   * @}
   */
 
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
   * @{
-  */ 
-#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
+  */
+#define ETH_MAC_IT_TST       0x00000200U  /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      0x00000040U  /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      0x00000020U  /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC       0x00000010U  /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       0x00000008U  /*!< PMT interrupt (on MAC) */
 /**
   * @}
   */
 
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
   * @{
-  */ 
-#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
-#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
+  */
+#define ETH_DMA_IT_TST       0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       0x10000000U  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       0x08000000U  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS       0x00010000U  /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS       0x00008000U  /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        0x00004000U  /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE       0x00002000U  /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        0x00000400U  /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT       0x00000200U  /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       0x00000100U  /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       0x00000080U  /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         0x00000040U  /*!< Receive interrupt */
+#define ETH_DMA_IT_TU        0x00000020U  /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO        0x00000010U  /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT       0x00000008U  /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       0x00000004U  /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       0x00000002U  /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         0x00000001U  /*!< Transmit interrupt */
 /**
   * @}
   */
 
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
   * @{
-  */ 
-#define ETH_DMA_TRANSMITPROCESS_STOPPED     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   ((uint32_t)0x00600000)  /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
+  */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED     0x00000000U  /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING    0x00100000U  /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING     0x00200000U  /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING     0x00300000U  /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   0x00600000U  /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING     0x00700000U  /*!< Running - closing Rx descriptor */
 
 /**
   * @}
-  */ 
+  */
 
 
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
   * @{
-  */ 
-#define ETH_DMA_RECEIVEPROCESS_STOPPED      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    ((uint32_t)0x00080000)  /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING      ((uint32_t)0x000E0000)  /*!< Running - queuing the receive frame into host memory */
+  */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED      0x00000000U  /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING     0x00020000U  /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING      0x00060000U  /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    0x00080000U  /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING      0x000A0000U  /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING      0x000E0000U  /*!< Running - queuing the receive frame into host memory */
 
 /**
   * @}
@@ -1599,17 +1583,17 @@ typedef struct
 
 /** @defgroup ETH_DMA_overflow ETH DMA overflow
   * @{
-  */ 
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
+  */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      0x10000000U  /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U  /*!< Overflow bit for missed frame counter */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
   * @{
-  */ 
-#define ETH_EXTI_LINE_WAKEUP              ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+  */
+#define ETH_EXTI_LINE_WAKEUP              0x00080000U  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
 
 /**
   * @}
@@ -1624,138 +1608,146 @@ typedef struct
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
- 
+
 /** @brief Reset ETH handle state
-  * @param  __HANDLE__: specifies the ETH handle.
+  * @param  __HANDLE__ specifies the ETH handle.
   * @retval None
   */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                 \
+                                                       (__HANDLE__)->State = HAL_ETH_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;          \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;        \
+                                                     } while(0)
+#else
 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
 
-/** 
+/**
   * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag of TDES0 to check.
+  * @param  __HANDLE__ ETH Handle
+  * @param  __FLAG__ specifies the flag of TDES0 to check.
   * @retval the ETH_DMATxDescFlag (SET or RESET).
   */
 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
 
 /**
   * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag of RDES0 to check.
+  * @param  __HANDLE__ ETH Handle
+  * @param  __FLAG__ specifies the flag of RDES0 to check.
   * @retval the ETH_DMATxDescFlag (SET or RESET).
   */
 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
 
 /**
   * @brief  Enables the specified DMA Rx Desc receive interrupt.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
 
 /**
   * @brief  Disables the specified DMA Rx Desc receive interrupt.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
 
 /**
   * @brief  Set the specified DMA Rx Desc Own bit.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
 
 /**
   * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
-  * @param  __HANDLE__: ETH Handle                     
+  * @param  __HANDLE__ ETH Handle
   * @retval The Transmit descriptor collision counter value.
   */
 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
 
 /**
   * @brief  Set the specified DMA Tx Desc Own bit.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
 
 /**
   * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
-  * @param  __HANDLE__: ETH Handle                   
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
 
 /**
   * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
-  * @param  __HANDLE__: ETH Handle             
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
 
 /**
   * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
-  * @param  __HANDLE__: ETH Handle  
-  * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+  * @param  __HANDLE__ ETH Handle
+  * @param  __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
   *   This parameter can be one of the following values:
   *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
   *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
-  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
+  *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
 
 /**
   * @brief  Enables the DMA Tx Desc CRC.
-  * @param  __HANDLE__: ETH Handle 
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
 
 /**
   * @brief  Disables the DMA Tx Desc CRC.
-  * @param  __HANDLE__: ETH Handle 
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
 
 /**
   * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
-  * @param  __HANDLE__: ETH Handle 
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
 
 /**
   * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
-  * @param  __HANDLE__: ETH Handle 
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
 
-/** 
+/**
  * @brief  Enables the specified ETHERNET MAC interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  * @param  __HANDLE__ ETH Handle
+  * @param  __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
   *   enabled or disabled.
   *   This parameter can be any combination of the following values:
-  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
-  *     @arg ETH_MAC_IT_PMT : PMT interrupt 
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+  *     @arg ETH_MAC_IT_PMT : PMT interrupt
   * @retval None
   */
 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
 
 /**
   * @brief  Disables the specified ETHERNET MAC interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  * @param  __HANDLE__ ETH Handle
+  * @param  __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
   *   enabled or disabled.
   *   This parameter can be any combination of the following values:
-  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
   *     @arg ETH_MAC_IT_PMT : PMT interrupt
   * @retval None
   */
@@ -1763,50 +1755,50 @@ typedef struct
 
 /**
   * @brief  Initiate a Pause Control Frame (Full-duplex only).
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
 
 /**
   * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval The new state of flow control busy status bit (SET or RESET).
   */
 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
 
 /**
   * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
 
 /**
   * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
 
 /**
   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ ETH Handle
+  * @param  __FLAG__ specifies the flag to check.
   *   This parameter can be one of the following values:
-  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
-  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
-  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
-  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
-  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag
   * @retval The state of ETHERNET MAC flag.
   */
 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
 
-/** 
+/**
   * @brief  Enables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  * @param  __HANDLE__ ETH Handle
+  * @param  __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
   *   enabled @ref ETH_DMA_Interrupts
   * @retval None
   */
@@ -1814,8 +1806,8 @@ typedef struct
 
 /**
   * @brief  Disables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  * @param  __HANDLE__ ETH Handle
+  * @param  __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
   *   disabled. @ref ETH_DMA_Interrupts
   * @retval None
   */
@@ -1823,32 +1815,32 @@ typedef struct
 
 /**
   * @brief  Clears the ETHERNET DMA IT pending bit.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+  * @param  __HANDLE__ ETH Handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
   * @retval None
   */
 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
 
 /**
   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-* @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
+* @param  __HANDLE__ ETH Handle
+  * @param  __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
   */
 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
 
 /**
   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
+  * @param  __HANDLE__ ETH Handle
+  * @param  __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
   */
 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))
 
 /**
   * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
+  * @param  __HANDLE__ ETH Handle
+  * @param  __OVERFLOW__ specifies the DMA overflow flag to check.
   *   This parameter can be one of the following values:
   *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
   *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
@@ -1858,16 +1850,16 @@ typedef struct
 
 /**
   * @brief  Set the DMA Receive status watchdog timer register value
-  * @param  __HANDLE__: ETH Handle
-  * @param  __VALUE__: DMA Receive status watchdog timer register value   
+  * @param  __HANDLE__ ETH Handle
+  * @param  __VALUE__ DMA Receive status watchdog timer register value
   * @retval None
   */
 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
 
-/** 
+/**
   * @brief  Enables any unicast packet filtered by the MAC address
   *   recognition to be a wake-up frame.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
@@ -1875,75 +1867,75 @@ typedef struct
 /**
   * @brief  Disables any unicast packet filtered by the MAC address
   *   recognition to be a wake-up frame.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
 
 /**
   * @brief  Enables the MAC Wake-Up Frame Detection.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
 
 /**
   * @brief  Disables the MAC Wake-Up Frame Detection.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
 
 /**
   * @brief  Enables the MAC Magic Packet Detection.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
 
 /**
   * @brief  Disables the MAC Magic Packet Detection.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
 
 /**
   * @brief  Enables the MAC Power Down.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
 
 /**
   * @brief  Disables the MAC Power Down.
-  * @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__ ETH Handle
   * @retval None
   */
 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
 
 /**
   * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
-  * @param  __HANDLE__: ETH Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ ETH Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *   This parameter can be one of the following values:
-  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 
-  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
+  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
   *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
   * @retval The new state of ETHERNET PMT Flag (SET or RESET).
   */
 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
 
-/** 
+/**
   * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
-  * @param   __HANDLE__: ETH Handle.
+  * @param   __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
 
 /**
   * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
@@ -1951,95 +1943,95 @@ typedef struct
 
 /**
   * @brief  Enables the MMC Counter Freeze.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
 
 /**
   * @brief  Disables the MMC Counter Freeze.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
 
 /**
   * @brief  Enables the MMC Reset On Read.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
 
 /**
   * @brief  Disables the MMC Reset On Read.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
 
 /**
   * @brief  Enables the MMC Counter Stop Rollover.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
 
 /**
   * @brief  Disables the MMC Counter Stop Rollover.
-  * @param  __HANDLE__: ETH Handle.
+  * @param  __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
 
 /**
   * @brief  Resets the MMC Counters.
-  * @param   __HANDLE__: ETH Handle.
+  * @param   __HANDLE__ ETH Handle.
   * @retval None
   */
 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
 
 /**
   * @brief  Enables the specified ETHERNET MMC Rx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  * @param   __HANDLE__ ETH Handle.
+  * @param  __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
   * @retval None
   */
 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
 /**
   * @brief  Disables the specified ETHERNET MMC Rx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values: 
-  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  * @param   __HANDLE__ ETH Handle.
+  * @param  __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
   * @retval None
   */
 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
 /**
   * @brief  Enables the specified ETHERNET MMC Tx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  * @param   __HANDLE__ ETH Handle.
+  * @param  __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
   * @retval None
   */
 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
 
 /**
   * @brief  Disables the specified ETHERNET MMC Tx interrupts.
-  * @param   __HANDLE__: ETH Handle.
-  * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:  
-  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
-  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  * @param   __HANDLE__ ETH Handle.
+  * @param  __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
   * @retval None
   */
 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
@@ -2090,12 +2082,12 @@ typedef struct
   * @brief  Disables the rising edge trigger to the ETH External interrupt line.
   * @retval None
   */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)                                                          
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
 
 /**
   * @brief  Enables falling edge trigger to the ETH External interrupt line.
   * @retval None
-  */                                                      
+  */
 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
 
 /**
@@ -2108,15 +2100,17 @@ typedef struct
   * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
   * @retval None
   */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
-                                                              EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+                                                                 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+                                                                }while(0)
 
 /**
   * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
   * @retval None
   */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
-                                                               EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+                                                                  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+                                                                  }while(0)
 
 /**
   * @brief Generate a Software interrupt on selected EXTI line.
@@ -2142,8 +2136,13 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -2181,7 +2180,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
 /**
   * @}
-  */ 
+  */
 
 /* Peripheral State functions  ************************************************/
 
@@ -2193,7 +2192,6 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
   * @}
   */
 
-#endif /* STM32F207xx || STM32F217xx */
 /**
   * @}
   */
@@ -2206,7 +2204,8 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
   * @}
   */
 
-  
+#endif /* ETH */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h
index 702b920c..5c8247da 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of FLASH HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_FLASH_H
@@ -64,7 +46,7 @@
   */
 typedef enum 
 {
-  FLASH_PROC_NONE = 0, 
+  FLASH_PROC_NONE = 0U, 
   FLASH_PROC_SECTERASE,
   FLASH_PROC_MASSERASE,
   FLASH_PROC_PROGRAM
@@ -105,12 +87,12 @@ typedef struct
   * @brief    FLASH Error Code 
   * @{
   */ 
-#define HAL_FLASH_ERROR_NONE         ((uint32_t)0x00000000)    /*!< No error                      */
-#define HAL_FLASH_ERROR_PGS          ((uint32_t)0x00000001)    /*!< Programming Sequence error    */
-#define HAL_FLASH_ERROR_PGP          ((uint32_t)0x00000002)    /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA          ((uint32_t)0x00000004)    /*!< Programming Alignment error   */
-#define HAL_FLASH_ERROR_WRP          ((uint32_t)0x00000008)    /*!< Write protection error        */
-#define HAL_FLASH_ERROR_OPERATION    ((uint32_t)0x00000010)    /*!< Operation Error               */
+#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */
+#define HAL_FLASH_ERROR_PGS          0x00000001U    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          0x00000002U    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          0x00000004U    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          0x00000008U    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    0x00000010U    /*!< Operation Error               */
 /**
   * @}
   */
@@ -118,10 +100,10 @@ typedef struct
 /** @defgroup FLASH_Type_Program FLASH Type Program
   * @{
   */ 
-#define FLASH_TYPEPROGRAM_BYTE        ((uint32_t)0x00)  /*!< Program byte (8-bit) at a specified address           */
-#define FLASH_TYPEPROGRAM_HALFWORD    ((uint32_t)0x01)  /*!< Program a half-word (16-bit) at a specified address   */
-#define FLASH_TYPEPROGRAM_WORD        ((uint32_t)0x02)  /*!< Program a word (32-bit) at a specified address        */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD  ((uint32_t)0x03)  /*!< Program a double word (64-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_BYTE        0x00U  /*!< Program byte (8-bit) at a specified address           */
+#define FLASH_TYPEPROGRAM_HALFWORD    0x01U  /*!< Program a half-word (16-bit) at a specified address   */
+#define FLASH_TYPEPROGRAM_WORD        0x02U  /*!< Program a word (32-bit) at a specified address        */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x03U  /*!< Program a double word (64-bit) at a specified address */
 /**
   * @}
   */
@@ -145,8 +127,8 @@ typedef struct
   * @brief FLASH Interrupt definition
   * @{
   */ 
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source                  */
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE           /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   0x02000000U  /*!< Error Interrupt source                  */
 /**
   * @}
   */  
@@ -154,11 +136,11 @@ typedef struct
 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
   * @{
   */
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
-#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
+#define FLASH_PSIZE_BYTE           0x00000000U
+#define FLASH_PSIZE_HALF_WORD      0x00000100U
+#define FLASH_PSIZE_WORD           0x00000200U
+#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U
+#define CR_PSIZE_MASK              0xFFFFFCFFU
 /**
   * @}
   */ 
@@ -167,10 +149,10 @@ typedef struct
   * @{
   */ 
 #define RDP_KEY                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               ((uint32_t)0x45670123)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
-#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
-#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
+#define FLASH_KEY1               0x45670123U
+#define FLASH_KEY2               0xCDEF89ABU
+#define FLASH_OPT_KEY1           0x08192A3BU
+#define FLASH_OPT_KEY2           0x4C5D6E7FU
 /**
   * @}
   */ 
@@ -185,7 +167,7 @@ typedef struct
   */
 /**
   * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency                   
+  * @param  __LATENCY__ FLASH Latency                   
   *         The value of this parameter depend on device used within the same series
   * @retval none
   */ 
@@ -241,7 +223,7 @@ typedef struct
   */
 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
                                                   FLASH->ACR &= ~FLASH_ACR_ICRST; \
-                                                 }while(0)
+                                                 }while(0U)
 
 /**
   * @brief  Resets the FLASH data Cache.
@@ -250,10 +232,10 @@ typedef struct
   */
 #define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
                                            FLASH->ACR &= ~FLASH_ACR_DCRST; \
-                                          }while(0)
+                                          }while(0U)
 /**
   * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
+  * @param  __INTERRUPT__ FLASH interrupt 
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
   *     @arg FLASH_IT_ERR: Error Interrupt    
@@ -263,7 +245,7 @@ typedef struct
 
 /**
   * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
+  * @param  __INTERRUPT__ FLASH interrupt 
   *         This parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
   *     @arg FLASH_IT_ERR: Error Interrupt    
@@ -273,8 +255,8 @@ typedef struct
 
 /**
   * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__: specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
+  * @param  __FLAG__ specifies the FLASH flags to check.
+  *          This parameter can be any combination of the following values:
   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
   *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
@@ -284,11 +266,11 @@ typedef struct
   *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
   * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
 
 /**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__: specifies the FLASH flags to clear.
+  * @brief  Clear the specified FLASH flags.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
   *          This parameter can be any combination of the following values:
   *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
   *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
@@ -369,23 +351,23 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
 /** 
   * @brief   ACR register byte 0 (Bits[7:0]) base address  
   */ 
-#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
+#define ACR_BYTE0_ADDRESS           0x40023C00U
 /** 
   * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
   */ 
-#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
+#define OPTCR_BYTE0_ADDRESS         0x40023C14U
 /** 
   * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
   */ 
-#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+#define OPTCR_BYTE1_ADDRESS         0x40023C15U
 /** 
   * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
   */ 
-#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
+#define OPTCR_BYTE2_ADDRESS         0x40023C16U
 /** 
   * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
   */ 
-#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
+#define OPTCR_BYTE3_ADDRESS         0x40023C17U
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h
index c113632d..9c0f4e95 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of FLASH HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_FLASH_EX_H
@@ -68,17 +50,17 @@ typedef struct
                              This parameter can be a value of @ref FLASHEx_Type_Erase */
 
   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */        
+                             This parameter must be a value of @ref FLASHEx_Banks */
 
   uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
-                             This parameter must be a value of @ref FLASHEx_Sectors */        
-  
+                             This parameter must be a value of @ref FLASHEx_Sectors */
+
   uint32_t NbSectors;   /*!< Number of sectors to be erased.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/           
-                                                          
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
   uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
-                             This parameter must be a value of @ref FLASHEx_Voltage_Range */        
-  
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
 } FLASH_EraseInitTypeDef;
 
 /**
@@ -117,8 +99,8 @@ typedef struct
 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
   * @{
   */ 
-#define FLASH_TYPEERASE_SECTORS         ((uint32_t)0x00)  /*!< Sectors erase only          */
-#define FLASH_TYPEERASE_MASSERASE       ((uint32_t)0x01)  /*!< Flash Mass erase activation */
+#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */
 /**
   * @}
   */
@@ -126,10 +108,10 @@ typedef struct
 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
   * @{
   */ 
-#define FLASH_VOLTAGE_RANGE_1        ((uint32_t)0x00)  /*!< Device operating range: 1.8V to 2.1V                */
-#define FLASH_VOLTAGE_RANGE_2        ((uint32_t)0x01)  /*!< Device operating range: 2.1V to 2.7V                */
-#define FLASH_VOLTAGE_RANGE_3        ((uint32_t)0x02)  /*!< Device operating range: 2.7V to 3.6V                */
-#define FLASH_VOLTAGE_RANGE_4        ((uint32_t)0x03)  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */
+#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */
+#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */
+#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
 /**
   * @}
   */
@@ -137,8 +119,8 @@ typedef struct
 /** @defgroup FLASHEx_WRP_State FLASH WRP State
   * @{
   */ 
-#define OB_WRPSTATE_DISABLE       ((uint32_t)0x00)  /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE        ((uint32_t)0x01)  /*!< Enable the write protection of the desired bank 1 sectors  */
+#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
 /**
   * @}
   */
@@ -146,10 +128,10 @@ typedef struct
 /** @defgroup FLASHEx_Option_Type FLASH Option Type
   * @{
   */ 
-#define OPTIONBYTE_WRP        ((uint32_t)0x01)  /*!< WRP option byte configuration  */
-#define OPTIONBYTE_RDP        ((uint32_t)0x02)  /*!< RDP option byte configuration  */
-#define OPTIONBYTE_USER       ((uint32_t)0x04)  /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR        ((uint32_t)0x08)  /*!< BOR option byte configuration  */
+#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */
 /**
   * @}
   */
@@ -159,8 +141,8 @@ typedef struct
   */
 #define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
 #define OB_RDP_LEVEL_1   ((uint8_t)0x55)
-#define OB_RDP_LEVEL_2   ((uint8_t)0xCC)   /*!< Warning: When enabling read protection level 2 
-                                            it s no more possible to go back to level 1 or 0 */
+#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
+                                              it s no more possible to go back to level 1 or 0 */
 /**
   * @}
   */ 
@@ -229,7 +211,7 @@ typedef struct
 /** @defgroup FLASHEx_Banks FLASH Banks
   * @{
   */
-#define FLASH_BANK_1     ((uint32_t)1) /*!< Bank 1   */
+#define FLASH_BANK_1     1U /*!< Bank 1   */
 /**
   * @}
   */ 
@@ -237,7 +219,7 @@ typedef struct
 /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
   * @{
   */
-#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
+#define FLASH_MER_BIT     FLASH_CR_MER /*!< only 1 MER Bit */
 /**
   * @}
   */ 
@@ -245,18 +227,18 @@ typedef struct
 /** @defgroup FLASHEx_Sectors FLASH Sectors
   * @{
   */
-#define FLASH_SECTOR_0     ((uint32_t)0)  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     ((uint32_t)1)  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     ((uint32_t)2)  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     ((uint32_t)3)  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     ((uint32_t)4)  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     ((uint32_t)5)  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     ((uint32_t)6)  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     ((uint32_t)7)  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     ((uint32_t)8)  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     ((uint32_t)9)  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    ((uint32_t)10) /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    ((uint32_t)11) /*!< Sector Number 11  */
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
 
 
 
@@ -267,19 +249,19 @@ typedef struct
 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
   * @{
   */
-#define OB_WRP_SECTOR_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
-#define OB_WRP_SECTOR_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
-#define OB_WRP_SECTOR_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
-#define OB_WRP_SECTOR_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
-#define OB_WRP_SECTOR_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
-#define OB_WRP_SECTOR_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
-#define OB_WRP_SECTOR_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
-#define OB_WRP_SECTOR_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
-#define OB_WRP_SECTOR_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
-#define OB_WRP_SECTOR_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
-#define OB_WRP_SECTOR_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
-#define OB_WRP_SECTOR_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
-#define OB_WRP_SECTOR_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0 */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1 */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2 */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3 */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4 */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5 */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6 */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7 */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8 */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9 */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10 */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11 */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
 
 
 /**
@@ -315,12 +297,19 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
   */
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Variables FLASH Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup FLASHEx_Private_Constants FLASH Private Constants
   * @{
   */
 
-#define FLASH_SECTOR_TOTAL  12
+#define FLASH_SECTOR_TOTAL  12U
 
 /**
   * @}
@@ -380,9 +369,10 @@ void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
 
 
 
-#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
+                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h
index 15694d3c..ec3234d9 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_GPIO_H
@@ -85,7 +67,7 @@ typedef struct
   */
 typedef enum
 {
-  GPIO_PIN_RESET = 0,
+  GPIO_PIN_RESET = 0U,
   GPIO_PIN_SET
 }GPIO_PinState;
 /**
@@ -119,7 +101,7 @@ typedef enum
 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
 
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
 /**
   * @}
   */
@@ -134,21 +116,21 @@ typedef enum
   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
   * @{
   */ 
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_INPUT                        0x00000000U   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    0x00000001U   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    0x00000011U   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        0x00000002U   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        0x00000012U   /*!< Alternate Function Open Drain Mode    */
 
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
+#define  GPIO_MODE_ANALOG                       0x00000003U   /*!< Analog Mode  */
     
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_RISING                    0x10110000U   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   0x10210000U   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            0x10310000U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
  
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+#define  GPIO_MODE_EVT_RISING                   0x10120000U   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  0x10220000U   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           0x10320000U   /*!< External Event Mode with Rising/Falling edge trigger detection       */
 /**
   * @}
   */
@@ -156,11 +138,11 @@ typedef enum
 /** @defgroup GPIO_speed_define  GPIO speed define
   * @brief GPIO Output Maximum frequency
   * @{
-  */  
-#define  GPIO_SPEED_FREQ_LOW         ((uint32_t)0x00000000)  /*!< IO works at 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM      ((uint32_t)0x00000001)  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH        ((uint32_t)0x00000002)  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
-#define  GPIO_SPEED_FREQ_VERY_HIGH   ((uint32_t)0x00000003)  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
+  */
+#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
 /**
   * @}
   */
@@ -169,9 +151,9 @@ typedef enum
    * @brief GPIO Pull-Up or Pull-Down Activation
    * @{
    */  
-#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
+#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
 /**
   * @}
   */
@@ -187,7 +169,7 @@ typedef enum
 
 /**
   * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -195,7 +177,7 @@ typedef enum
 
 /**
   * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -203,7 +185,7 @@ typedef enum
 
 /**
   * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -211,7 +193,7 @@ typedef enum
 
 /**
   * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -219,7 +201,7 @@ typedef enum
 
 /**
   * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval None
   */
@@ -280,7 +262,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
   * @{
   */
 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h
index e584ba6b..4e4f401c 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_GPIO_EX_H
@@ -139,22 +121,22 @@
 /** 
   * @brief   AF 10 selection  
   */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
 
 /** 
   * @brief   AF 11 selection  
   */ 
 #if defined(STM32F207xx) || defined(STM32F217xx)
-#define GPIO_AF11_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
 #endif /* STM32F207xx || STM32F217xx */
 
 /** 
   * @brief   AF 12 selection  
   */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
 
 /** 
   * @brief   AF 13 selection  
@@ -264,7 +246,7 @@
                           ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
                           ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
 #endif /* STM32F207xx || STM32F217xx */
-                          
+
 /**
   * @}
   */ 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h
index 2078e3db..8e78ff9d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h
@@ -2,180 +2,209 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hash.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of HASH HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_HASH_H
-#define __STM32F2xx_HAL_HASH_H
+#ifndef STM32F2xx_HAL_HASH_H
+#define STM32F2xx_HAL_HASH_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-#if defined(STM32F215xx) || defined(STM32F217xx)
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
-
-/** @addtogroup HASH    
-  * @brief HASH HAL module driver 
-  *  @{
-  */ 
+#if defined (HASH)
+/** @addtogroup HASH
+  * @{
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup HASH_Exported_Types HASH Exported Types
   * @{
   */
 
-/** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
-  * @{
+/**
+  * @brief  HASH Configuration Structure definition
   */
-
 typedef struct
 {
-  uint32_t DataType;  /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                           This parameter can be a value of @ref HASH_Data_Type */
+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
+                              This parameter can be a value of @ref HASH_Data_Type. */
 
-  uint32_t KeySize;   /*!< The key size is used only in HMAC operation          */
+  uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
 
-  uint8_t* pKey;      /*!< The key is used only in HMAC operation               */
-}HASH_InitTypeDef;
+  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
 
-/** 
-  * @}
-  */
+} HASH_InitTypeDef;
 
-/** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
-  * @{
+/**
+  * @brief HAL State structures definition
   */
+typedef enum
+{
+  HAL_HASH_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized            */
+  HAL_HASH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
+  HAL_HASH_STATE_BUSY              = 0x02U,    /*!< Processing (hashing) is ongoing          */
+  HAL_HASH_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                            */
+  HAL_HASH_STATE_ERROR             = 0x07U,    /*!< Error state                              */
+  HAL_HASH_STATE_SUSPENDED         = 0x08U     /*!< Suspended state                          */
+}HAL_HASH_StateTypeDef;
 
+/**
+  * @brief HAL phase structures definition
+  */
 typedef enum
 {
-  HAL_HASH_STATE_RESET     = 0x00,  /*!< HASH not yet initialized or disabled */
-  HAL_HASH_STATE_READY     = 0x01,  /*!< HASH initialized and ready for use   */
-  HAL_HASH_STATE_BUSY      = 0x02,  /*!< HASH internal process is ongoing     */
-  HAL_HASH_STATE_TIMEOUT   = 0x03,  /*!< HASH timeout state                   */
-  HAL_HASH_STATE_ERROR     = 0x04   /*!< HASH error state                     */
-}HAL_HASH_STATETypeDef;
-
-/** 
-  * @}
+  HAL_HASH_PHASE_READY             = 0x01U,    /*!< HASH peripheral is ready to start                    */
+  HAL_HASH_PHASE_PROCESS           = 0x02U,    /*!< HASH peripheral is in HASH processing phase          */
+  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03U,    /*!< HASH peripheral is in HMAC step 1 processing phase
+                                              (step 1 consists in entering the inner hash function key) */
+  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04U,    /*!< HASH peripheral is in HMAC step 2 processing phase
+                                              (step 2 consists in entering the message text) */
+  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase
+                                              (step 3 consists in entering the outer hash function key) */
+}HAL_HASH_PhaseTypeDef;
+
+/**
+  * @brief HAL HASH mode suspend definitions
   */
-  
-/** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
-  * @{
+typedef enum
+{
+  HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */
+  HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */
+}HAL_HASH_SuspendTypeDef;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  HAL HASH common Callback ID enumeration definition
   */
-  
 typedef enum
 {
-  HAL_HASH_PHASE_READY     = 0x01,  /*!< HASH peripheral is ready for initialization */
-  HAL_HASH_PHASE_PROCESS   = 0x02,  /*!< HASH peripheral is in processing phase      */
-}HAL_HASHPhaseTypeDef;
+  HAL_HASH_MSPINIT_CB_ID           = 0x00U,    /*!< HASH MspInit callback ID     */
+  HAL_HASH_MSPDEINIT_CB_ID         = 0x01U,    /*!< HASH MspDeInit callback ID   */
+  HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID */
+  HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */
+  HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID     */
+}HAL_HASH_CallbackIDTypeDef;
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
-/** 
-  * @}
+
+/**
+  * @brief  HASH Handle Structure definition
   */
- 
-/** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
-  * @{
-  */ 
-  
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+typedef struct __HASH_HandleTypeDef
+#else
 typedef struct
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 {
-      HASH_InitTypeDef           Init;              /*!< HASH required parameters       */
+  HASH_InitTypeDef           Init;             /*!< HASH required parameters */
+
+  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
+
+  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
+
+  uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
+
+  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+
+  uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
+
+  __IO uint32_t              HashInCount;      /*!< Counter of inputted data */
+
+  __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */
 
-      uint8_t                    *pHashInBuffPtr;   /*!< Pointer to input buffer        */
+  __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */
 
-      uint8_t                    *pHashOutBuffPtr;  /*!< Pointer to input buffer        */
+  HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */
 
-     __IO uint32_t               HashBuffSize;      /*!< Size of buffer to be processed */
+  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */
 
-     __IO uint32_t               HashInCount;       /*!< Counter of input data        */
+  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */
 
-     __IO uint32_t               HashITCounter;     /*!< Counter of issued interrupts   */
+  HAL_LockTypeDef            Lock;             /*!< Locking object */
 
-      HAL_StatusTypeDef          Status;            /*!< HASH peripheral status         */
+  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */
 
-      HAL_HASHPhaseTypeDef       Phase;             /*!< HASH peripheral phase          */
+  HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */
 
-      DMA_HandleTypeDef          *hdmain;           /*!< HASH In DMA handle parameters  */
+  FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
 
-      HAL_LockTypeDef            Lock;              /*!< HASH locking object            */
+  __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */
 
-     __IO HAL_HASH_STATETypeDef  State;             /*!< HASH peripheral state          */
+  __IO  uint32_t             ErrorCode;        /*!< HASH Error code */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */
+
+  void    (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash);  /*!< HASH digest computation completion callback */
+
+  void    (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash);     /*!< HASH error callback */
+
+  void    (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash);   /*!< HASH Msp Init callback */
+
+  void    (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 } HASH_HandleTypeDef;
 
-/** 
-  * @}
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  HAL HASH Callback pointer definition
   */
-  
+typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
 /**
   * @}
-  */ 
-  
+  */
+
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup HASH_Exported_Constants HASH Exported Constants
+
+/** @defgroup HASH_Exported_Constants  HASH Exported Constants
   * @{
   */
 
-/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
+/** @defgroup HASH_Algo_Selection   HASH algorithm selection
   * @{
   */
-#define HASH_ALGOSELECTION_SHA1      ((uint32_t)0x0000)  /*!< HASH function is SHA1   */
-#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0      /*!< HASH function is MD5    */
+#define HASH_ALGOSELECTION_SHA1      0x00000000U /*!< HASH function is SHA1   */
+#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
+/** @defgroup HASH_Algorithm_Mode   HASH algorithm mode
   * @{
   */
-#define HASH_ALGOMODE_HASH         ((uint32_t)0x00000000)  /*!< Algorithm is HASH */ 
-#define HASH_ALGOMODE_HMAC         HASH_CR_MODE            /*!< Algorithm is HMAC */
+#define HASH_ALGOMODE_HASH         0x00000000U /*!< Algorithm is HASH */
+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
 /**
   * @}
   */
 
-/** @defgroup HASH_Data_Type HASH Data Type
+/** @defgroup HASH_Data_Type      HASH input data type
   * @{
   */
-#define HASH_DATATYPE_32B          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
+#define HASH_DATATYPE_32B          0x00000000U /*!< 32-bit data. No swapping                     */
 #define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
 #define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
 #define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
@@ -183,33 +212,47 @@ typedef struct
   * @}
   */
 
-/** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key 
-  * @brief HASH HMAC Long key used only for HMAC mode
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type
   * @{
   */
-#define HASH_HMAC_KEYTYPE_SHORTKEY      ((uint32_t)0x00000000)  /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY            /*!< HMAC Key is > 64 bytes  */
+#define HASH_HMAC_KEYTYPE_SHORTKEY      0x00000000U /*!< HMAC Key size is <= 64 bytes */
+#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition 
+/** @defgroup HASH_flags_definition  HASH flags definitions
   * @{
   */
-#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
-#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
-#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
-#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
-#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
+
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition 
+/** @defgroup HASH_interrupts_definition   HASH interrupts definitions
   * @{
   */
 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Error_Definition   HASH Error Definition
+  * @{
+  */
+#define  HAL_HASH_ERROR_NONE             0x00000000U   /*!< No error                */
+#define  HAL_HASH_ERROR_IT               0x00000001U   /*!< IT-based process error  */
+#define  HAL_HASH_ERROR_DMA              0x00000002U   /*!< DMA-based process error */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
+#define  HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -218,215 +261,313 @@ typedef struct
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup HASH_Exported_Macros HASH Exported Macros
   * @{
   */
-  
-/** @brief Reset HASH handle state
-  * @param  __HANDLE__: specifies the HASH handle.
+
+/** @brief  Check whether or not the specified HASH flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
+  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
+  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
+  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
+                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+
+
+/** @brief  Clear the specified HASH flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
+
+
+/** @brief  Enable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief  Disable the specified HASH interrupt.
+  * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
+  *            @arg @ref HASH_IT_DCI   Digest calculation complete
+  * @retval None
+  */
+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
+
+/** @brief Reset HASH handle state.
+  * @param  __HANDLE__: HASH handle.
   * @retval None
   */
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;      \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                     }while(0)
+#else
 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
-/** @brief  Check whether the specified HASH flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer. 
-  *            @arg HASH_FLAG_DCIS: Digest calculation complete
-  *            @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
-  *            @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
-  *            @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+
+/** @brief Reset HASH handle status.
+  * @param  __HANDLE__: HASH handle.
+  * @retval None
   */
-#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
-                                                           ((HASH->SR & (__FLAG__)) == (__FLAG__)))
+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
+
+
 /**
-  * @brief  Start the digest computation
+  * @brief Start the digest computation.
   * @retval None
   */
-#define __HAL_HASH_START_DIGEST()       HASH->STR |= HASH_STR_DCAL
+#define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)
 
 /**
-  * @brief Set the number of valid bits in last word written in Data register
-  * @param  SIZE: size in byte of last data written in Data register.
+  * @brief Set the number of valid bits in the last word written in data register DIN.
+  * @param  __SIZE__: size in bytes of last data written in Data register.
   * @retval None
 */
-#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
-                                            HASH->STR |= 8 * ((SIZE) % 4);\
-                                           }while(0)
+#define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
+
+/**
+  * @brief Reset the HASH core.
+  * @retval None
+  */
+#define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)
 
 /**
   * @}
-  */ 
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup HASH_Private_Macros   HASH Private Macros
+  * @{
+  */
+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : 16)
+/**
+  * @brief  Return number of words already pushed in the FIFO.
+  * @retval Number of words already pushed in the FIFO
+  */
+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
+
+/**
+  * @brief Ensure that HASH input data type is valid.
+  * @param __DATATYPE__: HASH input data type.
+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
+  */
+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
+                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
+                                        ((__DATATYPE__) == HASH_DATATYPE_1B))
+
+
+
+/**
+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH
+  *        processing in polling mode.
+  * @note  This check is valid only for multi-buffer HASH processing in polling mode.
+  * @param __SIZE__: input data buffer size.
+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
+  */
+#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4U) == 0U)
+/**
+  * @brief Ensure that handle phase is set to HASH processing.
+  * @param __HANDLE__: HASH handle.
+  * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
+  */
+#define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
 
+/**
+  * @brief Ensure that handle phase is set to HMAC processing.
+  * @param __HANDLE__: HASH handle.
+  * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
+  */
+#define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 
-/** @defgroup HASH_Exported_Functions HASH Exported Functions
+/** @addtogroup HASH_Exported_Functions HASH Exported Functions
   * @{
   */
 
-/** @addtogroup HASH_Exported_Functions_Group1
+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
-  */  
+  */
+
+/* Initialization/de-initialization methods  **********************************/
 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup HASH_Exported_Functions_Group2
+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
   * @{
-  */  
+  */
+
+
+/* HASH processing using polling  *********************************************/
 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
 /**
   * @}
-  */ 
-  
-/** @addtogroup HASH_Exported_Functions_Group3
-  * @{
-  */  
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-/**
-  * @}
-  */ 
+  */
 
-/** @addtogroup HASH_Exported_Functions_Group4
+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
   * @{
-  */  
+  */
+
+/* HASH processing using IT  **************************************************/
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup HASH_Exported_Functions_Group5
+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
   * @{
-  */    
+  */
+
+/* HASH processing using DMA  *************************************************/
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-/**
-  * @}
-  */ 
-
-/** @addtogroup HASH_Exported_Functions_Group6
-  * @{
-  */  
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-/**
-  * @}
-  */ 
 
-/** @addtogroup HASH_Exported_Functions_Group7
-  * @{
-  */  
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
-  */ 
-
-/** @addtogroup HASH_Exported_Functions_Group8
-  * @{
   */
-HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
-/**
-  * @}
-  */ 
-  
- /**
-  * @}
-  */ 
- 
- /* Private types -------------------------------------------------------------*/
-/** @defgroup HASH_Private_Types HASH Private Types
+
+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
   * @{
   */
 
+/* HASH-MAC processing using polling  *****************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
 /**
   * @}
-  */ 
+  */
 
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Variables HASH Private Variables
+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
   * @{
   */
 
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+
 /**
   * @}
-  */ 
+  */
 
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Constants HASH Private Constants
+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
   * @{
   */
 
+/* HASH-HMAC processing using DMA  ********************************************/
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+
 /**
   * @}
-  */ 
+  */
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros HASH Private Macros
+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
   * @{
   */
-#define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1)   || \
-                                                  ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
-
-
-#define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
-                                        ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
-
-
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
-                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
-                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \
-                                        ((__DATATYPE__) == HASH_DATATYPE_1B))
 
 
-#define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
-                                           ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
+/* Peripheral State methods  **************************************************/
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
 
-#define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4) != 0)? 0U: 1U)
+/**
+  * @}
+  */
 
 /**
   * @}
-  */ 
+  */
+
+/* Private functions -----------------------------------------------------------*/
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/** @addtogroup HASH_Private_Functions HASH Private Functions
   * @{
   */
 
+/* Private functions */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+
 /**
   * @}
   */
- 
-#endif /* STM32F215xx || STM32F217xx */
+
 /**
   * @}
-  */ 
-
+  */
+#endif /*  HASH*/
 /**
   * @}
   */
-  
+
+
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* __STM32F2xx_HAL_HASH_H */
+#endif /* STM32F2xx_HAL_HASH_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h
index 2cca6c50..fc59baf9 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h
@@ -2,50 +2,33 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hcd.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of HCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_HCD_H
-#define __STM32F2xx_HAL_HCD_H
+#ifndef STM32F2xx_HAL_HCD_H
+#define STM32F2xx_HAL_HCD_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_usb.h"
-   
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
@@ -54,15 +37,15 @@
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup HCD_Exported_Types HCD Exported Types
   * @{
   */
 
-/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition 
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
   * @{
   */
-typedef enum 
+typedef enum
 {
   HAL_HCD_STATE_RESET    = 0x00,
   HAL_HCD_STATE_READY    = 0x01,
@@ -73,24 +56,41 @@ typedef enum
 
 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef       HCD_HCTypeDef ;   
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
-typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef ;
+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
 /**
   * @}
   */
 
 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
   * @{
-  */ 
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+typedef struct __HCD_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
 {
   HCD_TypeDef               *Instance;  /*!< Register base address    */
   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
-  HCD_HCTypeDef             hc[15];     /*!< Host channels parameters */
+  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */
   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
+  __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */
   void                      *pData;     /*!< Pointer Stack Handler    */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */
+  void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */
+  void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */
+  void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */
+  void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */
+  void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
+                                      HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */
+
+  void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
 } HCD_HandleTypeDef;
 /**
   * @}
@@ -98,7 +98,7 @@ typedef struct
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup HCD_Exported_Constants HCD Exported Constants
@@ -108,9 +108,10 @@ typedef struct
 /** @defgroup HCD_Speed HCD Speed
   * @{
   */
-#define HCD_SPEED_HIGH               0
-#define HCD_SPEED_LOW                2  
-#define HCD_SPEED_FULL               3
+#define HCD_SPEED_HIGH               USBH_HS_SPEED
+#define HCD_SPEED_FULL               USBH_FS_SPEED
+#define HCD_SPEED_LOW                USBH_LS_SPEED
+
 /**
   * @}
   */
@@ -118,33 +119,45 @@ typedef struct
 /** @defgroup HCD_PHY_Module HCD PHY Module
   * @{
   */
-#define HCD_PHY_ULPI                 1
-#define HCD_PHY_EMBEDDED             2
+#define HCD_PHY_ULPI                 1U
+#define HCD_PHY_EMBEDDED             2U
+/**
+  * @}
+  */
+
+/** @defgroup HCD_Error_Code_definition HCD Error Code definition
+  * @brief  HCD Error Code definition
+  * @{
+  */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup HCD_Exported_Macros HCD Exported Macros
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
-#define __HAL_HCD_ENABLE(__HANDLE__)               USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__)              USB_DisableGlobalInt ((__HANDLE__)->Instance)
-   
+#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)    
-  
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) 
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) 
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) 
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) 
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) 
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
 /**
   * @}
   */
@@ -154,24 +167,63 @@ typedef struct
   * @{
   */
 
-/* Initialization/de-initialization functions  ********************************/
-/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+                                       uint8_t ch_num,
+                                       uint8_t epnum,
+                                       uint8_t dev_address,
+                                       uint8_t speed,
+                                       uint8_t ep_type,
+                                       uint16_t mps);
+
+HAL_StatusTypeDef     HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+void                  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
+void                  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
+  * @brief  HAL USB OTG HCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_HCD_SOF_CB_ID           = 0x01,       /*!< USB HCD SOF callback ID           */
+  HAL_HCD_CONNECT_CB_ID       = 0x02,       /*!< USB HCD Connect callback ID       */
+  HAL_HCD_DISCONNECT_CB_ID   = 0x03,       /*!< USB HCD Disconnect callback ID    */
+  HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,      /*!< USB HCD Port Enable callback ID   */
+  HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,      /*!< USB HCD Port Disable callback ID  */
+
+  HAL_HCD_MSPINIT_CB_ID       = 0x06,       /*!< USB HCD MspInit callback ID       */
+  HAL_HCD_MSPDEINIT_CB_ID     = 0x07        /*!< USB HCD MspDeInit callback ID     */
+
+} HAL_HCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
+  * @brief  HAL USB OTG HCD Callback pointer definition
   * @{
   */
-HAL_StatusTypeDef   HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef   HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef   HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
-                                    uint8_t ch_num,
-                                    uint8_t epnum,
-                                    uint8_t dev_address,
-                                    uint8_t speed,
-                                    uint8_t ep_type,
-                                    uint16_t mps);
 
-HAL_StatusTypeDef   HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */
+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
+                                                       uint8_t epnum,
+                                                       HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
 
-void                HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -180,23 +232,25 @@ void                HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
-HAL_StatusTypeDef   HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
-                                             uint8_t pipe, 
-                                             uint8_t direction,
-                                             uint8_t ep_type,  
-                                             uint8_t token, 
-                                             uint8_t* pbuff, 
-                                             uint16_t length,
-                                             uint8_t do_ping);
+HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
+                                                 uint8_t ch_num,
+                                                 uint8_t direction,
+                                                 uint8_t ep_type,
+                                                 uint8_t token,
+                                                 uint8_t *pbuff,
+                                                 uint16_t length,
+                                                 uint8_t do_ping);
 
 /* Non-Blocking mode: Interrupt */
-void                HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void                HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void                HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void                HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void                HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, 
-                                                        uint8_t chnum, 
-                                                        HCD_URBStateTypeDef urb_state);
+void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+                                                     uint8_t chnum,
+                                                     HCD_URBStateTypeDef urb_state);
 /**
   * @}
   */
@@ -205,9 +259,9 @@ void                HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
-HAL_StatusTypeDef   HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef   HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef   HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
+HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
 /**
   * @}
   */
@@ -216,12 +270,12 @@ HAL_StatusTypeDef   HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
-HCD_StateTypeDef    HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t            HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t            HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 /**
   * @}
   */
@@ -234,15 +288,25 @@ uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 /** @defgroup HCD_Private_Macros HCD Private Macros
  * @{
  */
-/** @defgroup HCD_Instance_definition HCD Instance definition
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
   * @{
   */
- #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
+
 /**
   * @}
   */
 
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup HCD_Private_Functions HCD Private Functions
+  * @{
+  */
+
 /**
   * @}
   */
@@ -253,12 +317,13 @@ uint32_t            HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 
 /**
   * @}
-  */ 
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_HCD_H */
+#endif /* STM32F2xx_HAL_HCD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h
index 0027617e..4aeed36a 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -40,7 +22,7 @@
 #define __STM32F2xx_HAL_I2C_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -58,9 +40,10 @@
 /** @defgroup I2C_Exported_Types I2C Exported Types
   * @{
   */
-   
-/**
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
   * @brief  I2C Configuration Structure definition
+  * @{
   */
 typedef struct
 {
@@ -88,79 +71,218 @@ typedef struct
   uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
                                   This parameter can be a value of @ref I2C_nostretch_mode */
 
-}I2C_InitTypeDef;
+} I2C_InitTypeDef;
 
 /**
-  * @brief  HAL State structures definition
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @note  HAL I2C State value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : Abort (Abort user request on going)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initilisation status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
+  *          b4     (not used)
+  *             x  : Should be set to 0
+  *          b3
+  *             0  : Ready or Busy (No Listen mode ongoing)
+  *             1  : Listen (Peripheral in Address Listen Mode)
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  * @{
   */
 typedef enum
 {
-  HAL_I2C_STATE_RESET             = 0x00,  /*!< I2C not yet initialized or disabled         */
-  HAL_I2C_STATE_READY             = 0x01,  /*!< I2C initialized and ready for use           */
-  HAL_I2C_STATE_BUSY              = 0x02,  /*!< I2C internal process is ongoing             */
-  HAL_I2C_STATE_BUSY_TX           = 0x12,  /*!< Data Transmission process is ongoing        */
-  HAL_I2C_STATE_BUSY_RX           = 0x22,  /*!< Data Reception process is ongoing           */
-  HAL_I2C_STATE_MEM_BUSY_TX       = 0x32,  /*!< Memory Data Transmission process is ongoing */
-  HAL_I2C_STATE_MEM_BUSY_RX       = 0x42,  /*!< Memory Data Reception process is ongoing    */
-  HAL_I2C_STATE_TIMEOUT           = 0x03,  /*!< I2C timeout state                           */
-  HAL_I2C_STATE_ERROR             = 0x04   /*!< I2C error state                             */
+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                         */
+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
+
+} HAL_I2C_StateTypeDef;
 
-}HAL_I2C_StateTypeDef;
+/**
+  * @}
+  */
 
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @note  HAL I2C Mode value coding follow below described bitmap :\n
+  *          b7     (not used)\n
+  *             x  : Should be set to 0\n
+  *          b6\n
+  *             0  : None\n
+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
+  *          b5\n
+  *             0  : None\n
+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
+  *          b4\n
+  *             0  : None\n
+  *             1  : Master (HAL I2C communication is in Master Mode)\n
+  *          b3-b2-b1-b0  (not used)\n
+  *             xxxx : Should be set to 0000
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
+
+} HAL_I2C_ModeTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */
+#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */
+#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */
+#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 /**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
   * @brief  I2C handle Structure definition
+  * @{
   */
-typedef struct
+typedef struct __I2C_HandleTypeDef
 {
-  I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
+  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
+
+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
+
+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
+
+  uint16_t                   XferSize;       /*!< I2C transfer size                        */
+
+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
+
+  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
+
+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
+                                                  context for internal usage               */
+
+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
+
+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
+
+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
 
-  I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
 
-  uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
 
-  uint16_t                   XferSize;   /*!< I2C transfer size              */
+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
 
-  __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
 
-  DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
 
-  DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
+  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
 
-  HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
+  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
 
-  __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
 
-  __IO uint32_t              ErrorCode;  /*!<  I2C Error code                */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
 
-}I2C_HandleTypeDef;
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+
+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
+} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
 /**
-  * @}
+  * @brief  HAL I2C Callback ID enumeration definition
   */
+typedef enum
+{
+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2C Callback pointer definition
+  */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+/**
+  * @}
   */
 
-/** @defgroup I2C_Error_Code I2C Error Code
-  * @brief    I2C Error Code 
-  * @{
-  */ 
-#define HAL_I2C_ERROR_NONE       ((uint32_t)0x00000000)    /*!< No error           */
-#define HAL_I2C_ERROR_BERR       ((uint32_t)0x00000001)    /*!< BERR error         */
-#define HAL_I2C_ERROR_ARLO       ((uint32_t)0x00000002)    /*!< ARLO error         */
-#define HAL_I2C_ERROR_AF         ((uint32_t)0x00000004)    /*!< AF error           */
-#define HAL_I2C_ERROR_OVR        ((uint32_t)0x00000008)    /*!< OVR error          */
-#define HAL_I2C_ERROR_DMA        ((uint32_t)0x00000010)    /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT    ((uint32_t)0x00000020)    /*!< Timeout Error      */
 /**
   * @}
   */
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
 
 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
   * @{
   */
-#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_2                 0x00000000U
 #define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
 /**
   * @}
@@ -169,8 +291,8 @@ typedef struct
 /** @defgroup I2C_addressing_mode I2C addressing mode
   * @{
   */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+#define I2C_ADDRESSINGMODE_7BIT         0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
 /**
   * @}
   */
@@ -178,7 +300,7 @@ typedef struct
 /** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
   * @{
   */
-#define I2C_DUALADDRESS_DISABLE        ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_DISABLE        0x00000000U
 #define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
 /**
   * @}
@@ -187,7 +309,7 @@ typedef struct
 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
   * @{
   */
-#define I2C_GENERALCALL_DISABLE        ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_DISABLE        0x00000000U
 #define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
 /**
   * @}
@@ -196,7 +318,7 @@ typedef struct
 /** @defgroup I2C_nostretch_mode I2C nostretch mode
   * @{
   */
-#define I2C_NOSTRETCH_DISABLE          ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_DISABLE          0x00000000U
 #define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
 /**
   * @}
@@ -205,13 +327,44 @@ typedef struct
 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
   * @{
   */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010)
+#define I2C_MEMADD_SIZE_8BIT            0x00000001U
+#define I2C_MEMADD_SIZE_16BIT           0x00000010U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+  * @{
+  */
+#define I2C_DIRECTION_RECEIVE           0x00000000U
+#define I2C_DIRECTION_TRANSMIT          0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+  * @{
+  */
+#define  I2C_FIRST_FRAME                0x00000001U
+#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U
+#define  I2C_NEXT_FRAME                 0x00000004U
+#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U
+#define  I2C_LAST_FRAME_NO_STOP         0x00000010U
+#define  I2C_LAST_FRAME                 0x00000020U
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define  I2C_OTHER_FRAME                (0x00AA0000U)
+#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)
 /**
   * @}
   */
 
 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
   * @{
   */
 #define I2C_IT_BUF                      I2C_CR2_ITBUFEN
@@ -224,27 +377,23 @@ typedef struct
 /** @defgroup I2C_Flag_definition I2C Flag definition
   * @{
   */
-#define I2C_FLAG_SMBALERT               ((uint32_t)0x00018000)
-#define I2C_FLAG_TIMEOUT                ((uint32_t)0x00014000)
-#define I2C_FLAG_PECERR                 ((uint32_t)0x00011000)
-#define I2C_FLAG_OVR                    ((uint32_t)0x00010800)
-#define I2C_FLAG_AF                     ((uint32_t)0x00010400)
-#define I2C_FLAG_ARLO                   ((uint32_t)0x00010200)
-#define I2C_FLAG_BERR                   ((uint32_t)0x00010100)
-#define I2C_FLAG_TXE                    ((uint32_t)0x00010080)
-#define I2C_FLAG_RXNE                   ((uint32_t)0x00010040)
-#define I2C_FLAG_STOPF                  ((uint32_t)0x00010010)
-#define I2C_FLAG_ADD10                  ((uint32_t)0x00010008)
-#define I2C_FLAG_BTF                    ((uint32_t)0x00010004)
-#define I2C_FLAG_ADDR                   ((uint32_t)0x00010002)
-#define I2C_FLAG_SB                     ((uint32_t)0x00010001)
-#define I2C_FLAG_DUALF                  ((uint32_t)0x00100080)
-#define I2C_FLAG_SMBHOST                ((uint32_t)0x00100040)
-#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00100020)
-#define I2C_FLAG_GENCALL                ((uint32_t)0x00100010)
-#define I2C_FLAG_TRA                    ((uint32_t)0x00100004)
-#define I2C_FLAG_BUSY                   ((uint32_t)0x00100002)
-#define I2C_FLAG_MSL                    ((uint32_t)0x00100001)
+
+#define I2C_FLAG_OVR                    0x00010800U
+#define I2C_FLAG_AF                     0x00010400U
+#define I2C_FLAG_ARLO                   0x00010200U
+#define I2C_FLAG_BERR                   0x00010100U
+#define I2C_FLAG_TXE                    0x00010080U
+#define I2C_FLAG_RXNE                   0x00010040U
+#define I2C_FLAG_STOPF                  0x00010010U
+#define I2C_FLAG_ADD10                  0x00010008U
+#define I2C_FLAG_BTF                    0x00010004U
+#define I2C_FLAG_ADDR                   0x00010002U
+#define I2C_FLAG_SB                     0x00010001U
+#define I2C_FLAG_DUALF                  0x00100080U
+#define I2C_FLAG_GENCALL                0x00100010U
+#define I2C_FLAG_TRA                    0x00100004U
+#define I2C_FLAG_BUSY                   0x00100002U
+#define I2C_FLAG_MSL                    0x00100001U
 /**
   * @}
   */
@@ -253,35 +402,41 @@ typedef struct
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
 /** @defgroup I2C_Exported_Macros I2C Exported Macros
   * @{
   */
 
-/** @brief Reset I2C handle state
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
 
 /** @brief  Enable or disable the specified I2C interrupts.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *         This parameter can be one of the following values:
   *            @arg I2C_IT_BUF: Buffer interrupt enable
   *            @arg I2C_IT_EVT: Event interrupt enable
   *            @arg I2C_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 
 /** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2C_IT_BUF: Buffer interrupt enable
   *            @arg I2C_IT_EVT: Event interrupt enable
@@ -291,13 +446,9 @@ typedef struct
 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2C flag is set or not.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
-  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
   *            @arg I2C_FLAG_AF: Acknowledge failure flag
   *            @arg I2C_FLAG_ARLO: Arbitration lost flag
@@ -311,25 +462,20 @@ typedef struct
   *                                Address matched flag
   *            @arg I2C_FLAG_SB: Start bit flag
   *            @arg I2C_FLAG_DUALF: Dual flag
-  *            @arg I2C_FLAG_SMBHOST: SMBus host header
-  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
   *            @arg I2C_FLAG_GENCALL: General call header flag
   *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
   *            @arg I2C_FLAG_BUSY: Bus busy flag
   *            @arg I2C_FLAG_MSL: Master/Slave flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
-                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
+                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
+                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
 
 /** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
   *         This parameter can be any combination of the following values:
-  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
-  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
-  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
   *            @arg I2C_FLAG_AF: Acknowledge failure flag
   *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
@@ -339,33 +485,41 @@ typedef struct
 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
 
 /** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
+  * @param  __HANDLE__ specifies the I2C Handle.
   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
   * @retval None
   */
 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
   do{                                           \
-    __IO uint32_t tmpreg;                       \
+    __IO uint32_t tmpreg = 0x00U;               \
     tmpreg = (__HANDLE__)->Instance->SR1;       \
     tmpreg = (__HANDLE__)->Instance->SR2;       \
     UNUSED(tmpreg);                             \
   } while(0)
 
 /** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)    \
-  do{                                           \
-    __IO uint32_t tmpreg;                       \
-    tmpreg = (__HANDLE__)->Instance->SR1;       \
-    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
-    UNUSED(tmpreg);                             \
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \
+  do{                                                  \
+    __IO uint32_t tmpreg = 0x00U;                      \
+    tmpreg = (__HANDLE__)->Instance->SR1;              \
+    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \
+    UNUSED(tmpreg);                                    \
   } while(0)
-    
-#define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
-#define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
+
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
 
 /**
   * @}
@@ -376,22 +530,31 @@ typedef struct
   * @{
   */
 
-/** @addtogroup I2C_Exported_Functions_Group1
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
-/* Initialization/de-initialization functions  **********************************/
+/* Initialization and de-initialization functions******************************/
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @addtogroup I2C_Exported_Functions_Group2
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
-/* I/O operation functions  *****************************************************/
+/* IO operation functions  ****************************************************/
 /******* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -409,6 +572,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
 /******* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@@ -417,6 +588,17 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
 
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -424,18 +606,22 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
 /**
   * @}
   */
 
-/** @addtogroup I2C_Exported_Functions_Group3
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
   * @{
   */
-/* Peripheral Control and State functions  **************************************/
+/* Peripheral State, Mode and Error functions  *********************************/
 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 /**
@@ -451,7 +637,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /** @defgroup I2C_Private_Constants I2C Private Constants
   * @{
   */
-#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFF)
+#define I2C_FLAG_MASK                    0x0000FFFFU
+#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */
+#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */
 /**
   * @}
   */
@@ -460,24 +648,26 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 /** @defgroup I2C_Private_Macros I2C Private Macros
   * @{
   */
-    
-#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+
+#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
+#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
+#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
 
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
 #define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
 
-#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
 
-#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
 
 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
   * @{
@@ -494,9 +684,22 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
                                     ((STRETCH) == I2C_NOSTRETCH_ENABLE))
 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                   ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
+                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \
+                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
+                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
+                                                       ((REQUEST) == I2C_LAST_FRAME)               || \
+                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \
+                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h
index cc6c8819..0b79b488 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h
@@ -2,49 +2,31 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_I2S_H
-#define __STM32F2xx_HAL_I2S_H
+#ifndef STM32F2xx_HAL_I2S_H
+#define STM32F2xx_HAL_I2S_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"  
+#include "stm32f2xx_hal_def.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -52,187 +34,217 @@
 
 /** @addtogroup I2S
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup I2S_Exported_Types I2S Exported Types
   * @{
   */
-  
-/** 
-  * @brief I2S Init structure definition  
+
+/**
+  * @brief I2S Init structure definition
   */
 typedef struct
 {
-  uint32_t Mode;         /*!< Specifies the I2S operating mode.
-                              This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
-                              This parameter can be a value of @ref I2S_Standard */
+  uint32_t Mode;                /*!< Specifies the I2S operating mode.
+                                     This parameter can be a value of @ref I2S_Mode */
 
-  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
-                              This parameter can be a value of @ref I2S_Data_Format */
+  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Standard */
 
-  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                              This parameter can be a value of @ref I2S_MCLK_Output */
+  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Data_Format */
 
-  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                              This parameter can be a value of @ref I2S_Audio_Frequency */
+  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                     This parameter can be a value of @ref I2S_MCLK_Output */
 
-  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
-                              This parameter can be a value of @ref I2S_Clock_Polarity */
+  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
+                                     This parameter can be a value of @ref I2S_Audio_Frequency */
 
-  uint32_t ClockSource;  /*!< Specifies the I2S Clock Source.
-                              This parameter can be a value of @ref I2S_Clock_Source */
+  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
+                                     This parameter can be a value of @ref I2S_Clock_Polarity */
 
-}I2S_InitTypeDef;
+  uint32_t ClockSource;     /*!< Specifies the I2S Clock Source.
+                                 This parameter can be a value of @ref I2S_Clock_Source */
+} I2S_InitTypeDef;
 
-/** 
+/**
   * @brief  HAL State structures definition
-  */ 
+  */
 typedef enum
 {
-  HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_I2S_STATE_TIMEOUT    = 0x03,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x04   /*!< I2S error state                                    */
-
-}HAL_I2S_StateTypeDef;
+  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
+  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
+  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
+  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
+  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
+  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
+  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
+} HAL_I2S_StateTypeDef;
 
-/** 
-  * @brief I2S handle Structure definition  
+/**
+  * @brief I2S handle Structure definition
   */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
+typedef struct __I2S_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 {
-  SPI_TypeDef                *Instance;    /* I2S registers base address        */
-
-  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
-  
-  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
-  
-  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
-  
-  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
-  
-  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
-  
-  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
-  
-  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter           */
-
-  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
-
-  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
-  
-  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
-  
-  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
-  
-  __IO uint32_t              ErrorCode;    /* I2S Error code                    */
-  
-}I2S_HandleTypeDef;
+  SPI_TypeDef                *Instance;    /*!< I2S registers base address */
+
+  I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
+
+  uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
+
+  __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
+
+  __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
+
+  uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
+
+  __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
+
+  __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
+                                              (This field is initialized at the
+                                               same value as transfer size at the
+                                               beginning of the transfer and
+                                               decremented when a sample is received
+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
+  DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
+
+  DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
+
+  __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
+
+  __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
+
+  __IO uint32_t              ErrorCode;    /*!< I2S Error code
+                                                This parameter can be a value of @ref I2S_Error */
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
+  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
+  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
+  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
+  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
+  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
+  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
+
+#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
 /**
-  * @}
+  * @brief  HAL I2S Callback ID enumeration definition
   */
+typedef enum
+{
+  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
+  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
+  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
+  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
+  HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
+  HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
+  HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
+} HAL_I2S_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL I2S Callback pointer definition
   */
+typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
 
-/** @defgroup I2S_Error_Code I2S Error Code
-  * @brief    I2S Error Code 
-  * @{
-  */ 
-#define HAL_I2S_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error                    */
-#define HAL_I2S_ERROR_UDR           ((uint32_t)0x00000001)    /*!< I2S Underrun error          */
-#define HAL_I2S_ERROR_OVR           ((uint32_t)0x00000002)    /*!< I2S Overrun error           */
-#define HAL_I2SEX_ERROR_UDR         ((uint32_t)0x00000004)    /*!< I2S extended Underrun error */
-#define HAL_I2SEX_ERROR_OVR         ((uint32_t)0x00000008)    /*!< I2S extended Overrun error  */
-#define HAL_I2S_ERROR_FRE           ((uint32_t)0x00000010)    /*!< I2S Frame format error      */
-#define HAL_I2S_ERROR_DMA           ((uint32_t)0x00000020)    /*!< DMA transfer error          */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @defgroup I2S_Clock_Source I2S Clock Source 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_Exported_Constants I2S Exported Constants
+  * @{
+  */
+/** @defgroup I2S_Error I2S Error
   * @{
   */
-#define I2S_CLOCK_PLL                     ((uint32_t)0x00000000)
-#define I2S_CLOCK_EXTERNAL                ((uint32_t)0x00000001)
+#define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
+#define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
+#define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
+#define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
+#define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
+#define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @defgroup I2S_Mode I2S Mode 
+/** @defgroup I2S_Mode I2S Mode
   * @{
   */
-#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
-#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
-#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
-#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
+#define I2S_MODE_SLAVE_TX                (0x00000000U)
+#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
 /**
   * @}
   */
-  
+
 /** @defgroup I2S_Standard I2S Standard
   * @{
   */
-#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
-#define I2S_STANDARD_MSB                 ((uint32_t)0x00000010)
-#define I2S_STANDARD_LSB                 ((uint32_t)0x00000020)
-#define I2S_STANDARD_PCM_SHORT           ((uint32_t)0x00000030)
-#define I2S_STANDARD_PCM_LONG            ((uint32_t)0x000000B0)
+#define I2S_STANDARD_PHILIPS             (0x00000000U)
+#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
 /**
   * @}
   */
-  
+
 /** @defgroup I2S_Data_Format I2S Data Format
   * @{
   */
-#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)0x00000001)
-#define I2S_DATAFORMAT_24B               ((uint32_t)0x00000003)
-#define I2S_DATAFORMAT_32B               ((uint32_t)0x00000005)
+#define I2S_DATAFORMAT_16B               (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
 /**
   * @}
   */
 
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
   * @{
   */
-#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
+#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
 /**
   * @}
   */
 
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency 
+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
   * @{
   */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
+#define I2S_AUDIOFREQ_192K               (192000U)
+#define I2S_AUDIOFREQ_96K                (96000U)
+#define I2S_AUDIOFREQ_48K                (48000U)
+#define I2S_AUDIOFREQ_44K                (44100U)
+#define I2S_AUDIOFREQ_32K                (32000U)
+#define I2S_AUDIOFREQ_22K                (22050U)
+#define I2S_AUDIOFREQ_16K                (16000U)
+#define I2S_AUDIOFREQ_11K                (11025U)
+#define I2S_AUDIOFREQ_8K                 (8000U)
+#define I2S_AUDIOFREQ_DEFAULT            (2U)
 /**
   * @}
   */
 
-/** @defgroup I2S_Clock_Polarity  I2S Clock Polarity
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
   * @{
   */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
-#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
+#define I2S_CPOL_LOW                     (0x00000000U)
+#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
 /**
   * @}
   */
@@ -240,9 +252,9 @@ typedef struct
 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
   * @{
   */
-#define I2S_IT_TXE                      SPI_CR2_TXEIE
-#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
-#define I2S_IT_ERR                      SPI_CR2_ERRIE
+#define I2S_IT_TXE                       SPI_CR2_TXEIE
+#define I2S_IT_RXNE                      SPI_CR2_RXNEIE
+#define I2S_IT_ERR                       SPI_CR2_ERRIE
 /**
   * @}
   */
@@ -250,68 +262,103 @@ typedef struct
 /** @defgroup I2S_Flags_Definition I2S Flags Definition
   * @{
   */
-#define I2S_FLAG_TXE                    SPI_SR_TXE
-#define I2S_FLAG_RXNE                   SPI_SR_RXNE
+#define I2S_FLAG_TXE                     SPI_SR_TXE
+#define I2S_FLAG_RXNE                    SPI_SR_RXNE
+
+#define I2S_FLAG_UDR                     SPI_SR_UDR
+#define I2S_FLAG_OVR                     SPI_SR_OVR
+#define I2S_FLAG_FRE                     SPI_SR_FRE
 
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define I2S_FLAG_OVR                    SPI_SR_OVR
-#define I2S_FLAG_FRE                    SPI_SR_FRE
+#define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
+#define I2S_FLAG_BSY                     SPI_SR_BSY
 
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                    SPI_SR_BSY
+#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
+                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
 /**
   * @}
   */
 
+/** @defgroup I2S_Clock_Source I2S Clock Source
+  * @{
+  */
+#define I2S_CLOCK_PLL                     0x00000000U
+#define I2S_CLOCK_EXTERNAL                0x00000001U
 /**
   * @}
-  */ 
+  */
+/**
+  * @}
+  */
 
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup I2S_Exported_macros I2S Exported Macros
   * @{
   */
 
-/** @brief Reset I2S handle state
-  * @param  __HANDLE__: specifies the I2S Handle.
+/** @brief  Reset I2S handle state
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
+                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 
-/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
+/** @brief  Enable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief  Disable the specified SPI peripheral (in I2S mode).
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @retval None
+  */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief  Enable the specified I2S interrupts.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
 
-/** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+/** @brief  Disable the specified I2S interrupts.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *         This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg I2S_IT_ERR: Error interrupt enable
   * @retval None
-  */  
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
- 
+  */
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg I2S_IT_ERR: Error interrupt enable
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the I2S Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -325,31 +372,28 @@ typedef struct
 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg;                       \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    UNUSED(tmpreg);                             \
-  } while(0)
-    
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
+                                                __IO uint32_t tmpreg_ovr = 0x00U; \
+                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+                                                UNUSED(tmpreg_ovr); \
+                                              }while(0U)
 /** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
-  do{                                             \
-  __IO uint32_t tmpreg;                         \
-  tmpreg = (__HANDLE__)->Instance->SR;          \
-  UNUSED(tmpreg);                               \
-  } while(0)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
+                                                __IO uint32_t tmpreg_udr = 0x00U;\
+                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+                                                UNUSED(tmpreg_udr); \
+                                              }while(0U)
 /**
   * @}
   */
-  
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup I2S_Exported_Functions
   * @{
@@ -358,11 +402,18 @@ typedef struct
 /** @addtogroup I2S_Exported_Functions_Group1
   * @{
   */
-/* Initialization/de-initialization functions  **********************************/
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -370,12 +421,12 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
 /** @addtogroup I2S_Exported_Functions_Group2
   * @{
   */
-/* I/O operation functions  *****************************************************/
+/* I/O operation functions  ***************************************************/
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
 
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
@@ -388,10 +439,6 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
 
-/* Peripheral Control and State functions  **************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-
 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
@@ -400,7 +447,17 @@ void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
 /**
   * @}
-  */ 
+  */
+
+/** @addtogroup I2S_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control and State functions  ************************************/
+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -409,72 +466,92 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
   * @{
   */
 
-/**
-  * @}
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __SR__  copy of I2S SR regsiter.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
+  *            @arg I2S_FLAG_UDR: Underrun error flag
+  *            @arg I2S_FLAG_OVR: Overrun flag
+  *            @arg I2S_FLAG_CHSIDE: Channel side flag
+  *            @arg I2S_FLAG_BSY: Busy flag
+  * @retval SET or RESET.
   */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
+                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
+/** @brief  Check whether the specified SPI Interrupt is set or not.
+  * @param  __CR2__  copy of I2S CR2 regsiter.
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg I2S_IT_ERR: Error interrupt enable
+  * @retval SET or RESET.
   */
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
-                                   ((CLOCK) == I2S_CLOCK_PLL))
-                                   
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
-                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
-                           ((MODE) == I2S_MODE_MASTER_TX) || \
-                           ((MODE) == I2S_MODE_MASTER_RX))
-                           
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
-                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
-                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-                                    
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
-                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
-                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
-                           ((CPOL) == I2S_CPOL_HIGH))
- 
-/**
-  * @}
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
+                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks if I2S Mode parameter is in allowed range.
+  * @param  __MODE__ specifies the I2S Mode.
+  *         This parameter can be a value of @ref I2S_Mode
+  * @retval None
   */
+#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
+                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
+                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
+                               ((__MODE__) == I2S_MODE_MASTER_RX))
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
+#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
+                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
+                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
+                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
+                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
+                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
+                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
+                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
+                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
+                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+
+/** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
+  * @param  __CPOL__ specifies the I2S serial clock steady state.
+  *         This parameter can be a value of @ref I2S_Clock_Polarity
+  * @retval None
   */
+#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
+                               ((__CPOL__) == I2S_CPOL_HIGH))
+
+#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
+                                   ((CLOCK) == I2S_CLOCK_PLL))
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */  
+  */
 
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /* __STM32F2xx_HAL_I2S_H */
+#endif /* STM32F2xx_HAL_I2S_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h
index a6da289d..0737aad2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of IRDA HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_IRDA_H
 #define __STM32F2xx_HAL_IRDA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,15 +34,15 @@
 
 /** @addtogroup IRDA
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup IRDA_Exported_Types IRDA Exported Types
   * @{
   */
-/** 
-  * @brief IRDA Init Structure definition  
-  */ 
+/**
+  * @brief IRDA Init Structure definition
+  */
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
@@ -71,70 +53,177 @@ typedef struct
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
                                            This parameter can be a value of @ref IRDA_Word_Length */
 
-
-  uint32_t Parity;                   /*!< Specifies the parity mode.
+  uint32_t Parity;                    /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref IRDA_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref IRDA_Mode */
-                                            
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler */
-  
+
+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value to be programmed
+                                           in the IrDA low-power Baud Register, for defining pulse width on which
+                                           burst acceptance/rejection will be decided. This value is used as divisor
+                                           of system clock to achieve required pulse width. */
+
   uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
                                            This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
+} IRDA_InitTypeDef;
 
-/** 
-  * @brief HAL State structures definition  
-  */ 
+/**
+  * @brief HAL IRDA State structures definition
+  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains IRDA state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
 typedef enum
 {
-  HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
-  HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_IRDA_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
-  HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_IRDA_StateTypeDef;
-
-/** 
-  * @brief IRDA handle Structure definition  
-  */  
+  HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error
+                                                   Value is allowed for gState only */
+} HAL_IRDA_StateTypeDef;
+
+/**
+  * @brief IRDA handle Structure definition
+  */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
 typedef struct
+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 {
-  USART_TypeDef               *Instance;        /* USART registers base address       */
-  
-  IRDA_InitTypeDef            Init;             /* IRDA communication parameters      */
-  
-  uint8_t                     *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
-  
-  uint16_t                    TxXferSize;       /* IRDA Tx Transfer size              */
-  
-  uint16_t                    TxXferCount;      /* IRDA Tx Transfer Counter           */
-  
-  uint8_t                     *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
-  
-  uint16_t                    RxXferSize;       /* IRDA Rx Transfer size              */
-  
-  uint16_t                    RxXferCount;      /* IRDA Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef           *hdmatx;          /* IRDA Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef           *hdmarx;          /* IRDA Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef             Lock;             /* Locking object                     */
-  
-  __IO HAL_IRDA_StateTypeDef  State;            /* IRDA communication state           */
-  
-  __IO uint32_t               ErrorCode;        /* IRDA Error code                    */
-
-}IRDA_HandleTypeDef;
+  USART_TypeDef               *Instance;        /*!<  USART registers base address       */
+
+  IRDA_InitTypeDef            Init;             /*!<  IRDA communication parameters      */
+
+  uint8_t                     *pTxBuffPtr;      /*!<  Pointer to IRDA Tx transfer Buffer */
+
+  uint16_t                    TxXferSize;       /*!<  IRDA Tx Transfer size              */
+
+  __IO uint16_t               TxXferCount;      /*!<  IRDA Tx Transfer Counter           */
+
+  uint8_t                     *pRxBuffPtr;      /*!<  Pointer to IRDA Rx transfer Buffer */
+
+  uint16_t                    RxXferSize;       /*!<  IRDA Rx Transfer size              */
+
+  __IO uint16_t               RxXferCount;      /*!<  IRDA Rx Transfer Counter           */
+
+  DMA_HandleTypeDef           *hdmatx;          /*!<  IRDA Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef           *hdmarx;          /*!<  IRDA Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef             Lock;             /*!<  Locking object                     */
+
+  __IO HAL_IRDA_StateTypeDef  gState;           /*!<  IRDA state information related to global Handle management
+                                                   and also related to Tx operations.
+                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO HAL_IRDA_StateTypeDef  RxState;          /*!<  IRDA state information related to Rx operations.
+                                                   This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+  __IO uint32_t               ErrorCode;        /*!< IRDA Error code                    */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
+
+  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
+
+  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
+
+  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
+
+  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
+
+  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
+
+  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
+
+
+  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
+
+  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL IRDA Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
+  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
+  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
+  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
+  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
+  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
+  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
+  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
+
+  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
+  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL IRDA Callback pointer definition
+  */
+typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -144,15 +233,17 @@ typedef struct
   * @{
   */
 /** @defgroup IRDA_Error_Code IRDA Error Code
-  * @brief    IRDA Error Code 
   * @{
-  */ 
-#define HAL_IRDA_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
-#define HAL_IRDA_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
-#define HAL_IRDA_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
-#define HAL_IRDA_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
-#define HAL_IRDA_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
-#define HAL_IRDA_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
+  */
+#define HAL_IRDA_ERROR_NONE        0x00000000U   /*!< No error            */
+#define HAL_IRDA_ERROR_PE          0x00000001U   /*!< Parity error        */
+#define HAL_IRDA_ERROR_NE          0x00000002U   /*!< Noise error         */
+#define HAL_IRDA_ERROR_FE          0x00000004U   /*!< Frame error         */
+#define HAL_IRDA_ERROR_ORE         0x00000008U   /*!< Overrun error       */
+#define HAL_IRDA_ERROR_DMA         0x00000010U   /*!< DMA transfer error  */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)   /*!< Invalid Callback error  */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -160,28 +251,28 @@ typedef struct
 /** @defgroup IRDA_Word_Length IRDA Word Length
   * @{
   */
-#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define IRDA_WORDLENGTH_8B         0x00000000U
+#define IRDA_WORDLENGTH_9B         ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
 
 /** @defgroup IRDA_Parity  IRDA Parity
   * @{
-  */ 
-#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
-#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+  */
+#define IRDA_PARITY_NONE           0x00000000U
+#define IRDA_PARITY_EVEN           ((uint32_t)USART_CR1_PCE)
+#define IRDA_PARITY_ODD            ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup IRDA_Mode IRDA Transfer Mode 
+/** @defgroup IRDA_Mode IRDA Transfer Mode
   * @{
-  */ 
-#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+  */
+#define IRDA_MODE_RX               ((uint32_t)USART_CR1_RE)
+#define IRDA_MODE_TX               ((uint32_t)USART_CR1_TE)
+#define IRDA_MODE_TX_RX            ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
@@ -189,8 +280,8 @@ typedef struct
 /** @defgroup IRDA_Low_Power IRDA Low Power
   * @{
   */
-#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x00000000)
+#define IRDA_POWERMODE_LOWPOWER    ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL      0x00000000U
 /**
   * @}
   */
@@ -200,18 +291,18 @@ typedef struct
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define IRDA_FLAG_TXE                       ((uint32_t)0x00000080)
-#define IRDA_FLAG_TC                        ((uint32_t)0x00000040)
-#define IRDA_FLAG_RXNE                      ((uint32_t)0x00000020)
-#define IRDA_FLAG_IDLE                      ((uint32_t)0x00000010)
-#define IRDA_FLAG_ORE                       ((uint32_t)0x00000008)
-#define IRDA_FLAG_NE                        ((uint32_t)0x00000004)
-#define IRDA_FLAG_FE                        ((uint32_t)0x00000002)
-#define IRDA_FLAG_PE                        ((uint32_t)0x00000001)
+#define IRDA_FLAG_TXE              ((uint32_t)USART_SR_TXE)
+#define IRDA_FLAG_TC               ((uint32_t)USART_SR_TC)
+#define IRDA_FLAG_RXNE             ((uint32_t)USART_SR_RXNE)
+#define IRDA_FLAG_IDLE             ((uint32_t)USART_SR_IDLE)
+#define IRDA_FLAG_ORE              ((uint32_t)USART_SR_ORE)
+#define IRDA_FLAG_NE               ((uint32_t)USART_SR_NE)
+#define IRDA_FLAG_FE               ((uint32_t)USART_SR_FE)
+#define IRDA_FLAG_PE               ((uint32_t)USART_SR_PE)
 /**
   * @}
   */
-  
+
 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
   *        Elements values convention: 0xY000XXXX
   *           - XXXX  : Interrupt mask in the XX register
@@ -221,16 +312,16 @@ typedef struct
   *                 - 11: CR3 register
   * @{
   */
-#define IRDA_IT_PE                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define IRDA_IT_TXE                         ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define IRDA_IT_TC                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define IRDA_IT_RXNE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define IRDA_IT_PE                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define IRDA_IT_TXE                ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define IRDA_IT_TC                 ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define IRDA_IT_RXNE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE               ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
 
-#define IRDA_IT_LBD                         ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define IRDA_IT_LBD                ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
 
-#define IRDA_IT_CTS                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define IRDA_IT_ERR                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+#define IRDA_IT_CTS                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define IRDA_IT_ERR                ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
 /**
   * @}
   */
@@ -238,32 +329,45 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
   * @{
   */
 
-/** @brief Reset IRDA handle state
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief Reset IRDA handle gstate & RxState
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
-
-/** @brief  Flushes the IRDA DR register 
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
+
+/** @brief  Flush the IRDA DR register
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
   */
 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
 
-/** @brief  Checks whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+/** @brief  Check whether the specified IRDA flag is set or not.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
   *            @arg IRDA_FLAG_TC:   Transmission Complete flag
@@ -277,78 +381,78 @@ typedef struct
   */
 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clears the specified IRDA pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+/** @brief  Clear the specified IRDA pending flag.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+  *          error) and IDLE (Idle line detected) flags are cleared by software
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  * @note   TC flag can be also cleared by software sequence: a read operation to
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)     \
   do{                                           \
-    __IO uint32_t tmpreg;                       \
+    __IO uint32_t tmpreg = 0x00U;               \
     tmpreg = (__HANDLE__)->Instance->SR;        \
+    tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0)
+  } while(0U)
 
 /** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Enables or disables the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to check.
+/** @brief  Enable the specified IRDA interrupt.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg IRDA_IT_TC:   Transmission complete interrupt
@@ -358,57 +462,71 @@ typedef struct
   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
+/** @brief  Disable the specified IRDA interrupt.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg IRDA_IT_TC:   Transmission complete interrupt
+  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
+  *            @arg IRDA_IT_PE:   Parity Error interrupt
+  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-    
-/** @brief  Checks whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __IT__: specifies the IRDA interrupt source to check.
+
+/** @brief  Check whether the specified IRDA interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __IT__ specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
   *            @arg IRDA_IT_TC:  Transmission complete interrupt
   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
+  *            @arg IRDA_IT_ERR: Error interrupt
   *            @arg IRDA_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
 
 /** @brief  Macro to enable the IRDA's one bit sample method
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
-  */     
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+  */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the IRDA's one bit sample method
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
-  */      
+  */
 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
   *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_IRDA_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
 
 /** @brief  Disable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         IRDA Handle selects the USARTx or UARTy peripheral 
+  * @param  __HANDLE__ specifies the IRDA Handle.
+  *         IRDA Handle selects the USARTx or UARTy peripheral
   *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_IRDA_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+#define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
 
 /**
   * @}
@@ -418,7 +536,7 @@ typedef struct
 /** @addtogroup IRDA_Exported_Functions
   * @{
   */
-  
+
 /** @addtogroup IRDA_Exported_Functions_Group1
   * @{
   */
@@ -427,6 +545,13 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -444,12 +569,23 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
 /**
   * @}
   */
@@ -462,7 +598,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -476,14 +612,14 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
   */
 
 /** @brief IRDA interruptions flag mask
-  * 
-  */ 
+  *
+  */
 #define IRDA_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                   USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
 
-#define IRDA_CR1_REG_INDEX                  1    
-#define IRDA_CR2_REG_INDEX                  2    
-#define IRDA_CR3_REG_INDEX                  3 
+#define IRDA_CR1_REG_INDEX         1U
+#define IRDA_CR2_REG_INDEX         2U
+#define IRDA_CR3_REG_INDEX         3U
 /**
   * @}
   */
@@ -492,20 +628,31 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
   * @{
   */
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
-                                     ((LENGTH) == IRDA_WORDLENGTH_9B))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
-                                ((PARITY) == IRDA_PARITY_EVEN) || \
-                                ((PARITY) == IRDA_PARITY_ODD))
-#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
-                                 ((MODE) == IRDA_POWERMODE_NORMAL))
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201)
-
-#define IRDA_DIV(_PCLK_, _BAUD_)                  (((_PCLK_)*25)/(4*(_BAUD_)))
-#define IRDA_DIVMANT(_PCLK_, _BAUD_)              (IRDA_DIV((_PCLK_), (_BAUD_))/100)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_)              (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define IRDA_BRR(_PCLK_, _BAUD_)                  ((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+#define IS_IRDA_WORD_LENGTH(LENGTH)   (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+                                       ((LENGTH) == IRDA_WORDLENGTH_9B))
+
+#define IS_IRDA_PARITY(PARITY)        (((PARITY) == IRDA_PARITY_NONE) || \
+                                       ((PARITY) == IRDA_PARITY_EVEN) || \
+                                       ((PARITY) == IRDA_PARITY_ODD))
+
+#define IS_IRDA_MODE(MODE)            ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
+
+#define IS_IRDA_POWERMODE(MODE)       (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+                                       ((MODE) == IRDA_POWERMODE_NORMAL))
+
+#define IS_IRDA_BAUDRATE(BAUDRATE)    ((BAUDRATE) < 115201U)
+
+#define IRDA_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(4U*(_BAUD_)))
+
+#define IRDA_DIVMANT(_PCLK_, _BAUD_)  (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
+
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_)  (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define IRDA_BRR(_PCLK_, _BAUD_)      (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+                                        (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
 
 /**
   * @}
@@ -522,12 +669,12 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h
index a03716bb..a010fa5d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h
@@ -2,42 +2,24 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_IWDG_H
-#define __STM32F2xx_HAL_IWDG_H
+#ifndef STM32F2xx_HAL_IWDG_H
+#define STM32F2xx_HAL_IWDG_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -52,49 +34,35 @@
 
 /** @addtogroup IWDG
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup IWDG_Exported_Types IWDG Exported Types
   * @{
   */
-   
-/** 
-  * @brief  IWDG HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
-  HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
-  HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
-  HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
-  HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
-}HAL_IWDG_StateTypeDef;
 
 /** 
-  * @brief  IWDG Init structure definition  
-  */ 
+  * @brief  IWDG Init structure definition
+  */
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
                             This parameter can be a value of @ref IWDG_Prescaler */
-  
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
+
+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-}IWDG_InitTypeDef;
 
-/** 
-  * @brief  IWDG Handle Structure definition  
-  */ 
+} IWDG_InitTypeDef;
+
+/**
+  * @brief  IWDG Handle Structure definition
+  */
 typedef struct
 {
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
-  
+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
+
   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< IWDG Locking object      */
-  
-  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
+
 }IWDG_HandleTypeDef;
 
 /**
@@ -106,43 +74,20 @@ typedef struct
   * @{
   */
 
-/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
-  * @brief IWDG registers bit mask
+/** @defgroup IWDG_Prescaler IWDG Prescaler
   * @{
   */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define IWDG_KEY_RELOAD                            ((uint32_t)0xAAAA)  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                            ((uint32_t)0xCCCC)  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE               ((uint32_t)0x5555)  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE              ((uint32_t)0x0000)  /*!< IWDG KR Write Access Disable */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag_definition IWDG Flag definition
-  * @{
-  */ 
-#define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
+#define IWDG_PRESCALER_4                0x00000000U                   /*!< IWDG prescaler set to 4   */
+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
 /**
   * @}
   */
 
-/** @defgroup IWDG_Prescaler IWDG Prescaler
-  * @{
-  */ 
-#define IWDG_PRESCALER_4     ((uint8_t)0x00)  /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
-/**
-  * @}
-  */ 
-
 /**
   * @}
   */
@@ -152,120 +97,107 @@ typedef struct
   * @{
   */
 
-/** @brief Reset IWDG handle state
-  * @param  __HANDLE__: IWDG handle.
-  * @retval None
-  */
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
-
 /**
-  * @brief  Enables the IWDG peripheral.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Enable the IWDG peripheral.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
 
 /**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Reload IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR & IWDG_RLR registers disabled).
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
-  * @brief  Gets the selected IWDG's flag status.
-  * @param  __HANDLE__: IWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
-  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup IWDG_Exported_Functions
+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
   * @{
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group1
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
   * @{
   */
-/* Initialization/de-initialization functions  ********************************/
+/* Initialization/Start functions  ********************************************/
 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group2
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
   * @{
   */
 /* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
 /**
   * @}
   */
 
-/** @addtogroup IWDG_Exported_Functions_Group3
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
   * @{
   */
-/* Peripheral State functions  ************************************************/
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
 
 /**
-  * @}
+  * @brief  IWDG Key Register BitMask
   */
+#define IWDG_KEY_RELOAD                 0x0000AAAAU  /*!< IWDG Reload Counter Enable   */
+#define IWDG_KEY_ENABLE                 0x0000CCCCU  /*!< IWDG Peripheral Enable       */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555U  /*!< IWDG KR Write Access Enable  */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000U  /*!< IWDG KR Write Access Disable */
 
 /**
   * @}
-  */ 
+  */
 
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
 /** @defgroup IWDG_Private_Macros IWDG Private Macros
   * @{
   */
 
 /**
-  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
 
 /**
-  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
+  * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
+  * @param  __HANDLE__  IWDG handle
   * @retval None
   */
 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
 
-
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
-
 /**
-  * @}
+  * @brief  Check IWDG prescaler value.
+  * @param  __PRESCALER__  IWDG prescaler value
+  * @retval None
   */
+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
 
-/* Private define ------------------------------------------------------------*/
- /** @defgroup IWDG_Private_Constants IWDG Private Constants
-  * @{
+/**
+  * @brief  Check IWDG reload value.
+  * @param  __RELOAD__  IWDG reload value
+  * @retval None
   */
+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
 
 /**
   * @}
@@ -273,16 +205,17 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_IWDG_H */
+#endif /* STM32F2xx_HAL_IWDG_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h
index 1edf1e3f..2de16ae2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h
@@ -2,50 +2,32 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_NAND_H
-#define __STM32F2xx_HAL_NAND_H
+#ifndef STM32F2xx_HAL_NAND_H
+#define STM32F2xx_HAL_NAND_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-  #include "stm32f2xx_ll_fsmc.h"
 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_ll_fsmc.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -53,7 +35,7 @@
 
 /** @addtogroup NAND
   * @{
-  */ 
+  */
 
 /* Exported typedef ----------------------------------------------------------*/
 /* Exported types ------------------------------------------------------------*/
@@ -61,92 +43,139 @@
   * @{
   */
 
-/** 
+/**
   * @brief  HAL NAND State structures definition
   */
 typedef enum
 {
-  HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
-  HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
-  HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
-  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
-}HAL_NAND_StateTypeDef;
-   
-/** 
+  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
+  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
+  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
+  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
+} HAL_NAND_StateTypeDef;
+
+/**
   * @brief  NAND Memory electronic signature Structure definition
   */
 typedef struct
 {
   /*State = HAL_NAND_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+#endif
 
 /**
   * @}
@@ -156,43 +185,60 @@ typedef struct
 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
   * @{
   */
-    
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 
 /**
   * @}
   */
-  
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
   * @{
   */
 
 /* IO operation functions  ****************************************************/
-HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+
 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/* NAND callback registering/unregistering */
+HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
+#endif
+
 /**
   * @}
   */
 
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
 
@@ -204,8 +250,8 @@ HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
 /**
   * @}
   */
-    
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
 /* NAND State functions *******************************************************/
@@ -218,41 +264,41 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 /**
   * @}
   */
-    
+
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup NAND_Private_Constants NAND Private Constants
   * @{
   */
-#define NAND_DEVICE1               ((uint32_t)0x70000000) 
-#define NAND_DEVICE2               ((uint32_t)0x80000000) 
-#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
-
-#define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
-#define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A            ((uint8_t)0x00)
-#define NAND_CMD_AREA_B            ((uint8_t)0x01)
-#define NAND_CMD_AREA_C            ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0            ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
-#define NAND_CMD_ERASE0            ((uint8_t)0x60)
-#define NAND_CMD_ERASE1            ((uint8_t)0xD0)  
-#define NAND_CMD_READID            ((uint8_t)0x90)
-#define NAND_CMD_STATUS            ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
-#define NAND_CMD_RESET             ((uint8_t)0xFF)
+#define NAND_DEVICE1               ((uint32_t)0x70000000U)
+#define NAND_DEVICE2               ((uint32_t)0x80000000U)
+#define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
+
+#define CMD_AREA                   ((uint32_t)(1UL<<16U))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1UL<<17U))  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00U)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01U)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50U)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80U)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
+#define NAND_CMD_ERASE0            ((uint8_t)0x60U)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
+#define NAND_CMD_READID            ((uint8_t)0x90U)
+#define NAND_CMD_STATUS            ((uint8_t)0x70U)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
+#define NAND_CMD_RESET             ((uint8_t)0xFFU)
 
 /* NAND memory status */
-#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
-#define NAND_BUSY                  ((uint32_t)0x00000000)
-#define NAND_ERROR                 ((uint32_t)0x00000001)
-#define NAND_READY                 ((uint32_t)0x00000040)
+#define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
+#define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
+#define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
+#define NAND_BUSY                  ((uint32_t)0x00000000U)
+#define NAND_ERROR                 ((uint32_t)0x00000001U)
+#define NAND_READY                 ((uint32_t)0x00000040U)
 /**
   * @}
   */
@@ -264,42 +310,59 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 
 /**
   * @brief  NAND memory address computation.
-  * @param  __ADDRESS__: NAND memory address.
-  * @param  __HANDLE__ : NAND handle.
+  * @param  __ADDRESS__ NAND memory address.
+  * @param  __HANDLE__  NAND handle.
   * @retval NAND Raw address value
   */
 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
-                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+/**
+  * @brief  NAND memory Column address computation.
+  * @param  __HANDLE__ NAND handle.
+  * @retval NAND Raw address value
+  */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 
 /**
   * @brief  NAND memory address cycling.
-  * @param  __ADDRESS__: NAND memory address.
+  * @param  __ADDRESS__ NAND memory address.
   * @retval NAND address cycling value.
   */
 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @brief  NAND memory Columns cycling.
+  * @param  __ADDRESS__ NAND memory address.
+  * @retval NAND Column address cycling value.
+  */
+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
+
 /**
   * @}
   */
 
-    
 /**
   * @}
   */
+
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
+
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_NAND_H */
+#endif /* STM32F2xx_HAL_NAND_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h
index c0b54eba..44e098ee 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h
@@ -2,50 +2,32 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_NOR_H
-#define __STM32F2xx_HAL_NOR_H
+#ifndef STM32F2xx_HAL_NOR_H
+#define STM32F2xx_HAL_NOR_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-  #include "stm32f2xx_ll_fsmc.h"
 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_ll_fsmc.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -53,35 +35,35 @@
 
 /** @addtogroup NOR
   * @{
-  */ 
+  */
 
 /* Exported typedef ----------------------------------------------------------*/
 /** @defgroup NOR_Exported_Types NOR Exported Types
   * @{
   */
 
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
+/**
+  * @brief  HAL SRAM State structures definition
+  */
 typedef enum
-{  
-  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
-  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
-  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
-  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
-}HAL_NOR_StateTypeDef;
+{
+  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
+  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
+  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
+  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
+} HAL_NOR_StateTypeDef;
 
 /**
   * @brief  FSMC NOR Status typedef
   */
 typedef enum
 {
-  HAL_NOR_STATUS_SUCCESS  = 0,
+  HAL_NOR_STATUS_SUCCESS  = 0U,
   HAL_NOR_STATUS_ONGOING,
   HAL_NOR_STATUS_ERROR,
   HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef;
+} HAL_NOR_StatusTypeDef;
 
 /**
   * @brief  FSMC NOR ID typedef
@@ -94,11 +76,11 @@ typedef struct
 
   uint16_t Device_Code2;
 
-  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
-                                    These codes can be accessed by performing read operations with specific 
-                                    control signals and addresses set.They can also be accessed by issuing 
+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
+                                    These codes can be accessed by performing read operations with specific
+                                    control signals and addresses set.They can also be accessed by issuing
                                     an Auto Select command                                                   */
-}NOR_IDTypeDef;
+} NOR_IDTypeDef;
 
 /**
   * @brief  FSMC NOR CFI typedef
@@ -106,7 +88,7 @@ typedef struct
 typedef struct
 {
   /*!< Defines the information stored in the memory's Common flash interface
-       which contains a description of various electrical and timing parameters, 
+       which contains a description of various electrical and timing parameters,
        density information and functions supported by the memory                   */
 
   uint16_t CFI_1;
@@ -116,12 +98,17 @@ typedef struct
   uint16_t CFI_3;
 
   uint16_t CFI_4;
-}NOR_CFITypeDef;
+} NOR_CFITypeDef;
 
-/** 
+/**
   * @brief  NOR handle Structure definition
-  */ 
+  */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+typedef struct __NOR_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
+
 {
   FSMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
 
@@ -133,33 +120,62 @@ typedef struct
 
   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 
-}NOR_HandleTypeDef;
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+  void  (* MspInitCallback)        ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp Init callback              */
+  void  (* MspDeInitCallback)      ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp DeInit callback            */
+#endif
+} NOR_HandleTypeDef;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL NOR Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
+  HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
+}HAL_NOR_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL NOR Callback pointer definition
+  */
+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
+#endif
 /**
   * @}
   */
-  
+
 /* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup NOR_Exported_Macros NOR Exported Macros
   * @{
   */
 /** @brief Reset NOR handle state
-  * @param  __HANDLE__: specifies the NOR handle.
+  * @param  __HANDLE__ specifies the NOR handle.
   * @retval None
   */
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
+                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+#endif
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions 
- *  @{
- */
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+  * @{
+  */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
 
-/** @addtogroup NOR_Exported_Functions_Group1
- *  @{
- */
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
@@ -169,10 +185,11 @@ void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 /**
   * @}
   */
-  
-/** @addtogroup NOR_Exported_Functions_Group2
- *  @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+  * @{
+  */
+
 /* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
@@ -185,34 +202,42 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/* NOR callback registering/unregistering */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
+#endif
 /**
   * @}
   */
-  
-/** @addtogroup NOR_Exported_Functions_Group3
- *  @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
+  * @{
+  */
+
 /* NOR Control functions  *****************************************************/
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 /**
   * @}
   */
-  
-/** @addtogroup NOR_Exported_Functions_Group4
- *  @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
+  * @{
+  */
+
 /* NOR State functions ********************************************************/
 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 /**
   * @}
   */
-    
+
 /**
   * @}
   */
-  
+
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -220,29 +245,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   * @{
   */
 /* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
+#define MC_ADDRESS               ((uint16_t)0x0000U)
+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
 
 /* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x61)
-#define CFI2_ADDRESS             ((uint16_t)0x62)
-#define CFI3_ADDRESS             ((uint16_t)0x63)
-#define CFI4_ADDRESS             ((uint16_t)0x64)
+#define CFI1_ADDRESS             ((uint16_t)0x61U)
+#define CFI2_ADDRESS             ((uint16_t)0x62U)
+#define CFI3_ADDRESS             ((uint16_t)0x63U)
+#define CFI4_ADDRESS             ((uint16_t)0x64U)
 
 /* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFF)
-   
+#define NOR_TMEOUT               ((uint16_t)0xFFFFU)
+
 /* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x0)
-#define NOR_MEMORY_16B           ((uint8_t)0x1)
+#define NOR_MEMORY_8B            ((uint8_t)0x0U)
+#define NOR_MEMORY_16B           ((uint8_t)0x1U)
 
 /* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
-#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
-#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
-#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
+#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000U)
+#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000U)
+#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000U)
+#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000U)
 /**
   * @}
   */
@@ -253,21 +278,26 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   */
 /**
   * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS__: NOR base address 
-  * @param  NOR_MEMORY_WIDTH: NOR memory width
-  * @param  ADDRESS: NOR memory address 
+  * @param  __NOR_ADDRESS NOR base address
+  * @param  __NOR_MEMORY_WIDTH_ NOR memory width
+  * @param  __ADDRESS__ NOR memory address
   * @retval NOR shifted address value
   */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS)    (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS__) + (2 * (ADDRESS)))):\
-                                                                                 ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
- 
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
+              ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
+              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
+              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
 /**
   * @brief  NOR memory write data to specified address.
-  * @param  ADDRESS: NOR memory address 
-  * @param  DATA: Data to write
+  * @param  __ADDRESS__ NOR memory address
+  * @param  __DATA__ Data to write
   * @retval None
   */
-#define NOR_WRITE(ADDRESS, DATA)  (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
+#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
+                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
+                                               __DSB();                                                    \
+                                             } while(0)
 
 /**
   * @}
@@ -275,16 +305,17 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
 
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_NOR_H */
+#endif /* STM32F2xx_HAL_NOR_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h
index 30b998cc..b093945d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h
@@ -2,47 +2,30 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pccard.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of PCCARD HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_PCCARD_H
-#define __STM32F2xx_HAL_PCCARD_H
+#ifndef STM32F2xx_HAL_PCCARD_H
+#define STM32F2xx_HAL_PCCARD_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_fsmc.h"
 
@@ -50,49 +33,74 @@
   * @{
   */
 
-
 /** @addtogroup PCCARD
   * @{
-  */ 
+  */
 
 /* Exported typedef ----------------------------------------------------------*/
 /** @defgroup PCCARD_Exported_Types PCCARD Exported Types
   * @{
   */
 
-/** 
-  * @brief  HAL PCCARD State structures definition  
-  */ 
+/**
+  * @brief  HAL PCCARD State structures definition
+  */
 typedef enum
 {
-  HAL_PCCARD_STATE_RESET     = 0x00,    /*!< PCCARD peripheral not yet initialized or disabled */
-  HAL_PCCARD_STATE_READY     = 0x01,    /*!< PCCARD peripheral ready                           */
-  HAL_PCCARD_STATE_BUSY      = 0x02,    /*!< PCCARD peripheral busy                            */   
-  HAL_PCCARD_STATE_ERROR     = 0x04     /*!< PCCARD peripheral error                           */
-}HAL_PCCARD_StateTypeDef;
+  HAL_PCCARD_STATE_RESET     = 0x00U,    /*!< PCCARD peripheral not yet initialized or disabled */
+  HAL_PCCARD_STATE_READY     = 0x01U,    /*!< PCCARD peripheral ready                           */
+  HAL_PCCARD_STATE_BUSY      = 0x02U,    /*!< PCCARD peripheral busy                            */
+  HAL_PCCARD_STATE_ERROR     = 0x04U     /*!< PCCARD peripheral error                           */
+} HAL_PCCARD_StateTypeDef;
 
 typedef enum
 {
-  HAL_PCCARD_STATUS_SUCCESS = 0,
+  HAL_PCCARD_STATUS_SUCCESS = 0U,
   HAL_PCCARD_STATUS_ONGOING,
   HAL_PCCARD_STATUS_ERROR,
   HAL_PCCARD_STATUS_TIMEOUT
-}HAL_PCCARD_StatusTypeDef;
+} HAL_PCCARD_StatusTypeDef;
 
-/** 
-  * @brief  FSMC_PCCARD handle Structure definition  
-  */   
+/**
+  * @brief  FSMC_PCCARD handle Structure definition
+  */
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)  
+typedef struct __PCCARD_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS  */
 {
   FSMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
-  
+
   FSMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
 
   __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
-   
-  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */ 
- 
-}PCCARD_HandleTypeDef;
+
+  HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */
+
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+  void  (* MspInitCallback)        ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD Msp Init callback              */
+  void  (* MspDeInitCallback)      ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD Msp DeInit callback            */
+  void  (* ItCallback)             ( struct __PCCARD_HandleTypeDef * hpccard);    /*!< PCCARD IT callback                    */
+#endif
+} PCCARD_HandleTypeDef;
+
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL PCCARD Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_PCCARD_MSP_INIT_CB_ID       = 0x00U,  /*!< PCCARD MspInit Callback ID          */
+  HAL_PCCARD_MSP_DEINIT_CB_ID     = 0x01U,  /*!< PCCARD MspDeInit Callback ID        */
+  HAL_PCCARD_IT_CB_ID             = 0x02U   /*!< PCCARD IT Callback ID               */
+}HAL_PCCARD_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL PCCARD Callback pointer definition
+  */
+typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
+#endif
 /**
   * @}
   */
@@ -103,20 +111,28 @@ typedef struct
   * @{
   */
 /** @brief Reset PCCARD handle state
-  * @param  __HANDLE__: specifies the PCCARD handle.
+  * @param  __HANDLE__ specifies the PCCARD handle.
   * @retval None
   */
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__)       do {                                               \
+                                                               (__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;         \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                             } while(0)
+#else
 #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
+#endif
 /**
   * @}
-  */ 
+  */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions 
+/** @addtogroup PCCARD_Exported_Functions
   * @{
   */
 
-/** @addtogroup PCCARD_Exported_Functions_Group1 
+/** @addtogroup PCCARD_Exported_Functions_Group1
   * @{
   */
 /* Initialization/de-initialization functions  **********************************/
@@ -140,6 +156,11 @@ HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
 void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
 void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
 
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/* PCCARD callback registering/unregistering */
+HAL_StatusTypeDef  HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef  HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
+#endif
 /**
   * @}
   */
@@ -164,11 +185,11 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 /** @defgroup PCCARD_Private_Constants PCCARD Private Constants
   * @{
   */
-#define PCCARD_DEVICE_ADDRESS             ((uint32_t)0x90000000)
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS    ((uint32_t)0x98000000)   /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_DEVICE_ADDRESS             0x90000000U
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS    0x98000000U              /* Attribute space size to @0x9BFF FFFF */
 #define PCCARD_COMMON_SPACE_ADDRESS       PCCARD_DEVICE_ADDRESS    /* Common space size to @0x93FF FFFF    */
-#define PCCARD_IO_SPACE_ADDRESS           ((uint32_t)0x9C000000)   /* IO space size to @0x9FFF FFFF        */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR      ((uint32_t)0x9C0001F0)   /* IO space size to @0x9FFF FFFF        */
+#define PCCARD_IO_SPACE_ADDRESS           0x9C000000U              /* IO space size to @0x9FFF FFFF        */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR      0x9C0001F0U              /* IO space size to @0x9FFF FFFF        */
 
 /* Flash-ATA registers description */
 #define ATA_DATA                       ((uint8_t)0x00)    /* Data register */
@@ -194,7 +215,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define PCCARD_PROGR                   ((uint8_t)0x01)
 #define PCCARD_READY                   ((uint8_t)0x40)
 
-#define PCCARD_SECTOR_SIZE             ((uint32_t)255)    /* In half words */ 
+#define PCCARD_SECTOR_SIZE             255U               /* In half words */
 
 /**
   * @}
@@ -204,7 +225,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define HAL_CF_DeInit               HAL_PCCARD_DeInit
 #define HAL_CF_MspInit              HAL_PCCARD_MspInit
 #define HAL_CF_MspDeInit            HAL_PCCARD_MspDeInit
-                                        
+
 #define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
 #define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
 #define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
@@ -212,28 +233,27 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
 #define HAL_CF_Reset                HAL_PCCARD_Reset
 #define HAL_CF_IRQHandler           HAL_PCCARD_IRQHandler
 #define HAL_CF_ITCallback           HAL_PCCARD_ITCallback
-                                        
+
 #define HAL_CF_GetState             HAL_PCCARD_GetState
 #define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
 #define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
-                                        
+
 #define HAL_CF_STATUS_SUCCESS       HAL_PCCARD_STATUS_SUCCESS
 #define HAL_CF_STATUS_ONGOING       HAL_PCCARD_STATUS_ONGOING
 #define HAL_CF_STATUS_ERROR         HAL_PCCARD_STATUS_ERROR
 #define HAL_CF_STATUS_TIMEOUT       HAL_PCCARD_STATUS_TIMEOUT
 #define HAL_CF_StatusTypeDef        HAL_PCCARD_StatusTypeDef
 
-
-#define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS               
+#define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS
 #define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS   
-#define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS       
-#define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR  
+#define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR
 
 #define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
-#define CF_BUSY                     PCCARD_BUSY         
-#define CF_PROGR                    PCCARD_PROGR        
-#define CF_READY                    PCCARD_READY        
+#define CF_BUSY                     PCCARD_BUSY
+#define CF_PROGR                    PCCARD_PROGR
+#define CF_READY                    PCCARD_READY
 
 #define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
 
@@ -243,15 +263,15 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
   */
 
 
-
 /**
   * @}
   */
-  
+
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_PCCARD_H */
+#endif /* STM32F2xx_HAL_PCCARD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h
index 8c25b03c..157d987b 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h
@@ -2,67 +2,51 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_PCD_H
-#define __STM32F2xx_HAL_PCD_H
+#ifndef STM32F2xx_HAL_PCD_H
+#define STM32F2xx_HAL_PCD_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_usb.h"
-   
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup PCD
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup PCD_Exported_Types PCD Exported Types
   * @{
   */
-   
+
 /**
   * @brief  PCD State structure definition
   */
-typedef enum 
+typedef enum
 {
   HAL_PCD_STATE_RESET   = 0x00,
   HAL_PCD_STATE_READY   = 0x01,
@@ -71,30 +55,85 @@ typedef enum
   HAL_PCD_STATE_TIMEOUT = 0x04
 } PCD_StateTypeDef;
 
+/* Device LPM suspend state */
+typedef enum
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+  PCD_BCD_ERROR                     = 0xFF,
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
-/** 
-  * @brief  PCD Handle Structure definition  
-  */ 
+/**
+  * @brief  PCD Handle Structure definition
+  */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
-  PCD_TypeDef             *Instance;    /*!< Register base address              */
-  PCD_InitTypeDef         Init;         /*!< PCD required parameters            */
-  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */
-  HAL_LockTypeDef         Lock;         /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;        /*!< PCD communication state            */
-  uint32_t                Setup[12];    /*!< Setup packet buffer                */
-  void                    *pData;       /*!< Pointer to upper stack Handler     */
+  PCD_TypeDef             *Instance;   /*!< Register base address              */
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  __IO uint8_t            USB_Address; /*!< USB Address                        */
+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */
+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */
+  uint32_t                BESL;
+
+  void                    *pData;      /*!< Pointer to upper stack Handler */
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */
+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */
+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */
+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */
+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */
+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */
+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */
+
+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */
+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */
+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */
+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */
+
+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */
+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 } PCD_HandleTypeDef;
 
 /**
   * @}
   */
 
-/* Include PCD HAL Extension module */
+/* Include PCD HAL Extended module */
 #include "stm32f2xx_hal_pcd_ex.h"
 
 /* Exported constants --------------------------------------------------------*/
@@ -105,31 +144,31 @@ typedef struct
 /** @defgroup PCD_Speed PCD Speed
   * @{
   */
-#define PCD_SPEED_HIGH               0
-#define PCD_SPEED_HIGH_IN_FULL       1
-#define PCD_SPEED_FULL               2
+#define PCD_SPEED_HIGH               USBD_HS_SPEED
+#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED
+#define PCD_SPEED_FULL               USBD_FS_SPEED
 /**
   * @}
   */
-  
+
 /** @defgroup PCD_PHY_Module PCD PHY Module
   * @{
   */
-#define PCD_PHY_ULPI                 1
-#define PCD_PHY_EMBEDDED             2
+#define PCD_PHY_ULPI                 1U
+#define PCD_PHY_EMBEDDED             2U
+#define PCD_PHY_UTMI                 3U
 /**
   * @}
   */
 
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+  * @brief  PCD Error Code definition
   * @{
   */
-#ifndef USBD_HS_TRDT_VALUE
- #define USBD_HS_TRDT_VALUE           9
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE           5
-#endif /* USBD_FS_TRDT_VALUE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -143,68 +182,45 @@ typedef struct
  *  @brief macros to handle interrupts and specific clock configurations
  * @{
  */
-#define __HAL_PCD_ENABLE(__HANDLE__)                   USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__)                  USB_DisableGlobalInt ((__HANDLE__)->Instance)
-   
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
 
 
 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
-                                                           ~(USB_OTG_PCGCCTL_STOPCLK)
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
 
 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-                                                      
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
-                                                         
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
 
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
-#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
-#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
-
-#define USB_OTG_HS_WAKEUP_EXTI_LINE              ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
-#define USB_OTG_FS_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
 
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
 
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                          EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-                                                      
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                            EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()   EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
-                                                                    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
-                                                                    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
-                                                                    EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 
-
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+                        do { \
+                             EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
+                             EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
+                           } while(0U)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
 
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                          EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
-                                                      
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()  EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                            EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
+                        do { \
+                             EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
+                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
+                           } while(0U)
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()  EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
-                                                                   EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
-                                                                   EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE 
 
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) 
 /**
   * @}
   */
@@ -222,6 +238,61 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+  * @brief  HAL USB OTG PCD Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */
+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */
+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */
+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */
+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */
+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */
+  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */
+
+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */
+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+  * @brief  HAL USB OTG PCD Callback pointer definition
+  * @{
+  */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */
+
+/**
+  * @}
+  */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -231,22 +302,22 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
 /** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
-/* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
 
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 /**
   * @}
   */
@@ -262,7 +333,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
@@ -279,41 +350,88 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
- 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-/** @defgroup PCD_Instance_definition PCD Instance definition
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
   * @{
   */
- #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                        ((INSTANCE) == USB_OTG_HS))
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U
+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 20)  /*!< USB HS EXTI Line WakeUp Interrupt */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
 /**
   * @}
-  */ 
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#ifndef USB_OTG_DOEPINT_OTEPSPR
+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_OTEPSPRM
+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_NAK
+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NAKM
+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
+#endif
+
+#ifndef USB_OTG_DOEPINT_STPKTRX
+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
+#endif
+
+#ifndef USB_OTG_DOEPMSK_NYETM
+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
+#endif
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 #ifdef __cplusplus
 }
 #endif
 
-
-#endif /* __STM32F2xx_HAL_PCD_H */
+#endif /* STM32F2xx_HAL_PCD_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h
index 51594491..f0b180ee 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h
@@ -2,50 +2,33 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   Header file of PCD HAL module.
+  * @brief   Header file of PCD HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_PCD_EX_H
-#define __STM32F2xx_HAL_PCD_EX_H
+#ifndef STM32F2xx_HAL_PCD_EX_H
+#define STM32F2xx_HAL_PCD_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
-   
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
@@ -53,41 +36,47 @@
 /** @addtogroup PCDEx
   * @{
   */
-
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /* Exported macros -----------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
   * @{
   */
-/** @addtogroup PCDEx_Exported_Functions_Group1
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
   * @{
   */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* __STM32F2xx_HAL_PCD_EX_H */
+#endif /* STM32F2xx_HAL_PCD_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h
index b8d7a4cb..15b0c260 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_PWR_H
@@ -84,7 +66,7 @@ typedef struct
 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
   * @{
   */
-#define PWR_WAKEUP_PIN1                 ((uint32_t)0x00000100)
+#define PWR_WAKEUP_PIN1                 0x00000100U
 /**
   * @}
   */
@@ -108,13 +90,13 @@ typedef struct
 /** @defgroup PWR_PVD_Mode PWR PVD Mode
   * @{
   */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
 /**
   * @}
   */
@@ -123,7 +105,7 @@ typedef struct
 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
   * @{
   */
-#define PWR_MAINREGULATOR_ON                        ((uint32_t)0x00000000)
+#define PWR_MAINREGULATOR_ON                        0x00000000U
 #define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
 /**
   * @}
@@ -168,7 +150,7 @@ typedef struct
   */
 
 /** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *           This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
   *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
@@ -189,12 +171,12 @@ typedef struct
 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be one of the following values:
   *            @arg PWR_FLAG_WU: Wake Up flag
   *            @arg PWR_FLAG_SB: StandBy flag
   */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2)
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
 
 /**
   * @brief Enable the PVD Exti Line 16.
@@ -250,14 +232,18 @@ typedef struct
   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
+                                                              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
+                                                            }while(0)
 
 /**
   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
+                                                              __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
+                                                            }while(0)
 
 /**
   * @brief checks whether the specified PVD Exti interrupt flag is set or not.
@@ -355,8 +341,8 @@ void HAL_PWR_DisableSEVOnPend(void);
   */
 /* ------------- PWR registers bit address in the alias region ---------------*/
 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00
-#define PWR_CSR_OFFSET           0x04
+#define PWR_CR_OFFSET            0x00U
+#define PWR_CSR_OFFSET           0x04U
 #define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
 #define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
 /**
@@ -369,11 +355,11 @@ void HAL_PWR_DisableSEVOnPend(void);
 /* --- CR Register ---*/
 /* Alias word address of DBP bit */
 #define DBP_BIT_NUMBER   POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
+#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
 
 /* Alias word address of PVDE bit */
 #define PVDE_BIT_NUMBER  POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
+#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
 /**
   * @}
   */
@@ -384,7 +370,7 @@ void HAL_PWR_DisableSEVOnPend(void);
 /* --- CSR Register ---*/
 /* Alias word address of EWUP bit */
 #define EWUP_BIT_NUMBER  POSITION_VAL(PWR_CSR_EWUP)
-#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
+#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h
index 12437ca3..7fe91d36 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_PWR_EX_H
@@ -56,7 +38,7 @@
 
 /* Exported types ------------------------------------------------------------*/ 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+/** @defgroup PWREx_Exported_Constants PWR Exported Constants
   * @{
   */
 
@@ -65,7 +47,7 @@
   */ 
 
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+/** @defgroup PWREx_Exported_Constants PWR Exported Constants
   *  @{
   */
 /**
@@ -73,7 +55,7 @@
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+/** @addtogroup PWREx_Exported_Functions PWR Exported Functions
   *  @{
   */
  
@@ -94,30 +76,30 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWREx Private Constants
+/** @defgroup PWREx_Private_Constants PWR Private Constants
   * @{
   */
 
-/** @defgroup PWREx_register_alias_address PWREx Register alias address
+/** @defgroup PWREx_register_alias_address PWR Register alias address
   * @{
   */
 /* ------------- PWR registers bit address in the alias region ---------------*/
 /* --- CR Register ---*/
 /* Alias word address of FPDS bit */
 #define FPDS_BIT_NUMBER          POSITION_VAL(PWR_CR_FPDS)
-#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
+#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
 
  /**
   * @}
   */
 
-/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+/** @defgroup PWREx_CSR_register_alias PWR CSR Register alias address
   * @{
   */  
 /* --- CSR Register ---*/
 /* Alias word address of BRE bit */
 #define BRE_BIT_NUMBER   POSITION_VAL(PWR_CSR_BRE)
-#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))    
+#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))    
 /**
   * @}
   */
@@ -127,11 +109,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWREx Private Macros
+/** @defgroup PWREx_Private_Macros PWR Private Macros
   * @{
   */
 
-/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+/** @defgroup PWREx_IS_PWR_Definitions PWR Private macros to check input parameters
   * @{
   */
 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h
index f5c15b61..629db0ab 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -50,7 +32,7 @@
   * @{
   */
 
-/** @addtogroup RCC 
+/** @addtogroup RCC
   * @{
   */
 
@@ -80,12 +62,12 @@ typedef struct
                             This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
 
   uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
 
 }RCC_PLLInitTypeDef;
 
 /**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
   */
 typedef struct
 {
@@ -97,22 +79,21 @@ typedef struct
 
   uint32_t LSEState;             /*!< The new state of the LSE.
                                       This parameter can be a value of @ref RCC_LSE_Config                        */
-                                          
+
   uint32_t HSIState;             /*!< The new state of the HSI.
                                       This parameter can be a value of @ref RCC_HSI_Config                        */
 
-  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-                               
+  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
   uint32_t LSIState;             /*!< The new state of the LSI.
                                       This parameter can be a value of @ref RCC_LSI_Config                        */
 
   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
-
 }RCC_OscInitTypeDef;
 
 /**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
   */
 typedef struct
 {
@@ -145,11 +126,11 @@ typedef struct
 /** @defgroup RCC_Oscillator_Type Oscillator Type
   * @{
   */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
+#define RCC_OSCILLATORTYPE_NONE            0x00000000U
+#define RCC_OSCILLATORTYPE_HSE             0x00000001U
+#define RCC_OSCILLATORTYPE_HSI             0x00000002U
+#define RCC_OSCILLATORTYPE_LSE             0x00000004U
+#define RCC_OSCILLATORTYPE_LSI             0x00000008U
 /**
   * @}
   */
@@ -179,6 +160,8 @@ typedef struct
   */
 #define RCC_HSI_OFF                      ((uint8_t)0x00)
 #define RCC_HSI_ON                       ((uint8_t)0x01)
+
+#define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */
 /**
   * @}
   */
@@ -205,10 +188,10 @@ typedef struct
 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
   * @{
   */
-#define RCC_PLLP_DIV2                  ((uint32_t)0x00000002)
-#define RCC_PLLP_DIV4                  ((uint32_t)0x00000004)
-#define RCC_PLLP_DIV6                  ((uint32_t)0x00000006)
-#define RCC_PLLP_DIV8                  ((uint32_t)0x00000008)
+#define RCC_PLLP_DIV2                  0x00000002U
+#define RCC_PLLP_DIV4                  0x00000004U
+#define RCC_PLLP_DIV6                  0x00000006U
+#define RCC_PLLP_DIV8                  0x00000008U
 /**
   * @}
   */
@@ -225,15 +208,15 @@ typedef struct
 /** @defgroup RCC_System_Clock_Type System Clock Type
   * @{
   */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001)
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002)
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004)
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008)
+#define RCC_CLOCKTYPE_SYSCLK             0x00000001U
+#define RCC_CLOCKTYPE_HCLK               0x00000002U
+#define RCC_CLOCKTYPE_PCLK1              0x00000004U
+#define RCC_CLOCKTYPE_PCLK2              0x00000008U
 /**
   * @}
   */
-  
-/** @defgroup RCC_System_Clock_Source System Clock Source 
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
   * @{
   */
 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
@@ -267,8 +250,8 @@ typedef struct
 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
   * @{
   */
@@ -277,54 +260,45 @@ typedef struct
 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)0x00000100)
-#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)0x00000200)
-#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)0x00020300)
-#define RCC_RTCCLKSOURCE_HSE_DIV3        ((uint32_t)0x00030300)
-#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)0x00040300)
-#define RCC_RTCCLKSOURCE_HSE_DIV5        ((uint32_t)0x00050300)
-#define RCC_RTCCLKSOURCE_HSE_DIV6        ((uint32_t)0x00060300)
-#define RCC_RTCCLKSOURCE_HSE_DIV7        ((uint32_t)0x00070300)
-#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)0x00080300)
-#define RCC_RTCCLKSOURCE_HSE_DIV9        ((uint32_t)0x00090300)
-#define RCC_RTCCLKSOURCE_HSE_DIV10       ((uint32_t)0x000A0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV11       ((uint32_t)0x000B0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV12       ((uint32_t)0x000C0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV13       ((uint32_t)0x000D0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV14       ((uint32_t)0x000E0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV15       ((uint32_t)0x000F0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)0x00100300)
-#define RCC_RTCCLKSOURCE_HSE_DIV17       ((uint32_t)0x00110300)
-#define RCC_RTCCLKSOURCE_HSE_DIV18       ((uint32_t)0x00120300)
-#define RCC_RTCCLKSOURCE_HSE_DIV19       ((uint32_t)0x00130300)
-#define RCC_RTCCLKSOURCE_HSE_DIV20       ((uint32_t)0x00140300)
-#define RCC_RTCCLKSOURCE_HSE_DIV21       ((uint32_t)0x00150300)
-#define RCC_RTCCLKSOURCE_HSE_DIV22       ((uint32_t)0x00160300)
-#define RCC_RTCCLKSOURCE_HSE_DIV23       ((uint32_t)0x00170300)
-#define RCC_RTCCLKSOURCE_HSE_DIV24       ((uint32_t)0x00180300)
-#define RCC_RTCCLKSOURCE_HSE_DIV25       ((uint32_t)0x00190300)
-#define RCC_RTCCLKSOURCE_HSE_DIV26       ((uint32_t)0x001A0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV27       ((uint32_t)0x001B0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV28       ((uint32_t)0x001C0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV29       ((uint32_t)0x001D0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV30       ((uint32_t)0x001E0300)
-#define RCC_RTCCLKSOURCE_HSE_DIV31       ((uint32_t)0x001F0300)
 /**
   * @}
   */
 
-/** @defgroup RCC_I2S_Clock_Source I2S Clock Source
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
   * @{
   */
-#define RCC_I2SCLKSOURCE_PLLI2S         ((uint32_t)0x00000000)
-#define RCC_I2SCLKSOURCE_EXT            ((uint32_t)0x00000001)
+#define RCC_RTCCLKSOURCE_LSE             0x00000100U
+#define RCC_RTCCLKSOURCE_LSI             0x00000200U
+#define RCC_RTCCLKSOURCE_HSE_DIV2        0x00020300U
+#define RCC_RTCCLKSOURCE_HSE_DIV3        0x00030300U
+#define RCC_RTCCLKSOURCE_HSE_DIV4        0x00040300U
+#define RCC_RTCCLKSOURCE_HSE_DIV5        0x00050300U
+#define RCC_RTCCLKSOURCE_HSE_DIV6        0x00060300U
+#define RCC_RTCCLKSOURCE_HSE_DIV7        0x00070300U
+#define RCC_RTCCLKSOURCE_HSE_DIV8        0x00080300U
+#define RCC_RTCCLKSOURCE_HSE_DIV9        0x00090300U
+#define RCC_RTCCLKSOURCE_HSE_DIV10       0x000A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV11       0x000B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV12       0x000C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV13       0x000D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV14       0x000E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV15       0x000F0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV16       0x00100300U
+#define RCC_RTCCLKSOURCE_HSE_DIV17       0x00110300U
+#define RCC_RTCCLKSOURCE_HSE_DIV18       0x00120300U
+#define RCC_RTCCLKSOURCE_HSE_DIV19       0x00130300U
+#define RCC_RTCCLKSOURCE_HSE_DIV20       0x00140300U
+#define RCC_RTCCLKSOURCE_HSE_DIV21       0x00150300U
+#define RCC_RTCCLKSOURCE_HSE_DIV22       0x00160300U
+#define RCC_RTCCLKSOURCE_HSE_DIV23       0x00170300U
+#define RCC_RTCCLKSOURCE_HSE_DIV24       0x00180300U
+#define RCC_RTCCLKSOURCE_HSE_DIV25       0x00190300U
+#define RCC_RTCCLKSOURCE_HSE_DIV26       0x001A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV27       0x001B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV28       0x001C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV29       0x001D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV30       0x001E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV31       0x001F0300U
 /**
   * @}
   */
@@ -332,8 +306,8 @@ typedef struct
 /** @defgroup RCC_MCO_Index MCO Index
   * @{
   */
-#define RCC_MCO1                         ((uint32_t)0x00000000)
-#define RCC_MCO2                         ((uint32_t)0x00000001)
+#define RCC_MCO1                         0x00000000U
+#define RCC_MCO2                         0x00000001U
 /**
   * @}
   */
@@ -341,7 +315,7 @@ typedef struct
 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
   * @{
   */
-#define RCC_MCO1SOURCE_HSI               ((uint32_t)0x00000000)
+#define RCC_MCO1SOURCE_HSI               0x00000000U
 #define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
 #define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
 #define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
@@ -352,7 +326,7 @@ typedef struct
 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
   * @{
   */
-#define RCC_MCO2SOURCE_SYSCLK            ((uint32_t)0x00000000)
+#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
 #define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
 #define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
 #define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
@@ -363,7 +337,7 @@ typedef struct
 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
   * @{
   */
-#define RCC_MCODIV_1                    ((uint32_t)0x00000000)
+#define RCC_MCODIV_1                    0x00000000U
 #define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
 #define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
 #define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
@@ -385,7 +359,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup RCC_Flag Flags
   *        Elements values convention: 0XXYYYYYb
   *           - YYYYY  : Flag position in the register
@@ -415,7 +389,7 @@ typedef struct
 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -429,110 +403,110 @@ typedef struct
 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
   * @brief  Enable or disable the AHB1 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
   * @{
   */
 #define __HAL_RCC_GPIOA_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOB_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOD_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOE_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_CRC_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_BKPSRAM_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_DMA2_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()  do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()  do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
@@ -553,6 +527,47 @@ typedef struct
 #define __HAL_RCC_DMA2_CLK_DISABLE()            (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+/**
+  * @}
+  */
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()                  ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()              ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()                 ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()                 ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()           ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()      ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()                ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()                  ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()              ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()                 ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()                 ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()           ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED()      ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
 /**
   * @}
   */
@@ -560,7 +575,7 @@ typedef struct
 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
   * @brief  Enable or disable the AHB2 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
+  *         is disabled and the application software has to enable this clock before
   *         using it.
   * @{
   */
@@ -568,7 +583,7 @@ typedef struct
                                                __HAL_RCC_SYSCFG_CLK_ENABLE();\
                                               }while(0)
 #define __HAL_RCC_RNG_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
@@ -581,15 +596,31 @@ typedef struct
   * @}
   */
 
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()        ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
+/**
+  * @}
+  */
+
 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
   * @brief  Enables or disables the AHB3 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
   * @{
   */
 #define __HAL_RCC_FSMC_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
@@ -600,6 +631,19 @@ typedef struct
   * @}
   */
 
+/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
+/**
+  * @}
+  */
+
 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
@@ -608,161 +652,161 @@ typedef struct
   * @{
   */
 #define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM6_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM7_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM12_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM13_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM14_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_USART2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_USART3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_UART4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_UART5_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_CAN1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_CAN2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_PWR_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_DAC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
@@ -796,78 +840,136 @@ typedef struct
   * @}
   */
 
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET)
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET)
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET)
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET)
+/**
+  * @}
+  */
+
 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
+  *         is disabled and the application software has to enable this clock before
   *         using it.
   * @{
   */
 #define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg; \
+                                      __IO uint32_t tmpreg = 0x00U; \
                                       SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                       /* Delay after an RCC peripheral clock enabling */ \
                                       tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                       UNUSED(tmpreg); \
                                       } while(0)
 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_USART6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_ADC3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
                                         UNUSED(tmpreg); \
-                                        } while(0) 
+                                        } while(0)
 #define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
@@ -875,21 +977,21 @@ typedef struct
                                         } while(0)
 
 #define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         UNUSED(tmpreg); \
                                         } while(0)
 #define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg; \
+                                        __IO uint32_t tmpreg = 0x00U; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
@@ -912,11 +1014,49 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
   * @brief  Force or release AHB1 peripheral reset.
   * @{
-  */  
-#define __HAL_RCC_AHB1_FORCE_RESET()         (RCC->AHB1RSTR = 0xFFFFFFFF)
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()         (RCC->AHB1RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_GPIOA_FORCE_RESET()        (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
 #define __HAL_RCC_GPIOB_FORCE_RESET()        (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
 #define __HAL_RCC_GPIOC_FORCE_RESET()        (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
@@ -932,7 +1072,7 @@ typedef struct
 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
 #define __HAL_RCC_OTGHSULPI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST))
 
-#define __HAL_RCC_AHB1_RELEASE_RESET()       (RCC->AHB1RSTR = 0x00)
+#define __HAL_RCC_AHB1_RELEASE_RESET()       (RCC->AHB1RSTR = 0x00U)
 #define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
 #define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
 #define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
@@ -951,26 +1091,26 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
   * @brief  Force or release AHB2 peripheral reset.
   * @{
   */
-#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_RNG_FORCE_RESET()          (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
 
-#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00)
-#define __HAL_RCC_RNG_RELEASE_RESET()        (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))  
+#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_RNG_RELEASE_RESET()        (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
 /**
   * @}
   */
 
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
   * @brief  Force or release APB1 peripheral reset.
   * @{
   */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFF)  
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
 #define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
 #define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
@@ -995,7 +1135,7 @@ typedef struct
 #define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
 #define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
 
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00) 
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
 #define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
 #define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
 #define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
@@ -1023,11 +1163,11 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
   * @brief  Force or release APB2 peripheral reset.
   * @{
   */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFF)  
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
 #define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
 #define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
@@ -1040,7 +1180,7 @@ typedef struct
 #define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
 #define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
 
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
 #define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
 #define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
@@ -1056,20 +1196,20 @@ typedef struct
   * @}
   */
 
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
   * @brief  Force or release AHB3 peripheral reset.
   * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
+  */
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
 
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) 
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
 /**
   * @}
   */
 
-/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
   * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
   *         power consumption.
@@ -1141,6 +1281,7 @@ typedef struct
   *           power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()    (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
@@ -1246,23 +1387,23 @@ typedef struct
   */
 
 /** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
   *         It is used (enabled by hardware) as system clock source after startup
   *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
   *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).             
+  *         Security System CSS is enabled).
   * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.  
+  *         you have to select another source of the system clock then stop the HSI.
   * @note   After enabling the HSI, the application software should wait on HSIRDY
   *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.  
+  *         system clock source.
   *         This parameter can be: ENABLE or DISABLE.
   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.  
+  *         clock cycles.
   */
 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
@@ -1270,7 +1411,8 @@ typedef struct
 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
   * @note   The calibration is used to compensate for the variations in voltage
   *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICalibrationValue__: specifies the calibration trimming value.
+  * @param  __HSICalibrationValue__ specifies the calibration trimming value.
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
   *         This parameter must be a number between 0 and 0x1F.
   */
 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
@@ -1280,16 +1422,16 @@ typedef struct
   */
 
 /** @defgroup RCC_LSI_Configuration LSI Configuration
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on 
+  * @note   After enabling the LSI, the application software should wait on
   *         LSIRDY flag to be set indicating that LSI clock is stable and can
   *         be used to clock the IWDG and/or the RTC.
   * @note   LSI can not be disabled if the IWDG is running.
   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles. 
+  *         clock cycles.
   */
 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
@@ -1298,12 +1440,12 @@ typedef struct
   */
 
 /** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{   
-  */ 
+  * @{
+  */
 
 /**
   * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. 
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
   *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
   *         software should wait on HSERDY flag to be set indicating that HSE clock
@@ -1311,11 +1453,11 @@ typedef struct
   * @note   HSE state can not be changed if it is used directly or through the
   *         PLL as system clock. In this case, you have to select another source
   *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
   *         was previously enabled you have to enable it again after calling this
-  *         function.    
-  * @param  __STATE__: specifies the new state of the HSE.
+  *         function.
+  * @param  __STATE__ specifies the new state of the HSE.
   *         This parameter can be one of the following values:
   *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
   *                              6 HSE oscillator clock cycles.
@@ -1328,20 +1470,20 @@ typedef struct
   */
 
 /** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{   
+  * @{
   */
 /**
   * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
   *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
   * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using 
+  *         this domain after reset, you have to enable write access using
   *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).  
+  *         (to be done once after reset).
   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
   *         software should wait on LSERDY flag to be set indicating that LSE clock
   *         is stable and can be used to clock the RTC.
-  * @param  __STATE__: specifies the new state of the LSE.
+  * @param  __STATE__ specifies the new state of the LSE.
   *         This parameter can be one of the following values:
   *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
   *                              6 LSE oscillator clock cycles.
@@ -1355,7 +1497,7 @@ typedef struct
   */
 
 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
-  * @{   
+  * @{
   */
 
 /** @brief  Macros to enable or disable the RTC clock.
@@ -1368,11 +1510,11 @@ typedef struct
   * @note   As the RTC clock configuration bits are in the Backup domain and write
   *         access is denied to this domain after reset, you have to enable write
   *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).    
-  * @note   Once the RTC clock is configured it can't be changed unless the  
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
   *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
   *         a Power On Reset (POR).
-  * @param  __RTCCLKSource__: specifies the RTC clock source.
+  * @param  __RTCCLKSource__ specifies the RTC clock source.
   *         This parameter can be one of the following values:
   *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
   *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
@@ -1381,21 +1523,21 @@ typedef struct
   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
   *         work in STOP and STANDBY modes, and can be used as wake-up source.
   *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.    
+  *         cannot be used in STOP and STANDBY modes.
   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
   *         RTC clock source).
   */
 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
-                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-                                                   
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
-                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF);  \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
                                                    } while (0)
 
 /** @brief  Macros to force or release the Backup domain reset.
   * @note   This function resets the RTC peripheral (including the backup registers)
   *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.   
+  * @note   The BKPSRAM is not affected by this reset.
   */
 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
@@ -1404,11 +1546,11 @@ typedef struct
   */
 
 /** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{   
+  * @{
   */
 
 /** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on 
+  * @note   After enabling the main PLL, the application software should wait on
   *         PLLRDY flag to be set indicating that PLL clock is stable and can
   *         be used as system clock source.
   * @note   The main PLL can not be disabled if it is used as system clock source
@@ -1420,36 +1562,36 @@ typedef struct
 
 /** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
   * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__: specifies the PLL entry clock source.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
   *         This parameter can be one of the following values:
   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
   *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__: specifies the multiplication factor for PLL VCO output clock
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
   * @note   You have to set the PLLN parameter correctly to ensure that the VCO
   *         output frequency is between 192 and 432 MHz.
-  *   
-  * @param  __PLLP__: specifies the division factor for main system clock (SYSCLK)
+  *
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
   *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *           
-  * @param  __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.        
+  *
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
   * @note   If the USB OTG FS is used in your application, you have to set the
   *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
   *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
   *         correctly.
-  *      
+  *
   */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
-                            (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
-                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
-                            ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP))    | \
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)      \
+                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
+                            ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN))                 | \
+                            ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP))   | \
                             ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
 /**
   * @}
@@ -1457,30 +1599,30 @@ typedef struct
 
 /** @brief  Macro to configure the PLL clock source.
   * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__: specifies the PLL entry clock source.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
   *         This parameter can be one of the following values:
   *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
   *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  *      
+  *
   */
 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
 
 /** @brief  Macro to configure the PLL multiplication factor.
   * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLM__: specifies the division factor for PLL VCO input clock
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
   * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
   *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
   *         of 2 MHz to limit PLL jitter.
-  *      
+  *
   */
 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
-                                                     
+
 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
-  * @{   
+  * @{
   */
 
-/** @brief Macros to enable or disable the PLLI2S. 
+/** @brief Macros to enable or disable the PLLI2S.
   * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
   */
 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
@@ -1488,13 +1630,13 @@ typedef struct
 
 /** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
   * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).  
-  * @param  __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+  * @note   PLLI2S clock source is common with the main PLL (configured in
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
   *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO
   *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
-  * @param  __PLLI2SR__: specifies the division factor for I2S clock
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
   *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
   * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
   *         on the I2S clock frequency.
@@ -1503,7 +1645,7 @@ typedef struct
 
 /** @brief  Macro to configure the I2S clock source (I2SCLK).
   * @note   This function must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__: specifies the I2S clock source.
+  * @param  __SOURCE__ specifies the I2S clock source.
   *         This parameter can be one of the following values:
   *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
   *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
@@ -1516,8 +1658,8 @@ typedef struct
 
 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
   * @{
-  */ 
-  
+  */
+
 /** @brief  Macro to configure the MCO1 clock.
   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
   *          This parameter can be one of the following values:
@@ -1533,7 +1675,8 @@ typedef struct
   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
   */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
 
 /** @brief  Macro to configure the MCO2 clock.
   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
@@ -1550,7 +1693,8 @@ typedef struct
   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
   */
-#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
 /**
   * @}
   */
@@ -1560,7 +1704,7 @@ typedef struct
   */
 /**
   * @brief Macro to configure the system clock source.
-  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+  * @param  __RCC_SYSCLKSOURCE__ specifies the system clock source.
   * This parameter can be one of the following values:
   *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
   *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
@@ -1574,8 +1718,8 @@ typedef struct
   *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
   *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
   *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
-  */     
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
 
 /** @brief  Macro to get the oscillator used as PLL clock source.
   * @retval The oscillator used as PLL clock source. The returned value can be one
@@ -1595,7 +1739,7 @@ typedef struct
 
 /** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
   *         the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
   *         This parameter can be any combination of the following values:
   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1606,9 +1750,9 @@ typedef struct
   */
 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
 
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
   *        the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
   *         This parameter can be any combination of the following values:
   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1617,24 +1761,24 @@ typedef struct
   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
   *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
   */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
 
 /** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
   *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *         This parameter can be any combination of the following values:
   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
   *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
   *            @arg RCC_IT_HSERDY: HSE ready interrupt.
   *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.  
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
   *            @arg RCC_IT_CSS: Clock Security System interrupt
   */
 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
 
 /** @brief  Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
   *            @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1647,13 +1791,13 @@ typedef struct
   */
 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
 
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, 
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
   *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
   */
 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
 
 /** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
   *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
@@ -1670,14 +1814,14 @@ typedef struct
   *            @arg RCC_FLAG_LPWRRST: Low Power reset.
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define RCC_FLAG_MASK  ((uint8_t)0x1F)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
+#define RCC_FLAG_MASK  ((uint8_t)0x1FU)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
 
 #define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
 /**
   * @}
   */
-     
+
 /**
   * @}
   */
@@ -1691,9 +1835,9 @@ typedef struct
 
 /** @addtogroup RCC_Exported_Functions_Group1
   * @{
-  */                             
+  */
 /* Initialization and de-initialization functions  ******************************/
-void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
 /**
@@ -1717,7 +1861,7 @@ void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t
 /* CSS NMI IRQ handler */
 void HAL_RCC_NMI_IRQHandler(void);
 
-/* User Callbacks in non blocking mode (IT mode) */ 
+/* User Callbacks in non blocking mode (IT mode) */
 void HAL_RCC_CSSCallback(void);
 
 /**
@@ -1742,60 +1886,60 @@ void HAL_RCC_CSSCallback(void);
 #define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
 /* --- CR Register ---*/
 /* Alias word address of HSION bit */
-#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00)
-#define RCC_HSION_BIT_NUMBER       0x00
-#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
+#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
+#define RCC_HSION_BIT_NUMBER       0x00U
+#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
 /* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER       0x13
-#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
+#define RCC_CSSON_BIT_NUMBER       0x13U
+#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
 /* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER       0x18
-#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
+#define RCC_PLLON_BIT_NUMBER       0x18U
+#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
 /* Alias word address of PLLI2SON bit */
-#define RCC_PLLI2SON_BIT_NUMBER    0x1A
-#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
+#define RCC_PLLI2SON_BIT_NUMBER    0x1AU
+#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
 
 /* --- CFGR Register ---*/
 /* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08)
-#define RCC_I2SSRC_BIT_NUMBER      0x17
-#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
+#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
+#define RCC_I2SSRC_BIT_NUMBER      0x17U
+#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
 
 /* --- BDCR Register ---*/
 /* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70)
-#define RCC_RTCEN_BIT_NUMBER       0x0F
-#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
+#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
+#define RCC_RTCEN_BIT_NUMBER       0x0FU
+#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
 /* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER       0x10
-#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
+#define RCC_BDRST_BIT_NUMBER       0x10U
+#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
 
 /* --- CSR Register ---*/
 /* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74)
-#define RCC_LSION_BIT_NUMBER        0x00
-#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
+#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
+#define RCC_LSION_BIT_NUMBER        0x00U
+#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
 
 /* CR register byte 3 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS       ((uint32_t)0x40023802)
+#define RCC_CR_BYTE2_ADDRESS       0x40023802U
 
 /* CIR register byte 2 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
 
 /* CIR register byte 3 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
 
 /* BDCR register base address */
 #define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
 
-#define RCC_DBP_TIMEOUT_VALUE      ((uint32_t)100)
-#define RCC_LSE_TIMEOUT_VALUE      ((uint32_t)5000)
+#define RCC_DBP_TIMEOUT_VALUE      2U
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
 
 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
+#define HSI_TIMEOUT_VALUE          2U  /* 2 ms */
+#define LSI_TIMEOUT_VALUE          2U  /* 2 ms */
 
-#define PLLI2S_TIMEOUT_VALUE       ((uint32_t)100) /* Timeout value fixed to 100 ms  */
+#define PLLI2S_TIMEOUT_VALUE       2U  /* Timeout value fixed to 100 ms  */
 /**
   * @}
   */
@@ -1805,14 +1949,14 @@ void HAL_RCC_CSSCallback(void);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros RCC Private Macros
+/** @defgroup RCC_Private_Macros RCC Private Macros
   * @{
   */
-    
+
 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
   * @{
-  */  
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
+  */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
 
 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
                          ((HSE) == RCC_HSE_BYPASS))
@@ -1832,14 +1976,47 @@ void HAL_RCC_CSSCallback(void);
 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
                                      ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
                                      ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
- 
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
 
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
+
+#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
 
 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
                            ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
@@ -1847,7 +2024,7 @@ void HAL_RCC_CSSCallback(void);
                            ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
                            ((HCLK) == RCC_SYSCLK_DIV512))
 
-#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
 
 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
                            ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
@@ -1863,8 +2040,8 @@ void HAL_RCC_CSSCallback(void);
 
 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
                              ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
-                             ((DIV) == RCC_MCODIV_5)) 
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+                             ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
 
 /**
   * @}
@@ -1876,7 +2053,7 @@ void HAL_RCC_CSSCallback(void);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h
index fb7a3a9c..876d9851 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h
@@ -2,38 +2,20 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RCC_EX_H
@@ -126,7 +108,7 @@ typedef struct
   */
      
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+/** @defgroup RCCEx_Exported_Macros RCC Exported Macros
   * @{
   */
 
@@ -135,31 +117,32 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.
+  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
@@ -171,6 +154,31 @@ typedef struct
 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
 
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()    ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET) 
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+	                                       __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+	                                        __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+/**
+  * @}
+  */ 
+
 /**
   * @brief  Enable ETHERNET clock.
   */
@@ -197,10 +205,11 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.
+  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
@@ -212,14 +221,14 @@ typedef struct
 
 #if defined(STM32F215xx) || defined(STM32F217xx)
 #define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
                                        UNUSED(tmpreg); \
                                        } while(0)
 #define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg; \
+                                       __IO uint32_t tmpreg = 0x00; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
@@ -233,8 +242,31 @@ typedef struct
   * @}
   */
 
+/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F207xx) || defined(STM32F217xx)
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
+#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
+#if defined(STM32F215xx) || defined(STM32F217xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
+
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
+#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
+/**
+  * @}
+  */ 
+                                         
 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
   * @brief  Force or release AHB1 peripheral reset.
+  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
@@ -271,6 +303,7 @@ typedef struct
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
 #if defined(STM32F207xx) || defined(STM32F217xx)
 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
@@ -336,7 +369,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+/** @defgroup RCCEx_Private_Constants RCC Private Constants
   * @{
   */
 
@@ -354,7 +387,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
+/** @defgroup RCCEx_Private_Macros RCC Private Macros
   * @{
   */
 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h
index ced6c087..a8811e9a 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h
@@ -2,42 +2,24 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rng.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of RNG HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_RNG_H
-#define __STM32F2xx_HAL_RNG_H
+#ifndef STM32F2xx_HAL_RNG_H
+#define STM32F2xx_HAL_RNG_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -50,59 +32,103 @@
   * @{
   */
 
+#if defined (RNG)
+
 /** @defgroup RNG RNG
   * @brief RNG HAL module driver
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 
 /** @defgroup RNG_Exported_Types RNG Exported Types
   * @{
   */
 
-/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition 
+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
   * @{
   */
 typedef enum
 {
-  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
-  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
-    
-}HAL_RNG_StateTypeDef;
-
-/** 
+  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
+  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
+
+} HAL_RNG_StateTypeDef;
+
+/**
   * @}
   */
 
-/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition   
+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
   * @{
-  */ 
+  */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+typedef struct  __RNG_HandleTypeDef
+#else
 typedef struct
+#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
 {
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */ 
-  
+  RNG_TypeDef                 *Instance;    /*!< Register base address   */
+
   HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-  
+
   __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-  
+
+  __IO  uint32_t              ErrorCode;     /*!< RNG Error code               */
+
   uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
-  
-}RNG_HandleTypeDef;
 
-/** 
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
+  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
+
+  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
+  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
+#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+} RNG_HandleTypeDef;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL RNG Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
+
+  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
+  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
+
+} HAL_RNG_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL RNG Callback pointer definition
+  */
+typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
+typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
   * @}
   */
 
 /**
   * @}
-  */ 
-   
-/* Exported constants --------------------------------------------------------*/
+  */
 
+/* Exported constants --------------------------------------------------------*/
 /** @defgroup RNG_Exported_Constants RNG Exported Constants
   * @{
   */
@@ -123,57 +149,78 @@ typedef struct
 #define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
 #define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
 #define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
+/**
+  * @}
+  */
 
+/** @defgroup RNG_Error_Definition   RNG Error Definition
+  * @{
+  */
+#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error             */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */
+#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
+#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
+#define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
+  */
 
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup RNG_Exported_Macros RNG Exported Macros
   * @{
   */
 
 /** @brief Reset RNG handle state
-  * @param  __HANDLE__: RNG Handle
+  * @param  __HANDLE__ RNG Handle
   * @retval None
   */
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
+                                                       (__HANDLE__)->MspInitCallback = NULL;            \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                    } while(0U)
+#else
 #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
+  * @param  __HANDLE__ RNG Handle
   * @retval None
   */
 #define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
 
 /**
   * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__: RNG Handle
+  * @param  __HANDLE__ RNG Handle
   * @retval None
   */
 #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
 
 /**
   * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __FLAG__: RNG flag
+  * @param  __HANDLE__ RNG Handle
+  * @param  __FLAG__ RNG flag
   *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY: Data ready                
-  *            @arg RNG_FLAG_CECS: Clock error current status
-  *            @arg RNG_FLAG_SECS: Seed error current status 
+  *            @arg RNG_FLAG_DRDY:  Data ready
+  *            @arg RNG_FLAG_CECS:  Clock error current status
+  *            @arg RNG_FLAG_SECS:  Seed error current status
   * @retval The new state of __FLAG__ (SET or RESET).
   */
 #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
 /**
   * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__: RNG handle
-  * @param  __FLAG__: RNG flag to clear  
+  * @param  __HANDLE__ RNG handle
+  * @param  __FLAG__ RNG flag to clear
   * @note   WARNING: This is a dummy macro for HAL code alignment,
   *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
   * @retval None
@@ -182,130 +229,102 @@ typedef struct
 
 /**
   * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
+  * @param  __HANDLE__ RNG Handle
   * @retval None
   */
 #define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-    
+
 /**
   * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__: RNG Handle
+  * @param  __HANDLE__ RNG Handle
   * @retval None
   */
 #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
 
 /**
   * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
+  * @param  __HANDLE__ RNG Handle
+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
   *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt              
+  *            @arg RNG_IT_DRDY: Data ready interrupt
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__: RNG Handle
-  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:            
+  * @param  __HANDLE__ RNG Handle
+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:
   *            @arg RNG_IT_CEI: Clock error interrupt
   *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
   * @retval None
   */
 #define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
 
 /**
   * @}
-  */ 
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup RNG_Exported_Functions RNG Exported Functions
   * @{
   */
 
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
   * @{
-  */  
+  */
 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
 void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
 
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
 uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
 
 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
 HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Private_Types RNG Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */ 
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup RNG_Private_Defines RNG Private Defines
-  * @{
-  */
-
+uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
 /**
   * @}
-  */ 
-          
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Variables RNG Private Variables
-  * @{
   */
 
 /**
   * @}
-  */ 
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Constants RNG Private Constants
-  * @{
   */
 
-/**
-  * @}
-  */ 
-
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup RNG_Private_Macros RNG Private Macros
   * @{
@@ -314,43 +333,28 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
                        ((IT) == RNG_IT_SEI))
 
 #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                           ((FLAG) == RNG_FLAG_CECS) || \
-                           ((FLAG) == RNG_FLAG_SECS))
+                            ((FLAG) == RNG_FLAG_CECS) || \
+                            ((FLAG) == RNG_FLAG_SECS))
 
 /**
   * @}
-  */ 
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
-  * @{
   */
 
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private Functions
-  * @{
-  */
+#endif /* RNG */
 
 /**
   * @}
   */
 
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_RNG_H */
+
+#endif /* STM32F2xx_HAL_RNG_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h
index 119125b4..fad5b14e 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RTC_H
 #define __STM32F2xx_HAL_RTC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,52 +34,52 @@
 
 /** @addtogroup RTC
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup RTC_Exported_Types RTC Exported Types
   * @{
   */
-    
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
-  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */     
-  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */  
-  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */      
-                                                                        
-}HAL_RTCStateTypeDef;
+  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
+  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
+  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
 
-/** 
-  * @brief  RTC Configuration Structure definition  
+} HAL_RTCStateTypeDef;
+
+/**
+  * @brief  RTC Configuration Structure definition
   */
 typedef struct
 {
   uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */         
+                                 This parameter can be a value of @ref RTC_Hour_Formats */
 
   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        
-                               
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
   uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */   
-  
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   
-                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */      
-  
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ 
-  
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             
-}RTC_InitTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
+
+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
+                                 This parameter can be a value of @ref RTC_Output_selection_Definitions */
+
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+} RTC_InitTypeDef;
+
+/**
+  * @brief  RTC Time structure definition
   */
 typedef struct
 {
@@ -107,75 +89,117 @@ typedef struct
 
   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
+
   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
+
   uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ 
-  
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
   uint32_t DayLightSaving;  /*!< Specifies DayLight Save Operation.
                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-  
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
                                  in CR register to store the operation.
                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef; 
-  
-/** 
-  * @brief  RTC Date structure definition  
+} RTC_TimeTypeDef;
+
+/**
+  * @brief  RTC Date structure definition
   */
 typedef struct
 {
   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
-  
+
   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
 
   uint8_t Date;     /*!< Specifies the RTC Date.
                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-  
+
   uint8_t Year;     /*!< Specifies the RTC Date Year.
                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-                        
-}RTC_DateTypeDef;
 
-/** 
-  * @brief  RTC Alarm structure definition  
+} RTC_DateTypeDef;
+
+/**
+  * @brief  RTC Alarm structure definition
   */
 typedef struct
 {
   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-    
+
   uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
                                       This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-  
+
   uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-  
+
   uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
                                       If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
                                       If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-                                                                     
+
   uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            
-}RTC_AlarmTypeDef;
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
+} RTC_AlarmTypeDef;
 
-/** 
-  * @brief  RTC Handle Structure definition  
-  */ 
+/**
+  * @brief  RTC Handle Structure definition
+  */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
 typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
 {
   RTC_TypeDef                 *Instance;  /*!< Register base address    */
-   
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ 
-  
+
+  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
+
   HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-  
+
   __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-    
-}RTC_HandleTypeDef;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm A Event callback         */
+
+  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Alarm B Event callback         */
+
+  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);        /*!< RTC TimeStamp Event callback       */
+
+  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);      /*!< RTC WakeUpTimer Event callback     */
+
+  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);          /*!< RTC Tamper 1 Event callback        */
+
+  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);               /*!< RTC Msp Init callback              */
+
+  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);             /*!< RTC Msp DeInit callback            */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+} RTC_HandleTypeDef;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL RTC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00u,    /*!< RTC Alarm A Event Callback ID       */
+  HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01u,    /*!< RTC Alarm B Event Callback ID       */
+  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02u,    /*!< RTC TimeStamp Event Callback ID     */
+  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03u,    /*!< RTC Wake-Up Timer Event Callback ID */
+  HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04u,    /*!< RTC Tamper 1 Callback ID            */
+  HAL_RTC_MSPINIT_CB_ID                 = 0x0Eu,    /*!< RTC Msp Init callback ID            */
+  HAL_RTC_MSPDEINIT_CB_ID               = 0x0Fu     /*!< RTC Msp DeInit callback ID          */
+} HAL_RTC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL RTC Callback pointer definition
+  */
+typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -188,82 +212,82 @@ typedef struct
 
 /** @defgroup RTC_Hour_Formats RTC Hour Formats
   * @{
-  */ 
-#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
-#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
+  */
+#define RTC_HOURFORMAT_24              0x00000000U
+#define RTC_HOURFORMAT_12              0x00000040U
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
   * @{
-  */ 
-#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
-#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
-#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
-#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
+  */
+#define RTC_OUTPUT_DISABLE             0x00000000U
+#define RTC_OUTPUT_ALARMA              0x00200000U
+#define RTC_OUTPUT_ALARMB              0x00400000U
+#define RTC_OUTPUT_WAKEUP              0x00600000U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
   * @{
-  */ 
-#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
-#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
+  */
+#define RTC_OUTPUT_POLARITY_HIGH       0x00000000U
+#define RTC_OUTPUT_POLARITY_LOW        0x00100000U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
   * @{
-  */ 
-#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
-#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000)
+  */
+#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000U
+#define RTC_OUTPUT_TYPE_PUSHPULL       0x00040000U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
   * @{
-  */ 
+  */
 #define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
 #define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
   * @{
-  */ 
-#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
-#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
-#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
+  */
+#define RTC_DAYLIGHTSAVING_SUB1H       0x00020000U
+#define RTC_DAYLIGHTSAVING_ADD1H       0x00010000U
+#define RTC_DAYLIGHTSAVING_NONE        0x00000000U
 /**
   * @}
   */
 
 /** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
   * @{
-  */ 
-#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
-#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
+  */
+#define RTC_STOREOPERATION_RESET        0x00000000U
+#define RTC_STOREOPERATION_SET          0x00040000U
 /**
   * @}
   */
 
 /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
   * @{
-  */ 
-#define RTC_FORMAT_BIN                      ((uint32_t)0x000000000)
-#define RTC_FORMAT_BCD                      ((uint32_t)0x000000001)
+  */
+#define RTC_FORMAT_BIN                      0x00000000U
+#define RTC_FORMAT_BCD                      0x00000001U
 /**
   * @}
   */
 
 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
   * @{
-  */ 
+  */
 /* Coded in BCD format */
 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
@@ -279,11 +303,11 @@ typedef struct
 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
   * @{
-  */   
+  */
 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
@@ -293,197 +317,205 @@ typedef struct
 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
   * @{
-  */ 
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
+  */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   0x40000000U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
   * @{
-  */ 
-#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
+  */
+#define RTC_ALARMMASK_NONE                0x00000000U
 #define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
 #define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
 #define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
 #define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
+#define RTC_ALARMMASK_ALL                 0x80808080U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
   * @{
-  */ 
+  */
 #define RTC_ALARM_A                       RTC_CR_ALRAE
 #define RTC_ALARM_B                       RTC_CR_ALRBE
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
   * @{
-  */ 
-#define RTC_IT_TS                         ((uint32_t)0x00008000)
-#define RTC_IT_WUT                        ((uint32_t)0x00004000)
-#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
-#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
-#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+  */
+#define RTC_IT_TS                         0x00008000U
+#define RTC_IT_WUT                        0x00004000U
+#define RTC_IT_ALRB                       0x00002000U
+#define RTC_IT_ALRA                       0x00001000U
+#define RTC_IT_TAMP                       0x00000004U /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      0x00020000U
 /**
   * @}
   */
 
 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
   * @{
-  */ 
-#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
-#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+  */
+#define RTC_FLAG_TAMP1F                   0x00002000U
+#define RTC_FLAG_TSOVF                    0x00001000U
+#define RTC_FLAG_TSF                      0x00000800U
+#define RTC_FLAG_WUTF                     0x00000400U
+#define RTC_FLAG_ALRBF                    0x00000200U
+#define RTC_FLAG_ALRAF                    0x00000100U
+#define RTC_FLAG_INITF                    0x00000040U
+#define RTC_FLAG_RSF                      0x00000020U
+#define RTC_FLAG_INITS                    0x00000010U
+#define RTC_FLAG_WUTWF                    0x00000004U
+#define RTC_FLAG_ALRBWF                   0x00000002U
+#define RTC_FLAG_ALRAWF                   0x00000001U
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
-  
+  */
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup RTC_Exported_Macros RTC Exported Macros
   * @{
   */
 
 /** @brief Reset RTC handle state
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                     }while(0u)
+#else
 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
 
 /**
   * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
                         do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCA;   \
-                            (__HANDLE__)->Instance->WPR = 0x53;   \
-                          } while(0)
+                            (__HANDLE__)->Instance->WPR = 0xCAU;  \
+                            (__HANDLE__)->Instance->WPR = 0x53U;  \
+                          } while(0U)
 
 /**
   * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
                         do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFF;   \
-                          } while(0)                            
- 
+                            (__HANDLE__)->Instance->WPR = 0xFFU;  \
+                          } while(0U)
+
 /**
   * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
 
 /**
   * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
 
 /**
   * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
 
 /**
   * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
 
 /**
   * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt  
+  *             @arg RTC_IT_ALRB: Alarm B interrupt
   * @retval None
-  */   
+  */
 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *         This parameter can be any combination of the following values:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
   * @retval None
   */
 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
   * @retval None
   */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)           (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
 
 /**
   * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag to check.
   *         This parameter can be:
   *            @arg RTC_FLAG_ALRAF
   *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF     
-  *            @arg RTC_FLAG_ALRBWF    
+  *            @arg RTC_FLAG_ALRAWF
+  *            @arg RTC_FLAG_ALRBWF
   * @retval None
   */
 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
   *          This parameter can be:
   *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF 
+  *             @arg RTC_FLAG_ALRBF
   * @retval None
   */
 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-  
-  
+
+
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_ALRA: Alarm A interrupt
   *            @arg RTC_IT_ALRB: Alarm B interrupt
@@ -516,40 +548,44 @@ typedef struct
 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
-  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
 /**
-  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();\
+                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
+                                                            }while(0U)
 
 /**
-  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
+                                                               __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
+                                                             }while(0U)
 
 /**
   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
@@ -588,6 +624,12 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
 void       HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
 void       HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -623,7 +665,7 @@ void         HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
 /**
   * @}
   */
@@ -648,16 +690,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Masks Definition */
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_TR_RESERVED_MASK    0x007F7F7FU
+#define RTC_DR_RESERVED_MASK    0x00FFFF3FU
+#define RTC_INIT_MASK           0xFFFFFFFFU
+#define RTC_RSF_MASK            0xFFFFFF5FU
 #define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
                                             RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
                                             RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
                                             RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
 
-#define RTC_TIMEOUT_VALUE       1000
+#define RTC_TIMEOUT_VALUE       1000U
 
 #define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
 /**
@@ -682,12 +724,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                 ((POL) == RTC_OUTPUT_POLARITY_LOW))
 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x1FFF)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x1FFFU)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
 
 #define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
@@ -696,9 +738,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                            ((OPERATION) == RTC_STOREOPERATION_SET))
 #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                  ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -706,7 +748,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                  ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
                                  ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
                                  ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -716,7 +758,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                                     ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
 #define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
 /**
   * @}
@@ -730,7 +772,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 /** @defgroup RTC_Private_Functions RTC Private Functions
   * @{
   */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
 uint8_t            RTC_ByteToBcd2(uint8_t Value);
 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 /**
@@ -739,12 +781,12 @@ uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h
index 101ba3c6..4b7dbe24 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_RTC_EX_H
 #define __STM32F2xx_HAL_RTC_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -53,73 +35,73 @@
 /** @addtogroup RTCEx
   * @{
   */
- 
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTCEx_Exported_Types RTC Exported Types
   * @{
   */
 
-/** @brief  RTC Tamper structure definition  
+/** @brief  RTC Tamper structure definition
   */
-typedef struct 
+typedef struct
 {
   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-  
+
   uint32_t PinSelection;                /*!< Specifies the Tamper Pin.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Selection */
-                                             
+
   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-}RTC_TamperTypeDef;
+} RTC_TamperTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
+/** @defgroup RTCEx_Exported_Constants RTC Exported Constants
   * @{
-  */ 
+  */
 
 /** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
   * @{
   */
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+#define RTC_BKP_DR0                       0x00000000U
+#define RTC_BKP_DR1                       0x00000001U
+#define RTC_BKP_DR2                       0x00000002U
+#define RTC_BKP_DR3                       0x00000003U
+#define RTC_BKP_DR4                       0x00000004U
+#define RTC_BKP_DR5                       0x00000005U
+#define RTC_BKP_DR6                       0x00000006U
+#define RTC_BKP_DR7                       0x00000007U
+#define RTC_BKP_DR8                       0x00000008U
+#define RTC_BKP_DR9                       0x00000009U
+#define RTC_BKP_DR10                      0x0000000AU
+#define RTC_BKP_DR11                      0x0000000BU
+#define RTC_BKP_DR12                      0x0000000CU
+#define RTC_BKP_DR13                      0x0000000DU
+#define RTC_BKP_DR14                      0x0000000EU
+#define RTC_BKP_DR15                      0x0000000FU
+#define RTC_BKP_DR16                      0x00000010U
+#define RTC_BKP_DR17                      0x00000011U
+#define RTC_BKP_DR18                      0x00000012U
+#define RTC_BKP_DR19                      0x00000013U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
   * @{
-  */ 
-#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
+  */
+#define RTC_TIMESTAMPEDGE_RISING          0x00000000U
+#define RTC_TIMESTAMPEDGE_FALLING         0x00000008U
 /**
   * @}
   */
-  
+
 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
   * @{
-  */ 
+  */
 #define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
 /**
   * @}
@@ -127,62 +109,62 @@ typedef struct
 
 /** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
   * @{
-  */ 
-#define RTC_TAMPERPIN_DEFAULT               ((uint32_t)0x00000000)
-#define RTC_TAMPERPIN_POS1                  ((uint32_t)0x00010000)
+  */
+#define RTC_TAMPERPIN_DEFAULT               0x00000000U
+#define RTC_TAMPERPIN_POS1                  0x00010000U
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
   * @{
-  */ 
-#define RTC_TIMESTAMPPIN_DEFAULT            ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPPIN_POS1               ((uint32_t)0x00020000)
+  */
+#define RTC_TIMESTAMPPIN_DEFAULT            0x00000000U
+#define RTC_TIMESTAMPPIN_POS1               0x00020000U
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
   * @{
-  */ 
-#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
+  */
+#define RTC_TAMPERTRIGGER_RISINGEDGE       0x00000000U
+#define RTC_TAMPERTRIGGER_FALLINGEDGE      0x00000002U
 
 /**
   * @}
-  */  
+  */
 
 /** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
   * @{
-  */ 
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
+  */
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         0x00000001U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         0x00000002U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         0x00000003U
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      0x00000004U
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      0x00000006U
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
   * @{
-  */ 
-#define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000) 
-#define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080)
+  */
+#define RTC_CALIBSIGN_POSITIVE            0x00000000U
+#define RTC_CALIBSIGN_NEGATIVE            0x00000080U
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
-  
+  */
+
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
+/** @defgroup RTCEx_Exported_Macros RTC Exported Macros
   * @{
   */
 
@@ -193,22 +175,22 @@ typedef struct
 
 /**
   * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
 
 /**
   * @brief  Disable the RTC Wake-up Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
 
 /**
   * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
   * @retval None
@@ -217,8 +199,8 @@ typedef struct
 
 /**
   * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
   *         This parameter can be:
   *            @arg RTC_IT_WUT: WakeUpTimer A interrupt
   * @retval None
@@ -227,18 +209,18 @@ typedef struct
 
 /**
   * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
   * @retval None
   */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
   *         This parameter can be:
   *            @arg RTC_IT_WUT:  WakeUpTimer interrupt
   * @retval None
@@ -247,24 +229,24 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to check.
   *          This parameter can be:
-  *             @arg RTC_FLAG_WUTF   
-  *             @arg RTC_FLAG_WUTWF     
+  *             @arg RTC_FLAG_WUTF
+  *             @arg RTC_FLAG_WUTWF
   * @retval None
   */
 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
   *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF   
+  *            @arg RTC_FLAG_WUTF
   * @retval None
   */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))  
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
 
 /**
   * @brief  Enable interrupt on the RTC Wake-up Timer associated Exti line.
@@ -291,7 +273,7 @@ typedef struct
 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line. 
+  * @brief  Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -318,14 +300,18 @@ typedef struct
   * @brief  Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
+                                                                    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
+                                                                  }while(0U)
 
 /**
   * @brief  Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
+                                                                     __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
+                                                                   }while(0U)
 
 /**
   * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
@@ -356,22 +342,22 @@ typedef struct
 
 /**
   * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
 
 /**
   * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
 
 /**
   * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -380,8 +366,8 @@ typedef struct
 
 /**
   * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -390,18 +376,18 @@ typedef struct
 
 /**
   * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
   */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)         (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TS: TimeStamp interrupt
   * @retval None
@@ -410,21 +396,21 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp flag to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC TimeStamp flag to check.
   *         This parameter can be:
-  *            @arg RTC_FLAG_TSF   
-  *            @arg RTC_FLAG_TSOVF     
+  *            @arg RTC_FLAG_TSF
+  *            @arg RTC_FLAG_TSOVF
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
   *          This parameter can be:
-  *             @arg RTC_FLAG_TSF  
+  *             @arg RTC_FLAG_TSF
   * @retval None
   */
 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)          ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -440,32 +426,32 @@ typedef struct
 
 /**
   * @brief  Enable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Disable the RTC Tamper1 input detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
   *         This parameter can be:
   *            @arg  RTC_IT_TAMP1
   * @retval None
   */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
   *         This parameter can be:
   *            @arg RTC_IT_TAMP: Tamper interrupt
   * @retval None
@@ -474,18 +460,18 @@ typedef struct
 
 /**
   * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
   *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP1F 
+  *             @arg RTC_FLAG_TAMP1F
   * @retval None
   */
 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
 
 /**
   * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag to clear.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
   *          This parameter can be:
   *             @arg RTC_FLAG_TAMP1F
   * @retval None
@@ -525,7 +511,7 @@ typedef struct
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
 
 /**
-  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. 
+  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * @retval None.
   */
 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -552,14 +538,18 @@ typedef struct
   * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * @retval None.
   */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
+                                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\
+                                                                       }while(0U)
 
 /**
   * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
   * This parameter can be:
   * @retval None.
   */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
+                                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
+                                                                        }while(0U)
 
 /**
   * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
@@ -589,42 +579,42 @@ typedef struct
 
 /**
   * @brief  Enable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
 
 /**
   * @brief  Disable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
 
 /**
   * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
 
 /**
   * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
 
 /**
   * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
 
 /**
   * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
 #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
@@ -638,7 +628,7 @@ typedef struct
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+/** @defgroup RTCEx_Exported_Functions RTC Exported Functions
   * @{
   */
 
@@ -651,8 +641,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
 
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
 
@@ -688,7 +678,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
 
 HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
@@ -700,7 +690,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
   * @{
   */
 /* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
 /**
   * @}
@@ -710,26 +700,26 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+/** @defgroup RTCEx_Private_Constants RTC Private Constants
   * @{
   */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */  
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)EXTI_IMR_MR21)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)EXTI_IMR_MR22)  /*!< External interrupt line 22 Connected to the RTC Wake-up event */
 /**
   * @}
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+/** @defgroup RTCEx_Private_Macros RTC Private Macros
   * @{
   */
 
 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
   * @{
-  */ 
+  */
 #define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0)  || \
                                            ((BKP) == RTC_BKP_DR1)  || \
                                            ((BKP) == RTC_BKP_DR2)  || \
@@ -769,12 +759,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
                                     ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
 
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFFU)
 #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
                                  ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
 
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E))) == 0x00) && ((TAMPER) != (uint32_t)RESET)) 
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~(RTC_TAFCR_TAMP1E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
 /**
   * @}
   */
@@ -785,11 +775,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
index 796ee074..a4317e48 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
@@ -2,47 +2,31 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sd.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_SD_H
-#define __STM32F2xx_HAL_SD_H
+#ifndef STM32F2xx_HAL_SD_H
+#define STM32F2xx_HAL_SD_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#if defined(SDIO)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_sdmmc.h"
 
@@ -53,55 +37,135 @@
 /** @defgroup SD SD
   * @brief SD HAL module driver
   * @{
-  */
+  */ 
 
 /* Exported types ------------------------------------------------------------*/ 
 /** @defgroup SD_Exported_Types SD Exported Types
   * @{
   */
 
-/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */
+  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */
+  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */
+  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */
+  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */
+  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */
+  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */
+  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */
+}HAL_SD_StateTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+  * @{
+  */   
+typedef uint32_t HAL_SD_CardStateTypeDef;
+
+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition   
   * @{
   */
 #define SD_InitTypeDef      SDIO_InitTypeDef 
 #define SD_TypeDef          SDIO_TypeDef
 
+/** 
+  * @brief  SD Card Information Structure definition
+  */ 
 typedef struct
 {
-  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
+  uint32_t CardType;                     /*!< Specifies the card Type                         */
   
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
+  uint32_t CardVersion;                  /*!< Specifies the card version                      */
+
+  uint32_t Class;                        /*!< Specifies the class of the card class           */
+
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
   
-  uint32_t                     CardType;         /*!< SD card type                                   */
+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
+
+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
   
-  uint32_t                     RCA;              /*!< SD relative card address                       */
+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
+
+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
+
+}HAL_SD_CardInfoTypeDef;
+
+/** 
+  * @brief  SD handle Structure definition
+  */ 
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+typedef struct __SD_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+{
+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */
   
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
   
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
   
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
+
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
+
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
   
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
+ 
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
   
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */  
+ 
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
+
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
   
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
   
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
+  uint32_t                     CSD[4];           /*!< SD card specific data table         */
   
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
+  uint32_t                     CID[4];           /*!< SD card identification number table */
   
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);
+  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);
+  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);
+
+  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);
+  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 }SD_HandleTypeDef;
+
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register 
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register 
   * @{
-  */ 
+  */
 typedef struct
 {
   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
@@ -133,7 +197,7 @@ typedef struct
   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
   __IO uint8_t  Reserved3;            /*!< Reserved                              */
   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */
   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
@@ -141,15 +205,14 @@ typedef struct
   __IO uint8_t  ECC;                  /*!< ECC code                              */
   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
   __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
+}HAL_SD_CardCSDTypeDef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
   * @{
-  */ 
+  */
 typedef struct
 {
   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
@@ -163,304 +226,202 @@ typedef struct
   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
   __IO uint8_t  Reserved2;       /*!< Always 1              */
 
-}HAL_SD_CIDTypedef;
+}HAL_SD_CardCIDTypeDef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 
   * @{
-  */ 
+  */
 typedef struct
 {
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t CardType;               /*!< Carries information about card type                        */
+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypeDef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group5 SD Card information structure 
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition 
   * @{
-  */ 
-typedef struct
+  */
+typedef enum
 {
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */
+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */
+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */
+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */
+
+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */
+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */
+}HAL_SD_CallbackIDTypeDef;
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition 
+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition 
   * @{
-  */ 
-typedef enum
-{
-/** 
-  * @brief  SD specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDIO_DISABLED                   = (30),
-  SD_SDIO_FUNCTION_BUSY              = (31),
-  SD_SDIO_FUNCTION_FAILED            = (32),
-  SD_SDIO_UNKNOWN_FUNCTION           = (33),
-
+  */
+typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);
 /** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR                  = (34),
-  SD_NOT_CONFIGURED                  = (35),
-  SD_REQUEST_PENDING                 = (36),
-  SD_REQUEST_NOT_APPLICABLE          = (37),
-  SD_INVALID_PARAMETER               = (38),
-  SD_UNSUPPORTED_FEATURE             = (39),
-  SD_UNSUPPORTED_HW                  = (40),
-  SD_ERROR                           = (41),
-  SD_OK                              = (0) 
-
-}HAL_SD_ErrorTypedef;
+  * @}
+  */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 /** 
   * @}
   */
 
-/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
   * @{
-  */ 
-typedef enum
-{
-  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-/** 
-  * @}
   */
 
-/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
+#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition 
   * @{
   */  
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the 
+                                                                                       number of transferred bytes does not match the block length   */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock 
+                                                                                       command or if there was an attempt to access a locked card    */
+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out 
+                                                                                       of erase sequence command was received                        */
+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */        
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */        
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */  
+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */  
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */ 
+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
+                                                
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 /** 
   * @}
   */
-
-/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
+ 
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
   * @{
-  */  
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
+  */ 
+#define SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */
+#define SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */
+#define SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */
+#define SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */
 
-}HAL_SD_OperationTypedef;
 /**
   * @}
   */
 
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
+  * @{
+  */
+#define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
+#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
+#define CARD_SECURED               ((uint32_t)0x00000003U)
+    
 /**
   * @}
   */
 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
   * @{
   */
-
-/** 
-  * @brief SD Commands Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64) 
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
-
-/** 
-  * @brief Supported SD Memory Cards 
+#define CARD_V1_X                  ((uint32_t)0x00000000U)
+#define CARD_V2_X                  ((uint32_t)0x00000001U)
+/**
+  * @}
   */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+      
 /**
   * @}
   */
   
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup SD_Exported_macros SD Exported Macros
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+/** @brief Reset SD handle state.
+  * @param  __HANDLE__ : SD handle.
+  * @retval None
   */
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \
+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
  
 /**
   * @brief  Enable the SD device.
   * @retval None
   */ 
-#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
+#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
 
 /**
   * @brief  Disable the SD device.
   * @retval None
   */
-#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
+#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
 
 /**
-  * @brief  Enable the SDIO DMA transfer.
+  * @brief  Enable the SDMMC DMA transfer.
   * @retval None
   */ 
-#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
 
 /**
-  * @brief  Disable the SDIO DMA transfer.
+  * @brief  Disable the SDMMC DMA transfer.
   * @retval None
   */
-#define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
+#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
  
 /**
   * @brief  Enable the SD device interrupt.
   * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
   *         This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -470,9 +431,7 @@ typedef enum
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -485,16 +444,15 @@ typedef enum
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
   * @retval None
   */
-#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 
 /**
   * @brief  Disable the SD device interrupt.
   * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -504,9 +462,7 @@ typedef enum
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -519,11 +475,10 @@ typedef enum
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
   * @retval None
   */
-#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 
 /**
   * @brief  Check whether the specified SD flag is set or not. 
@@ -538,8 +493,7 @@ typedef enum
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
@@ -552,11 +506,10 @@ typedef enum
   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
   * @retval The new state of SD FLAG (SET or RESET).
   */
-#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
 
 /**
   * @brief  Clear the SD's pending flags.
@@ -571,19 +524,17 @@ typedef enum
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
   * @retval None
   */
-#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
 
 /**
   * @brief  Check whether the specified SD interrupt has occurred or not.
   * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
   *          This parameter can be one of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -593,9 +544,7 @@ typedef enum
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -608,15 +557,14 @@ typedef enum
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
   * @retval The new state of SD IT (SET or RESET).
   */
-#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
 
 /**
   * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__ : SD Handle
+  * @param  __HANDLE__: SD Handle
   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
   *          This parameter can be one or a combination of the following values:
   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -627,14 +575,12 @@ typedef enum
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
   * @retval None
   */
-#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
 /**
   * @}
   */
@@ -643,68 +589,87 @@ typedef enum
 /** @defgroup SD_Exported_Functions SD Exported Functions
   * @{
   */
-
+  
 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
-
-/** @defgroup SD_Exported_Functions_Group2 I/O operation functions
+  
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
 /* Blocking mode: Polling */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 
-/* Non-Blocking mode: Interrupt */
 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
 
 /* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/* SD callback registering/unregistering */
+HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
 
-/* Non-Blocking mode: DMA */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
 /**
   * @}
   */
-
+  
 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
   * @{
   */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);
 /**
   * @}
   */
-  
-/* Peripheral State functions  ************************************************/
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
+
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
   * @{
   */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
 /**
   * @}
   */
-  
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
+  * @{
+  */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+  * @{
+  */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
@@ -772,18 +737,26 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
   * @}
   */
 
+
 /**
   * @}
   */ 
 
 /**
   * @}
-  */ 
+  */
+
+/**
+  * @}
+  */
+
+#endif /* SDIO */
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_SD_H */
+
+#endif /* STM32F2xx_HAL_SD_H */ 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h
index 4007d182..f2cdfb84 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h
@@ -2,35 +2,17 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of SMARTCARD HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -54,20 +36,20 @@
   * @{
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
   * @{
   */
 
-/** 
+/**
   * @brief SMARTCARD Init Structure definition
   */
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
                                            The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
+                                           - IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
 
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
                                            This parameter can be a value of @ref SMARTCARD_Word_Length */
@@ -75,7 +57,7 @@ typedef struct
   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits */
 
-  uint32_t Parity;                   /*!< Specifies the parity mode.
+  uint32_t Parity;                    /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref SMARTCARD_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
@@ -95,65 +77,157 @@ typedef struct
                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
 
-  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock 
-                                           to provide the smartcard clock
+  uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
+                                           to provide the smartcard clock. The value given in the register (5 significant bits)
+                                           is multiplied by 2 to give the division factor of the source clock frequency.
                                            This parameter can be a value of @ref SMARTCARD_Prescaler */
-  
-  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks
-                                           The value given in the register (5 significant bits) is multiplied by 2 
-                                           to give the division factor of the source clock frequency */
+
+  uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
 
   uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state.
                                            This parameter can be a value of @ref SMARTCARD_NACK_State */
 }SMARTCARD_InitTypeDef;
 
-/** 
-  * @brief HAL State structures definition
+/**
+  * @brief HAL SMARTCARD State structures definition
+  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains SMARTCARD state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
   */
 typedef enum
 {
-  HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
-  HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */ 
-  HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error                                              */
+  HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                        Value is allowed for RxState only */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
+                                                        Not to be used for neither gState nor RxState.
+                                                        Value is result of combination (Or) between gState and RxState values */
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error
+                                                        Value is allowed for gState only */
 }HAL_SMARTCARD_StateTypeDef;
 
-/** 
+/**
   * @brief  SMARTCARD handle Structure definition
   */
-typedef struct
+typedef struct __SMARTCARD_HandleTypeDef
 {
-  USART_TypeDef                    *Instance;        /* USART registers base address */
+  USART_TypeDef                    *Instance;        /*!< USART registers base address */
+
+  SMARTCARD_InitTypeDef            Init;             /*!< SmartCard communication parameters */
+
+  uint8_t                          *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer */
+
+  uint16_t                         TxXferSize;       /*!< SmartCard Tx Transfer size */
+
+  __IO uint16_t                    TxXferCount;      /*!< SmartCard Tx Transfer Counter */
 
-  SMARTCARD_InitTypeDef            Init;             /* SmartCard communication parameters */
+  uint8_t                          *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer */
 
-  uint8_t                          *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer */
+  uint16_t                         RxXferSize;       /*!< SmartCard Rx Transfer size */
 
-  uint16_t                         TxXferSize;       /* SmartCard Tx Transfer size */
+  __IO uint16_t                    RxXferCount;      /*!< SmartCard Rx Transfer Counter */
 
-  uint16_t                         TxXferCount;      /* SmartCard Tx Transfer Counter */
+  DMA_HandleTypeDef                *hdmatx;          /*!< SmartCard Tx DMA Handle parameters */
 
-  uint8_t                          *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer */
+  DMA_HandleTypeDef                *hdmarx;          /*!< SmartCard Rx DMA Handle parameters */
 
-  uint16_t                         RxXferSize;       /* SmartCard Rx Transfer size */
+  HAL_LockTypeDef                  Lock;             /*!< Locking object */
 
-  uint16_t                         RxXferCount;      /* SmartCard Rx Transfer Counter */
+  __IO HAL_SMARTCARD_StateTypeDef  gState;           /*!< SmartCard state information related to global Handle management
+                                                        and also related to Tx operations.
+                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
 
-  DMA_HandleTypeDef                *hdmatx;          /* SmartCard Tx DMA Handle parameters */
+  __IO HAL_SMARTCARD_StateTypeDef  RxState;          /*!< SmartCard state information related to Rx operations.
+                                                        This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
 
-  DMA_HandleTypeDef                *hdmarx;          /* SmartCard Rx DMA Handle parameters */
+  __IO uint32_t                    ErrorCode;        /*!< SmartCard Error code */
 
-  HAL_LockTypeDef                  Lock;             /* Locking object */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Tx Complete Callback             */
 
-  __IO HAL_SMARTCARD_StateTypeDef  State;            /* SmartCard communication state */
+  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);            /*!< SMARTCARD Rx Complete Callback             */
 
-  __IO uint32_t  ErrorCode;                          /* SmartCard Error code */
+  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc);             /*!< SMARTCARD Error Callback                   */
 
-}SMARTCARD_HandleTypeDef;
+  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Abort Complete Callback          */
+
+  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc);  /*!< SMARTCARD Abort Receive Complete Callback  */
+
+  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);           /*!< SMARTCARD Msp Init callback                */
+
+  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc);         /*!< SMARTCARD Msp DeInit callback              */
+#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SMARTCARD Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
+  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
+  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
+  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
+  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
+  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
+
+  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
+  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SMARTCARD Callback pointer definition
+  */
+typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc);  /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -163,16 +237,19 @@ typedef struct
 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
   * @{
   */
+
 /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
-  * @brief    SMARTCARD Error Code 
   * @{
-  */ 
-#define HAL_SMARTCARD_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
-#define HAL_SMARTCARD_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
-#define HAL_SMARTCARD_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
-#define HAL_SMARTCARD_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
-#define HAL_SMARTCARD_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
-#define HAL_SMARTCARD_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
+  */
+#define HAL_SMARTCARD_ERROR_NONE             0x00000000U   /*!< No error            */
+#define HAL_SMARTCARD_ERROR_PE               0x00000001U   /*!< Parity error        */
+#define HAL_SMARTCARD_ERROR_NE               0x00000002U   /*!< Noise error         */
+#define HAL_SMARTCARD_ERROR_FE               0x00000004U   /*!< Frame error         */
+#define HAL_SMARTCARD_ERROR_ORE              0x00000008U   /*!< Overrun error       */
+#define HAL_SMARTCARD_ERROR_DMA              0x00000010U   /*!< DMA transfer error  */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -180,7 +257,7 @@ typedef struct
 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
   * @{
   */
-#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
@@ -188,8 +265,8 @@ typedef struct
 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
   * @{
   */
-#define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)
+#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
 /**
   * @}
   */
@@ -197,8 +274,8 @@ typedef struct
 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
   * @{
   */
-#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)
+#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
 /**
   * @}
   */
@@ -206,9 +283,9 @@ typedef struct
 /** @defgroup SMARTCARD_Mode SMARTCARD Mode
   * @{
   */
-#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)
+#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)
+#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
 /**
   * @}
   */
@@ -216,17 +293,17 @@ typedef struct
 /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
   * @{
   */
-#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
-#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
+#define SMARTCARD_POLARITY_LOW              0x00000000U
+#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
   * @{
   */
-#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
-#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
+#define SMARTCARD_PHASE_1EDGE               0x00000000U
+#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
   */
@@ -234,8 +311,8 @@ typedef struct
 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
   * @{
   */
-#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
-#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
+#define SMARTCARD_LASTBIT_DISABLE           0x00000000U
+#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
   */
@@ -243,8 +320,8 @@ typedef struct
 /** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
   * @{
   */
-#define SMARTCARD_NACK_ENABLE                  ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE                 ((uint32_t)0x00000000)
+#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE              0x00000000U
 /**
   * @}
   */
@@ -252,8 +329,8 @@ typedef struct
 /** @defgroup SMARTCARD_DMA_Requests   SMARTCARD DMA requests
   * @{
   */
-#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
+#define SMARTCARD_DMAREQ_TX                 ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX                 ((uint32_t)USART_CR3_DMAR)
 /**
   * @}
   */
@@ -261,72 +338,72 @@ typedef struct
 /** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
   * @{
   */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2         ((uint32_t)0x00000001)          /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4         ((uint32_t)0x00000002)          /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6         ((uint32_t)0x00000003)          /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8         ((uint32_t)0x00000004)          /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10        ((uint32_t)0x00000005)          /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12        ((uint32_t)0x00000006)          /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14        ((uint32_t)0x00000007)          /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16        ((uint32_t)0x00000008)          /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18        ((uint32_t)0x00000009)          /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20        ((uint32_t)0x0000000A)          /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22        ((uint32_t)0x0000000B)          /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24        ((uint32_t)0x0000000C)          /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26        ((uint32_t)0x0000000D)          /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28        ((uint32_t)0x0000000E)          /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30        ((uint32_t)0x0000000F)          /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32        ((uint32_t)0x00000010)          /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34        ((uint32_t)0x00000011)          /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36        ((uint32_t)0x00000012)          /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38        ((uint32_t)0x00000013)          /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40        ((uint32_t)0x00000014)          /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42        ((uint32_t)0x00000015)          /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44        ((uint32_t)0x00000016)          /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46        ((uint32_t)0x00000017)          /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48        ((uint32_t)0x00000018)          /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50        ((uint32_t)0x00000019)          /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52        ((uint32_t)0x0000001A)          /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54        ((uint32_t)0x0000001B)          /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56        ((uint32_t)0x0000001C)          /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58        ((uint32_t)0x0000001D)          /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60        ((uint32_t)0x0000001E)          /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62        ((uint32_t)0x0000001F)          /*!< SYSCLK divided by 62 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2     0x00000001U          /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4     0x00000002U          /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6     0x00000003U          /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8     0x00000004U          /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10    0x00000005U          /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12    0x00000006U          /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14    0x00000007U          /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16    0x00000008U          /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18    0x00000009U          /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20    0x0000000AU          /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22    0x0000000BU          /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24    0x0000000CU          /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26    0x0000000DU          /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28    0x0000000EU          /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30    0x0000000FU          /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32    0x00000010U          /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34    0x00000011U          /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36    0x00000012U          /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38    0x00000013U          /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40    0x00000014U          /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42    0x00000015U          /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44    0x00000016U          /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46    0x00000017U          /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48    0x00000018U          /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50    0x00000019U          /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52    0x0000001AU          /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54    0x0000001BU          /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56    0x0000001CU          /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58    0x0000001DU          /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60    0x0000001EU          /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62    0x0000001FU          /*!< SYSCLK divided by 62 */
 /**
   * @}
   */
 
-/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+/** @defgroup SmartCard_Flags SMARTCARD Flags
   *        Elements values convention: 0xXXXX
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define SMARTCARD_FLAG_TXE                       ((uint32_t)0x00000080)
-#define SMARTCARD_FLAG_TC                        ((uint32_t)0x00000040)
-#define SMARTCARD_FLAG_RXNE                      ((uint32_t)0x00000020)
-#define SMARTCARD_FLAG_IDLE                      ((uint32_t)0x00000010)
-#define SMARTCARD_FLAG_ORE                       ((uint32_t)0x00000008)
-#define SMARTCARD_FLAG_NE                        ((uint32_t)0x00000004)
-#define SMARTCARD_FLAG_FE                        ((uint32_t)0x00000002)
-#define SMARTCARD_FLAG_PE                        ((uint32_t)0x00000001)
+#define SMARTCARD_FLAG_TXE                  ((uint32_t)USART_SR_TXE)
+#define SMARTCARD_FLAG_TC                   ((uint32_t)USART_SR_TC)
+#define SMARTCARD_FLAG_RXNE                 ((uint32_t)USART_SR_RXNE)
+#define SMARTCARD_FLAG_IDLE                 ((uint32_t)USART_SR_IDLE)
+#define SMARTCARD_FLAG_ORE                  ((uint32_t)USART_SR_ORE)
+#define SMARTCARD_FLAG_NE                   ((uint32_t)USART_SR_NE)
+#define SMARTCARD_FLAG_FE                   ((uint32_t)USART_SR_FE)
+#define SMARTCARD_FLAG_PE                   ((uint32_t)USART_SR_PE)
 /**
   * @}
   */
 
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
   *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
+  *           - XXXX  : Interrupt mask in the Y register
   *           - Y  : Interrupt source register (2bits)
   *                 - 01: CR1 register
-  *                 - 10: CR3 register
+  *                 - 11: CR3 register
   * @{
   */
-#define SMARTCARD_IT_PE                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE                        ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR                        ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+#define SMARTCARD_IT_PE                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE                    ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC                     ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE                   ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR                    ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
 /**
   * @}
   */
@@ -334,26 +411,42 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
   * @{
   */
 
-/** @brief Reset SMARTCARD handle state
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+/** @brief Reset SMARTCARD handle gstate & RxState
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
-
-/** @brief  Flushes the Smartcard DR register 
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
+                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                           (__HANDLE__)->MspInitCallback = NULL;                  \
+                                                           (__HANDLE__)->MspDeInitCallback = NULL;                \
+                                                          } while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
+                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                          } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
+
+/** @brief  Flush the Smartcard DR register
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @retval None
   */
 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-    
-/** @brief  Checks whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __FLAG__: specifies the flag to check.
+
+/** @brief  Check whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
@@ -367,73 +460,70 @@ typedef struct
   */
 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clears the specified Smartcard pending flags.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __FLAG__: specifies the flag to check.
+/** @brief  Clear the specified Smartcard pending flags.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun 
-  *          error) flags are cleared by software sequence: a read operation to 
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
+  *          error) flags are cleared by software sequence: a read operation to
   *          USART_SR register followed by a read operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  * @note   TC flag can be also cleared by software sequence: a read operation to
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
+  * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)     \
-  do{                                                \
-    __IO uint32_t tmpreg;                            \
-    tmpreg = (__HANDLE__)->Instance->SR;             \
-    tmpreg = (__HANDLE__)->Instance->DR;             \
-    UNUSED(tmpreg);                                  \
-  } while(0)
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)  \
+    do{                                           \
+      __IO uint32_t tmpreg = 0x00U;               \
+      tmpreg = (__HANDLE__)->Instance->SR;        \
+      tmpreg = (__HANDLE__)->Instance->DR;        \
+      UNUSED(tmpreg);                             \
+    } while(0U)
 
 /** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
 
-
-/** @brief  Enables or disables the specified SmartCard interrupts.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
+/** @brief  Enable the specified SmartCard interrupt.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
@@ -441,15 +531,30 @@ typedef struct
   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
   */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                  ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+
+/** @brief  Disable the specified SmartCard interrupt.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
+  *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
+  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
+  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                  ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
 
 /** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the SmartCard Handle.
-  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  * @param  __HANDLE__ specifies the SmartCard Handle.
+  * @param  __IT__ specifies the SMARTCARD interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
   *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
@@ -459,42 +564,52 @@ typedef struct
   *            @arg SMARTCARD_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
 
 /** @brief  Macro to enable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
-  */     
+  */
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the SMARTCARD's one bit sample method
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
-  */      
+  */
 #define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __HANDLE__ specifies the SMARTCARD Handle.
   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 
-/** @brief  Macros to enable or disable the SmartCard DMA request.
-  * @param  __HANDLE__: specifies the SmartCard Handle.
-  * @param  __REQUEST__: specifies the SmartCard DMA request.
+/** @brief  Macros to enable the SmartCard DMA request.
+  * @param  __HANDLE__ specifies the SmartCard Handle.
+  * @param  __REQUEST__ specifies the SmartCard DMA request.
   *          This parameter can be one of the following values:
   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+  * @retval None
   */
 #define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
+
+/** @brief  Macros to disable the SmartCard DMA request.
+  * @param  __HANDLE__ specifies the SmartCard Handle.
+  * @param  __REQUEST__ specifies the SmartCard DMA request.
+  *          This parameter can be one of the following values:
+  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
+  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
+  * @retval None
+  */
 #define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
 
 /**
@@ -505,7 +620,7 @@ typedef struct
 /** @addtogroup SMARTCARD_Exported_Functions
   * @{
   */
-  
+
 /** @addtogroup SMARTCARD_Exported_Functions_Group1
   * @{
   */
@@ -515,6 +630,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -529,10 +649,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
+
 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
 /**
   * @}
   */
@@ -543,10 +674,9 @@ void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
 /* Peripheral State functions  **************************************************/
 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -559,17 +689,13 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
   */
 
 /** @brief SMARTCARD interruptions flag mask
-  * 
-  */ 
-#define SMARTCARD_IT_MASK   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
-                                        USART_CR1_IDLEIE | USART_CR3_EIE )
-#define SMARTCARD_DIV(_PCLK_, _BAUD_)              (((_PCLK_)*25)/(4*(_BAUD_)))
-#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_)          (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100)
-#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_)          (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define SMARTCARD_BRR(_PCLK_, _BAUD_)              ((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define SMARTCARD_CR1_REG_INDEX                 1
-#define SMARTCARD_CR3_REG_INDEX                 3
+  *
+  */
+#define SMARTCARD_IT_MASK                   ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
+                                                        USART_CR1_IDLEIE | USART_CR3_EIE )
+
+#define SMARTCARD_CR1_REG_INDEX             1U
+#define SMARTCARD_CR3_REG_INDEX             3U
 /**
   * @}
   */
@@ -578,19 +704,29 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
 /** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
   * @{
   */
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
-                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
-                                     ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
-                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
-                                       ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH)    ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS)     (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+                                             ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY)         (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+                                             ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
+#define IS_SMARTCARD_POLARITY(CPOL)         (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA)            (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT)       (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+                                             ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK)       (((NACK) == SMARTCARD_NACK_ENABLE) || \
+                                             ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE)     ((BAUDRATE) < 10500001U)
+
+#define SMARTCARD_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25U)/(4U*(__BAUD__)))
+#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__)            (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
+#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__)            (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U)
+/* SMARTCARD BRR = mantissa + overflow + fraction
+            = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
+#define SMARTCARD_BRR(__PCLK__, __BAUD__)       (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
+                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
+                                                 (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
+
 /**
   * @}
   */
@@ -606,11 +742,12 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h
index 7c8b9585..0461d114 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h
@@ -2,49 +2,31 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_SPI_H
-#define __STM32F2xx_HAL_SPI_H
+#ifndef STM32F2xx_HAL_SPI_H
+#define STM32F2xx_HAL_SPI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"  
+#include "stm32f2xx_hal_def.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
@@ -58,102 +40,140 @@
 /** @defgroup SPI_Exported_Types SPI Exported Types
   * @{
   */
-  
-/** 
-  * @brief  SPI Configuration Structure definition  
+
+/**
+  * @brief  SPI Configuration Structure definition
   */
 typedef struct
 {
-  uint32_t Mode;               /*!< Specifies the SPI operating mode.
-                                    This parameter can be a value of @ref SPI_mode */
-
-  uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
-                                    This parameter can be a value of @ref SPI_Direction_mode */
+  uint32_t Mode;                /*!< Specifies the SPI operating mode.
+                                     This parameter can be a value of @ref SPI_Mode */
 
-  uint32_t DataSize;           /*!< Specifies the SPI data size.
-                                    This parameter can be a value of @ref SPI_data_size */
+  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
+                                     This parameter can be a value of @ref SPI_Direction */
 
-  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
-                                    This parameter can be a value of @ref SPI_Clock_Polarity */
+  uint32_t DataSize;            /*!< Specifies the SPI data size.
+                                     This parameter can be a value of @ref SPI_Data_Size */
 
-  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
-                                    This parameter can be a value of @ref SPI_Clock_Phase */
+  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
+                                     This parameter can be a value of @ref SPI_Clock_Polarity */
 
-  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
-                                    hardware (NSS pin) or by software using the SSI bit.
-                                    This parameter can be a value of @ref SPI_Slave_Select_management */
+  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
+                                     This parameter can be a value of @ref SPI_Clock_Phase */
 
-  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
-                                    used to configure the transmit and receive SCK clock.
-                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                    @note The communication clock is derived from the master
-                                    clock. The slave clock does not need to be set */
+  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                     hardware (NSS pin) or by software using the SSI bit.
+                                     This parameter can be a value of @ref SPI_Slave_Select_management */
 
-  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                     used to configure the transmit and receive SCK clock.
+                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                     @note The communication clock is derived from the master
+                                     clock. The slave clock does not need to be set. */
 
-  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
-                                    This parameter can be a value of @ref SPI_TI_mode */
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
 
-  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
-                                    This parameter can be a value of @ref SPI_CRC_Calculation */
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
+                                     This parameter can be a value of @ref SPI_TI_mode */
 
-  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
-                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
+                                     This parameter can be a value of @ref SPI_CRC_Calculation */
 
-}SPI_InitTypeDef;
+  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
+                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
+} SPI_InitTypeDef;
 
 /**
   * @brief  HAL SPI State structure definition
   */
 typedef enum
 {
-  HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
-  HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
-  HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
-  HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
-    
-}HAL_SPI_StateTypeDef;
-
-/** 
+  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
+  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
+  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
+} HAL_SPI_StateTypeDef;
+
+/**
   * @brief  SPI handle Structure definition
   */
 typedef struct __SPI_HandleTypeDef
 {
-  SPI_TypeDef                *Instance;    /* SPI registers base address */
+  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
+
+  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
+
+  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
+
+  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
 
-  SPI_InitTypeDef            Init;         /* SPI communication parameters */
+  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
 
-  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
+  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
 
-  uint16_t                   TxXferSize;   /* SPI Tx transfer size */
-  
-  uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
+  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
 
-  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
+  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
 
-  uint16_t                   RxXferSize;   /* SPI Rx transfer size */
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
 
-  uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
 
-  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
+  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
 
-  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
+  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
 
-  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
+  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
 
-  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
+  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
 
-  HAL_LockTypeDef            Lock;         /* SPI locking object */
+  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
 
-  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
+  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
+  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
+  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
+  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
+  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
+  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
+  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
+  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
+  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
 
-  __IO uint32_t              ErrorCode;    /* SPI Error code */
+#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
 
-}SPI_HandleTypeDef;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  HAL SPI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
+  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
+  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
+  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
+  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
+  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
+  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
+  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
+  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
+  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SPI Callback pointer definition
+  */
+typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -164,52 +184,55 @@ typedef struct __SPI_HandleTypeDef
   */
 
 /** @defgroup SPI_Error_Code SPI Error Code
-  * @brief    SPI Error Code 
   * @{
-  */ 
-#define HAL_SPI_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error             */
-#define HAL_SPI_ERROR_MODF         ((uint32_t)0x00000001)   /*!< MODF error           */
-#define HAL_SPI_ERROR_CRC          ((uint32_t)0x00000002)   /*!< CRC error            */
-#define HAL_SPI_ERROR_OVR          ((uint32_t)0x00000004)   /*!< OVR error            */
-#define HAL_SPI_ERROR_FRE          ((uint32_t)0x00000008)   /*!< FRE error            */
-#define HAL_SPI_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error   */
-#define HAL_SPI_ERROR_FLAG         ((uint32_t)0x00000020)   /*!< Flag: RXNE,TXE, BSY  */
+  */
+#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
+#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
+#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
+#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
+#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
+#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
+#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY Flag             */
+#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @defgroup SPI_mode SPI Mode
+/** @defgroup SPI_Mode SPI Mode
   * @{
   */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_SLAVE                  (0x00000000U)
 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 /**
   * @}
   */
 
-/** @defgroup SPI_Direction_mode SPI Direction Mode
+/** @defgroup SPI_Direction SPI Direction Mode
   * @{
   */
-#define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
-#define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
+#define SPI_DIRECTION_2LINES            (0x00000000U)
+#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
 /**
   * @}
   */
 
-/** @defgroup SPI_data_size SPI Data Size
+/** @defgroup SPI_Data_Size SPI Data Size
   * @{
   */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
+#define SPI_DATASIZE_8BIT               (0x00000000U)
 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity 
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
   * @{
   */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_LOW                (0x00000000U)
 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 /**
   * @}
@@ -218,7 +241,7 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_Clock_Phase SPI Clock Phase
   * @{
   */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_1EDGE                 (0x00000000U)
 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 /**
   * @}
@@ -228,31 +251,31 @@ typedef struct __SPI_HandleTypeDef
   * @{
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
+#define SPI_NSS_HARD_INPUT              (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
   * @{
   */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
+#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transsmission 
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
   * @{
   */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_MSB                (0x00000000U)
 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 /**
   * @}
@@ -261,8 +284,8 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_TI_mode SPI TI Mode
   * @{
   */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLE              SPI_CR2_FRF
+#define SPI_TIMODE_DISABLE              (0x00000000U)
+#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
 /**
   * @}
   */
@@ -270,8 +293,8 @@ typedef struct __SPI_HandleTypeDef
 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
   * @{
   */
-#define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
+#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
+#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
 /**
   * @}
   */
@@ -286,16 +309,18 @@ typedef struct __SPI_HandleTypeDef
   * @}
   */
 
-/** @defgroup SPI_Flags_definition SPI Flags Definition 
+/** @defgroup SPI_Flags_definition SPI Flags Definition
   * @{
   */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE
-#define SPI_FLAG_TXE                    SPI_SR_TXE
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
-#define SPI_FLAG_MODF                   SPI_SR_MODF
-#define SPI_FLAG_OVR                    SPI_SR_OVR
-#define SPI_FLAG_BSY                    SPI_SR_BSY
-#define SPI_FLAG_FRE                    SPI_SR_FRE
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
+#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
+                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
 /**
   * @}
   */
@@ -304,46 +329,67 @@ typedef struct __SPI_HandleTypeDef
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup SPI_Exported_Macros SPI Exported Macros
   * @{
   */
-/** @brief Reset SPI handle state
-  * @param  __HANDLE__: specifies the SPI handle.
+
+/** @brief  Reset SPI handle state.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
+                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                                  } while(0)
+#else
 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI handle.
+/** @brief  Enable the specified SPI interrupts.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief  Disable the specified SPI interrupts.
+  * @param  __HANDLE__ specifies the SPI handle.
+  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
   *         This parameter can be one of the following values:
   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
   *            @arg SPI_IT_ERR: Error interrupt enable
   * @retval None
   */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
 
-/** @brief  Check if the specified SPI interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the SPI handle.
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
   *          This parameter can be one of the following values:
-  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *             @arg SPI_IT_ERR: Error interrupt enable
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
@@ -351,71 +397,245 @@ typedef struct __SPI_HandleTypeDef
   *            @arg SPI_FLAG_MODF: Mode fault flag
   *            @arg SPI_FLAG_OVR: Overrun flag
   *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag  
+  *            @arg SPI_FLAG_FRE: Frame format error flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
 
 /** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)            \
-  do{                                                   \
-    __IO uint32_t tmpreg;                               \
-    tmpreg = (__HANDLE__)->Instance->SR;                \
-    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);      \
-    UNUSED(tmpreg);                                     \
-  } while(0) 
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
+  do{                                                    \
+    __IO uint32_t tmpreg_modf = 0x00U;                   \
+    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
+    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+    UNUSED(tmpreg_modf);                                 \
+  } while(0U)
 
 /** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg;                       \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    UNUSED(tmpreg);                             \
-  } while(0) 
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
+  do{                                              \
+    __IO uint32_t tmpreg_ovr = 0x00U;              \
+    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
+    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
+    UNUSED(tmpreg_ovr);                            \
+  } while(0U)
 
 /** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
+  * @param  __HANDLE__ specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
-  */                                           
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)     \
-  do{                                             \
-  __IO uint32_t tmpreg;                         \
-  tmpreg = (__HANDLE__)->Instance->SR;          \
-  UNUSED(tmpreg);                               \
-  }while(0) 
-
-/** @brief Enable SPI
-  * @param __HANDLE__: specifies the SPI Handle.
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
+  do{                                              \
+    __IO uint32_t tmpreg_fre = 0x00U;              \
+    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
+    UNUSED(tmpreg_fre);                            \
+  }while(0U)
+
+/** @brief  Enable the SPI peripheral.
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
 
-/** @brief Disable SPI
-  * @param __HANDLE__: specifies the SPI Handle.
+/** @brief  Disable the SPI peripheral.
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SPI_CR1_SPE)
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
+
 /**
   * @}
   */
-  
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+  * @{
+  */
+
+/** @brief  Set the SPI transmit-only mode.
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief  Set the SPI receive-only mode.
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+
+/** @brief  Reset the CRC calculation of the SPI.
+  * @param  __HANDLE__ specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __SR__  copy of SPI SR regsiter.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
+  *            @arg SPI_FLAG_CRCERR: CRC error flag
+  *            @arg SPI_FLAG_MODF: Mode fault flag
+  *            @arg SPI_FLAG_OVR: Overrun flag
+  *            @arg SPI_FLAG_BSY: Busy flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag
+  * @retval SET or RESET.
+  */
+#define SPI_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI Interrupt is set or not.
+  * @param  __CR2__  copy of SPI CR2 regsiter.
+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval SET or RESET.
+  */
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks if SPI Mode parameter is in allowed range.
+  * @param  __MODE__ specifies the SPI Mode.
+  *         This parameter can be a value of @ref SPI_Mode
+  * @retval None
+  */
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+                               ((__MODE__) == SPI_MODE_MASTER))
+
+/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
+  * @param  __MODE__ specifies the SPI Direction Mode.
+  *         This parameter can be a value of @ref SPI_Direction
+  * @retval None
+  */
+#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
+                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+                                    ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
+  * @param  __MODE__ specifies the SPI Direction Mode.
+  * @retval None
+  */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
+
+/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
+  * @param  __MODE__ specifies the SPI Direction Mode.
+  * @retval None
+  */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
+
+/** @brief  Checks if SPI Data Size parameter is in allowed range.
+  * @param  __DATASIZE__ specifies the SPI Data Size.
+  *         This parameter can be a value of @ref SPI_Data_Size
+  * @retval None
+  */
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))
+
+/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
+  * @param  __CPOL__ specifies the SPI serial clock steady state.
+  *         This parameter can be a value of @ref SPI_Clock_Polarity
+  * @retval None
+  */
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+                               ((__CPOL__) == SPI_POLARITY_HIGH))
+
+/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
+  * @param  __CPHA__ specifies the SPI Clock Phase.
+  *         This parameter can be a value of @ref SPI_Clock_Phase
+  * @retval None
+  */
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+                               ((__CPHA__) == SPI_PHASE_2EDGE))
+
+/** @brief  Checks if SPI Slave Select parameter is in allowed range.
+  * @param  __NSS__ specifies the SPI Slave Select management parameter.
+  *         This parameter can be a value of @ref SPI_Slave_Select_management
+  * @retval None
+  */
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT)       || \
+                             ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+                             ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+
+/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
+  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
+  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+  * @retval None
+  */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
+
+/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
+  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
+  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
+  * @retval None
+  */
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+                                   ((__BIT__) == SPI_FIRSTBIT_LSB))
+
+/** @brief  Checks if SPI TI mode parameter is in allowed range.
+  * @param  __MODE__ specifies the SPI TI mode.
+  *         This parameter can be a value of @ref SPI_TI_mode
+  * @retval None
+  */
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+                                 ((__MODE__) == SPI_TIMODE_ENABLE))
+
+/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
+  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
+  *         This parameter can be a value of @ref SPI_CRC_Calculation
+  * @retval None
+  */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
+
+/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
+  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
+  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
+  * @retval None
+  */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
+
+/** @brief  Checks if DMA handle is valid.
+  * @param  __HANDLE__ specifies a DMA Handle.
+  * @retval None
+  */
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
+
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SPI_Exported_Functions
   * @{
@@ -424,11 +644,17 @@ typedef struct __SPI_HandleTypeDef
 /** @addtogroup SPI_Exported_Functions_Group1
   * @{
   */
-/* Initialization/de-initialization functions  **********************************/
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -436,140 +662,65 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 /** @addtogroup SPI_Exported_Functions_Group2
   * @{
   */
-/* I/O operation functions  *****************************************************/
+/* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+                                          uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 
 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
-  
+
 /** @addtogroup SPI_Exported_Functions_Group3
   * @{
   */
-/* Peripheral State and Control functions  **************************************/
+/* Peripheral State and Error functions ***************************************/
 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-
-/**
-  * @}
-  */ 
-
+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
-  
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
-                           ((MODE) == SPI_MODE_MASTER))
-                           
-
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
-                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                     ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
-                                                ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-  
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_8BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
-                           ((CPOL) == SPI_POLARITY_HIGH))                         
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
-                           ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
-                         ((NSS) == SPI_NSS_HARD_INPUT) || \
-                         ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
-                               ((BIT) == SPI_FIRSTBIT_LSB))
 
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
-                             ((MODE) == SPI_TIMODE_ENABLE))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
-                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-                                                                                                      
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
- 
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE) 
-
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
-                                           (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)                           
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-
 /**
   * @}
   */
 
-/**
-  * @}
-  */ 
-
 /**
   * @}
   */
 
-  
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_SPI_H */
+#endif /* STM32F2xx_HAL_SPI_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h
index 6c415907..07f75e4f 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h
@@ -2,95 +2,105 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sram.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_SRAM_H
-#define __STM32F2xx_HAL_SRAM_H
+#ifndef STM32F2xx_HAL_SRAM_H
+#define STM32F2xx_HAL_SRAM_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_ll_fsmc.h"
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
-
 /** @addtogroup SRAM
   * @{
-  */ 
+  */
 
 /* Exported typedef ----------------------------------------------------------*/
 
 /** @defgroup SRAM_Exported_Types SRAM Exported Types
   * @{
-  */ 
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
+  */
+/**
+  * @brief  HAL SRAM State structures definition
+  */
 typedef enum
 {
-  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
-  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
-  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
-  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
-  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
-  
-}HAL_SRAM_StateTypeDef;
-
-/** 
-  * @brief  SRAM handle Structure definition  
-  */ 
+  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
+  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
+  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
+  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
+  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
+
+} HAL_SRAM_StateTypeDef;
+
+/**
+  * @brief  SRAM handle Structure definition
+  */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+typedef struct __SRAM_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */	
 {
-  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */ 
-  
+  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
+
   FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
-  
+
   FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
 
-  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
-  
+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
+
   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
-  
+
   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
-  
-}SRAM_HandleTypeDef; 
 
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  void  (* MspInitCallback)        ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp Init callback              */
+  void  (* MspDeInitCallback)      ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp DeInit callback            */
+  void  (* DmaXferCpltCallback)    ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Complete callback     */
+  void  (* DmaXferErrorCallback)   ( DMA_HandleTypeDef * hdma);               /*!< SRAM DMA Xfer Error callback        */
+#endif
+} SRAM_HandleTypeDef;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL SRAM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
+  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
+  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
+  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
+}HAL_SRAM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL SRAM Callback pointer definition
+  */
+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
+typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
+#endif
 /**
   * @}
   */
@@ -99,42 +109,51 @@ typedef struct
 /* Exported macro ------------------------------------------------------------*/
 
 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
-  * @{
-  */
+ * @{
+ */
+
 /** @brief Reset SRAM handle state
-  * @param  __HANDLE__: SRAM handle
+  * @param  __HANDLE__ SRAM handle
   * @retval None
   */
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
+                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;       \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                             } while(0)
+#else
 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
+#endif
 
 /**
   * @}
   */
+
 /* Exported functions --------------------------------------------------------*/
+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
+  * @{
+  */
 
-/** @addtogroup SRAM_Exported_Functions
- *  @{
+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
  */
 
-/** @addtogroup SRAM_Exported_Functions_Group1
- *  @{
- */
-/* Initialization/de-initialization functions  **********************************/
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 
-void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup SRAM_Exported_Functions_Group2
- *  @{
+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+ * @{
  */
-/* I/O operation functions  *****************************************************/
+
+/* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
@@ -143,25 +162,40 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+
+void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/* SRAM callback registering/unregistering */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
+#endif
+
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup SRAM_Exported_Functions_Group3
- *  @{
+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
+ * @{
  */
-/* SRAM Control functions  ******************************************************/
+
+/* SRAM Control functions  ****************************************************/
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
+
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup SRAM_Exported_Functions_Group4
- *  @{
+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ * @{
  */
-/* SRAM State functions *********************************************************/
+
+/* SRAM  State functions ******************************************************/
 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+
 /**
   * @}
   */
@@ -170,22 +204,19 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
+
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_SRAM_H */
+#endif /* STM32F2xx_HAL_SRAM_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h
index 0b9e0f30..42351361 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_TIM_H
-#define __STM32F2xx_HAL_TIM_H
+#ifndef STM32F2xx_HAL_TIM_H
+#define STM32F2xx_HAL_TIM_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -58,9 +40,9 @@
 /** @defgroup TIM_Exported_Types TIM Exported Types
   * @{
   */
-  
-/** 
-  * @brief  TIM Time base Configuration Structure definition  
+
+/**
+  * @brief  TIM Time base Configuration Structure definition
   */
 typedef struct
 {
@@ -83,20 +65,22 @@ typedef struct
                                     This means in PWM mode that (N+1) corresponds to:
                                         - the number of PWM periods in edge-aligned mode
                                         - the number of half PWM period in center-aligned mode
-                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 
-                                     @note This parameter is valid only for TIM1 and TIM8. */
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */
 } TIM_Base_InitTypeDef;
 
-/** 
-  * @brief  TIM Output Compare Configuration Structure definition  
+/**
+  * @brief  TIM Output Compare Configuration Structure definition
   */
-
 typedef struct
 {
   uint32_t OCMode;        /*!< Specifies the TIM mode.
                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
 
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
 
   uint32_t OCPolarity;    /*!< Specifies the output polarity.
@@ -104,31 +88,31 @@ typedef struct
 
   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
-  
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
+                               @note This parameter is valid only for timer instances supporting break feature. */
+
+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
                                This parameter can be a value of @ref TIM_Output_Fast_State
                                @note This parameter is valid only in PWM1 and PWM2 mode. */
 
 
   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
+                               @note This parameter is valid only for timer instances supporting break feature. */
 
   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;  
+                               @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
 
-/** 
-  * @brief  TIM One Pulse Mode Configuration Structure definition  
+/**
+  * @brief  TIM One Pulse Mode Configuration Structure definition
   */
 typedef struct
 {
   uint32_t OCMode;        /*!< Specifies the TIM mode.
                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
 
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
 
   uint32_t OCPolarity;    /*!< Specifies the output polarity.
@@ -136,15 +120,15 @@ typedef struct
 
   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                               @note This parameter is valid only for TIM1 and TIM8. */
+                               @note This parameter is valid only for timer instances supporting break feature. */
 
   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
+                               @note This parameter is valid only for timer instances supporting break feature. */
 
   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
+                               @note This parameter is valid only for timer instances supporting break feature. */
 
   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -153,18 +137,16 @@ typedef struct
                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
 
   uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-} TIM_OnePulse_InitTypeDef;  
-
+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
 
-/** 
-  * @brief  TIM Input Capture Configuration Structure definition  
+/**
+  * @brief  TIM Input Capture Configuration Structure definition
   */
-
 typedef struct
 {
-  uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */
 
   uint32_t ICSelection;  /*!< Specifies the input.
                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -176,15 +158,14 @@ typedef struct
                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 } TIM_IC_InitTypeDef;
 
-/** 
-  * @brief  TIM Encoder Configuration Structure definition  
+/**
+  * @brief  TIM Encoder Configuration Structure definition
   */
-
 typedef struct
 {
   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
                                This parameter can be a value of @ref TIM_Encoder_Mode */
-                                  
+
   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
 
@@ -196,7 +177,7 @@ typedef struct
 
   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-                                  
+
   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
 
@@ -210,408 +191,564 @@ typedef struct
                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 } TIM_Encoder_InitTypeDef;
 
-/** 
-  * @brief  Clock Configuration Handle Structure definition  
-  */ 
+/**
+  * @brief  Clock Configuration Handle Structure definition
+  */
 typedef struct
 {
-  uint32_t ClockSource;     /*!< TIM clock sources. 
-                                 This parameter can be a value of @ref TIM_Clock_Source */ 
-  uint32_t ClockPolarity;   /*!< TIM clock polarity. 
+  uint32_t ClockSource;     /*!< TIM clock sources
+                                 This parameter can be a value of @ref TIM_Clock_Source */
+  uint32_t ClockPolarity;   /*!< TIM clock polarity
                                  This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler. 
+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;    /*!< TIM clock filter. 
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
+  uint32_t ClockFilter;     /*!< TIM clock filter
+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
 
-/** 
-  * @brief  Clear Input Configuration Handle Structure definition  
-  */ 
+/**
+  * @brief  TIM Clear Input Configuration Handle Structure definition
+  */
 typedef struct
-{ 
-  uint32_t ClearInputState;      /*!< TIM clear Input state. 
-                                      This parameter can be ENABLE or DISABLE */  
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources. 
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */ 
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity. 
+{
+  uint32_t ClearInputState;      /*!< TIM clear Input state
+                                      This parameter can be ENABLE or DISABLE */
+  uint32_t ClearInputSource;     /*!< TIM clear Input sources
+                                      This parameter can be a value of @ref TIM_ClearInput_Source */
+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler. 
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;    /*!< TIM Clear Input filter. 
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/** 
-  * @brief  TIM Slave configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  SlaveMode;         /*!< Slave mode selection 
-                                  This parameter can be a value of @ref TIM_Slave_Mode */ 
-  uint32_t  InputTrigger;      /*!< Input Trigger source 
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity 
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler 
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter 
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-
-}TIM_SlaveConfigTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+  * @brief  TIM Master configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */
+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+  * @brief  TIM Slave configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t  SlaveMode;         /*!< Slave mode selection
+                                    This parameter can be a value of @ref TIM_Slave_Mode */
+  uint32_t  InputTrigger;      /*!< Input Trigger source
+                                    This parameter can be a value of @ref TIM_Trigger_Selection */
+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */
+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */
+  uint32_t  TriggerFilter;     /*!< Input trigger filter
+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+  * @brief  TIM Break input(s) and Dead time configuration Structure definition
+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
+  *        filter and polarity.
+  */
+typedef struct
+{
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+  uint32_t LockLevel;            /*!< TIM Lock level
+                                      This parameter can be a value of @ref TIM_Lock_level */
+  uint32_t DeadTime;             /*!< TIM dead Time
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+  uint32_t BreakState;           /*!< TIM Break State
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.
+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
-  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/** 
-  * @brief  HAL Active channel structures definition  
-  */ 
+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
+} HAL_TIM_StateTypeDef;
+
+/**
+  * @brief  HAL Active channel structures definition
+  */
 typedef enum
 {
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00     /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/** 
-  * @brief  TIM Time Base Handle Structure definition  
-  */ 
+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+  * @brief  TIM Time Base Handle Structure definition
+  */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
 typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 {
   TIM_TypeDef                 *Instance;     /*!< Register base address             */
   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
   DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref DMA_Handle_index */
+                                                  This array is accessed by a @ref DMA_Handle_index */
   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
-}TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL TIM Callback ID enumeration definition
+  */
+typedef enum
+{
+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */
+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */
+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */
+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */
+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */
+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */
+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */
+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */
+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */
+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */
+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */
+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */
+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */
+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */
+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */
+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */
+
+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */
+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */
+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */
+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */
+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */
+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */
+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */
+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */
+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL TIM Callback pointer definition
+  */
+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
+/* End of exported types -----------------------------------------------------*/
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants  TIM Exported Constants
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
   * @{
   */
 
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
   * @{
   */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
 /**
   * @}
   */
 
-/** @defgroup TIM_ETR_Polarity  TIM ETR Polarity
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
   * @{
   */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
+#define TIM_DMABASE_CR1                    0x00000000U
+#define TIM_DMABASE_CR2                    0x00000001U
+#define TIM_DMABASE_SMCR                   0x00000002U
+#define TIM_DMABASE_DIER                   0x00000003U
+#define TIM_DMABASE_SR                     0x00000004U
+#define TIM_DMABASE_EGR                    0x00000005U
+#define TIM_DMABASE_CCMR1                  0x00000006U
+#define TIM_DMABASE_CCMR2                  0x00000007U
+#define TIM_DMABASE_CCER                   0x00000008U
+#define TIM_DMABASE_CNT                    0x00000009U
+#define TIM_DMABASE_PSC                    0x0000000AU
+#define TIM_DMABASE_ARR                    0x0000000BU
+#define TIM_DMABASE_RCR                    0x0000000CU
+#define TIM_DMABASE_CCR1                   0x0000000DU
+#define TIM_DMABASE_CCR2                   0x0000000EU
+#define TIM_DMABASE_CCR3                   0x0000000FU
+#define TIM_DMABASE_CCR4                   0x00000010U
+#define TIM_DMABASE_BDTR                   0x00000011U
+#define TIM_DMABASE_DCR                    0x00000012U
+#define TIM_DMABASE_DMAR                   0x00000013U
 /**
   * @}
   */
 
-/** @defgroup TIM_ETR_Prescaler  TIM ETR Prescaler
+/** @defgroup TIM_Event_Source TIM Event Source
   * @{
   */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
 /**
   * @}
   */
 
-/** @defgroup TIM_Counter_Mode  TIM Counter Mode
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
   * @{
   */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
 /**
   * @}
   */
 
-/** @defgroup TIM_ClockDivision TIM Clock Division
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
   * @{
   */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
-#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
 /**
   * @}
   */
 
-/** @defgroup TIM_Output_Compare_and_PWM_modes  TIM Output Compare and PWM modes
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
   * @{
   */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
-#define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
-
+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
 /**
   * @}
   */
 
-/** @defgroup TIM_Output_Fast_State  TIM Output Fast State 
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
   * @{
   */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
-#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
 /**
   * @}
   */
 
-/** @defgroup TIM_Output_Compare_Polarity  TIM Output Compare Polarity
+/** @defgroup TIM_ClockDivision TIM Clock Division
   * @{
   */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
 /**
   * @}
   */
 
-/** @defgroup TIM_Output_Compare_N_Polarity  TIM Output CompareN Polarity 
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
   * @{
   */
-#define TIM_OCNPOLARITY_HIGH               ((uint32_t)0x0000)
-#define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
 /**
   * @}
   */
 
-/** @defgroup TIM_Output_Compare_Idle_State  TIM Output Compare Idle State
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
   * @{
   */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
+
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup TIM_Output_Compare_N_Idle_State  TIM Output Compare N Idle State
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
   * @{
   */
-#define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET             ((uint32_t)0x0000)
+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup TIM_Channel  TIM Channel
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
   * @{
   */
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
-                                 
+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
 /**
   * @}
   */
 
-/** @defgroup TIM_Input_Capture_Polarity  TIM Input Capture Polarity 
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
   * @{
   */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
 /**
   * @}
   */
 
-/** @defgroup TIM_Input_Capture_Selection  TIM Input Capture Selection
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
   * @{
   */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be 
-                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
+/**
+  * @}
+  */
 
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+  * @{
+  */
+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
 /**
   * @}
   */
 
-/** @defgroup TIM_Input_Capture_Prescaler  TIM Input Capture Prescaler
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
   * @{
   */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)       /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
   * @{
   */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
 /**
   * @}
   */
 
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
   * @{
   */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+  * @}
+  */
 
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+  * @{
+  */
+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
 /**
   * @}
   */
 
-/** @defgroup TIM_Interrupt_definition  TIM Interrupt definition
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
   * @{
-  */ 
-#define TIM_IT_UPDATE           (TIM_DIER_UIE)
-#define TIM_IT_CC1              (TIM_DIER_CC1IE)
-#define TIM_IT_CC2              (TIM_DIER_CC2IE)
-#define TIM_IT_CC3              (TIM_DIER_CC3IE)
-#define TIM_IT_CC4              (TIM_DIER_CC4IE)
-#define TIM_IT_COM              (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
-#define TIM_IT_BREAK            (TIM_DIER_BIE)
+  */
+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
 /**
   * @}
   */
-  
-/** @defgroup TIM_Commutation_Source  TIM Commutation Source 
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
   * @{
-  */  
-#define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE          ((uint32_t)0x0000)
+  */
+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
 /**
   * @}
   */
 
-/** @defgroup TIM_DMA_sources  TIM DMA sources
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
   * @{
   */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_COM                        (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
 /**
   * @}
   */
 
-/** @defgroup TIM_Event_Source  TIM Event Source 
+/** @defgroup TIM_Commutation_Source  TIM Commutation Source
   * @{
   */
-#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG  
-#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG  
-#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG  
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+  * @}
+  */
 
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+  * @{
+  */
+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
 /**
   * @}
   */
 
-/** @defgroup TIM_Flag_definition  TIM Flag definition
+/** @defgroup TIM_Flag_definition TIM Flag Definition
   * @{
   */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_COM                       (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_BREAK                     (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
 /**
   * @}
   */
 
-/** @defgroup TIM_Clock_Source  TIM Clock Source
+/** @defgroup TIM_Channel TIM Channel
   * @{
   */
-#define	TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1) 
-#define	TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0) 
-#define	TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
-#define	TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define	TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define	TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define	TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
 /**
   * @}
   */
 
-/** @defgroup TIM_Clock_Polarity  TIM Clock Polarity
+/** @defgroup TIM_Clock_Source TIM Clock Source
   * @{
   */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED          /*!< Polarity for ETRx clock sources */ 
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED       /*!< Polarity for ETRx clock sources */ 
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING   /*!< Polarity for TIx clock sources */ 
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */ 
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */ 
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
 /**
   * @}
   */
 
-/** @defgroup TIM_Clock_Prescaler  TIM Clock Prescaler
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
   * @{
   */
-#define TIM_CLOCKPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
 /**
   * @}
   */
 
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
   * @{
   */
-#define TIM_CLEARINPUTSOURCE_ETR           ((uint32_t)0x0001) 
-#define TIM_CLEARINPUTSOURCE_NONE          ((uint32_t)0x0000)
+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
 /**
   * @}
   */
 
-/** @defgroup TIM_ClearInput_Polarity  TIM Clear Input Polarity
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
   * @{
   */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */ 
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */ 
+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
 /**
   * @}
   */
@@ -619,430 +756,534 @@ typedef struct
 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
   * @{
   */
-#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
 /**
   * @}
   */
 
 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
   * @{
-  */  
-#define TIM_OSSR_ENABLE 	      (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE        ((uint32_t)0x0000)
+  */
+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
 /**
   * @}
   */
-  
+
 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
   * @{
   */
-#define TIM_OSSI_ENABLE	 	    (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
 /**
   * @}
   */
-  
 /** @defgroup TIM_Lock_level  TIM Lock level
   * @{
   */
-#define TIM_LOCKLEVEL_OFF	   ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
 /**
   * @}
-  */  
-/** @defgroup TIM_Break_Input_enable_disable  TIM Break Input State
+  */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
   * @{
-  */                         
-#define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE         ((uint32_t)0x0000)
+  */
+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
 /**
   * @}
   */
-  
-/** @defgroup TIM_Break_Polarity  TIM Break Polarity 
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
   * @{
   */
-#define TIM_BREAKPOLARITY_LOW        ((uint32_t)0x0000)
-#define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
 /**
   * @}
   */
-  
-/** @defgroup TIM_AOE_Bit_Set_Reset  TIM AOE Bit State
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
   * @{
   */
-#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define	TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 
+                                                                                    (if none of the break inputs BRK and BRK2 is active) */
 /**
   * @}
-  */  
-  
+  */
+
 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
   * @{
-  */  
-#define	TIM_TRGO_RESET            ((uint32_t)0x0000)             
-#define	TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)           
-#define	TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)             
-#define	TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))    
-#define	TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)           
-#define	TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))          
-#define	TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))           
-#define	TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))     
+  */
+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
 /**
   * @}
-  */ 
-  
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
+  */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
   * @{
   */
-#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
-#define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
-#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
-#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
 /**
   * @}
   */
 
-/** @defgroup TIM_Master_Slave_Mode  TIM Master Slave Mode
+/** @defgroup TIM_Slave_Mode TIM Slave mode
   * @{
   */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
 /**
   * @}
-  */ 
-  
-/** @defgroup TIM_Trigger_Selection  TIM Trigger Selection
+  */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
   * @{
   */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
 /**
   * @}
-  */  
+  */
 
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
   * @{
   */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */ 
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */ 
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 
+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
 /**
   * @}
   */
 
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
   * @{
   */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
 /**
   * @}
   */
 
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Selection
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
   * @{
   */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
-#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup TIM_DMA_Base_address  TIM DMA Base address
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
   * @{
   */
-#define TIM_DMABASE_CR1                    (0x00000000)
-#define TIM_DMABASE_CR2                    (0x00000001)
-#define TIM_DMABASE_SMCR                   (0x00000002)
-#define TIM_DMABASE_DIER                   (0x00000003)
-#define TIM_DMABASE_SR                     (0x00000004)
-#define TIM_DMABASE_EGR                    (0x00000005)
-#define TIM_DMABASE_CCMR1                  (0x00000006)
-#define TIM_DMABASE_CCMR2                  (0x00000007)
-#define TIM_DMABASE_CCER                   (0x00000008)
-#define TIM_DMABASE_CNT                    (0x00000009)
-#define TIM_DMABASE_PSC                    (0x0000000A)
-#define TIM_DMABASE_ARR                    (0x0000000B)
-#define TIM_DMABASE_RCR                    (0x0000000C)
-#define TIM_DMABASE_CCR1                   (0x0000000D)
-#define TIM_DMABASE_CCR2                   (0x0000000E)
-#define TIM_DMABASE_CCR3                   (0x0000000F)
-#define TIM_DMABASE_CCR4                   (0x00000010)
-#define TIM_DMABASE_BDTR                   (0x00000011)
-#define TIM_DMABASE_DCR                    (0x00000012)
-#define TIM_DMABASE_OR                     (0x00000013)
+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup TIM_DMA_Burst_Length  TIM DMA Burst Length 
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
   * @{
   */
-#define TIM_DMABURSTLENGTH_1TRANSFER           (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS          (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS          (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS          (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS          (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS          (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS          (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS          (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS          (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS         (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS         (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS         (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS         (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS         (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS         (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS         (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS         (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS         (0x00001100)
+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */
+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */
+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
 /**
   * @}
   */
 
-/** @defgroup DMA_Handle_index  DMA Handle index
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
   * @{
   */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup Channel_CC_State  Channel CC State
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
   * @{
   */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE                  ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE                 ((uint32_t)0x0000)
+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */   
-  
-/* Exported macro ------------------------------------------------------------*/
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup TIM_Exported_Macros TIM Exported Macros
   * @{
   */
-/** @brief Reset TIM handle state
-  * @param  __HANDLE__: TIM handle
+
+/** @brief  Reset TIM handle state.
+  * @param  __HANDLE__ TIM handle.
   * @retval None
   */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \
+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \
+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \
+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \
+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \
+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \
+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \
+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \
+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \
+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \
+                                                     } while(0)
+#else
 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
- */
+  */
 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
 
 /**
   * @brief  Enable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
   */
 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
 
-
 /**
   * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
   */
 #define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                            } \
-                          } \
-                        } while(0)
-
-/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+      } \
+    } \
+  } while(0)
+
 /**
   * @brief  Disable the TIM main Output.
-  * @param  __HANDLE__: TIM handle
+  * @param  __HANDLE__ TIM handle
   * @retval None
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
   */
 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
-                          { \
-                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
-                            { \
-                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
-                            } \
-                          } \
-                        } while(0)
+  do { \
+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+    { \
+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+      { \
+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+      } \
+    } \
+  } while(0)
 
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+/**
+  * @brief  Disable the TIM main Output.
+  * @param  __HANDLE__ TIM handle
+  * @retval None
+  * @note The Main Output Enable of a timer instance is disabled unconditionally
+  */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
 
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+/** @brief  Enable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
 
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
+/** @brief  Disable the specified TIM interrupt.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
 
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+/** @brief  Enable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to enable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
 
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+/** @brief  Disable the specified DMA request.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __DMA__ specifies the TIM DMA request to disable.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMA_UPDATE: Update DMA request
+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
+  *            @arg TIM_DMA_COM:   Commutation DMA request
+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
 
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+/** @brief  Check whether the specified TIM interrupt flag is set or not.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
 
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+/** @brief  Clear the specified TIM interrupt flag.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.
+  *        This parameter can be one of the following values:
+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag
+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag
+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+  *            @arg TIM_FLAG_BREAK: Break interrupt flag
+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /**
-  * @brief  Sets the TIM Capture Compare Register value on runtime without
-  *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
+  * @brief  Check whether the specified TIM interrupt source is enabled or not.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
   *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
+  * @retval The state of TIM_IT (SET or RESET).
+  */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+                                                             == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+  * @param  __HANDLE__ TIM handle
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_UPDATE: Update interrupt
+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
+  *            @arg TIM_IT_COM:   Commutation interrupt
+  *            @arg TIM_IT_TRIGGER: Trigger interrupt
+  *            @arg TIM_IT_BREAK: Break interrupt
   * @retval None
   */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
 
 /**
-  * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval None
+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.
+  * @param  __HANDLE__ TIM handle.
+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
   */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
-  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
 
 /**
-  * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
+  * @brief  Set the TIM Prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __PRESC__ specifies the Prescaler new value.
   * @retval None
   */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
 
 /**
-  * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
+  * @brief  Set the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __COUNTER__ specifies the Counter register new value.
   * @retval None
   */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
 
 /**
-  * @brief  Sets the TIM Autoreload Register value on runtime without calling 
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
+  * @brief  Get the TIM Counter Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
   */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)                  \
-                        do{                                                  \
-                            (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                            (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
+
 /**
-  * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __AUTORELOAD__ specifies the Counter register new value.
   * @retval None
   */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+  do{                                                    \
+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
+  } while(0)
 
 /**
-  * @brief  Sets the TIM Clock Division value on runtime without calling 
-  *         another time any Init function. 
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
+  * @brief  Get the TIM Autoreload Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+  */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
+
+/**
+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CKD__ specifies the clock division value.
   *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
   * @retval None
   */
 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
-                        do{                                                             \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-/**
-  * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
+  do{                                                   \
+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
+  } while(0)
+
+/**
+  * @brief  Get the TIM Clock Division value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @retval The clock division can be one of the following values:
+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
   */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
 
 /**
-  * @brief  Sets the TIM Input Capture prescaler on runtime without calling 
-  *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
   *          This parameter can be one of the following values:
   *            @arg TIM_ICPSC_DIV1: no prescaler
   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
@@ -1051,90 +1292,478 @@ typedef struct
   * @retval None
   */
 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
-                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
+  do{                                                    \
+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+  } while(0)
 
 /**
-  * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
+  * @brief  Get the TIM Input Capture prescaler on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
+  * @retval The input capture prescaler can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
   */
 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-    
+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @param  __COMPARE__ specifies the Capture Compare register new value.
+  * @retval None
+  */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+  * @brief  Get the TIM Capture Compare Register value on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+  */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+   ((__HANDLE__)->Instance->CCR4))
+
+/**
+  * @brief  Set the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Reset the TIM Output compare preload.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
+
 /**
-  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is set, only counter 
+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter
   *        overflow/underflow generates an update interrupt or DMA request (if
   *        enabled)
   * @retval None
   */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
-    ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
 
 /**
-  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
-  * @param  __HANDLE__: TIM handle.
-  * @note  When the USR bit of the TIMx_CR1 register is reset, any of the 
-  *        following events generate an update interrupt or DMA request (if 
+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+  * @param  __HANDLE__ TIM handle.
+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
+  *        following events generate an update interrupt or DMA request (if
   *        enabled):
-  *          _ Counter overflow/underflow
-  *          _ Setting the UG bit
-  *          _ Update generation through the slave mode controller
+  *           _ Counter overflow underflow
+  *           _ Setting the UG bit
+  *           _ Update generation through the slave mode controller
   * @retval None
   */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
-      ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
 
 /**
-  * @brief  Sets the TIM Capture x input polarity on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__: TIM Channels to be configured.
+  * @brief  Set the TIM Capture x input polarity on runtime.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __POLARITY__: Polarity for TIx source   
+  * @param  __POLARITY__ Polarity for TIx source
   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
-  * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.     
   * @retval None
   */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)                          \
-                       do{                                                                            \
-                           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
-                           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
-                         }while(0)
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
+  do{                                                                     \
+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+  }while(0)
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+  * @{
+  */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+   channels have been disabled */
+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+  * @{
+  */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \
+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \
+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \
+                                   ((__BASE__) == TIM_DMABASE_SR)    || \
+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \
+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \
+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \
+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \
+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \
+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \
+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \
+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \
+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \
+                                   ((__BASE__) == TIM_DMABASE_BDTR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
+                                            ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                            ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \
+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
+                                            ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
+                                            ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \
+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
+                                   ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
+                                                               ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
 /**
   * @}
   */
+/* End of private macros -----------------------------------------------------*/
 
-/* Include TIM HAL Extension module */
+/* Include TIM HAL Extended module */
 #include "stm32f2xx_hal_tim_ex.h"
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
   * @{
   */
 
-/** @addtogroup TIM_Exported_Functions_Group1
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief   Time Base functions
   * @{
   */
-
 /* Time Base functions ********************************************************/
 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
@@ -1153,10 +1782,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group2
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief   TIM Output Compare functions
   * @{
   */
-/* Timer Output Compare functions **********************************************/
+/* Timer Output Compare functions *********************************************/
 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
@@ -1170,15 +1800,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group3
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief   TIM PWM functions
   * @{
   */
-/* Timer PWM functions *********************************************************/
+/* Timer PWM functions ********************************************************/
 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
@@ -1192,15 +1822,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 /* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group4
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief   TIM Input Capture functions
   * @{
   */
-/* Timer Input Capture functions ***********************************************/
+/* Timer Input Capture functions **********************************************/
 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
@@ -1214,15 +1844,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group5
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief   TIM One Pulse functions
   * @{
   */
-/* Timer One Pulse functions ***************************************************/
+/* Timer One Pulse functions **************************************************/
 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
@@ -1230,380 +1860,159 @@ void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
 /* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group6
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief   TIM Encoder functions
   * @{
   */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group7
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief   IRQ handler management
   * @{
   */
-/* Interrupt Handler functions  **********************************************/
+/* Interrupt Handler functions  ***********************************************/
 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group8
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief   Peripheral Control functions
   * @{
   */
 /* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);    
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group9
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+  *  @brief   TIM Callbacks functions
   * @{
   */
 /* Callback in non blocking modes (Interrupt and DMA) *************************/
 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
 
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @addtogroup TIM_Exported_Functions_Group10
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief  Peripheral State functions
   * @{
   */
-/* Peripheral State functions  **************************************************/
+/* Peripheral State functions  ************************************************/
 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-  
 /**
   * @}
   */
-  
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
-  * @{
-  */
-
-/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
-  * @{
-  */
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
-                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
-                               ((MODE) == TIM_OCMODE_PWM2))
-                              
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
-                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
-                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
-                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
-                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
-                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
-                                  ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
-                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
-                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCIDLESTATE_RESET))
 
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                      ((CHANNEL) == TIM_CHANNEL_2))
-                                      
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                                ((CHANNEL) == TIM_CHANNEL_2) || \
-                                                ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
-                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
-                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
-                               ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF) 
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE)  (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
-                                         ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) 
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY)   (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
-                                  ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
-                                  ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
-                                   ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
-                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
-                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
-                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
-                                    ((SOURCE) == TIM_TRGO_OC1) || \
-                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
-                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
-                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                             ((SELECTION) == TIM_TS_ITR1) || \
-                                             ((SELECTION) == TIM_TS_ITR2) || \
-                                             ((SELECTION) == TIM_TS_ITR3) || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1) || \
-                                             ((SELECTION) == TIM_TS_TI2FP2) || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                           ((SELECTION) == TIM_TS_ITR1) || \
-                                                           ((SELECTION) == TIM_TS_ITR2) || \
-                                                           ((SELECTION) == TIM_TS_ITR3) || \
-                                                           ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xF) 
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
-                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
-                               ((BASE) == TIM_DMABASE_CR2) || \
-                               ((BASE) == TIM_DMABASE_SMCR) || \
-                               ((BASE) == TIM_DMABASE_DIER) || \
-                               ((BASE) == TIM_DMABASE_SR) || \
-                               ((BASE) == TIM_DMABASE_EGR) || \
-                               ((BASE) == TIM_DMABASE_CCMR1) || \
-                               ((BASE) == TIM_DMABASE_CCMR2) || \
-                               ((BASE) == TIM_DMABASE_CCER) || \
-                               ((BASE) == TIM_DMABASE_CNT) || \
-                               ((BASE) == TIM_DMABASE_PSC) || \
-                               ((BASE) == TIM_DMABASE_ARR) || \
-                               ((BASE) == TIM_DMABASE_RCR) || \
-                               ((BASE) == TIM_DMABASE_CCR1) || \
-                               ((BASE) == TIM_DMABASE_CCR2) || \
-                               ((BASE) == TIM_DMABASE_CCR3) || \
-                               ((BASE) == TIM_DMABASE_CCR4) || \
-                               ((BASE) == TIM_DMABASE_BDTR) || \
-                               ((BASE) == TIM_DMABASE_DCR) || \
-                               ((BASE) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
-                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))                           
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Mask_Definitions TIM Mask Definition
-  * @{
-  */  
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
-   channels have been disabled */
-#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
-  * @}
-  */
-  
 /**
   * @}
   */
+/* End of exported functions -------------------------------------------------*/
 
-/* Private functions ---------------------------------------------------------*/
+/* Private functions----------------------------------------------------------*/
 /** @defgroup TIM_Private_Functions TIM Private Functions
   * @{
   */
 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
 void TIM_DMAError(DMA_HandleTypeDef *hdma);
 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);  
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
 /**
   * @}
-  */ 
-      
+  */
+/* End of private functions --------------------------------------------------*/
+
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_TIM_H */
+#endif /* STM32F2xx_HAL_TIM_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h
index 3f1a87c0..a9094f40 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   Header file of TIM HAL Extension module.
+  * @brief   Header file of TIM HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_TIM_EX_H
-#define __STM32F2xx_HAL_TIM_EX_H
+#ifndef STM32F2xx_HAL_TIM_EX_H
+#define STM32F2xx_HAL_TIM_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,256 +34,250 @@
 
 /** @addtogroup TIMEx
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup TIMEx_Exported_Types TIM Exported Types
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
   * @{
   */
-  
-/** 
-  * @brief  TIM Hall sensor Configuration Structure definition  
+
+/**
+  * @brief  TIM Hall sensor Configuration Structure definition
   */
 
 typedef struct
 {
-                                  
-  uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
-                                        This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-                                                                   
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-                                  
+
   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
-  uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
-} TIM_HallSensor_InitTypeDef;
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 
-/** 
-  * @brief  TIM Master configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection. 
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ 
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection. 
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/** 
-  * @brief  TIM Break and Dead time configuration Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t OffStateRunMode;            /*!< TIM off state in run mode.
-                                         This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;          /*!< TIM off state in IDLE mode.
-                                         This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;                     /*!< TIM Lock level.
-                                         This parameter can be a value of @ref TIM_Lock_level */                             
-  uint32_t DeadTime;                     /*!< TIM dead Time. 
-                                         This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;                   /*!< TIM Break State. 
-                                         This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;                 /*!< TIM Break input polarity. 
-                                         This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t AutomaticOutput;               /*!< TIM Automatic Output Enable state. 
-                                         This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */           
-}TIM_BreakDeadTimeConfigTypeDef;
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
 /**
   * @}
   */
-  
+/* End of exported types -----------------------------------------------------*/
+
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants  TIM Exported Constants
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
   * @{
   */
-  
-/** @defgroup TIMEx_Remap  TIM Remap
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
   * @{
   */
-#define TIM_TIM2_TIM8_TRGO                     (0x00000000)
-#define TIM_TIM2_ETH_PTP                       (0x00000400)
-#define TIM_TIM2_USBFS_SOF                     (0x00000800)
-#define TIM_TIM2_USBHS_SOF                     (0x00000C00)
-#define TIM_TIM5_GPIO                          (0x00000000)
-#define TIM_TIM5_LSI                           (0x00000040)
-#define TIM_TIM5_LSE                           (0x00000080)
-#define TIM_TIM5_RTC                           (0x000000C0)
-#define TIM_TIM11_GPIO                         (0x00000000)
-#define TIM_TIM11_HSE                          (0x00000002)
+#define TIM_TIM2_TIM8_TRGO                     0x00000000U                              /*!< TIM2 ITR1 is connected to TIM8 TRGO */
+#define TIM_TIM2_ETH_PTP                       TIM_OR_ITR1_RMP_0                        /*!< TIM2 ITR1 is connected to PTP trigger output */
+#define TIM_TIM2_USBFS_SOF                     TIM_OR_ITR1_RMP_1                        /*!< TIM2 ITR1 is connected to OTG FS SOF */
+#define TIM_TIM2_USBHS_SOF                     (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0)  /*!< TIM2 ITR1 is connected to OTG HS SOF */
+
+#define TIM_TIM5_GPIO                          0x00000000U                              /*!< TIM5 TI4 is connected to GPIO */
+#define TIM_TIM5_LSI                           TIM_OR_TI4_RMP_0                         /*!< TIM5 TI4 is connected to LSI */
+#define TIM_TIM5_LSE                           TIM_OR_TI4_RMP_1                         /*!< TIM5 TI4 is connected to LSE */
+#define TIM_TIM5_RTC                           (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)    /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
 
+#define TIM_TIM11_GPIO                         0x00000000U                              /*!< TIM11 TI1 is connected to GPIO */
+#define TIM_TIM11_HSE                          TIM_OR_TI1_RMP_1                         /*!< TIM11 TI1 is connected to HSE_RTC clock */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+/* End of exported constants -------------------------------------------------*/
+
 /* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */
+#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                       \
+        ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \
+                                    ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \
+                                    ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \
+         (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \
+                                    ((TIM_REMAP) == TIM_TIM5_LSI)            || \
+                                    ((TIM_REMAP) == TIM_TIM5_LSE)            || \
+                                    ((TIM_REMAP) == TIM_TIM5_RTC)))          || \
+         (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \
+                                    ((TIM_REMAP) == TIM_TIM11_HSE))))
+
+/**
+  * @}
+  */
+/* End of private macro ------------------------------------------------------*/
+
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
   * @{
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group1
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  *  @brief    Timer Hall Sensor functions
   * @{
   */
 /*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
 
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
 
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group2
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
   * @{
   */
 /*  Timer Complementary Output Compare functions  *****************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group3
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  *  @brief    Timer Complementary PWM functions
   * @{
   */
 /*  Timer Complementary PWM functions  ****************************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group4
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  *  @brief    Timer Complementary One Pulse functions
   * @{
   */
 /*  Timer Complementary One Pulse functions  **********************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group5
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  *  @brief    Peripheral Control functions
   * @{
   */
-/* Extension Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group6
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
   * @{
-  */ 
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
 /**
   * @}
   */
 
-/** @addtogroup TIMEx_Exported_Functions_Group7
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
   * @{
   */
-/* Extension Peripheral State functions  **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Private Macros
-  * @{
   */
-#define IS_TIM_REMAP(TIM_REMAP)   (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
-                                  ((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
-                                  ((TIM_REMAP) == TIM_TIM5_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSI)||\
-                                  ((TIM_REMAP) == TIM_TIM5_LSE)||\
-                                  ((TIM_REMAP) == TIM_TIM5_RTC)||\
-                                  ((TIM_REMAP) == TIM_TIM11_GPIO)||\
-                                  ((TIM_REMAP) == TIM_TIM11_HSE))
-
-#define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFF) 
-/**
-  * @}
-  */  
-  
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIM Private Functions
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
   * @{
   */
-  
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
+/* End of private functions --------------------------------------------------*/
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-    
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_HAL_TIM_EX_H */
+
+#endif /* STM32F2xx_HAL_TIM_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h
index e9aed656..6b723a7f 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of UART HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_UART_H
 #define __STM32F2xx_HAL_UART_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,22 +34,22 @@
 
 /** @addtogroup UART
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup UART_Exported_Types UART Exported Types
   * @{
   */
 
-/** 
-  * @brief UART Init Structure definition  
-  */ 
+/**
+  * @brief UART Init Structure definition
+  */
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
                                            The baud rate is computed using the following formula:
                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
                                            Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
 
   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
@@ -82,84 +64,179 @@ typedef struct
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
- 
+
   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref UART_Mode */
 
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled
-                                           or disabled.
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
                                            This parameter can be a value of @ref UART_Hardware_Flow_Control */
-  
+
   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */ 
-}UART_InitTypeDef;
+                                           This parameter can be a value of @ref UART_Over_Sampling */
+} UART_InitTypeDef;
 
-/** 
-  * @brief HAL UART State structures definition  
-  */ 
+/**
+  * @brief HAL UART State structures definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
 typedef enum
 {
-  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized                  */
-  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */   
-  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */ 
-  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */  
-  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */      
-}HAL_UART_StateTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition  
-  */  
-typedef struct
+  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
+                                                   Value is allowed for gState only */
+} HAL_UART_StateTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
 {
   USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-  
+
   UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-  
+
   uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-  
+
   uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-  
-  uint16_t                      TxXferCount;      /*!< UART Tx Transfer Counter           */
-  
+
+  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
+
   uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-  
+
   uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-  
-  uint16_t                      RxXferCount;      /*!< UART Rx Transfer Counter           */  
-  
+
+  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
+
   DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-    
+
   DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-  
+
   HAL_LockTypeDef               Lock;             /*!< Locking object                     */
 
-  __IO HAL_UART_StateTypeDef    State;            /*!< UART communication state           */
-  
+  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
+                                                       and also related to Tx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
   __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
 
-}UART_HandleTypeDef;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
+/** @defgroup UART_Exported_Constants UART Exported Constants
   * @{
   */
 
 /** @defgroup UART_Error_Code UART Error Code
-  * @brief    UART Error Code 
   * @{
-  */ 
-#define HAL_UART_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
-#define HAL_UART_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
-#define HAL_UART_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
-#define HAL_UART_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
-#define HAL_UART_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
+  */
+#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
+#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
+#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
+#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
+#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -167,7 +244,7 @@ typedef struct
 /** @defgroup UART_Word_Length UART Word Length
   * @{
   */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_8B                  0x00000000U
 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
@@ -176,26 +253,26 @@ typedef struct
 /** @defgroup UART_Stop_Bits UART Number of Stop Bits
   * @{
   */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
+#define UART_STOPBITS_1                     0x00000000U
 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup UART_Parity UART Parity
   * @{
-  */ 
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
+  */
+#define UART_PARITY_NONE                    0x00000000U
 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
   * @{
-  */ 
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U
 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
@@ -205,18 +282,18 @@ typedef struct
 
 /** @defgroup UART_Mode UART Transfer Mode
   * @{
-  */ 
+  */
 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
 /**
   * @}
   */
-    
- /** @defgroup UART_State UART State
+
+/** @defgroup UART_State UART State
   * @{
-  */ 
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
+  */
+#define UART_STATE_DISABLE                  0x00000000U
 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
 /**
   * @}
@@ -225,7 +302,7 @@ typedef struct
 /** @defgroup UART_Over_Sampling UART Over Sampling
   * @{
   */
-#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_16                    0x00000000U
 #define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
 /**
   * @}
@@ -233,18 +310,18 @@ typedef struct
 
 /** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
   * @{
-  */  
-#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)0x00000020)
+  */
+#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
+#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
 /**
   * @}
   */
-                                         
+
 /** @defgroup UART_WakeUp_functions  UART Wakeup Functions
   * @{
   */
-#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)0x00000800)
+#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
+#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
 /**
   * @}
   */
@@ -272,23 +349,22 @@ typedef struct
   *        Elements values convention: 0xY000XXXX
   *           - XXXX  : Interrupt mask (16 bits) in the Y register
   *           - Y  : Interrupt source register (2bits)
-  *                 - 0001: CR1 register
-  *                 - 0010: CR2 register
-  *                 - 0011: CR3 register
-  *
+  *                   - 0001: CR1 register
+  *                   - 0010: CR2 register
+  *                   - 0011: CR3 register
   * @{
-  */ 
+  */
 
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
 
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
 
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
 /**
   * @}
   */
@@ -296,30 +372,44 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup UART_Exported_Macros UART Exported Macros
   * @{
   */
 
-/** @brief Reset UART handle state
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief Reset UART handle gstate & RxState
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-
-/** @brief  Flushes the UART DR register 
-  * @param  __HANDLE__: specifies the UART Handle.
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flushes the UART DR register
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   */
 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
 
 /** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
   *            @arg UART_FLAG_LBD:  LIN Break detection flag
@@ -333,84 +423,83 @@ typedef struct
   *            @arg UART_FLAG_PE:   Parity Error flag
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-     
 /** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
   *            @arg UART_FLAG_LBD:  LIN Break detection flag.
   *            @arg UART_FLAG_TC:   Transmission Complete flag.
   *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+  *          error) and IDLE (Idle line detected) flags are cleared by software
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  * @note   TC flag can be also cleared by software sequence: a read operation to
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
+  *
   * @retval None
   */
 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief  Clears the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
   do{                                           \
-    __IO uint32_t tmpreg;                       \
+    __IO uint32_t tmpreg = 0x00U;               \
     tmpreg = (__HANDLE__)->Instance->SR;        \
     tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0)
+  } while(0U)
 
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief  Clears the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief  Clears the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief  Clears the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
+/** @brief  Clears the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
   * @retval None
   */
 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-                                                 
+
 /** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS:  CTS change interrupt
   *            @arg UART_IT_LBD:  LIN Break detection interrupt
@@ -422,15 +511,15 @@ typedef struct
   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define UART_IT_MASK  ((uint32_t)0x0000FFFF)
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+
 /** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS:  CTS change interrupt
   *            @arg UART_IT_LBD:  LIN Break detection interrupt
@@ -442,15 +531,15 @@ typedef struct
   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
   * @retval None
   */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-    
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
 /** @brief  Checks whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or 
-  *         UART peripheral.
-  * @param  __IT__: specifies the UART interrupt source to check.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __IT__ specifies the UART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
   *            @arg UART_IT_LBD: LIN Break detection interrupt
@@ -458,110 +547,114 @@ typedef struct
   *            @arg UART_IT_TC:  Transmission complete interrupt
   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
   *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
+  *            @arg UART_IT_ERR: Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
 
-/** @brief  Enable CTS flow control 
-  *         This macro allows to enable CTS hardware flow control for a given UART instance, 
+/** @brief  Enable CTS flow control
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).                                                                                                                  
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
   do{                                                      \
     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0)
+  } while(0U)
 
-/** @brief  Disable CTS flow control 
-  *         This macro allows to disable CTS hardware flow control for a given UART instance, 
+/** @brief  Disable CTS flow control
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
   do{                                                       \
     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0)
+  } while(0U)
 
-/** @brief  Enable RTS flow control 
-  *         This macro allows to enable RTS hardware flow control for a given UART instance, 
+/** @brief  Enable RTS flow control
+  *         This macro allows to enable RTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
   do{                                                     \
     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0)
+  } while(0U)
 
-/** @brief  Disable RTS flow control 
-  *         This macro allows to disable RTS hardware flow control for a given UART instance, 
+/** @brief  Disable RTS flow control
+  *         This macro allows to disable RTS hardware flow control for a given UART instance,
   *         without need to call HAL_UART_Init() function.
   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). 
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USART1, USART2 or LPUART.
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
   do{                                                      \
     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0)
+  } while(0U)
 
-/** @brief  macros to enables the UART's one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.  
+/** @brief  Macro to enable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
-  */     
+  */
 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
-/** @brief  macros to disables the UART's one bit sample method
-  * @param  __HANDLE__: specifies the UART Handle.  
+/** @brief  Macro to disable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
-  */      
+  */
 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
-  */    
+  */
 #define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART
-  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
-  */    
+  */
 #define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
 /**
   * @}
@@ -571,25 +664,34 @@ typedef struct
 /** @addtogroup UART_Exported_Functions
   * @{
   */
-  
-/** @addtogroup UART_Exported_Functions_Group1
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
-  */    
+  */
+
 /* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @addtogroup UART_Exported_Functions_Group2
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
   * @{
   */
+
 /* IO operation functions *******************************************************/
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -600,12 +702,24 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
 /**
   * @}
   */
@@ -631,11 +745,11 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
 uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -643,11 +757,13 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
   * @{
   */
 /** @brief UART interruptions flag mask
-  * 
-  */ 
-#define UART_CR1_REG_INDEX               1    
-#define UART_CR2_REG_INDEX               2    
-#define UART_CR3_REG_INDEX               3
+  *
+  */
+#define UART_IT_MASK                     0x0000FFFFU
+
+#define UART_CR1_REG_INDEX               1U
+#define UART_CR2_REG_INDEX               2U
+#define UART_CR3_REG_INDEX               3U
 /**
   * @}
   */
@@ -669,7 +785,7 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
                                ((CONTROL) == UART_HWCONTROL_RTS) || \
                                ((CONTROL) == UART_HWCONTROL_CTS) || \
                                ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
                               ((STATE) == UART_STATE_ENABLE))
 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
@@ -679,18 +795,26 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
                                                  ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
                                       ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25)/(4*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25)/(2*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
 
 /**
   * @}
@@ -711,7 +835,8 @@ uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
 
 /**
   * @}
-  */   
+  */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h
index f18e30b8..a2d21ee4 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of USART HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_USART_H
 #define __STM32F2xx_HAL_USART_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,16 +34,16 @@
 
 /** @addtogroup USART
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup USART_Exported_Types USART Exported Types
   * @{
   */
-   
-/** 
-  * @brief USART Init Structure definition  
-  */ 
+
+/**
+  * @brief USART Init Structure definition
+  */
 typedef struct
 {
   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
@@ -75,13 +57,13 @@ typedef struct
   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
                                            This parameter can be a value of @ref USART_Stop_Bits */
 
-  uint32_t Parity;                   /*!< Specifies the parity mode.
+  uint32_t Parity;                    /*!< Specifies the parity mode.
                                            This parameter can be a value of @ref USART_Parity
                                            @note When parity is enabled, the computed parity is inserted
                                                  at the MSB position of the transmitted data (9th bit when
                                                  the word length is set to 9 data bits; 8th bit when the
                                                  word length is set to 8 data bits). */
- 
+
   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
                                            This parameter can be a value of @ref USART_Mode */
 
@@ -94,55 +76,95 @@ typedef struct
   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
                                            This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
+} USART_InitTypeDef;
 
-/** 
-  * @brief HAL State structures definition  
-  */ 
+/**
+  * @brief HAL State structures definition
+  */
 typedef enum
 {
-  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized   */
-  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */   
-  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */ 
-  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_USART_STATE_ERROR             = 0x04     /*!< Error */      
-}HAL_USART_StateTypeDef;
-
-/** 
-  * @brief  USART handle Structure definition  
-  */  
-typedef struct
+  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized   */
+  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
+  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
+  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */
+  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */
+  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
+  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
+  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */
+} HAL_USART_StateTypeDef;
+
+/**
+  * @brief  USART handle Structure definition
+  */
+typedef struct __USART_HandleTypeDef
 {
-  USART_TypeDef                 *Instance;        /* USART registers base address        */
-  
-  USART_InitTypeDef             Init;             /* Usart communication parameters      */
-  
-  uint8_t                       *pTxBuffPtr;      /* Pointer to Usart Tx transfer Buffer */
-  
-  uint16_t                      TxXferSize;       /* Usart Tx Transfer size              */
-  
-  __IO uint16_t                 TxXferCount;      /* Usart Tx Transfer Counter           */
-  
-  uint8_t                       *pRxBuffPtr;      /* Pointer to Usart Rx transfer Buffer */
-  
-  uint16_t                      RxXferSize;       /* Usart Rx Transfer size              */
-  
-  __IO uint16_t                 RxXferCount;      /* Usart Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef             *hdmatx;          /* Usart Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef             *hdmarx;          /* Usart Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef                Lock;            /* Locking object                      */
-  
-  __IO HAL_USART_StateTypeDef    State;           /* Usart communication state           */
-  
-  __IO uint32_t                  ErrorCode;       /* USART Error code                    */
-
-}USART_HandleTypeDef;
+  USART_TypeDef                 *Instance;        /*!< USART registers base address        */
+
+  USART_InitTypeDef             Init;             /*!< Usart communication parameters      */
+
+  uint8_t                       *pTxBuffPtr;      /*!< Pointer to Usart Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< Usart Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< Usart Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to Usart Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< Usart Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< Usart Rx Transfer Counter           */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< Usart Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< Usart Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef                Lock;            /*!< Locking object                      */
+
+  __IO HAL_USART_StateTypeDef    State;           /*!< Usart communication state           */
+
+  __IO uint32_t                  ErrorCode;       /*!< USART Error code                    */
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */
+  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */
+  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */
+  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */
+
+  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */
+#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+} USART_HandleTypeDef;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL USART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */
+  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */
+  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */
+  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */
+  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */
+  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */
+  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */
+
+  HAL_USART_MSPINIT_CB_ID                 = 0x07U,    /*!< USART MspInit callback ID                 */
+  HAL_USART_MSPDEINIT_CB_ID               = 0x08U     /*!< USART MspDeInit callback ID               */
+
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL USART Callback pointer definition
+  */
+typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -153,15 +175,18 @@ typedef struct
   */
 
 /** @defgroup USART_Error_Code USART Error Code
-  * @brief    USART Error Code 
+  * @brief    USART Error Code
   * @{
-  */ 
-#define HAL_USART_ERROR_NONE         ((uint32_t)0x00000000)   /*!< No error            */
-#define HAL_USART_ERROR_PE           ((uint32_t)0x00000001)   /*!< Parity error        */
-#define HAL_USART_ERROR_NE           ((uint32_t)0x00000002)   /*!< Noise error         */
-#define HAL_USART_ERROR_FE           ((uint32_t)0x00000004)   /*!< Frame error         */
-#define HAL_USART_ERROR_ORE          ((uint32_t)0x00000008)   /*!< Overrun error       */
-#define HAL_USART_ERROR_DMA          ((uint32_t)0x00000010)   /*!< DMA transfer error  */
+  */
+#define HAL_USART_ERROR_NONE             0x00000000U   /*!< No error                */
+#define HAL_USART_ERROR_PE               0x00000001U   /*!< Parity error            */
+#define HAL_USART_ERROR_NE               0x00000002U   /*!< Noise error             */
+#define HAL_USART_ERROR_FE               0x00000004U   /*!< Frame error             */
+#define HAL_USART_ERROR_ORE              0x00000008U   /*!< Overrun error           */
+#define HAL_USART_ERROR_DMA              0x00000010U   /*!< DMA transfer error      */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U    /*!< Invalid Callback error */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -169,8 +194,8 @@ typedef struct
 /** @defgroup USART_Word_Length USART Word Length
   * @{
   */
-#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+#define USART_WORDLENGTH_8B          0x00000000U
+#define USART_WORDLENGTH_9B          ((uint32_t)USART_CR1_M)
 /**
   * @}
   */
@@ -178,66 +203,66 @@ typedef struct
 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
   * @{
   */
-#define USART_STOPBITS_1                     ((uint32_t)0x00000000)
-#define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define USART_STOPBITS_1             0x00000000U
+#define USART_STOPBITS_0_5           ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2             ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5           ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USART_Parity USART Parity
   * @{
-  */ 
-#define USART_PARITY_NONE                    ((uint32_t)0x00000000)
-#define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+  */
+#define USART_PARITY_NONE            0x00000000U
+#define USART_PARITY_EVEN            ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD             ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USART_Mode USART Mode
   * @{
-  */ 
-#define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+  */
+#define USART_MODE_RX                ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX                ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX             ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
 /**
   * @}
   */
-    
+
 /** @defgroup USART_Clock USART Clock
   * @{
-  */ 
-#define USART_CLOCK_DISABLE                 ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)
+  */
+#define USART_CLOCK_DISABLE          0x00000000U
+#define USART_CLOCK_ENABLE           ((uint32_t)USART_CR2_CLKEN)
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USART_Clock_Polarity USART Clock Polarity
   * @{
   */
-#define USART_POLARITY_LOW                   ((uint32_t)0x00000000)
-#define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
+#define USART_POLARITY_LOW           0x00000000U
+#define USART_POLARITY_HIGH          ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup USART_Clock_Phase  USART Clock Phase
+/** @defgroup USART_Clock_Phase USART Clock Phase
   * @{
   */
-#define USART_PHASE_1EDGE                    ((uint32_t)0x00000000)
-#define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
+#define USART_PHASE_1EDGE            0x00000000U
+#define USART_PHASE_2EDGE            ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
   */
 
-/** @defgroup USART_Last_Bit  USART Last Bit
+/** @defgroup USART_Last_Bit USART Last Bit
   * @{
   */
-#define USART_LASTBIT_DISABLE                ((uint32_t)0x00000000)
-#define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
+#define USART_LASTBIT_DISABLE        0x00000000U
+#define USART_LASTBIT_ENABLE         ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
   */
@@ -245,8 +270,8 @@ typedef struct
 /** @defgroup USART_NACK_State USART NACK State
   * @{
   */
-#define USART_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE          ((uint32_t)0x00000000)
+#define USART_NACK_ENABLE            ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE           0x00000000U
 /**
   * @}
   */
@@ -256,14 +281,14 @@ typedef struct
   *           - 0xXXXX  : Flag mask in the SR register
   * @{
   */
-#define USART_FLAG_TXE                       ((uint32_t)0x00000080)
-#define USART_FLAG_TC                        ((uint32_t)0x00000040)
-#define USART_FLAG_RXNE                      ((uint32_t)0x00000020)
-#define USART_FLAG_IDLE                      ((uint32_t)0x00000010)
-#define USART_FLAG_ORE                       ((uint32_t)0x00000008)
-#define USART_FLAG_NE                        ((uint32_t)0x00000004)
-#define USART_FLAG_FE                        ((uint32_t)0x00000002)
-#define USART_FLAG_PE                        ((uint32_t)0x00000001)
+#define USART_FLAG_TXE               ((uint32_t)USART_SR_TXE)
+#define USART_FLAG_TC                ((uint32_t)USART_SR_TC)
+#define USART_FLAG_RXNE              ((uint32_t)USART_SR_RXNE)
+#define USART_FLAG_IDLE              ((uint32_t)USART_SR_IDLE)
+#define USART_FLAG_ORE               ((uint32_t)USART_SR_ORE)
+#define USART_FLAG_NE                ((uint32_t)USART_SR_NE)
+#define USART_FLAG_FE                ((uint32_t)USART_SR_FE)
+#define USART_FLAG_PE                ((uint32_t)USART_SR_PE)
 /**
   * @}
   */
@@ -275,19 +300,14 @@ typedef struct
   *                 - 01: CR1 register
   *                 - 10: CR2 register
   *                 - 11: CR3 register
-  *
   * @{
-  */  
-#define USART_IT_PE                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define USART_IT_TXE                    ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define USART_IT_TC                     ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define USART_IT_RXNE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define USART_IT_IDLE                   ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-
-#define USART_IT_LBD                    ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-
-#define USART_IT_CTS                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define USART_IT_ERR                    ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+  */
+#define USART_IT_PE                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define USART_IT_TXE                 ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define USART_IT_TC                  ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define USART_IT_RXNE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define USART_IT_IDLE                ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define USART_IT_ERR                 ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
 /**
   * @}
   */
@@ -302,16 +322,24 @@ typedef struct
   */
 
 /** @brief Reset USART handle state
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief  Checks whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
+                                                      (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback = NULL;        \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
+                                                    } while(0U)
+#else
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+/** @brief  Check whether the specified USART flag is set or not.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg USART_FLAG_TXE:  Transmit data register empty flag
   *            @arg USART_FLAG_TC:   Transmission Complete flag
@@ -325,72 +353,72 @@ typedef struct
   */
 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clears the specified Smartcard pending flags.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
+/** @brief  Clear the specified USART pending flags.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg USART_FLAG_TC:   Transmission Complete flag.
   *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+  *          error) and IDLE (Idle line detected) flags are cleared by software
   *          sequence: a read operation to USART_SR register followed by a read
   *          operation to USART_DR register.
   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  * @note   TC flag can be also cleared by software sequence: a read operation to
   *          USART_SR register followed by a write operation to USART_DR register.
   * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
+  *
   * @retval None
   */
 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
 /** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)    \
   do{                                           \
-    __IO uint32_t tmpreg;                       \
+    __IO uint32_t tmpreg = 0x00U;               \
     tmpreg = (__HANDLE__)->Instance->SR;        \
     tmpreg = (__HANDLE__)->Instance->DR;        \
     UNUSED(tmpreg);                             \
-  } while(0)
-                                               
+  } while(0U)
+
 /** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+/** @brief  Clear the USART ORE pending flag.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
 
 /** @brief  Enables or disables the specified USART interrupts.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
-  * @param  __INTERRUPT__: specifies the USART interrupt source to check.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __INTERRUPT__ specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
   *            @arg USART_IT_TC:   Transmission complete interrupt
@@ -398,20 +426,19 @@ typedef struct
   *            @arg USART_IT_IDLE: Idle line detection interrupt
   *            @arg USART_IT_PE:   Parity Error interrupt
   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  *          This parameter can be: ENABLE or DISABLE.
   * @retval None
   */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
                                                              ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                            (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                              ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-    
+
 /** @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
-  * @param  __IT__: specifies the USART interrupt source to check.
+  * @param  __HANDLE__ specifies the USART Handle.
+  *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
+  * @param  __IT__ specifies the USART interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
   *            @arg USART_IT_TC:  Transmission complete interrupt
@@ -421,34 +448,34 @@ typedef struct
   *            @arg USART_IT_PE: Parity Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
 
 /** @brief  Macro to enable the USART's one bit sample method
-  * @param  __HANDLE__: specifies the USART Handle.  
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
-  */     
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+  */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
 
 /** @brief  Macro to disable the USART's one bit sample method
-  * @param  __HANDLE__: specifies the USART Handle.  
+  * @param  __HANDLE__ specifies the USART Handle.
   * @retval None
-  */      
+  */
 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable USART
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
   */
-#define __HAL_USART_ENABLE(__HANDLE__)               ( (__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+#define __HAL_USART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
 
 /** @brief  Disable USART
-  * @param  __HANDLE__: specifies the USART Handle.
+  * @param  __HANDLE__ specifies the USART Handle.
   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
   * @retval None
-  */ 
-#define __HAL_USART_DISABLE(__HANDLE__)              ( (__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+  */
+#define __HAL_USART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
 
 /**
   * @}
@@ -466,6 +493,13 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -486,6 +520,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
@@ -493,9 +531,10 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup USART_Exported_Functions_Group3
   * @{
@@ -505,7 +544,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
@@ -517,14 +556,14 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
   * @{
   */
 /** @brief USART interruptions flag mask
-  * 
-  */ 
+  *
+  */
 #define USART_IT_MASK  ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
                                    USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
 
-#define USART_CR1_REG_INDEX             1    
-#define USART_CR2_REG_INDEX             2    
-#define USART_CR3_REG_INDEX             3 
+#define USART_CR1_REG_INDEX          1U
+#define USART_CR2_REG_INDEX          2U
+#define USART_CR3_REG_INDEX          3U
 /**
   * @}
   */
@@ -533,30 +572,49 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 /** @defgroup USART_Private_Macros USART Private Macros
   * @{
   */
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
-                                   ((NACK) == USART_NACK_DISABLE))
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
-                                       ((LASTBIT) == USART_LASTBIT_ENABLE))
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
-                               ((CLOCK) == USART_CLOCK_ENABLE))
+#define IS_USART_NACK_STATE(NACK)    (((NACK) == USART_NACK_ENABLE) || \
+                                      ((NACK) == USART_NACK_DISABLE))
+
+#define IS_USART_LASTBIT(LASTBIT)    (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+                                      ((LASTBIT) == USART_LASTBIT_ENABLE))
+
+#define IS_USART_PHASE(CPHA)         (((CPHA) == USART_PHASE_1EDGE) || \
+                                      ((CPHA) == USART_PHASE_2EDGE))
+
+#define IS_USART_POLARITY(CPOL)      (((CPOL) == USART_POLARITY_LOW) || \
+                                      ((CPOL) == USART_POLARITY_HIGH))
+
+#define IS_USART_CLOCK(CLOCK)        (((CLOCK) == USART_CLOCK_DISABLE) || \
+                                      ((CLOCK) == USART_CLOCK_ENABLE))
+
 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
-                                          ((LENGTH) == USART_WORDLENGTH_9B))
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
-                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_2))
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
-                                     ((PARITY) == USART_PARITY_EVEN) || \
-                                     ((PARITY) == USART_PARITY_ODD))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
-
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 7500001)
-#define USART_DIV(_PCLK_, _BAUD_)                  (((_PCLK_)*25)/(2*(_BAUD_)))
-#define USART_DIVMANT(_PCLK_, _BAUD_)              (USART_DIV((_PCLK_), (_BAUD_))/100)
-#define USART_DIVFRAQ(_PCLK_, _BAUD_)              (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define USART_BRR(_PCLK_, _BAUD_)                  ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+                                      ((LENGTH) == USART_WORDLENGTH_9B))
+
+#define IS_USART_STOPBITS(STOPBITS)  (((STOPBITS) == USART_STOPBITS_1) || \
+                                      ((STOPBITS) == USART_STOPBITS_0_5) || \
+                                      ((STOPBITS) == USART_STOPBITS_1_5) || \
+                                      ((STOPBITS) == USART_STOPBITS_2))
+
+#define IS_USART_PARITY(PARITY)      (((PARITY) == USART_PARITY_NONE) || \
+                                      ((PARITY) == USART_PARITY_EVEN) || \
+                                      ((PARITY) == USART_PARITY_ODD))
+
+#define IS_USART_MODE(MODE)          ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
+
+#define IS_USART_BAUDRATE(BAUDRATE)  ((BAUDRATE) <= 7500000U)
+
+#define USART_DIV(_PCLK_, _BAUD_)      (((_PCLK_)*25U)/(2U*(_BAUD_)))
+
+#define USART_DIVMANT(_PCLK_, _BAUD_)  (USART_DIV((_PCLK_), (_BAUD_))/100U)
+
+#define USART_DIVFRAQ(_PCLK_, _BAUD_)  (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+
+  /* UART BRR = mantissa + overflow + fraction
+              = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+              
+#define USART_BRR(_PCLK_, _BAUD_)      (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+                                        ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+                                         (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U))
 /**
   * @}
   */
@@ -572,12 +630,12 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h
index 14d826b3..2ae02442 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_WWDG_H
-#define __STM32F2xx_HAL_WWDG_H
+#ifndef STM32F2xx_HAL_WWDG_H
+#define STM32F2xx_HAL_WWDG_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -52,68 +34,83 @@
 
 /** @addtogroup WWDG
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
+
 /** @defgroup WWDG_Exported_Types WWDG Exported Types
   * @{
   */
-   
+
 /**
-  * @brief  WWDG HAL State Structure definition
+  * @brief  WWDG Init structure definition
   */
-typedef enum
-{
-  HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
-  HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
-  HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */
-  HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
-  HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
-}HAL_WWDG_StateTypeDef;
-
-/** 
-  * @brief  WWDG Init structure definition  
-  */ 
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
-                            This parameter can be a value of @ref WWDG_Prescaler */
-  
-  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
-                            This parameter must be a number lower than Max_Data = 0x80 */ 
-  
-  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
-                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-}WWDG_InitTypeDef;
-
-/** 
-  * @brief  WWDG handle Structure definition  
-  */ 
+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
+                               This parameter can be a value of @ref WWDG_Prescaler */
+
+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+                               This parameter can be a value of @ref WWDG_EWI_Mode */
+
+} WWDG_InitTypeDef;
+
+/**
+  * @brief  WWDG handle Structure definition
+  */
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
 typedef struct
+#endif
 {
-  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
-  
-  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
-  
-  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
-  
-}WWDG_HandleTypeDef;
+  WWDG_TypeDef      *Instance;  /*!< Register base address */
+
+  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+  void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);     /*!< WWDG Early WakeUp Interrupt callback */
+
+  void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif
+} WWDG_HandleTypeDef;
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL WWDG common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_WWDG_EWI_CB_ID          = 0x00u,    /*!< WWDG EWI callback ID */
+  HAL_WWDG_MSPINIT_CB_ID      = 0x01u,    /*!< WWDG MspInit callback ID */
+} HAL_WWDG_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL WWDG Callback pointer definition
+  */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */
+
+#endif
 /**
   * @}
-  */ 
+  */
 
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
   * @{
   */
 
 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
   * @{
-  */ 
-#define WWDG_IT_EWI                       WWDG_CFR_EWI  /*!< Early wakeup interrupt */
+  */
+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
 /**
   * @}
   */
@@ -121,130 +118,136 @@ typedef struct
 /** @defgroup WWDG_Flag_definition WWDG Flag definition
   * @brief WWDG Flag definition
   * @{
-  */ 
-#define WWDG_FLAG_EWIF                    WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
+  */
+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
 /**
   * @}
   */
 
 /** @defgroup WWDG_Prescaler WWDG Prescaler
   * @{
-  */ 
-#define WWDG_PRESCALER_1                 ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
+  */
+#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */
 /**
   * @}
-  */ 
+  */
 
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+  * @{
+  */
+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */
+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
 /**
   * @}
-  */ 
+  */
 
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
   * @{
   */
+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \
+                                             ((__PRESCALER__) == WWDG_PRESCALER_8))
 
-/** @brief Reset WWDG handle state
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
+
+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
+                                             ((__MODE__) == WWDG_EWI_DISABLE))
+/**
+  * @}
+  */
+
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
+  * @{
   */
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
 
 /**
-  * @brief  Enables the WWDG peripheral.
-  * @param  __HANDLE__: WWDG handle
+  * @brief  Enable the WWDG peripheral.
+  * @param  __HANDLE__  WWDG handle
   * @retval None
   */
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
 
 /**
-  * @brief  Disables the WWDG peripheral.
+  * @brief  Enable the WWDG early wakeup interrupt.
   * @param  __HANDLE__: WWDG handle
-  * @note   WARNING: This is a dummy macro for HAL code alignment.
-  *         Once enable, WWDG Peripheral cannot be disabled except by a system reset.
+  * @param  __INTERRUPT__  specifies the interrupt to enable.
+  *         This parameter can be one of the following values:
+  *            @arg WWDG_IT_EWI: Early wakeup interrupt
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
   * @retval None
   */
-#define __HAL_WWDG_DISABLE(__HANDLE__)                      /* dummy  macro */
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
 
 /**
-  * @brief  Gets the selected WWDG's it status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the it to check.
+  * @brief  Check whether the selected WWDG interrupt has occurred or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the it to check.
   *        This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
   * @retval The new state of WWDG_FLAG (SET or RESET).
   */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
 
-/** @brief  Clear the WWDG's interrupt pending bits
+/** @brief  Clear the WWDG interrupt pending bits.
   *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
 
 /**
-  * @brief  Enables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-    
-/**
-  * @brief  Disables the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt to disable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   WARNING: This is a dummy macro for HAL code alignment. 
-  *         Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__)                   /* dummy  macro */
-    
-/**
-  * @brief  Gets the selected WWDG's flag status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @brief  Check whether the specified WWDG flag is set or not.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   * @retval The new state of WWDG_FLAG (SET or RESET).
   */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
 
 /**
-  * @brief  Clears the WWDG's pending flags.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @brief  Clear the WWDG's pending flags.
+  * @param  __HANDLE__  WWDG handle
+  * @param  __FLAG__  specifies the flag to clear.
   *         This parameter can be one of the following values:
   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
   * @retval None
   */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))
 
-/** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
-  * @param  __HANDLE__: WWDG Handle.
-  * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
-  *          This parameter can be one of the following values:
+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.
+  * @param  __HANDLE__  WWDG Handle.
+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.
+  *         This parameter can be one of the following values:
   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
   * @retval state of __INTERRUPT__ (TRUE or FALSE).
   */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
+
 /** @addtogroup WWDG_Exported_Functions
   * @{
   */
@@ -253,11 +256,14 @@ typedef struct
   * @{
   */
 /* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif
+
 /**
   * @}
   */
@@ -266,42 +272,9 @@ void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
   * @{
   */
 /* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup WWDG_Private_Constants WWDG Private Constants
-  * @{
-  */
-/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress
-  * @brief WWDG registers bit address in the alias region
-  * @{
-  */
-
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define WWDG_CFR_BASE   (uint32_t)(WWDG_BASE + 0x04)
-
+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
 /**
   * @}
   */
@@ -310,36 +283,14 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
-  * @{
-  */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_8))
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
 /**
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup WWDG_Private_Functions WWDG Private Functions
-  * @{
-  */
-
 /**
   * @}
   */
 
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
 #ifdef __cplusplus
 }
 #endif
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h
index 110ef48c..9873dba1 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h
@@ -2,45 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_fsmc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of FSMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_FSMC_H
-#define __STM32F2xx_LL_FSMC_H
+#ifndef STM32F2xx_LL_FSMC_H
+#define STM32F2xx_LL_FSMC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -49,26 +31,117 @@
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
-   
+
 /** @addtogroup FSMC_LL
   * @{
   */
 
-/* Private types -------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Types FSMC Private Types
+/** @addtogroup FSMC_LL_Private_Macros
   * @{
   */
 
-/** 
-  * @brief FSMC NORSRAM Configuration Structure definition
-  */ 
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+                                       ((__BANK__) == FSMC_NORSRAM_BANK4))
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+                             ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+                                   ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+                                      ((__MODE__) == FSMC_ACCESS_MODE_D))
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+                                     ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                            ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE))     
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+                                               ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+                                               ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+                                         ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+                                        ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                    ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+                                       ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+                                            ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+
+#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
+#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+                                          ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+                                             ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
+                                     ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+                                       ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
+#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
+
+#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
+
+
+/**
+  * @}
+  */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
+  * @{
+  */
+
+#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef               FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef             FSMC_Bank4_TypeDef
+
+#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
+#define FSMC_NAND_DEVICE                FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE              FSMC_Bank4
+
+/**
+  * @brief  FSMC NORSRAM Configuration Structure definition
+  */
 typedef struct
 {
   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
                                               This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */
 
   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
-                                              multiplexed on the data bus or not. 
+                                              multiplexed on the data bus or not.
                                               This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
 
   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
@@ -92,14 +165,14 @@ typedef struct
 
   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
                                               clock cycle before the wait state or during the wait state,
-                                              valid only when accessing memories in burst mode. 
+                                              valid only when accessing memories in burst mode.
                                               This parameter can be a value of @ref FSMC_Wait_Timing                      */
 
-  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC. 
+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC.
                                               This parameter can be a value of @ref FSMC_Write_Operation                  */
 
   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
-                                              signal, valid for Flash memory access in burst mode. 
+                                              signal, valid for Flash memory access in burst mode.
                                               This parameter can be a value of @ref FSMC_Wait_Signal                      */
 
   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
@@ -114,25 +187,25 @@ typedef struct
 
 }FSMC_NORSRAM_InitTypeDef;
 
-/** 
-  * @brief FSMC NORSRAM Timing parameters structure definition
+/**
+  * @brief  FSMC NORSRAM Timing parameters structure definition
   */
 typedef struct
 {
   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address setup time. 
+                                              the duration of the address setup time.
                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 
   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
                                               the duration of the address hold time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. 
+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.
                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 
   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
                                               the duration of the data setup time.
                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
-                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 
+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
                                               NOR Flash memories.                                                        */
 
   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
@@ -140,9 +213,9 @@ typedef struct
                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
 
-  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of 
+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
-                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 
+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
                                               accesses.                                                                  */
 
   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
@@ -153,30 +226,29 @@ typedef struct
                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
                                                 with synchronous burst mode enable                                       */
 
-  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. 
+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
                                               This parameter can be a value of @ref FSMC_Access_Mode                      */
-
 }FSMC_NORSRAM_TimingTypeDef;
 
-/** 
-  * @brief FSMC NAND Configuration Structure definition
-  */ 
+/**
+  * @brief  FSMC NAND Configuration Structure definition
+  */
 typedef struct
 {
   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
-                                        This parameter can be a value of @ref FSMC_NAND_Bank                   */
+                                        This parameter can be a value of @ref FSMC_NAND_Bank                    */
 
   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
-                                        This parameter can be any value of @ref FSMC_Wait_feature              */
+                                        This parameter can be any value of @ref FSMC_Wait_feature               */
 
   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
-                                        This parameter can be any value of @ref FSMC_NAND_Data_Width           */
+                                        This parameter can be any value of @ref FSMC_NAND_Data_Width            */
 
   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
-                                        This parameter can be any value of @ref FSMC_ECC                       */
+                                        This parameter can be any value of @ref FSMC_ECC                        */
 
   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
-                                        This parameter can be any value of @ref FSMC_ECC_Page_Size             */
+                                        This parameter can be any value of @ref FSMC_ECC_Page_Size              */
 
   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
                                         delay between CLE low and RE low.
@@ -185,11 +257,10 @@ typedef struct
   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
                                         delay between ALE low and RE low.
                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
+}FSMC_NAND_InitTypeDef;
 
-}FSMC_NAND_InitTypeDef;  
-
-/** 
-  * @brief FSMC NAND/PCCARD Timing parameters structure definition
+/**
+  * @brief  FSMC NAND Timing parameters structure definition
   */
 typedef struct
 {
@@ -197,36 +268,35 @@ typedef struct
                                       the command assertion for NAND-Flash read or write access
                                       to common/Attribute or I/O memory space (depending on
                                       the memory space timing to be configured).
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */
 
   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
                                       command for NAND-Flash read or write access to
                                       common/Attribute or I/O memory space (depending on the
-                                      memory space timing to be configured). 
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+                                      memory space timing to be configured).
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
 
   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
                                       (and data for write access) after the command de-assertion
                                       for NAND-Flash read or write access to common/Attribute
                                       or I/O memory space (depending on the memory space timing
                                       to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
 
   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
                                       data bus is kept in HiZ after the start of a NAND-Flash
                                       write access to common/Attribute or I/O memory space (depending
                                       on the memory space timing to be configured).
-                                      This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
-
+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */
 }FSMC_NAND_PCC_TimingTypeDef;
 
 /** 
-  * @brief  FSMC NAND Configuration Structure definition
-  */
+  * @brief FSMC PCCARD Configuration Structure definition
+  */ 
 typedef struct
 {
   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
-                                        This parameter can be any value of @ref FSMC_Wait_feature              */
+                                        This parameter can be any value of @ref FSMC_Wait_feature      */
 
   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
                                         delay between CLE low and RE low.
@@ -235,27 +305,28 @@ typedef struct
   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
                                         delay between ALE low and RE low.
                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
 }FSMC_PCCARD_InitTypeDef;
+
 /**
   * @}
   */
 
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
+/* Exported constants --------------------------------------------------------*/
+/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
   * @{
   */
 
-/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller 
+/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
   * @{
-  */ 
+  */
+
 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
   * @{
   */
-#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
-#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
-#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000U)
+#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002U)
+#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004U)
+#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006U)
 /**
   * @}
   */
@@ -263,8 +334,8 @@ typedef struct
 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
   * @{
   */
-#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)
+#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000U)
+#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002U)
 /**
   * @}
   */
@@ -272,19 +343,19 @@ typedef struct
 /** @defgroup FSMC_Memory_Type FSMC Memory Type
   * @{
   */
-#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
-#define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)
-#define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)
+#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000U)
+#define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004U)
+#define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008U)
 /**
   * @}
   */
 
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
+/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
   * @{
   */
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000U)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010U)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020U)
 /**
   * @}
   */
@@ -292,8 +363,8 @@ typedef struct
 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
   * @{
   */
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040U)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000U)
 /**
   * @}
   */
@@ -301,8 +372,8 @@ typedef struct
 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
   * @{
   */
-#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
-#define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)
+#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000U)
+#define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100U)
 /**
   * @}
   */
@@ -310,17 +381,17 @@ typedef struct
 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
   * @{
   */
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000U)
+#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200U)
 /**
   * @}
   */
 
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
+/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode 
   * @{
   */
-#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
-#define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)0x00000400)
+#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000U)
+#define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)0x00000400U)
 /**
   * @}
   */
@@ -328,8 +399,8 @@ typedef struct
 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
   * @{
   */
-#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
-#define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800)
+#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000U)
+#define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800U)
 /**
   * @}
   */
@@ -337,8 +408,8 @@ typedef struct
 /** @defgroup FSMC_Write_Operation FSMC Write Operation
   * @{
   */
-#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
-#define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)
+#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000U)
+#define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000U)
 /**
   * @}
   */
@@ -346,8 +417,8 @@ typedef struct
 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
   * @{
   */
-#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)
+#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000U)
+#define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000U)
 /**
   * @}
   */
@@ -355,8 +426,8 @@ typedef struct
 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
   * @{
   */
-#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
-#define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)
+#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000U)
+#define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000U)
 /**
   * @}
   */
@@ -364,52 +435,54 @@ typedef struct
 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
   * @{
   */
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000U)
+#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000U)
 /**
   * @}
-  */  
+  */
 
 /** @defgroup FSMC_Write_Burst FSMC Write Burst
   * @{
   */
-#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000)
+#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000U)
+#define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000U)
 /**
   * @}
   */
-  
-/** @defgroup FSMC_Continuous_Clock FSMC Continuous Clock
+
+/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
   * @{
   */
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000U)
+#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000U)
 /**
   * @}
   */
 
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
+  /** @defgroup FSMC_Access_Mode FSMC Access Mode
   * @{
   */
-#define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
-#define FSMC_ACCESS_MODE_B                        ((uint32_t)0x10000000) 
-#define FSMC_ACCESS_MODE_C                        ((uint32_t)0x20000000)
-#define FSMC_ACCESS_MODE_D                        ((uint32_t)0x30000000)
+#define FSMC_ACCESS_MODE_A                       ((uint32_t)0x00000000U)
+#define FSMC_ACCESS_MODE_B                       ((uint32_t)0x10000000U)
+#define FSMC_ACCESS_MODE_C                       ((uint32_t)0x20000000U)
+#define FSMC_ACCESS_MODE_D                       ((uint32_t)0x30000000U)
 /**
   * @}
   */
+
 /**
   * @}
   */
 
-/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
+
+/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
   * @{
   */
 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
   * @{
   */
-#define FSMC_NAND_BANK2                          ((uint32_t)0x00000010)
-#define FSMC_NAND_BANK3                          ((uint32_t)0x00000100)
+#define FSMC_NAND_BANK2                          ((uint32_t)0x00000010U)
+#define FSMC_NAND_BANK3                          ((uint32_t)0x00000100U)
 /**
   * @}
   */
@@ -417,8 +490,8 @@ typedef struct
 /** @defgroup FSMC_Wait_feature FSMC Wait feature
   * @{
   */
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE       ((uint32_t)0x00000000U)
+#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE        ((uint32_t)0x00000002U)
 /**
   * @}
   */
@@ -426,8 +499,8 @@ typedef struct
 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
   * @{
   */
-#define FSMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
-#define FSMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)0x00000008)
+#define FSMC_PCR_MEMORY_TYPE_PCCARD              ((uint32_t)0x00000000U)
+#define FSMC_PCR_MEMORY_TYPE_NAND                ((uint32_t)0x00000008U)
 /**
   * @}
   */
@@ -435,8 +508,8 @@ typedef struct
 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
   * @{
   */
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000U)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010U)
 /**
   * @}
   */
@@ -444,8 +517,8 @@ typedef struct
 /** @defgroup FSMC_ECC FSMC ECC
   * @{
   */
-#define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
-#define FSMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)
+#define FSMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000U)
+#define FSMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040U)
 /**
   * @}
   */
@@ -453,54 +526,38 @@ typedef struct
 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
   * @{
   */
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
-#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)
-#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)
-#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)
-#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)
-#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000U)
+#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000U)
 /**
   * @}
   */
-/**
-  * @}
-  */  
-   
-/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
-  * @{
-  */  
-#define FSMC_IT_RISING_EDGE                ((uint32_t)0x00000008)
-#define FSMC_IT_LEVEL                      ((uint32_t)0x00000010)
-#define FSMC_IT_FALLING_EDGE               ((uint32_t)0x00000020)
-#define FSMC_IT_REFRESH_ERROR              ((uint32_t)0x00004000)
+
 /**
   * @}
   */
-    
-/** @defgroup FSMC_LL_Flag_definition  FSMC Flag definition
+
+
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
   * @{
-  */ 
-#define FSMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)
-#define FSMC_FLAG_LEVEL                          ((uint32_t)0x00000002)
-#define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+  */
+#define FSMC_IT_RISING_EDGE                      ((uint32_t)0x00000008U)
+#define FSMC_IT_LEVEL                            ((uint32_t)0x00000010U)
+#define FSMC_IT_FALLING_EDGE                     ((uint32_t)0x00000020U)
 /**
   * @}
   */
 
-/** @defgroup FSMC_LL_Alias_definition  FSMC Alias definition
+/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
   * @{
   */
-#define FSMC_NORSRAM_TypeDef                  FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef         FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef                     FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef                   FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE                   FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE          FSMC_Bank1E
-#define FSMC_NAND_DEVICE                      FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE                    FSMC_Bank4
-
+#define FSMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001U)
+#define FSMC_FLAG_LEVEL                          ((uint32_t)0x00000002U)
+#define FSMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004U)
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040U)
 /**
   * @}
   */
@@ -509,156 +566,175 @@ typedef struct
   * @}
   */
 
+/**
+  * @}
+  */
+  
 /* Private macro -------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
+/** @defgroup FSMC_LL_Private_Macros FSMC_LL  Private Macros
+  * @{
+  */
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
+  * @brief macros to handle NOR device enable/disable and read/write operations
   * @{
   */
 
-/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
- *  @brief macros to handle NOR device enable/disable and read/write operations
- *  @{
- */
 /**
   * @brief  Enable the NORSRAM device access.
-  * @param  __INSTANCE__: FSMC_NORSRAM Instance
-  * @param  __BANK__: FSMC_NORSRAM Bank    
-  * @retval none
-  */ 
+  * @param  __INSTANCE__ FSMC_NORSRAM Instance
+  * @param  __BANK__ FSMC_NORSRAM Bank
+  * @retval None
+  */
 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
 
 /**
   * @brief  Disable the NORSRAM device access.
-  * @param  __INSTANCE__: FSMC_NORSRAM Instance
-  * @param  __BANK__: FSMC_NORSRAM Bank   
-  * @retval none
-  */ 
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)  
+  * @param  __INSTANCE__ FSMC_NORSRAM Instance
+  * @param  __BANK__ FSMC_NORSRAM Bank
+  * @retval None
+  */
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
+
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
  *  @brief macros to handle NAND device enable/disable
  *  @{
  */
+
 /**
   * @brief  Enable the NAND device access.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__: FSMC_NAND Bank    
-  * @retval none
-  */  
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @retval None
+  */
 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
-                                                    ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
+                                                             ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
 
 /**
   * @brief  Disable the NAND device access.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__: FSMC_NAND Bank  
-  * @retval none
-  */                                          
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
-                                                   ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @retval None
+  */
+#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \
+                                                             CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
+
 /**
   * @}
-  */ 
-  
-/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
-  *  @brief macros to handle SRAM read/write operations 
-  *  @{
   */
+
+/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
+ *  @brief macros to handle PCCARD read/write operations 
+ *  @{
+ */
 /**
   * @brief  Enable the PCCARD device access.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance  
-  * @retval none
+  * @param  __INSTANCE__ FSMC_PCCARD Instance  
+  * @retval None
   */ 
 #define __FSMC_PCCARD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
 
 /**
   * @brief  Disable the PCCARD device access.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance   
-  * @retval none
+  * @param  __INSTANCE__ FSMC_PCCARD Instance     
+  * @retval None
   */ 
 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
 /**
   * @}
   */
-  
-/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
- *  @brief macros to handle FSMC flags and interrupts
- * @{
- */ 
+
+/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
+  * @brief macros to handle NAND interrupts
+  * @{
+  */
+
 /**
   * @brief  Enable the NAND device interrupt.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__: FSMC_NAND Bank 
-  * @param  __INTERRUPT__: FSMC_NAND interrupt 
+  * @param  __INSTANCE__  FSMC_NAND instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __INTERRUPT__ FSMC_NAND interrupt
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
   *            @arg FSMC_IT_LEVEL: Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.        
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
   * @retval None
-  */  
+  */
 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
-                                                                                                      ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+                                                                               ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
 
 /**
   * @brief  Disable the NAND device interrupt.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__: FSMC_NAND Bank 
-  * @param  __INTERRUPT__: FSMC_NAND interrupt
+  * @param  __INSTANCE__  FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __INTERRUPT__ FSMC_NAND interrupt
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
   *            @arg FSMC_IT_LEVEL: Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.    
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
   * @retval None
   */
 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
-                                                                                                      ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 
-                                                                                                                             
+                                                                                ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) 
+
 /**
   * @brief  Get flag status of the NAND device.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__    : FSMC_NAND Bank 
-  * @param  __FLAG__    : FSMC_NAND flag
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __FLAG__     FSMC_NAND flag
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
   * @retval The state of FLAG (SET or RESET).
   */
 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
-                                                                                                (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+                                                                         (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
 /**
   * @brief  Clear flag status of the NAND device.
-  * @param  __INSTANCE__: FSMC_NAND Instance
-  * @param  __BANK__: FSMC_NAND Bank 
-  * @param  __FLAG__: FSMC_NAND flag
+  * @param  __INSTANCE__ FSMC_NAND Instance
+  * @param  __BANK__     FSMC_NAND Bank
+  * @param  __FLAG__     FSMC_NAND flag
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
   *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
   *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.
   * @retval None
   */
 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
-                                                                                                  ((__INSTANCE__)->SR3 &= ~(__FLAG__))) 
+                                                                           ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
+  * @brief macros to handle PCCARD interrupts
+  * @{
+  */
+
 /**
   * @brief  Enable the PCCARD device interrupt.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance  
-  * @param  __INTERRUPT__: FSMC_PCCARD interrupt 
+  * @param  __INSTANCE__ FSMC_PCCARD instance  
+  * @param  __INTERRUPT__ FSMC_PCCARD interrupt 
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
   *            @arg FSMC_IT_LEVEL: Interrupt level.
-  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.        
+  *            @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.       
   * @retval None
   */ 
 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the PCCARD device interrupt.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance  
-  * @param  __INTERRUPT__: FSMC_PCCARD interrupt 
+  * @param  __INSTANCE__ FSMC_PCCARD instance  
+  * @param  __INTERRUPT__ FSMC_PCCARD interrupt 
   *         This parameter can be any combination of the following values:
   *            @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
   *            @arg FSMC_IT_LEVEL: Interrupt level.
@@ -669,144 +745,41 @@ typedef struct
 
 /**
   * @brief  Get flag status of the PCCARD device.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance  
-  * @param  __FLAG__: FSMC_PCCARD flag
+  * @param  __INSTANCE__ FSMC_PCCARD instance  
+  * @param  __FLAG__ FSMC_PCCARD flag
   *         This parameter can be any combination of the following values:
-  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.   
   * @retval The state of FLAG (SET or RESET).
   */
 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
 
 /**
   * @brief  Clear flag status of the PCCARD device.
-  * @param  __INSTANCE__: FSMC_PCCARD Instance
-  * @param  __FLAG__: FSMC_PCCARD flag
+  * @param  __INSTANCE__ FSMC_PCCARD instance  
+  * @param  __FLAG__ FSMC_PCCARD flag
   *         This parameter can be any combination of the following values:
-  *            @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg FSMC_FLAG_FEMPT: FIFO empty flag.   
+  *            @arg  FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg  FSMC_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg  FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg  FSMC_FLAG_FEMPT: FIFO empty flag.   
   * @retval None
   */
 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR4 &= ~(__FLAG__))
+
 /**
   * @}
   */
 
-/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
-  * @{
-  */
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK2) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK3) || \
-                                        ((__BANK__) == FSMC_NORSRAM_BANK4))
-
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
-                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
-                                ((BANK) == FSMC_NAND_BANK3))
-
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
-                                      ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
-                                         ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
-                                 ((STATE) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
-                                   ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
-                                   ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
-                                   ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
-                                   ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
-                                   ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
-
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
-
-#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
-
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
-                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
-                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
-                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 
-
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
-                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
-                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 
-
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
-                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
-                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 
-
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-
-#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
-                                         ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-
-#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-
 /**
   * @}
   */
+
 /**
   * @}
-  */ 
+  */
 
 /* Private functions ---------------------------------------------------------*/
 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
@@ -816,8 +789,7 @@ typedef struct
 /** @defgroup FSMC_LL_NORSRAM  NOR SRAM
   *  @{
   */
-
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
   *  @{
   */
 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
@@ -826,16 +798,16 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
 HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
 /**
   * @}
-  */ 
+  */
 
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 
+/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
   *  @{
   */
 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 /**
   * @}
-  */ 
+  */
 /**
   * @}
   */
@@ -843,7 +815,7 @@ HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev
 /** @defgroup FSMC_LL_NAND NAND
   *  @{
   */
-/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
   *  @{
   */
 HAL_StatusTypeDef  FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
@@ -854,7 +826,7 @@ HAL_StatusTypeDef  FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
   * @}
   */
 
-/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions 
+/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
   *  @{
   */
 HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
@@ -862,21 +834,21 @@ HAL_StatusTypeDef  FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Ban
 HAL_StatusTypeDef  FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
 /**
   * @}
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup FSMC_LL_PCCARD PCCARD
   *  @{
   */
-/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions 
+/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
   *  @{
   */
 HAL_StatusTypeDef  FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
 HAL_StatusTypeDef  FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
 HAL_StatusTypeDef  FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); 
+HAL_StatusTypeDef  FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
 HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
 /**
   * @}
@@ -885,23 +857,23 @@ HAL_StatusTypeDef  FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
   * @}
   */
 
+
 /**
   * @}
   */
 
-
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_LL_FSMC_H */
+#endif /* STM32F2xx_LL_FSMC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
index 83df9db2..181b4b78 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
@@ -2,47 +2,31 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_SDMMC_H
-#define __STM32F2xx_LL_SDMMC_H
+#ifndef STM32F2xx_LL_SDMMC_H
+#define STM32F2xx_LL_SDMMC_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+#if defined(SDIO)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
@@ -65,56 +49,56 @@
 typedef struct
 {
   uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDIO_Clock_Edge                 */
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
 
-  uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
                                       enabled or disabled.
-                                      This parameter can be a value of @ref SDIO_Clock_Bypass               */
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
 
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
                                       disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDIO_Clock_Power_Save           */
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
 
-  uint32_t BusWide;              /*!< Specifies the SDIO bus width.
-                                      This parameter can be a value of @ref SDIO_Bus_Wide                   */
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
 
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDIO_Hardware_Flow_Control      */
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
 
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
   
 }SDIO_InitTypeDef;
   
 
 /** 
-  * @brief  SDIO Command Control structure 
+  * @brief  SDMMC Command Control structure 
   */
 typedef struct                                                                                            
 {
-  uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
                                      to a card as part of a command message. If a command
                                      contains an argument, it must be loaded into this register
                                      before writing the command to the command register.              */
 
-  uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
                                      Max_Data = 64                                                    */
 
-  uint32_t Response;            /*!< Specifies the SDIO response type.
-                                     This parameter can be a value of @ref SDIO_Response_Type         */
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
 
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is 
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
                                      enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_Wait_Interrupt_State  */
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
 
-  uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
                                      is enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_CPSM_State            */
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
 }SDIO_CmdInitTypeDef;
 
 
 /** 
-  * @brief  SDIO Data Control structure 
+  * @brief  SDMMC Data Control structure 
   */
 typedef struct
 {
@@ -123,18 +107,18 @@ typedef struct
   uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
  
   uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDIO_Data_Block_Size    */
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
  
   uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
                                      is a read or write.
-                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
  
   uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDIO_Transfer_Type      */
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
  
-  uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
                                      is enabled or disabled.
-                                     This parameter can be a value of @ref SDIO_DPSM_State         */
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
 }SDIO_DataInitTypeDef;
 
 /**
@@ -145,267 +129,458 @@ typedef struct
 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
   * @{
   */
+#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */
+#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */
+#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */
+#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */
+#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */
+#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */
+#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */
+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the
+                                                                            number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */
+#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock
+                                                                            command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */
+#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */
+#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */
+#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */
+#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */
+#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */
+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out
+                                                                            of erase sequence command was received                        */
+#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */
+#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */
+#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */
+#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */
+#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */
+#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */
+
+/** 
+  * @brief SDMMC Commands Index 
+  */
+#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */
+#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+                                                                           operating condition register (OCR) content in the response on the CMD line.                  */
+#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+                                                                           and asks the card whether card supports voltage.                                             */
+#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11U)  /*!< SD card doesn't support it.                                                              */
+#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */
+#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
+#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */
+#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands
+                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                           for SDHS and SDXC.                                                                       */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by
+                                                                           STOP_TRANSMISSION command.                                                               */
+#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
+#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
+#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command
+                                                                           system set by switch function command (CMD6).                                            */
+#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased.
+                                                                           Reserved for each command system set by switch function command (CMD6).                  */
+#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
+#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+                                                                           the SET_BLOCK_LEN command.                                                               */
+#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather
+                                                                           than a standard command.                                                                 */
+#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card
+                                                                           for general purpose/application specific commands.                                       */
+#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+                                                                            widths are given in SCR register.                                                       */
+#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+                                                                           32bit+CRC data block.                                                                    */
+#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
+#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */
+#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)
+#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)
+
+/** 
+  * @brief  Masks for errors Card Status R1 (OCR Register) 
+  */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)
+#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)
+#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)
+#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)
+#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)
+#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)
+#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)
+#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)
+#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)
+#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)
+#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)
+#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)
+#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)
+#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)
+#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)
+#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)
+#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)
+
+/** 
+  * @brief  Masks for R6 Response 
+  */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)
+#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)
+#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)
+
+#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)
+#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)
+#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)
+#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)
+#define SD_SWITCH_1_8V_CAPACITY            ((uint32_t)0x01000000U)
+
+#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)
+
+#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)
 
-/** @defgroup SDIO_Clock_Edge Clock Edge
+#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)
+#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
+#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
+
+#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
+
+#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
+#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)
+#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)
+#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)
+#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)
+
+#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)
+#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)
+
+/** 
+  * @brief  Command Class supported
+  */
+#define SDIO_CCCC_ERASE                   ((uint32_t)0x00000020U)
+
+#define SDIO_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s            */
+#define SDIO_STOPTRANSFERTIMEOUT          ((uint32_t)100000000U)   /* Timeout for STOP TRANSMISSION command */
+
+/** @defgroup SDIO_LL_Clock_Edge Clock Edge
   * @{
   */
-#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)
 #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
 
 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
+                                          ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Clock_Bypass Clock Bypass
+/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
   * @{
   */
-#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000U)
 #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
 
 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
+                                              ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
 /**
   * @}
   */ 
 
-/** @defgroup SDIO_Clock_Power_Save Clock Power Saving
+/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
   * @{
   */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)
 #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
 
 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
+                                                ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Bus_Wide Bus Width
+/** @defgroup SDIO_LL_Bus_Wide Bus Width
   * @{
   */
-#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000U)
 #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
 #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
 
 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_4B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_8B))
+                                        ((WIDE) == SDIO_BUS_WIDE_4B) || \
+                                        ((WIDE) == SDIO_BUS_WIDE_8B))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
+/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
   * @{
   */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)
 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
 
 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
+                                                        ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
 /**
   * @}
   */
   
-/** @defgroup SDIO_Clock_Division Clock Division
+/** @defgroup SDIO_LL_Clock_Division Clock Division
   * @{
   */
-#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
+#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)
 /**
   * @}
   */  
     
-/** @defgroup SDIO_Command_Index Command Index
+/** @defgroup SDIO_LL_Command_Index Command Index
   * @{
   */
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)
 /**
   * @}
   */
 
-/** @defgroup SDIO_Response_Type Response Type
+/** @defgroup SDIO_LL_Response_Type Response Type
   * @{
   */
-#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000U)
 #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
 #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
 
 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDIO_RESPONSE_LONG))
+                                            ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
+                                            ((RESPONSE) == SDIO_RESPONSE_LONG))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
+/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
   * @{
   */
-#define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
+#define SDIO_WAIT_NO                        ((uint32_t)0x00000000U)
 #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
 #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
 
 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
-                            ((WAIT) == SDIO_WAIT_IT) || \
-                            ((WAIT) == SDIO_WAIT_PEND))
+                                    ((WAIT) == SDIO_WAIT_IT) || \
+                                    ((WAIT) == SDIO_WAIT_PEND))
 /**
   * @}
   */
 
-/** @defgroup SDIO_CPSM_State CPSM State
+/** @defgroup SDIO_LL_CPSM_State CPSM State
   * @{
   */
-#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
+#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000U)
 #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
 
 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
-                            ((CPSM) == SDIO_CPSM_ENABLE))
+                                    ((CPSM) == SDIO_CPSM_ENABLE))
 /**
   * @}
   */  
 
-/** @defgroup SDIO_Response_Registers Response Register
+/** @defgroup SDIO_LL_Response_Registers Response Register
   * @{
   */
-#define SDIO_RESP1                          ((uint32_t)0x00000000)
-#define SDIO_RESP2                          ((uint32_t)0x00000004)
-#define SDIO_RESP3                          ((uint32_t)0x00000008)
-#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define SDIO_RESP1                          ((uint32_t)0x00000000U)
+#define SDIO_RESP2                          ((uint32_t)0x00000004U)
+#define SDIO_RESP3                          ((uint32_t)0x00000008U)
+#define SDIO_RESP4                          ((uint32_t)0x0000000CU)
 
 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
-                            ((RESP) == SDIO_RESP2) || \
-                            ((RESP) == SDIO_RESP3) || \
-                            ((RESP) == SDIO_RESP4))
+                                    ((RESP) == SDIO_RESP2) || \
+                                    ((RESP) == SDIO_RESP3) || \
+                                    ((RESP) == SDIO_RESP4))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Data_Length Data Lenght
+/** @defgroup SDIO_LL_Data_Length Data Lenght
   * @{
   */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
 /**
   * @}
   */
 
-/** @defgroup SDIO_Data_Block_Size Data Block Size
+/** @defgroup SDIO_LL_Data_Block_Size  Data Block Size
   * @{
   */
-#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)
 #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
 #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
+#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
 #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
-#define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
-#define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
+#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
+#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
 #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
-#define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
-#define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
-#define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
-#define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
-#define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
+#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 
+#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
+#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
 
 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
+                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
 /**
   * @}
   */
 
-/** @defgroup SDIO_Transfer_Direction Transfer Direction
+/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
   * @{
   */
-#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
+#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)
+#define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
 
 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
+                                           ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
 /**
   * @}
   */
 
-/** @defgroup SDIO_Transfer_Type Transfer Type
+/** @defgroup SDIO_LL_Transfer_Type Transfer Type
   * @{
   */
-#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)
 #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
 
 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDIO_TRANSFER_MODE_STREAM))
+                                             ((MODE) == SDIO_TRANSFER_MODE_STREAM))
 /**
   * @}
   */
 
-/** @defgroup SDIO_DPSM_State DPSM State
+/** @defgroup SDIO_LL_DPSM_State DPSM State
   * @{
   */
-#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000U)
 #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
 
 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
-                            ((DPSM) == SDIO_DPSM_ENABLE))
+                                    ((DPSM) == SDIO_DPSM_ENABLE))
 /**
   * @}
   */
   
-/** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
+/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
   * @{
   */
-#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000001)
+#define SDIO_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)
+#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
 
 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
+                                             ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
 /**
   * @}
   */  
 
-/** @defgroup SDIO_Interrupt_sources Interrupt Sources
+/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
   * @{
   */
-#define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
-#define SDIO_IT_TXACT                       SDIO_STA_TXACT
-#define SDIO_IT_RXACT                       SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
+#define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
+#define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
+#define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
+#define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
+#define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
+#define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
+#define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
+#define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
+#define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
+#define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
+#define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
+#define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
+#define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
+#define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
+#define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
+#define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
+#define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
+#define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
+#define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
+#define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
+#define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
+#define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
+#define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
+#define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
 /**
   * @}
   */ 
 
-/** @defgroup SDIO_Flags Flags
+/** @defgroup SDIO_LL_Flags Flags
   * @{
   */
 #define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
@@ -432,6 +607,16 @@ typedef struct
 #define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
 #define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
 #define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
+#define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+                                                         SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
+                                                         SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
+                                                         SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
+
+#define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
+                                                         SDIO_FLAG_CMDSENT))
+
+#define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
+                                                         SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))
 /**
   * @}
   */
@@ -439,8 +624,9 @@ typedef struct
 /**
   * @}
   */
+  
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
   * @{
   */
 
@@ -452,58 +638,57 @@ typedef struct
 
 /* --- CLKCR Register ---*/
 /* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
-#define CLKEN_BITNUMBER           0x08
-#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
+#define CLKEN_BITNUMBER           0x08U
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
 
 /* --- CMD Register ---*/
 /* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BITNUMBER     0x0B
-#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
+#define SDIOSUSPEND_BITNUMBER     0x0BU
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
 
 /* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER      0x0C
-#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
+#define ENCMDCOMPL_BITNUMBER      0x0CU
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
 
 /* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER            0x0D
-#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
+#define NIEN_BITNUMBER            0x0DU
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
 
 /* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER          0x0E
-#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
+#define ATACMD_BITNUMBER          0x0EU
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
 
 /* --- DCTRL Register ---*/
 /* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
-#define DMAEN_BITNUMBER           0x03
-#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
+#define DMAEN_BITNUMBER           0x03U
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
 
 /* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER         0x08
-#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
+#define RWSTART_BITNUMBER         0x08U
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
 
 /* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER          0x09
-#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
+#define RWSTOP_BITNUMBER          0x09U
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
 
 /* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER           0x0A
-#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
+#define RWMOD_BITNUMBER           0x0AU
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
 
 /* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER          0x0B
-#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
+#define SDIOEN_BITNUMBER          0x0BU
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
 /**
   * @}
   */
 
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
+/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
+  * @brief SDIO_LL registers bit address in the alias region
   * @{
   */
-
 /* ---------------------- SDIO registers bit mask --------------------------- */
 /* --- CLKCR Register ---*/
 /* CLKCR register clear mask */ 
@@ -511,7 +696,6 @@ typedef struct
                                              SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
                                              SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
 
-/* --- PWRCTRL Register ---*/
 /* --- DCTRL Register ---*/
 /* SDIO DCTRL Clear Mask */
 #define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
@@ -523,46 +707,47 @@ typedef struct
                                              SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
                                              SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
 
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
-
 /* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
+#define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
 
 /* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
+#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x2)
 /**
   * @}
   */
 
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
-
+/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
 /**
   * @brief  Enable the SDIO device.
+  * @param  __INSTANCE__: SDIO Instance  
   * @retval None
-  */ 
-#define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
+  */
+#define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SDIO device.
+  * @param  __INSTANCE__: SDIO Instance  
   * @retval None
   */
-#define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
+#define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
 
 /**
   * @brief  Enable the SDIO DMA transfer.
+  * @param  __INSTANCE__: SDIO Instance  
   * @retval None
-  */ 
-#define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
+  */
+#define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SDIO DMA transfer.
+  * @param  __INSTANCE__: SDIO Instance   
   * @retval None
   */
-#define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
+#define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
  
 /**
   * @brief  Enable the SDIO device interrupt.
@@ -577,9 +762,7 @@ typedef struct
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -592,8 +775,7 @@ typedef struct
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt 
   * @retval None
   */
 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
@@ -611,9 +793,7 @@ typedef struct
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -626,8 +806,7 @@ typedef struct
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt   
   * @retval None
   */
 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
@@ -645,8 +824,7 @@ typedef struct
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
@@ -659,11 +837,10 @@ typedef struct
   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
   * @retval The new state of SDIO_FLAG (SET or RESET).
   */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
 
 
 /**
@@ -679,14 +856,12 @@ typedef struct
   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)
   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received
   * @retval None
   */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
 
 /**
   * @brief  Checks whether the specified SDIO interrupt has occurred or not.
@@ -701,9 +876,7 @@ typedef struct
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
@@ -716,11 +889,10 @@ typedef struct
   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
   * @retval The new state of SDIO_IT (SET or RESET).
   */
-#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Clears the SDIO's interrupt pending bits.
@@ -735,63 +907,68 @@ typedef struct
   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt
+  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt
   * @retval None
   */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
 
 /**
   * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
   * @retval None
-  */  
-#define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
+  */
+#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
 
 /**
   * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
   * @retval None
-  */  
-#define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
+  */
+#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
 
 /**
   * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
   * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
+  */
+#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
 
 /**
   * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
   * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
+  */
+#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
 
 /**
   * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base   
   * @retval None
-  */  
-#define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
+  */
+#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
 
 /**
   * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__ : Pointer to SDIO register base 
   * @retval None
-  */  
-#define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
+  */
+#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
 
 /**
   * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
   * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
+  */
+#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
 
 /**
   * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__ : Pointer to SDIO register base  
   * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-    
+  */
+#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
+
 /**
   * @brief  Enable the command completion signal.
   * @retval None
@@ -808,13 +985,13 @@ typedef struct
   * @brief  Enable the CE-ATA interrupt.
   * @retval None
   */    
-#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
+#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
 
 /**
   * @brief  Disable the CE-ATA interrupt.
   * @retval None
   */  
-#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
+#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
 
 /**
   * @brief  Enable send CE-ATA command (CMD61).
@@ -827,7 +1004,7 @@ typedef struct
   * @retval None
   */  
 #define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-  
+   
 /**
   * @}
   */
@@ -854,7 +1031,6 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
 /** @addtogroup HAL_SDMMC_LL_Group2
   * @{
   */
-/* Blocking mode: Polling */
 uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
 /**
@@ -870,17 +1046,44 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
 uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
 
 /* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
 uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
+uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
 
 /* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
 uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
 uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
 
-/* SDIO IO Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
+
+/* SDMMC Commands management functions */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
 
 /**
   * @}
@@ -898,10 +1101,12 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
   * @}
   */
 
+#endif /* SDIO */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32F2xx_LL_SDMMC_H */
+#endif /* STM32F2xx_LL_SDMMC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h
index e081a907..5083796d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h
@@ -2,460 +2,510 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_usb.h
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   Header file of USB Core HAL module.
+  * @brief   Header file of USB Low Layer HAL module.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_USB_H
-#define __STM32F2xx_LL_USB_H
+#ifndef STM32F2xx_LL_USB_H
+#define STM32F2xx_LL_USB_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal_def.h"
 
-/** @addtogroup STM32F2xx_HAL
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
-/** @addtogroup USB_Core
+/** @addtogroup USB_LL
   * @{
-  */ 
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  USB Mode definition
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 
-/* Exported types ------------------------------------------------------------*/ 
+typedef enum
+{
+  USB_DEVICE_MODE  = 0,
+  USB_HOST_MODE    = 1,
+  USB_DRD_MODE     = 2
+} USB_OTG_ModeTypeDef;
 
-/** 
-  * @brief  USB Mode definition  
-  */  
-typedef enum 
+/**
+  * @brief  URB States definition
+  */
+typedef enum
 {
-   USB_OTG_DEVICE_MODE  = 0,
-   USB_OTG_HOST_MODE    = 1,
-   USB_OTG_DRD_MODE     = 2
-   
-}USB_OTG_ModeTypeDef;
-
-/** 
-  * @brief  URB States definition  
-  */ 
-typedef enum {
   URB_IDLE = 0,
   URB_DONE,
   URB_NOTREADY,
   URB_NYET,
   URB_ERROR,
   URB_STALL
-    
-}USB_OTG_URBStateTypeDef;
+} USB_OTG_URBStateTypeDef;
 
-/** 
-  * @brief  Host channel States  definition  
-  */ 
-typedef enum {
+/**
+  * @brief  Host channel States  definition
+  */
+typedef enum
+{
   HC_IDLE = 0,
   HC_XFRC,
   HC_HALTED,
   HC_NAK,
   HC_NYET,
   HC_STALL,
-  HC_XACTERR,  
-  HC_BBLERR,   
+  HC_XACTERR,
+  HC_BBLERR,
   HC_DATATGLERR
-    
-}USB_OTG_HCStateTypeDef;
+} USB_OTG_HCStateTypeDef;
 
-/** 
-  * @brief  PCD Initialization Structure definition  
+/**
+  * @brief  USB OTG Initialization Structure definition
   */
 typedef struct
 {
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
-  
-  uint32_t Host_channels;        /*!< Host Channels number.
-                                      This parameter Depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
-
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed_                */        
-                               
-  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
-
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
-                       
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
-                                
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
-                               
-  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
-                          
-  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
-
-  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
-  
-  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
-  
-}USB_OTG_CfgTypeDef;
+  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+                                         This parameter depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t Host_channels;           /*!< Host Channels number.
+                                         This parameter Depends on the used USB core.
+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+  uint32_t speed;                   /*!< USB Core speed.
+                                         This parameter can be any value of @ref USB_Core_Speed_                */
+
+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
+
+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+
+  uint32_t phy_itface;              /*!< Select the used PHY interface.
+                                         This parameter can be any value of @ref USB_Core_PHY_                  */
+
+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+
+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
+
+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+
+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+
+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+
+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+} USB_OTG_CfgTypeDef;
 
 typedef struct
 {
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
-                                
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
-                                
-  uint8_t   data_pid_start; /*!< Initial data PID
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
-                                
-  uint8_t   even_odd_frame; /*!< IFrame parity
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
-                                
-  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
-                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
-                                
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-                                
-  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
-  
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-  
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-}USB_OTG_EPTypeDef;
+  uint8_t   num;                  /*!< Endpoint number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint8_t   is_in;                /*!< Endpoint direction
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   is_stall;             /*!< Endpoint stall condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   type;                 /*!< Endpoint type
+                                       This parameter can be any value of @ref USB_EP_Type_                     */
+
+  uint8_t   data_pid_start;       /*!< Initial data PID
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint8_t   even_odd_frame;       /*!< IFrame parity
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+} USB_OTG_EPTypeDef;
 
 typedef struct
 {
-  uint8_t   dev_addr ;     /*!< USB device address.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
-
-  uint8_t   ch_num;        /*!< Host channel number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
-                                
-  uint8_t   ep_num;        /*!< Endpoint number.
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
-                                
-  uint8_t   ep_is_in;      /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
-                                
-  uint8_t   speed;         /*!< USB Host speed.
-                                This parameter can be any value of @ref USB_Core_Speed_                    */
-                                
-  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
-  
-  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
-
-  uint8_t   ep_type;       /*!< Endpoint Type.
-                                This parameter can be any value of @ref USB_EP_Type_                       */
-                                
-  uint16_t  max_packet;    /*!< Endpoint Max packet size.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
-                                
-  uint8_t   data_pid;      /*!< Initial data PID.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-                                
-  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
-  
-  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
-  
-  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
-  
-  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-                                
-  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
-  
-  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
-  
-  uint32_t  ErrCnt;        /*!< Host channel error count.*/
-  
-  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
-                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
-  
-  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
-                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
-                                             
-}USB_OTG_HCTypeDef;
-  
+  uint8_t   dev_addr ;          /*!< USB device address.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */
+
+  uint8_t   ch_num;             /*!< Host channel number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_num;             /*!< Endpoint number.
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */
+
+  uint8_t   ep_is_in;           /*!< Endpoint direction
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   speed;              /*!< USB Host speed.
+                                     This parameter can be any value of @ref USB_Core_Speed_                    */
+
+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+
+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;            /*!< Endpoint Type.
+                                     This parameter can be any value of @ref USB_EP_Type_                       */
+
+  uint16_t  max_packet;         /*!< Endpoint Max packet size.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+
+  uint8_t   data_pid;           /*!< Initial data PID.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
+
+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
+
+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */
+
+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+
+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
+
+  uint32_t  ErrCnt;             /*!< Host channel error count.*/
+
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.
+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */
+} USB_OTG_HCTypeDef;
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup PCD_Exported_Constants PCD Exported Constants
   * @{
   */
 
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/** @defgroup USB_OTG_CORE VERSION ID
+  * @{
+  */
+#define USB_OTG_CORE_ID_300A          0x4F54300AU
+#define USB_OTG_CORE_ID_310A          0x4F54310AU
+/**
+  * @}
+  */
+
 /** @defgroup USB_Core_Mode_ USB Core Mode
   * @{
   */
-#define USB_OTG_MODE_DEVICE                    0
-#define USB_OTG_MODE_HOST                      1
-#define USB_OTG_MODE_DRD                       2
+#define USB_OTG_MODE_DEVICE                    0U
+#define USB_OTG_MODE_HOST                      1U
+#define USB_OTG_MODE_DRD                       2U
 /**
   * @}
   */
 
-/** @defgroup USB_Core_Speed_   USB Core Speed
+/** @defgroup USB_LL Device Speed
   * @{
-  */  
-#define USB_OTG_SPEED_HIGH                     0
-#define USB_OTG_SPEED_HIGH_IN_FULL             1
-#define USB_OTG_SPEED_LOW                      2  
-#define USB_OTG_SPEED_FULL                     3
+  */
+#define USBD_HS_SPEED               0U
+#define USBD_HSINFS_SPEED           1U
+#define USBH_HS_SPEED               0U
+#define USBD_FS_SPEED               2U
+#define USBH_FS_SPEED               1U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
+  * @{
+  */
+#define USB_OTG_SPEED_HIGH                     0U
+#define USB_OTG_SPEED_HIGH_IN_FULL             1U
+#define USB_OTG_SPEED_FULL                     3U
 /**
   * @}
   */
-  
-/** @defgroup USB_Core_PHY_   USB Core PHY
+
+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
   * @{
-  */   
-#define USB_OTG_ULPI_PHY                       1
-#define USB_OTG_EMBEDDED_PHY                   2
+  */
+#define USB_OTG_ULPI_PHY                       1U
+#define USB_OTG_EMBEDDED_PHY                   2U
 /**
   * @}
   */
-  
-/** @defgroup USB_Core_MPS_   USB Core MPS
+
+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
   * @{
   */
-#define USB_OTG_HS_MAX_PACKET_SIZE           512
-#define USB_OTG_FS_MAX_PACKET_SIZE           64
-#define USB_OTG_MAX_EP0_SIZE                 64
+#ifndef USBD_HS_TRDT_VALUE
+#define USBD_HS_TRDT_VALUE           9U
+#endif /* USBD_HS_TRDT_VALUE */
+#ifndef USBD_FS_TRDT_VALUE
+#define USBD_FS_TRDT_VALUE           5U
+#define USBD_DEFAULT_TRDT_VALUE      9U
+#endif /* USBD_HS_TRDT_VALUE */
 /**
   * @}
   */
 
-/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
   * @{
   */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
+#define USB_OTG_HS_MAX_PACKET_SIZE             512U
+#define USB_OTG_FS_MAX_PACKET_SIZE             64U
+#define USB_OTG_MAX_EP0_SIZE                   64U
 /**
   * @}
   */
-  
-/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
+
+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
   * @{
-  */  
-#define DCFG_FRAME_INTERVAL_80                 0
-#define DCFG_FRAME_INTERVAL_85                 1
-#define DCFG_FRAME_INTERVAL_90                 2
-#define DCFG_FRAME_INTERVAL_95                 3
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2U << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
 /**
   * @}
   */
 
-/** @defgroup USB_EP0_MPS_  USB EP0 MPS
+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
   * @{
   */
-#define DEP0CTL_MPS_64                         0
-#define DEP0CTL_MPS_32                         1
-#define DEP0CTL_MPS_16                         2
-#define DEP0CTL_MPS_8                          3
+#define DCFG_FRAME_INTERVAL_80                 0U
+#define DCFG_FRAME_INTERVAL_85                 1U
+#define DCFG_FRAME_INTERVAL_90                 2U
+#define DCFG_FRAME_INTERVAL_95                 3U
 /**
   * @}
   */
 
-/** @defgroup USB_EP_Speed_  USB EP Speed
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
   * @{
   */
-#define EP_SPEED_LOW                           0
-#define EP_SPEED_FULL                          1
-#define EP_SPEED_HIGH                          2
+#define DEP0CTL_MPS_64                         0U
+#define DEP0CTL_MPS_32                         1U
+#define DEP0CTL_MPS_16                         2U
+#define DEP0CTL_MPS_8                          3U
 /**
   * @}
   */
 
-/** @defgroup USB_EP_Type_  USB EP Type
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
   * @{
   */
-#define EP_TYPE_CTRL                           0
-#define EP_TYPE_ISOC                           1
-#define EP_TYPE_BULK                           2
-#define EP_TYPE_INTR                           3
-#define EP_TYPE_MSK                            3
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
 /**
   * @}
   */
 
-/** @defgroup USB_STS_Defines_   USB STS Defines
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
   * @{
   */
-#define STS_GOUT_NAK                           1
-#define STS_DATA_UPDT                          2
-#define STS_XFER_COMP                          3
-#define STS_SETUP_COMP                         4
-#define STS_SETUP_UPDT                         6
+#define EP_TYPE_CTRL                           0U
+#define EP_TYPE_ISOC                           1U
+#define EP_TYPE_BULK                           2U
+#define EP_TYPE_INTR                           3U
+#define EP_TYPE_MSK                            3U
 /**
   * @}
   */
 
-/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
   * @{
-  */  
-#define HCFG_30_60_MHZ                         0
-#define HCFG_48_MHZ                            1
-#define HCFG_6_MHZ                             2
+  */
+#define STS_GOUT_NAK                           1U
+#define STS_DATA_UPDT                          2U
+#define STS_XFER_COMP                          3U
+#define STS_SETUP_COMP                         4U
+#define STS_SETUP_UPDT                         6U
 /**
   * @}
   */
-    
-/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
+
+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
   * @{
-  */    
-#define HPRT0_PRTSPD_HIGH_SPEED                0
-#define HPRT0_PRTSPD_FULL_SPEED                1
-#define HPRT0_PRTSPD_LOW_SPEED                 2
+  */
+#define HCFG_30_60_MHZ                         0U
+#define HCFG_48_MHZ                            1U
+#define HCFG_6_MHZ                             2U
 /**
   * @}
-  */  
-   
-#define HCCHAR_CTRL                            0
-#define HCCHAR_ISOC                            1
-#define HCCHAR_BULK                            2
-#define HCCHAR_INTR                            3
-       
-#define HC_PID_DATA0                           0
-#define HC_PID_DATA2                           1
-#define HC_PID_DATA1                           2
-#define HC_PID_SETUP                           3
-
-#define GRXSTS_PKTSTS_IN                       2
-#define GRXSTS_PKTSTS_IN_XFER_COMP             3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
-#define GRXSTS_PKTSTS_CH_HALTED                7
-    
-#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
-#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+  */
+
+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
+  * @{
+  */
+#define HPRT0_PRTSPD_HIGH_SPEED                0U
+#define HPRT0_PRTSPD_FULL_SPEED                1U
+#define HPRT0_PRTSPD_LOW_SPEED                 2U
 /**
   * @}
   */
+
+#define HCCHAR_CTRL                            0U
+#define HCCHAR_ISOC                            1U
+#define HCCHAR_BULK                            2U
+#define HCCHAR_INTR                            3U
+
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+
+#define GRXSTS_PKTSTS_IN                       2U
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
+#define GRXSTS_PKTSTS_CH_HALTED                7U
+
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+#define EP_ADDR_MSK                            0xFU
+/**
+  * @}
+  */
+
 /* Exported macro ------------------------------------------------------------*/
+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
 #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-    
+
 #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+  * @{
+  */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
 uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
 uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
-                                  uint8_t ch_num,
-                                  uint8_t epnum,
-                                  uint8_t dev_address,
-                                  uint8_t speed,
-                                  uint8_t ep_type,
-                                  uint16_t mps);
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+                              uint8_t ch_num,
+                              uint8_t epnum,
+                              uint8_t dev_address,
+                              uint8_t speed,
+                              uint8_t ep_type,
+                              uint16_t mps);
 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
 #ifdef __cplusplus
 }
 #endif
 
 
-#endif /* __STM32F2xx_LL_USB_H */
+#endif /* STM32F2xx_LL_USB_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c
index 9dd53252..dd6e4d1c 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -15,7 +13,7 @@
     The common HAL driver contains a set of generic and common APIs that can be
     used by the PPP peripheral drivers and the user to start using the HAL. 
     [..]
-    The HAL contains two APIs categories: 
+    The HAL contains two APIs' categories: 
          (+) Common HAL APIs
          (+) Services HAL APIs
 
@@ -23,32 +21,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -68,18 +50,18 @@
   * @{
   */
 /**
-  * @brief STM32F2xx HAL Driver version number V1.1.0
-  */
-#define __STM32F2xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F2xx_HAL_VERSION_SUB1   (0x01) /*!< [23:16] sub1 version */
-#define __STM32F2xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F2xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F2xx_HAL_VERSION         ((__STM32F2xx_HAL_VERSION_MAIN << 24)\
-                                        |(__STM32F2xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32F2xx_HAL_VERSION_SUB2 << 8 )\
+  * @brief STM32F2xx HAL Driver version number V1.2.3
+  */
+#define __STM32F2xx_HAL_VERSION_MAIN   0x01U /*!< [31:24] main version */
+#define __STM32F2xx_HAL_VERSION_SUB1   0x02U /*!< [23:16] sub1 version */
+#define __STM32F2xx_HAL_VERSION_SUB2   0x03U /*!< [15:8]  sub2 version */
+#define __STM32F2xx_HAL_VERSION_RC     0x00U /*!< [7:0]  release candidate */ 
+#define __STM32F2xx_HAL_VERSION         ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
+                                        |(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
+                                        |(__STM32F2xx_HAL_VERSION_SUB2 << 8U) \
                                         |(__STM32F2xx_HAL_VERSION_RC))
                                         
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define IDCODE_DEVID_MASK    0x00000FFFU
 
 /* ------------ RCC registers bit address in the alias region ----------- */
 #define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
@@ -87,23 +69,25 @@
 /* Alias word address of UFB_MODE bit */ 
 #define MEMRMP_OFFSET             SYSCFG_OFFSET 
 #define UFB_MODE_BIT_NUMBER       POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
-#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BIT_NUMBER * 4)) 
+#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
 
 /* ---  CMPCR Register ---*/ 
 /* Alias word address of CMP_PD bit */ 
-#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
 #define CMP_PD_BIT_NUMBER         POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
-#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BIT_NUMBER * 4))
+#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
 /**
   * @}
   */
 
 /* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Private_Variables
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
   * @{
   */
-static __IO uint32_t uwTick;
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
 /**
   * @}
   */
@@ -167,15 +151,15 @@ static __IO uint32_t uwTick;
 HAL_StatusTypeDef HAL_Init(void)
 {
   /* Configure Flash prefetch, Instruction cache, Data cache */ 
-#if (INSTRUCTION_CACHE_ENABLE != 0)
+#if (INSTRUCTION_CACHE_ENABLE != 0U)
    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 #endif /* INSTRUCTION_CACHE_ENABLE */
 
-#if (DATA_CACHE_ENABLE != 0)
+#if (DATA_CACHE_ENABLE != 0U)
    __HAL_FLASH_DATA_CACHE_ENABLE();
 #endif /* DATA_CACHE_ENABLE */
 
-#if (PREFETCH_ENABLE != 0)
+#if (PREFETCH_ENABLE != 0U)
   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 #endif /* PREFETCH_ENABLE */
 
@@ -257,16 +241,27 @@ __weak void HAL_MspDeInit(void)
   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *       The function is declared as __weak  to be overwritten  in case of other
   *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
+  * @param  TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
-  /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
 
-  /*Configure the SysTick IRQ priority */
-  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
 
   /* Return function status */
   return HAL_OK;
@@ -310,7 +305,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
   */
 __weak void HAL_IncTick(void)
 {
-  uwTick++;
+  uwTick += uwTickFreq;
 }
 
 /**
@@ -325,21 +320,68 @@ __weak uint32_t HAL_GetTick(void)
 }
 
 /**
-  * @brief This function provides accurate delay (in milliseconds) based 
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+    if (status == HAL_OK)
+    {
+      uwTickFreq = Freq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based 
   *        on variable incremented.
   * @note In the default implementation , SysTick timer is the source of time base.
   *       It is used to generate interrupts at regular time intervals where uwTick
   *       is incremented.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
+  * @param  Delay specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(__IO uint32_t Delay)
 {
-  uint32_t tickstart = 0;
-  tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
   {
   }
 }
@@ -391,7 +433,7 @@ uint32_t HAL_GetHalVersion(void)
   */
 uint32_t HAL_GetREVID(void)
 {
-   return((DBGMCU->IDCODE) >> 16);
+   return((DBGMCU->IDCODE) >> 16U);
 }
 
 /**
@@ -479,6 +521,33 @@ void HAL_DisableCompensationCell(void)
   *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
 }
 
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c
index 53561b5a..bff4369d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
   *           + Initialization and de-initialization functions
@@ -159,37 +157,93 @@
   (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA using function HAL_DMA_DeInit().
         (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   
+                      *** Callback registration ***
+  ==============================================================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+     or @ref HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
 
     @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -251,7 +305,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
   *         External trigger source and edge, DMA continuous request after the  
   *         last transfer and End of conversion selection).
   *             
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval HAL status
   */
@@ -285,14 +339,30 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   
   if(hadc->State == HAL_ADC_STATE_RESET)
   {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
     /* Initialize ADC error code */
     ADC_CLEAR_ERRORCODE(hadc);
     
     /* Allocate lock resource and initialize it */
     hadc->Lock = HAL_UNLOCKED;
-    
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
   }
   
   /* Configuration of ADC parameters if previous preliminary actions are      */ 
@@ -329,7 +399,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Deinitializes the ADCx peripheral registers to their default reset values. 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval HAL status
   */
@@ -357,8 +427,18 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   /* correctly completed.                                                     */
   if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
   {
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  if (hadc->MspDeInitCallback == NULL)
+  {
+    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: RCC clock, NVIC */
+  hadc->MspDeInitCallback(hadc);
+#else
+  /* DeInit the low level hardware: RCC clock, NVIC */
+  HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
     
     /* Set ADC error code to none */
     ADC_CLEAR_ERRORCODE(hadc);
@@ -374,14 +454,218 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   return tmp_hal_status;
 }
 
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
 /**
   * @brief  Initializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspInit could be implemented in the user file
    */ 
@@ -389,12 +673,14 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_MspDeInit could be implemented in the user file
    */ 
@@ -426,13 +712,13 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables ADC and starts conversion of the regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0;
+  __IO uint32_t counter = 0U;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -451,8 +737,8 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -494,7 +780,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
     
     /* Check if Multimode enabled */
     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@@ -526,7 +812,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   * 
   * @note   Caution: This function will stop also injected channels.  
   *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   *
   * @retval HAL status.
@@ -569,14 +855,14 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
   *         In this case, DMA resets the flag EOC and polling cannot be
   *         performed on each conversion. Nevertheless, polling can still 
   *         be performed on the complete sequence.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.  
+  * @param  Timeout Timeout value in millisecond.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
  
   /* Verification that ADC configuration is compliant with polling for      */
   /* each conversion:                                                       */
@@ -605,7 +891,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
     /* Check if timeout is disabled (set to infinite wait) */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update ADC state machine to timeout */
         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -650,18 +936,18 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
 
 /**
   * @brief  Poll for conversion event
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  EventType: the ADC event type.
+  * @param  EventType the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
   *            @arg ADC_OVR_EVENT: ADC Overrun event.
-  * @param  Timeout: Timeout value in millisecond.   
+  * @param  Timeout Timeout value in millisecond.   
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
   
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -676,7 +962,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update ADC state machine to timeout */
         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -717,13 +1003,13 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
 
 /**
   * @brief  Enables the interrupt and starts ADC conversion of regular channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0;
+  __IO uint32_t counter = 0U;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -742,8 +1028,8 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -785,7 +1071,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
     
     /* Enable end of conversion interrupt for regular group */
     __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
@@ -820,7 +1106,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   * 
   * @note   Caution: This function will stop also injected channels.  
   *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status.
   */
@@ -857,13 +1143,13 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Handles ADC interrupt request  
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 {
-  uint32_t tmp1 = 0, tmp2 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -908,8 +1194,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
       }
     }
     
-    /* Conversion complete callback */ 
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
     HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
     
     /* Clear regular group conversion flag */
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
@@ -951,7 +1241,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
     }
 
     /* Conversion complete callback */ 
-    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->InjectedConvCpltCallback(hadc);
+#else
+      HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
     
     /* Clear injected group conversion flag */
     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
@@ -967,8 +1261,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
       /* Set ADC state */
       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
       
-      /* Level out of window callback */ 
+      /* Level out of window callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->LevelOutOfWindowCallback(hadc);
+#else
       HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
       
       /* Clear the ADC analog watchdog flag */
       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
@@ -991,7 +1289,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
     
     /* Error callback */ 
-    HAL_ADC_ErrorCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
     
     /* Clear the Overrun flag */
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
@@ -1000,15 +1302,15 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
 {
-  __IO uint32_t counter = 0;
+  __IO uint32_t counter = 0U;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -1027,8 +1329,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -1083,7 +1385,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
     
     /* Clear regular group conversion flag and overrun flag */
     /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
 
     /* Enable ADC overrun interrupt */
     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
@@ -1121,7 +1423,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
 
 /**
   * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
@@ -1167,7 +1469,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Gets the converted value from data register of regular channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval Converted value
   */
@@ -1179,12 +1481,14 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Regular conversion complete callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvCpltCallback could be implemented in the user file
    */
@@ -1192,12 +1496,14 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Regular conversion half DMA transfer callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
    */
@@ -1205,12 +1511,14 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Analog watchdog callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
    */
@@ -1218,12 +1526,20 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Error ADC callback.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @note   In case of error due to overrun when using ADC with DMA transfer 
+  *         (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_ErrorCallback could be implemented in the user file
    */
@@ -1253,14 +1569,14 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
   /**
   * @brief  Configures for the selected ADC regular channel its corresponding
   *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  sConfig: ADC configuration structure. 
+  * @param  sConfig ADC configuration structure. 
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
 {
-  __IO uint32_t counter = 0;
+  __IO uint32_t counter = 0U;
   
   /* Check the parameters */
   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
@@ -1289,7 +1605,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
   }
   
   /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7)
+  if (sConfig->Rank < 7U)
   {
     /* Clear the old SQx bits for the selected rank */
     hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
@@ -1298,7 +1614,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
     hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
   }
   /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13)
+  else if (sConfig->Rank < 13U)
   {
     /* Clear the old SQx bits for the selected rank */
     hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
@@ -1333,8 +1649,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
     {
       /* Delay for temperature sensor stabilization time */
       /* Compute number of CPU cycles to wait for */
-      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
-      while(counter != 0)
+      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+      while(counter != 0U)
       {
         counter--;
       }
@@ -1350,16 +1666,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
 
 /**
   * @brief  Configures the analog watchdog.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @note Analog watchdog thresholds can be modified while ADC conversion
+  * is on going.
+  * In this case, some constraints must be taken into account:
+  * The programmed threshold values are effective from the next
+  * ADC EOC (end of unitary conversion).
+  * Considering that registers write delay may happen due to
+  * bus activity, this might cause an uncertainty on the
+  * effective timing of the new programmed threshold values.
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure 
+  * @param  AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure 
   *         that contains the configuration information of ADC analog watchdog.
   * @retval HAL status	  
   */
 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
 {
 #ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0;
+  uint32_t tmp = 0U;
 #endif /* USE_FULL_ASSERT  */  
   
   /* Check the parameters */
@@ -1434,7 +1758,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   
 /**
   * @brief  return the ADC state
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL state
   */
@@ -1446,7 +1770,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Return the ADC error code
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval ADC Error Code
   */
@@ -1466,7 +1790,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
 /**
   * @brief  Initializes the ADCx peripheral according to the specified parameters 
   *         in the ADC_InitStruct without initializing the ADC MSP.       
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.  
   * @retval None
   */
@@ -1547,7 +1871,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1589,31 +1913,52 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
     }
     
     /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
     HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
   }
-  else
+  else /* DMA and-or internal error occurred */
   {
-    /* Call DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback(hdma);
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+	else
+	{
+      /* Call DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
   }
 }
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
 {
   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* Conversion complete callback */
-  HAL_ADC_ConvHalfCpltCallback(hadc); 
+  
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 }
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1623,7 +1968,12 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
   hadc->State= HAL_ADC_STATE_ERROR_DMA;
   /* Set ADC error code to DMA error */
   hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-  HAL_ADC_ErrorCallback(hadc); 
+   /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c
index c6325e84..30cc2f64 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the ADC extension peripheral:
   *           + Extended features functions
@@ -86,32 +84,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -170,14 +152,14 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma);
 
 /**
   * @brief  Enables the selected ADC software start conversion of the injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0;
-  uint32_t tmp1 = 0, tmp2 = 0;
+  __IO uint32_t counter = 0U;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Process locked */
   __HAL_LOCK(hadc);
@@ -193,8 +175,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -258,15 +240,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Enables the interrupt and starts ADC conversion of injected channels.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   *
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
 {
-  __IO uint32_t counter = 0;
-  uint32_t tmp1 = 0, tmp2 = 0;
+  __IO uint32_t counter = 0U;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Process locked */
   __HAL_LOCK(hadc);
@@ -282,8 +264,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     
     /* Delay for ADC stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -319,7 +301,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
     
     /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
     
     /* Check if Multimode enabled */
     if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@@ -357,7 +339,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
   * @note   If injected group mode auto-injection is enabled,
   *         function HAL_ADC_Stop must be used.
   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -409,14 +391,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Poll for injected conversion complete
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  Timeout: Timeout value in millisecond.  
+  * @param  Timeout Timeout value in millisecond.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   /* Get tick */ 
   tickstart = HAL_GetTick();
@@ -427,7 +409,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         hadc->State= HAL_ADC_STATE_TIMEOUT;
         /* Process unlocked */
@@ -478,7 +460,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
   *         injected and regular groups, and disable the ADC.
   * @note   If injected group mode auto-injection is enabled,
   *         function HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -508,7 +490,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
     if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
     {
       /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
+      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
       
       /* Set ADC state */
       ADC_STATE_CLR_SET(hadc->State,
@@ -533,9 +515,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Gets the converted value from data register of injected channel.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  InjectedRank: the ADC injected rank.
+  * @param  InjectedRank the ADC injected rank.
   *          This parameter can be one of the following values:
   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -545,7 +527,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
   */
 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
 {
-  __IO uint32_t tmp = 0;
+  __IO uint32_t tmp = 0U;
   
   /* Check the parameters */
   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
@@ -588,15 +570,15 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   * 
   * @note   Caution: This function must be used only with the ADC master.  
   *
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  pData:   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
-  * @param  Length:  The length of data to be transferred from ADC peripheral to memory.  
+  * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 
+  * @param  Length  The length of data to be transferred from ADC peripheral to memory.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
 {
-  __IO uint32_t counter = 0;
+  __IO uint32_t counter = 0U;
   
   /* Check the parameters */
   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
@@ -615,8 +597,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
     
     /* Delay for temperature sensor stabilization time */
     /* Compute number of CPU cycles to wait for */
-    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
-    while(counter != 0)
+    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+    while(counter != 0U)
     {
       counter--;
     }
@@ -703,7 +685,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
 
 /**
   * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval HAL status
   */
@@ -750,24 +732,28 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
   *         data in the selected multi mode.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval The converted data value.
   */
 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* Return the multi mode conversion value */
   return ADC->CDR;
 }
 
 /**
   * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
   * @retval None
   */
 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
    */
@@ -776,16 +762,16 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Configures for the selected ADC injected channel its corresponding
   *         rank in the sequencer and its sample time.
-  * @param  hadc: pointer to a ADC_HandleTypeDef structure that contains
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
   *         the configuration information for the specified ADC.
-  * @param  sConfigInjected: ADC configuration structure for injected channel. 
+  * @param  sConfigInjected ADC configuration structure for injected channel. 
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
 {
   
 #ifdef USE_FULL_ASSERT  
-  uint32_t tmp = 0;
+  uint32_t tmp = 0U;
 #endif /* USE_FULL_ASSERT  */
   
   /* Check the parameters */
@@ -802,7 +788,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
 #endif /* USE_FULL_ASSERT  */
 
-  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
+  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
   {
     assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
   }
@@ -931,9 +917,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
 
 /**
   * @brief  Configures the ADC multi-mode 
-  * @param  hadc      : pointer to a ADC_HandleTypeDef structure that contains
-  *                     the configuration information for the specified ADC.  
-  * @param  multimode : pointer to an ADC_MultiModeTypeDef structure that contains 
+  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
+  *              the configuration information for the specified ADC.  
+  * @param  multimode pointer to an ADC_MultiModeTypeDef structure that contains 
   *                     the configuration information for  multimode.
   * @retval HAL status
   */
@@ -970,9 +956,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   * @}
   */
 
-  /**
+/**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1025,7 +1011,7 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1038,7 +1024,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_can.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_can.c
index 59ea6c5d..2adc37b3 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_can.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_can.c
@@ -2,99 +2,209 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_can.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   This file provides firmware functions to manage the following 
+  * @brief   CAN HAL module driver.
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Controller Area Network (CAN) peripheral:
-  *           + Initialization and de-initialization functions 
-  *           + IO operation functions
-  *           + Peripheral Control functions
+  *           + Initialization and de-initialization functions
+  *           + Configuration functions
+  *           + Control functions
+  *           + Interrupts management
+  *           + Callbacks functions
   *           + Peripheral State and Error functions
   *
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
-    [..]            
-      (#) Enable the CAN controller interface clock using 
-          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
-      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-       
-      (#) CAN pins configuration
-        (++) Enable the clock for the CAN GPIOs using the following function:
-             __GPIOx_CLK_ENABLE()   
-        (++) Connect and configure the involved CAN pins to AF9 using the 
-              following function HAL_GPIO_Init() 
-              
-      (#) Initialize and configure the CAN using CAN_Init() function.   
-                 
-      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-           
-      (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the CAN peripheral transmission and wait the end of this operation 
-           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
-           according to his end application
-       (+) Start the CAN peripheral reception and wait the end of this operation 
-           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
-           according to his end application 
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
-       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()         
-       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
-       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_TxCpltCallback 
-       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_CAN_ErrorCallback
- 
-     *** CAN HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in CAN HAL driver.
-       
-      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
-      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
-      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
-      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
-      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-      
-     [..] 
-      (@) You can refer to the CAN HAL driver header file for more useful macros 
-                
+    [..]
+      (#) Initialize the CAN low level resources by implementing the
+          HAL_CAN_MspInit():
+         (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+         (++) Configure CAN pins
+             (+++) Enable the clock for the CAN GPIOs
+             (+++) Configure CAN pins as alternate function open-drain
+         (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+             (+++) Configure the CAN interrupt priority using
+                   HAL_NVIC_SetPriority()
+             (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+      (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+          function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+      (#) Configure the reception filters using the following configuration
+          functions:
+            (++) HAL_CAN_ConfigFilter()
+
+      (#) Start the CAN module using HAL_CAN_Start() function. At this level
+          the node is active on the bus: it receive messages, and can send
+          messages.
+
+      (#) To manage messages transmission, the following Tx control functions
+          can be used:
+            (++) HAL_CAN_AddTxMessage() to request transmission of a new
+                 message.
+            (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+                 message.
+            (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+                 mailboxes.
+            (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+                 in a Tx mailbox.
+            (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+                 sent, if time triggered communication mode is enabled.
+
+      (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+          using the HAL_CAN_GetRxMessage() function. The function
+          HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+          stored in the Rx Fifo.
+
+      (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+      (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+      *** Polling mode operation ***
+      ==============================
+    [..]
+      (#) Reception:
+            (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+                 until at least one message is received.
+            (++) Then get the message using HAL_CAN_GetRxMessage().
+
+      (#) Transmission:
+            (++) Monitor the Tx mailboxes availability until at least one Tx
+                 mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+            (++) Then request transmission of a message using
+                 HAL_CAN_AddTxMessage().
+
+
+      *** Interrupt mode operation ***
+      ================================
+    [..]
+      (#) Notifications are activated using HAL_CAN_ActivateNotification()
+          function. Then, the process can be controlled through the
+          available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+          HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+      (#) Notifications can be deactivated using
+          HAL_CAN_DeactivateNotification() function.
+
+      (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+          CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+          the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+          HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+          here.
+            (++) Directly get the Rx message in the callback, using
+                 HAL_CAN_GetRxMessage().
+            (++) Or deactivate the notification in the callback without
+                 getting the Rx message. The Rx message can then be got later
+                 using HAL_CAN_GetRxMessage(). Once the Rx message have been
+                 read, the notification can be activated again.
+
+
+      *** Sleep mode ***
+      ==================
+    [..]
+      (#) The CAN peripheral can be put in sleep mode (low power), using
+          HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+          current CAN activity (transmission or reception of a CAN frame) will
+          be completed.
+
+      (#) A notification can be activated to be informed when the sleep mode
+          will be entered.
+
+      (#) It can be checked if the sleep mode is entered using
+          HAL_CAN_IsSleepActive().
+          Note that the CAN state (accessible from the API HAL_CAN_GetState())
+          is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+          submitted (the sleep mode is not yet entered), and become
+          HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+      (#) The wake-up from sleep mode can be trigged by two ways:
+            (++) Using HAL_CAN_WakeUp(). When returning from this function,
+                 the sleep mode is exited (if return status is HAL_OK).
+            (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+                 if automatic wake up mode is enabled.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.
+
+  Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:
+    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
+    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
+    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
+    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
+    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
+    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
+    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
+    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
+    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
+    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
+    (+) SleepCallback                : Sleep Callback.
+    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : CAN MspInit.
+    (+) MspDeInitCallback            : CAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
+    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
+    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
+    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
+    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
+    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
+    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
+    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
+    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
+    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
+    (+) SleepCallback                : Sleep Callback.
+    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : CAN MspInit.
+    (+) MspDeInitCallback            : CAN MspDeInit.
+
+  By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  example @ref HAL_CAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()
+  or @ref HAL_CAN_Init() function.
+
+  When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
   @endverbatim
-           
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -106,1131 +216,2101 @@
   * @{
   */
 
+#if defined(CAN1)
+
 /** @defgroup CAN CAN
   * @brief CAN driver modules
   * @{
-  */ 
-  
-#ifdef HAL_CAN_MODULE_ENABLED  
-  
+  */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @addtogroup CAN_Private_Constants
+/** @defgroup CAN_Private_Constants CAN Private Constants
   * @{
   */
-#define CAN_TIMEOUT_VALUE  10
+#define CAN_TIMEOUT_VALUE 10U
 /**
   * @}
   */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CAN_Private_Functions
-  * @{
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
-  * @}
-  */
-
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup CAN_Exported_Functions CAN Exported Functions
   * @{
   */
 
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
   ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize and configure the CAN. 
-      (+) De-initialize the CAN. 
-         
+      (+) HAL_CAN_Init                       : Initialize and configure the CAN.
+      (+) HAL_CAN_DeInit                     : De-initialize the CAN.
+      (+) HAL_CAN_MspInit                    : Initialize the CAN MSP.
+      (+) HAL_CAN_MspDeInit                  : DeInitialize the CAN MSP.
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the CAN peripheral according to the specified
   *         parameters in the CAN_InitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
 {
-  uint32_t InitStatus = 3;
-  uint32_t tickstart = 0;
-  
+  uint32_t tickstart;
+
   /* Check CAN handle */
-  if(hcan == NULL)
+  if (hcan == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
   assert_param(IS_CAN_MODE(hcan->Init.Mode));
-  assert_param(IS_CAN_SJW(hcan->Init.SJW));
-  assert_param(IS_CAN_BS1(hcan->Init.BS1));
-  assert_param(IS_CAN_BS2(hcan->Init.BS2));
+  assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+  assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+  assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-  
-
-  if(hcan->State == HAL_CAN_STATE_RESET)
-  {    
-    /* Allocate lock resource and initialize it */
-    hcan->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CAN_MspInit(hcan);
-  }
-  
-  /* Initialize the CAN state*/
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* Exit from sleep mode */
-  hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
-  /* Request initialisation */
-  hcan->Instance->MCR |= CAN_MCR_INRQ ;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
 
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  if (hcan->State == HAL_CAN_STATE_RESET)
   {
-    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+    /* Reset callbacks to legacy functions */
+    hcan->RxFifo0MsgPendingCallback  =  HAL_CAN_RxFifo0MsgPendingCallback;  /* Legacy weak RxFifo0MsgPendingCallback  */
+    hcan->RxFifo0FullCallback        =  HAL_CAN_RxFifo0FullCallback;        /* Legacy weak RxFifo0FullCallback        */
+    hcan->RxFifo1MsgPendingCallback  =  HAL_CAN_RxFifo1MsgPendingCallback;  /* Legacy weak RxFifo1MsgPendingCallback  */
+    hcan->RxFifo1FullCallback        =  HAL_CAN_RxFifo1FullCallback;        /* Legacy weak RxFifo1FullCallback        */
+    hcan->TxMailbox0CompleteCallback =  HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
+    hcan->TxMailbox1CompleteCallback =  HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
+    hcan->TxMailbox2CompleteCallback =  HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
+    hcan->TxMailbox0AbortCallback    =  HAL_CAN_TxMailbox0AbortCallback;    /* Legacy weak TxMailbox0AbortCallback    */
+    hcan->TxMailbox1AbortCallback    =  HAL_CAN_TxMailbox1AbortCallback;    /* Legacy weak TxMailbox1AbortCallback    */
+    hcan->TxMailbox2AbortCallback    =  HAL_CAN_TxMailbox2AbortCallback;    /* Legacy weak TxMailbox2AbortCallback    */
+    hcan->SleepCallback              =  HAL_CAN_SleepCallback;              /* Legacy weak SleepCallback              */
+    hcan->WakeUpFromRxMsgCallback    =  HAL_CAN_WakeUpFromRxMsgCallback;    /* Legacy weak WakeUpFromRxMsgCallback    */
+    hcan->ErrorCallback              =  HAL_CAN_ErrorCallback;              /* Legacy weak ErrorCallback              */
+
+    if (hcan->MspInitCallback == NULL)
     {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
+      hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
     }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hcan->MspInitCallback(hcan);
   }
 
-  /* Check acknowledge */
-  if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+#else
+  if (hcan->State == HAL_CAN_STATE_RESET)
   {
-    InitStatus = CAN_INITSTATUS_FAILED;
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_CAN_MspInit(hcan);
   }
-  else 
-  {
-    /* Set the time triggered communication mode */
-    if (hcan->Init.TTCM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TTCM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
-    }
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
 
-    /* Set the automatic bus-off management */
-    if (hcan->Init.ABOM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_ABOM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
-    }
+  /* Exit from sleep mode */
+  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
 
-    /* Set the automatic wake-up mode */
-    if (hcan->Init.AWUM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_AWUM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
-    }
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-    /* Set the no automatic retransmission */
-    if (hcan->Init.NART == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_NART;
-    }
-    else
+  /* Check Sleep mode leave acknowledge */
+  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
     {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
-    }
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
 
-    /* Set the receive FIFO locked mode */
-    if (hcan->Init.RFLM == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_RFLM;
-    }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
-    }
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_ERROR;
 
-    /* Set the transmit FIFO priority */
-    if (hcan->Init.TXFP == ENABLE)
-    {
-      hcan->Instance->MCR |= CAN_MCR_TXFP;
+      return HAL_ERROR;
     }
-    else
-    {
-      hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
-    }
-
-    /* Set the bit timing register */
-    hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
-                ((uint32_t)hcan->Init.SJW) | \
-                ((uint32_t)hcan->Init.BS1) | \
-                ((uint32_t)hcan->Init.BS2) | \
-               ((uint32_t)hcan->Init.Prescaler - 1);
+  }
 
-    /* Request leave initialisation */
-    hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+  /* Request initialisation */
+  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
-   /* Wait the acknowledge */
-   while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-   {
-    if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
-     {
-       hcan->State= HAL_CAN_STATE_TIMEOUT;
-       /* Process unlocked */
-       __HAL_UNLOCK(hcan);
-       return HAL_TIMEOUT;
-     }
-   }
-
-    /* Check acknowledged */
-    if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
-    {
-      InitStatus = CAN_INITSTATUS_FAILED;
-    }
-    else
+  /* Wait initialisation acknowledge */
+  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
     {
-      InitStatus = CAN_INITSTATUS_SUCCESS;
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_ERROR;
+
+      return HAL_ERROR;
     }
   }
- 
-  if(InitStatus == CAN_INITSTATUS_SUCCESS)
+
+  /* Set the time triggered communication mode */
+  if (hcan->Init.TimeTriggeredMode == ENABLE)
   {
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  
-    /* Return function status */
-    return HAL_OK;
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
   }
   else
   {
-    /* Initialize the CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR;
-    
-    /* Return function status */
-    return HAL_ERROR;
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
   }
-}
-
-/**
-  * @brief  Configures the CAN reception filter according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
-  uint32_t filternbrbitpos = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
-  assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
-  assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
-  assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
-  assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-  assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-  
-  filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
 
-  /* Initialisation mode for the filter */
-  CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
-  
-  /* Select the start slave bank */
-  CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
-  CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
-     
-  /* Filter Deactivation */
-  CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
-
-  /* Filter Scale */
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+  /* Set the automatic bus-off management */
+  if (hcan->Init.AutoBusOff == ENABLE)
   {
-    /* 16-bit scale for the filter */
-    CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
-
-    /* First 16-bit identifier and First 16-bit mask */
-    /* Or First 16-bit identifier and Second 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
-    /* Second 16-bit identifier and Second 16-bit mask */
-    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
   }
 
-  if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+  /* Set the automatic wake-up mode */
+  if (hcan->Init.AutoWakeUp == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+  }
+  else
   {
-    /* 32-bit scale for the filter */
-    CAN1->FS1R |= filternbrbitpos;
-    /* 32-bit identifier or First 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-    /* 32-bit mask or Second 32-bit identifier */
-    CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 = 
-       ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
-        (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
   }
 
-  /* Filter Mode */
-  if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+  /* Set the automatic retransmission */
+  if (hcan->Init.AutoRetransmission == ENABLE)
   {
-    /*Id/Mask mode for the filter*/
-    CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
   }
-  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  else
   {
-    /*Identifier list mode for the filter*/
-    CAN1->FM1R |= (uint32_t)filternbrbitpos;
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
   }
 
-  /* Filter FIFO assignment */
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+  /* Set the receive FIFO locked mode */
+  if (hcan->Init.ReceiveFifoLocked == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+  }
+  else
   {
-    /* FIFO 0 assignation for the filter */
-    CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
   }
 
-  if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+  /* Set the transmit FIFO priority */
+  if (hcan->Init.TransmitFifoPriority == ENABLE)
   {
-    /* FIFO 1 assignation for the filter */
-    CAN1->FFA1R |= (uint32_t)filternbrbitpos;
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
   }
-  
-  /* Filter activation */
-  if (sFilterConfig->FilterActivation == ENABLE)
+  else
   {
-    CAN1->FA1R |= filternbrbitpos;
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
   }
 
-  /* Leave the initialisation mode for the filter */
-  CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-  
+  /* Set the bit timing register */
+  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
+                                            hcan->Init.SyncJumpWidth  |
+                                            hcan->Init.TimeSeg1       |
+                                            hcan->Init.TimeSeg2       |
+                                            (hcan->Init.Prescaler - 1U)));
+
+  /* Initialize the error code */
+  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+  /* Initialize the CAN state */
+  hcan->State = HAL_CAN_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Deinitializes the CANx peripheral registers to their default reset values. 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @brief  Deinitializes the CAN peripheral registers to their default
+  *         reset values.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
 {
   /* Check CAN handle */
-  if(hcan == NULL)
+  if (hcan == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
+
+  /* Stop the CAN module */
+  (void)HAL_CAN_Stop(hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  if (hcan->MspDeInitCallback == NULL)
+  {
+    hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hcan->MspDeInitCallback(hcan);
+
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
   HAL_CAN_MspDeInit(hcan);
-  
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+
+  /* Reset the CAN peripheral */
+  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+  /* Reset the CAN ErrorCode */
+  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
   /* Change CAN state */
   hcan->State = HAL_CAN_STATE_RESET;
 
-  /* Release Lock */
-  __HAL_UNLOCK(hcan);
-
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
   * @retval None
   */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DeInitializes the CAN MSP.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
   * @retval None
   */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
 /**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Transmit a CAN frame message.
-      (+) Receive a CAN frame message.
-      (+) Enter CAN peripheral in sleep mode. 
-      (+) Wake up the CAN peripheral from sleep mode.
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  Timeout: Specify Timeout value   
+  * @brief  Register a CAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for CAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+  *           @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+  *           @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
 {
-  uint32_t  transmitmailbox = 5;
-  uint32_t tickstart = 0;
+  HAL_StatusTypeDef status = HAL_OK;
 
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-  }
-  
-  /* Select one empty transmit mailbox */
-  if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  if (pCallback == NULL)
   {
-    transmitmailbox = 0;
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
   }
-  else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+
+  if (hcan->State == HAL_CAN_STATE_READY)
   {
-    transmitmailbox = 1;
+    switch (CallbackID)
+    {
+      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+        hcan->TxMailbox0CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+        hcan->TxMailbox1CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+        hcan->TxMailbox2CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+        hcan->TxMailbox0AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+        hcan->TxMailbox1AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+        hcan->TxMailbox2AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+        hcan->RxFifo0MsgPendingCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+        hcan->RxFifo0FullCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+        hcan->RxFifo1MsgPendingCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+        hcan->RxFifo1FullCallback = pCallback;
+        break;
+
+      case HAL_CAN_SLEEP_CB_ID :
+        hcan->SleepCallback = pCallback;
+        break;
+
+      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+        hcan->WakeUpFromRxMsgCallback = pCallback;
+        break;
+
+      case HAL_CAN_ERROR_CB_ID :
+        hcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
   }
-  else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  else if (hcan->State == HAL_CAN_STATE_RESET)
   {
-    transmitmailbox = 2;
+    switch (CallbackID)
+    {
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
   }
   else
   {
-    transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
   }
 
-  if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+  return status;
+}
+
+/**
+  * @brief  Unregister a CAN CallBack.
+  *         CAN callabck is redirected to the weak predefined callback
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for CAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+  *           @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+  *           @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hcan->State == HAL_CAN_STATE_READY)
   {
-    /* Set up the Id */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-    if (hcan->pTxMsg->IDE == CAN_ID_STD)
-    {
-      assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    else
+    switch (CallbackID)
     {
-      assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
-    }
-    
-    /* Set up the DLC */
-    hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-    hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
-    /* Set up the data field */
-    hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-    hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
-    /* Request transmission */
-    hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-  
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-  
-    /* Check End of transmission flag */
-    while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-       {
-         hcan->State = HAL_CAN_STATE_TIMEOUT;
-         /* Process unlocked */
-         __HAL_UNLOCK(hcan);
-         return HAL_TIMEOUT;
-        }
-      }
-    }
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-    {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
-      
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
+      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+        hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+        hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+        hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+        hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+        hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+        hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+        hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+        hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+        hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+        hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
+        break;
+
+      case HAL_CAN_SLEEP_CB_ID :
+        hcan->SleepCallback = HAL_CAN_SleepCallback;
+        break;
+
+      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+        hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
+        break;
+
+      case HAL_CAN_ERROR_CB_ID :
+        hcan->ErrorCallback = HAL_CAN_ErrorCallback;
+        break;
+
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = HAL_CAN_MspInit;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
-    else
+  }
+  else if (hcan->State == HAL_CAN_STATE_RESET)
+  {
+    switch (CallbackID)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_READY;
-      
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = HAL_CAN_MspInit;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
-    
-    /* Return function status */
-    return HAL_OK;
   }
   else
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_ERROR; 
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
 
-    /* Return function status */
-    return HAL_ERROR;
+    /* Return error status */
+    status =  HAL_ERROR;
   }
+
+  return status;
 }
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
 
 /**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @retval HAL status
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_ConfigFilter            : Configure the CAN reception filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that
+  *         contains the filter configuration information.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
 {
-  uint32_t  transmitmailbox = 5;
-  uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
-  assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
-  assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-  
-  tmp = hcan->State;
-  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcan);
-    
-    /* Select one empty transmit mailbox */
-    if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  uint32_t filternbrbitpos;
+  CAN_TypeDef *can_ip = hcan->Instance;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+    assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+    assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+    assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+    assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
+
+#if   defined(CAN2)
+    /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+    /* Select master instance to access the filter banks */
+    can_ip = CAN1;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+    /* CAN1 is single instance with 14 dedicated filters banks */
+
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+    /* Initialisation mode for the filter */
+    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if   defined(CAN2)
+    /* Select the start filter number of CAN2 slave instance */
+    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+    /* Convert filter number into bit position */
+    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
+
+    /* Filter Deactivation */
+    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+    /* Filter Scale */
+    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
     {
-      transmitmailbox = 0;
+      /* 16-bit scale for the filter */
+      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+      /* First 16-bit identifier and First 16-bit mask */
+      /* Or First 16-bit identifier and Second 16-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+      /* Second 16-bit identifier and Second 16-bit mask */
+      /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
     }
-    else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+
+    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
     {
-      transmitmailbox = 1;
+      /* 32-bit scale for the filter */
+      SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+      /* 32-bit identifier or First 32-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+      /* 32-bit mask or Second 32-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
     }
-    else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+
+    /* Filter Mode */
+    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
     {
-      transmitmailbox = 2;
+      /* Id/Mask mode for the filter*/
+      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
     }
-    else
+    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
     {
-      transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+      /* Identifier list mode for the filter*/
+      SET_BIT(can_ip->FM1R, filternbrbitpos);
     }
 
-    if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+    /* Filter FIFO assignment */
+    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
     {
+      /* FIFO 0 assignation for the filter */
+      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+    }
+    else
+    {
+      /* FIFO 1 assignation for the filter */
+      SET_BIT(can_ip->FFA1R, filternbrbitpos);
+    }
+
+    /* Filter activation */
+    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
+    {
+      SET_BIT(can_ip->FA1R, filternbrbitpos);
+    }
+
+    /* Leave the initialisation mode for the filter */
+    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_Start                    : Start the CAN module
+      (+) HAL_CAN_Stop                     : Stop the CAN module
+      (+) HAL_CAN_RequestSleep             : Request sleep mode entry.
+      (+) HAL_CAN_WakeUp                   : Wake up from sleep mode.
+      (+) HAL_CAN_IsSleepActive            : Check is sleep mode is active.
+      (+) HAL_CAN_AddTxMessage             : Add a message to the Tx mailboxes
+                                             and activate the corresponding
+                                             transmission request
+      (+) HAL_CAN_AbortTxRequest           : Abort transmission request
+      (+) HAL_CAN_GetTxMailboxesFreeLevel  : Return Tx mailboxes free level
+      (+) HAL_CAN_IsTxMessagePending       : Check if a transmission request is
+                                             pending on the selected Tx mailbox
+      (+) HAL_CAN_GetRxMessage             : Get a CAN frame from the Rx FIFO
+      (+) HAL_CAN_GetRxFifoFillLevel       : Return Rx FIFO fill level
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the CAN module.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
+{
+  uint32_t tickstart;
+
+  if (hcan->State == HAL_CAN_STATE_READY)
+  {
+    /* Change CAN peripheral state */
+    hcan->State = HAL_CAN_STATE_LISTENING;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait the acknowledge */
+    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Reset the CAN ErrorCode */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the CAN module and enable access to configuration registers.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+  uint32_t tickstart;
+
+  if (hcan->State == HAL_CAN_STATE_LISTENING)
+  {
+    /* Request initialisation */
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait the acknowledge */
+    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Exit from sleep mode */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Change CAN peripheral state */
+    hcan->State = HAL_CAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Request the sleep mode (low power) entry.
+  *         When returning from this function, Sleep mode will be entered
+  *         as soon as the current CAN activity (transmission or reception
+  *         of a CAN frame) has been completed.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Request Sleep mode */
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Wake up from sleep mode.
+  *         When returning with HAL_OK status from this function, Sleep mode
+  *         is exited.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = 1000000U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Wake up request */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Wait sleep mode is exited */
+    do
+    {
+      /* Increment counter */
+      count++;
+
+      /* Check if timeout is reached */
+      if (count > timeout)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        return HAL_ERROR;
+      }
+    }
+    while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Check is sleep mode is active.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval Status
+  *          - 0 : Sleep mode is not active.
+  *          - 1 : Sleep mode is active.
+  */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+  uint32_t status = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Sleep mode */
+    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+    {
+      status = 1U;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Add a message to the first free Tx mailbox and activate the
+  *         corresponding transmission request.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  pHeader pointer to a CAN_TxHeaderTypeDef structure.
+  * @param  aData array containing the payload of the Tx frame.
+  * @param  pTxMailbox pointer to a variable where the function will return
+  *         the TxMailbox used to store the Tx message.
+  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
+{
+  uint32_t transmitmailbox;
+  HAL_CAN_StateTypeDef state = hcan->State;
+  uint32_t tsr = READ_REG(hcan->Instance->TSR);
+
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+  assert_param(IS_CAN_RTR(pHeader->RTR));
+  assert_param(IS_CAN_DLC(pHeader->DLC));
+  if (pHeader->IDE == CAN_ID_STD)
+  {
+    assert_param(IS_CAN_STDID(pHeader->StdId));
+  }
+  else
+  {
+    assert_param(IS_CAN_EXTID(pHeader->ExtId));
+  }
+  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check that all the Tx mailboxes are not full */
+    if (((tsr & CAN_TSR_TME0) != 0U) ||
+        ((tsr & CAN_TSR_TME1) != 0U) ||
+        ((tsr & CAN_TSR_TME2) != 0U))
+    {
+      /* Select an empty transmit mailbox */
+      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+      /* Check transmit mailbox value */
+      if (transmitmailbox > 2U)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+        return HAL_ERROR;
+      }
+
+      /* Store the Tx mailbox */
+      *pTxMailbox = (uint32_t)1 << transmitmailbox;
+
       /* Set up the Id */
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
-      if(hcan->pTxMsg->IDE == CAN_ID_STD)
+      if (pHeader->IDE == CAN_ID_STD)
       {
-        assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));  
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
-                                                  hcan->pTxMsg->RTR);
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+                                                           pHeader->RTR);
       }
       else
       {
-        assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
-                                                  hcan->pTxMsg->IDE | \
-                                                  hcan->pTxMsg->RTR);
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+                                                           pHeader->IDE |
+                                                           pHeader->RTR);
       }
-    
+
       /* Set up the DLC */
-      hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
+
+      /* Set up the Transmit Global Time mode */
+      if (pHeader->TransmitGlobalTime == ENABLE)
+      {
+        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+      }
 
       /* Set up the data field */
-      hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[1] << 8) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[0]));
-      hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) | 
-                                             ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
-                                             ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
-                                             ((uint32_t)hcan->pTxMsg->Data[4]));
-    
-      if(hcan->State == HAL_CAN_STATE_BUSY_RX) 
+      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+                ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+      /* Request transmission */
+      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Abort transmission requests
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailboxes List of the Tx Mailboxes to abort.
+  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Tx Mailbox 0 */
+    if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 0 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
+    }
+
+    /* Check Tx Mailbox 1 */
+    if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 1 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+    }
+
+    /* Check Tx Mailbox 2 */
+    if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 2 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Return Tx Mailboxes free level: number of free Tx Mailboxes.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval Number of free Tx Mailboxes.
+  */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+  uint32_t freelevel = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Tx Mailbox 0 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
+    {
+      freelevel++;
+    }
+
+    /* Check Tx Mailbox 1 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
+    {
+      freelevel++;
+    }
+
+    /* Check Tx Mailbox 2 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
+    {
+      freelevel++;
+    }
+  }
+
+  /* Return Tx Mailboxes free level */
+  return freelevel;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx
+  *         Mailboxes.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailboxes List of Tx Mailboxes to check.
+  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+  * @retval Status
+  *          - 0 : No pending transmission request on any selected Tx Mailboxes.
+  *          - 1 : Pending transmission request on at least one of the selected
+  *                Tx Mailbox.
+  */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+  uint32_t status = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check pending transmission request on the selected Tx Mailboxes */
+    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+    {
+      status = 1U;
+    }
+  }
+
+  /* Return status */
+  return status;
+}
+
+/**
+  * @brief  Return timestamp of Tx message sent, if time triggered communication
+            mode is enabled.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailbox Tx Mailbox where the timestamp of message sent will be
+  *         read.
+  *         This parameter can be one value of @arg CAN_Tx_Mailboxes.
+  * @retval Timestamp of message sent from Tx Mailbox.
+  */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+  uint32_t timestamp = 0U;
+  uint32_t transmitmailbox;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Select the Tx mailbox */
+    transmitmailbox = POSITION_VAL(TxMailbox);
+
+    /* Get timestamp */
+    timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+  }
+
+  /* Return the timestamp */
+  return timestamp;
+}
+
+/**
+  * @brief  Get an CAN frame from the Rx FIFO zone into the message RAM.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  RxFifo Fifo number of the received message to be read.
+  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
+  * @param  pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+  *         of the Rx frame will be stored.
+  * @param  aData array where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check the Rx FIFO */
+    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
       {
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+    }
+    else /* Rx element is assigned to Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 is not empty */
+      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the header */
+    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+    if (pHeader->IDE == CAN_ID_STD)
+    {
+      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+    }
+    else
+    {
+      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
+    }
+    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
+    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+    /* Get the data */
+    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
+
+    /* Release the FIFO */
+    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+    {
+      /* Release RX FIFO 0 */
+      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+    }
+    else /* Rx element is assigned to Rx FIFO 1 */
+    {
+      /* Release RX FIFO 1 */
+      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
+  * @retval Number of messages available in Rx FIFO.
+  */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+  uint32_t filllevel = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    if (RxFifo == CAN_RX_FIFO0)
+    {
+      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+    }
+    else /* RxFifo == CAN_RX_FIFO1 */
+    {
+      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
+    }
+  }
+
+  /* Return Rx FIFO fill level */
+  return filllevel;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_ActivateNotification      : Enable interrupts
+      (+) HAL_CAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_CAN_IRQHandler                : Handles CAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg CAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_IT(ActiveITs));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Enable the selected interrupts */
+    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg CAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_IT(InactiveITs));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Disable the selected interrupts */
+    __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles CAN interrupt request
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+  uint32_t errorcode = HAL_CAN_ERROR_NONE;
+  uint32_t interrupts = READ_REG(hcan->Instance->IER);
+  uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+  uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+  /* Transmit Mailbox empty interrupt management *****************************/
+  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
+  {
+    /* Transmit Mailbox 0 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP0) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+      if ((tsrflags & CAN_TSR_TXOK0) != 0U)
+      {
+        /* Transmission Mailbox 0 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox0CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox0CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
       }
       else
       {
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_BUSY_TX;
+        if ((tsrflags & CAN_TSR_ALST0) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST0;
+        }
+        else if ((tsrflags & CAN_TSR_TERR0) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR0;
+        }
+        else
+        {
+          /* Transmission Mailbox 0 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox0AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox0AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* Transmit Mailbox 1 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP1) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+      if ((tsrflags & CAN_TSR_TXOK1) != 0U)
+      {
+        /* Transmission Mailbox 1 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox1CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox1CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        if ((tsrflags & CAN_TSR_ALST1) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST1;
+        }
+        else if ((tsrflags & CAN_TSR_TERR1) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR1;
+        }
+        else
+        {
+          /* Transmission Mailbox 1 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox1AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox1AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* Transmit Mailbox 2 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP2) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+      if ((tsrflags & CAN_TSR_TXOK2) != 0U)
+      {
+        /* Transmission Mailbox 2 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox2CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox2CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        if ((tsrflags & CAN_TSR_ALST2) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST2;
+        }
+        else if ((tsrflags & CAN_TSR_TERR2) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR2;
+        }
+        else
+        {
+          /* Transmission Mailbox 2 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox2AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox2AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
       }
-      
-      /* Set CAN error code to none */
-      hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcan);
-      
-      /* Enable Error warning Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-      
-      /* Enable Error passive Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-      
-      /* Enable Bus-off Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-      
-      /* Enable Last error code Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-      
-      /* Enable Error Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-      
-      /* Enable Transmit mailbox empty Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
-      
-      /* Request transmission */
-      hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
     }
   }
-  else
-  {
-    return HAL_BUSY;
-  }
-  
-  return HAL_OK;
-}
 
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: FIFO Number value
-  * @param  Timeout: Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
-  }
-  else
+  /* Receive FIFO 0 overrun interrupt management *****************************/
+  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
+    if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
+    {
+      /* Set CAN error code to Rx Fifo 0 overrun error */
+      errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+      /* Clear FIFO0 Overrun Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+    }
   }
-    
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-  
-  /* Check pending message */
-  while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+
+  /* Receive FIFO 0 full interrupt management ********************************/
+  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
   {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hcan->State = HAL_CAN_STATE_TIMEOUT;
-        /* Process unlocked */
-        __HAL_UNLOCK(hcan);
-        return HAL_TIMEOUT;
-      }
+      /* Clear FIFO 0 full Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+      /* Receive FIFO 0 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo0FullCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo0FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
     }
   }
-  
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
+
+  /* Receive FIFO 0 message pending interrupt management *********************/
+  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
   {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+    /* Check if message is still pending */
+    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
+    {
+      /* Receive FIFO 0 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo0MsgPendingCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
   }
-  else
+
+  /* Receive FIFO 1 overrun interrupt management *****************************/
+  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
   {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  
-  /* Release the FIFO */
-  if(FIFONumber == CAN_FIFO0)
-  {
-    /* Release FIFO0 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-  }
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    /* Release FIFO1 */
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
+    if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
+    {
+      /* Set CAN error code to Rx Fifo 1 overrun error */
+      errorcode |= HAL_CAN_ERROR_RX_FOV1;
+
+      /* Clear FIFO1 Overrun Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+    }
   }
-  else
+
+  /* Receive FIFO 1 full interrupt management ********************************/
+  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
+    if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
+    {
+      /* Clear FIFO 1 full Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+      /* Receive FIFO 1 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo1FullCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo1FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
   }
-  
-  /* Return function status */
-  return HAL_OK;
-}
 
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_CAN_FIFO(FIFONumber));
-  
-  tmp = hcan->State;
-  if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
-  {
-    /* Process locked */
-    __HAL_LOCK(hcan);
-  
-    if(hcan->State == HAL_CAN_STATE_BUSY_TX) 
+  /* Receive FIFO 1 message pending interrupt management *********************/
+  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
+  {
+    /* Check if message is still pending */
+    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+      /* Receive FIFO 1 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo1MsgPendingCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
     }
-    else
+  }
+
+  /* Sleep interrupt management *********************************************/
+  if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
+  {
+    if ((msrflags & CAN_MSR_SLAKI) != 0U)
     {
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_BUSY_RX;
+      /* Clear Sleep interrupt Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+      /* Sleep Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->SleepCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_SleepCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
     }
-    
-    /* Set CAN error code to none */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-    
-    /* Enable Error warning Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-      
-    /* Enable Error passive Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-      
-    /* Enable Bus-off Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-      
-    /* Enable Last error code Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-      
-    /* Enable Error Interrupt */
-    __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
-
-    if(FIFONumber == CAN_FIFO0)
+  }
+
+  /* WakeUp interrupt management *********************************************/
+  if ((interrupts & CAN_IT_WAKEUP) != 0U)
+  {
+    if ((msrflags & CAN_MSR_WKUI) != 0U)
     {
-      /* Enable FIFO 0 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+      /* Clear WakeUp Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
+
+      /* WakeUp Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->WakeUpFromRxMsgCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
     }
-    else
+  }
+
+  /* Error interrupts management *********************************************/
+  if ((interrupts & CAN_IT_ERROR) != 0U)
+  {
+    if ((msrflags & CAN_MSR_ERRI) != 0U)
     {
-      /* Enable FIFO 1 message pending Interrupt */
-      __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+      /* Check Error Warning Flag */
+      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+          ((esrflags & CAN_ESR_EWGF) != 0U))
+      {
+        /* Set CAN error code to Error Warning */
+        errorcode |= HAL_CAN_ERROR_EWG;
+
+        /* No need for clear of Error Warning Flag as read-only */
+      }
+
+      /* Check Error Passive Flag */
+      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+          ((esrflags & CAN_ESR_EPVF) != 0U))
+      {
+        /* Set CAN error code to Error Passive */
+        errorcode |= HAL_CAN_ERROR_EPV;
+
+        /* No need for clear of Error Passive Flag as read-only */
+      }
+
+      /* Check Bus-off Flag */
+      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+          ((esrflags & CAN_ESR_BOFF) != 0U))
+      {
+        /* Set CAN error code to Bus-Off */
+        errorcode |= HAL_CAN_ERROR_BOF;
+
+        /* No need for clear of Error Bus-Off as read-only */
+      }
+
+      /* Check Last Error Code Flag */
+      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+          ((esrflags & CAN_ESR_LEC) != 0U))
+      {
+        switch (esrflags & CAN_ESR_LEC)
+        {
+          case (CAN_ESR_LEC_0):
+            /* Set CAN error code to Stuff error */
+            errorcode |= HAL_CAN_ERROR_STF;
+            break;
+          case (CAN_ESR_LEC_1):
+            /* Set CAN error code to Form error */
+            errorcode |= HAL_CAN_ERROR_FOR;
+            break;
+          case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+            /* Set CAN error code to Acknowledgement error */
+            errorcode |= HAL_CAN_ERROR_ACK;
+            break;
+          case (CAN_ESR_LEC_2):
+            /* Set CAN error code to Bit recessive error */
+            errorcode |= HAL_CAN_ERROR_BR;
+            break;
+          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+            /* Set CAN error code to Bit Dominant error */
+            errorcode |= HAL_CAN_ERROR_BD;
+            break;
+          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+            /* Set CAN error code to CRC error */
+            errorcode |= HAL_CAN_ERROR_CRC;
+            break;
+          default:
+            break;
+        }
+
+        /* Clear Last error code Flag */
+        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+      }
     }
-    
+
+    /* Clear ERRI Flag */
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
   }
-  else
+
+  /* Call the Error call Back in case of Errors */
+  if (errorcode != HAL_CAN_ERROR_NONE)
   {
-    return HAL_BUSY;
+    /* Update error code in handle */
+    hcan->ErrorCode |= errorcode;
+
+    /* Call Error callback function */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hcan->ErrorCallback(hcan);
+#else
+    /* Call weak (surcharged) callback */
+    HAL_CAN_ErrorCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
   }
-  
-  /* Return function status */
-  return HAL_OK;
 }
 
 /**
-  * @brief  Enters the Sleep (low power) mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ *  @brief   CAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_CAN_TxMailbox0CompleteCallback
+      (+) HAL_CAN_TxMailbox1CompleteCallback
+      (+) HAL_CAN_TxMailbox2CompleteCallback
+      (+) HAL_CAN_TxMailbox0AbortCallback
+      (+) HAL_CAN_TxMailbox1AbortCallback
+      (+) HAL_CAN_TxMailbox2AbortCallback
+      (+) HAL_CAN_RxFifo0MsgPendingCallback
+      (+) HAL_CAN_RxFifo0FullCallback
+      (+) HAL_CAN_RxFifo1MsgPendingCallback
+      (+) HAL_CAN_RxFifo1FullCallback
+      (+) HAL_CAN_SleepCallback
+      (+) HAL_CAN_WakeUpFromRxMsgCallback
+      (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmission Mailbox 0 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
-  * @retval HAL status.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
 {
-  uint32_t tickstart = 0;
-   
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY; 
-    
-  /* Request Sleep mode */
-   hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-   
-  /* Sleep mode status */
-  if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
 
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-  
-  /* Wait the acknowledge */
-  while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State = HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+            user file
+   */
 }
 
 /**
-  * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
-  *         is in the normal mode.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  Transmission Mailbox 1 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
-  * @retval HAL status.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
 {
-  uint32_t tickstart = 0;
-    
-  /* Process locked */
-  __HAL_LOCK(hcan);
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_BUSY;  
- 
-  /* Wake up request */
-  hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
 
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+            user file
+   */
+}
 
-  /* Sleep mode status */
-  while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    if((HAL_GetTick()  - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      hcan->State= HAL_CAN_STATE_TIMEOUT;
-      /* Process unlocked */
-      __HAL_UNLOCK(hcan);
-      return HAL_TIMEOUT;
-    }
-  }
-  if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hcan);
- 
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hcan);
-  
-  /* Return function status */
-  return HAL_OK;
+/**
+  * @brief  Transmission Mailbox 2 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+            user file
+   */
 }
 
 /**
-  * @brief  Handles CAN interrupt request  
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  Transmission Mailbox 0 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
 {
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
-  
-  /* Check End of transmission flag */
-  if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
-  {
-    tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
-    tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
-    tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
-    if(tmp1 || tmp2 || tmp3)  
-    {
-      /* Call transmit function */
-      CAN_Transmit_IT(hcan);
-    }
-  }
-  
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
-  /* Check End of reception flag for FIFO0 */
-  if((tmp1 != 0) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO0);
-  }
-  
-  tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
-  /* Check End of reception flag for FIFO1 */
-  if((tmp1 != 0) && tmp2)
-  {
-    /* Call receive function */
-    CAN_Receive_IT(hcan, CAN_FIFO1);
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Error Warning Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EWG error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
-    /* Clear Error Warning Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EWG);
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); 
-  /* Check Error Passive Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to EPV error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
-    /* Clear Error Passive Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_EPV);
-  }
-  
-  tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);  
-  /* Check Bus-Off Flag */
-  if(tmp1 && tmp2 && tmp3)
-  {
-    /* Set CAN error code to BOF error */
-    hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
-    /* Clear Bus-Off Flag */ 
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_BOF);
-  }
-  
-  tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
-  tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
-  tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
-  /* Check Last error code Flag */
-  if((!tmp1) && tmp2 && tmp3)
-  {
-    tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
-    switch(tmp1)
-    {
-      case(CAN_ESR_LEC_0):
-          /* Set CAN error code to STF error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_STF;
-          break;
-      case(CAN_ESR_LEC_1):
-          /* Set CAN error code to FOR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
-          break;
-      case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
-          /* Set CAN error code to ACK error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
-          break;
-      case(CAN_ESR_LEC_2):
-          /* Set CAN error code to BR error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BR;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
-          /* Set CAN error code to BD error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_BD;
-          break;
-      case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
-          /* Set CAN error code to CRC error */
-          hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
-          break;
-      default:
-          break;
-    }
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
 
-    /* Clear Last error code Flag */ 
-    hcan->Instance->ESR &= ~(CAN_ESR_LEC);
-  }
-  
-  /* Call the Error call Back in case of Errors */
-  if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
-  {
-    /* Set the CAN state ready to be able to start again the process */
-    hcan->State = HAL_CAN_STATE_READY;
-    /* Call Error callback function */
-    HAL_CAN_ErrorCallback(hcan);
-  }  
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 1 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 2 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 message pending callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 full callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+            file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 message pending callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 full callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+            file
+   */
 }
 
 /**
-  * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  Sleep callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxCpltCallback could be implemented in the user file
+            the HAL_CAN_SleepCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Transmission  complete callback in non blocking mode 
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  WakeUp from Rx message callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxCpltCallback could be implemented in the user file
+            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+            user file
    */
 }
 
 /**
   * @brief  Error CAN callback.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval None
   */
 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CAN_ErrorCallback could be implemented in the user file
    */
@@ -1240,192 +2320,115 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
   * @}
   */
 
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
             ##### Peripheral State and Error functions #####
   ==============================================================================
     [..]
     This subsection provides functions allowing to :
-      (+) Check the CAN state.
-      (+) Check CAN Errors detected during interrupt process
-         
+      (+) HAL_CAN_GetState()  : Return the CAN state.
+      (+) HAL_CAN_GetError()  : Return the CAN error codes if any.
+      (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  return the CAN state
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  Return the CAN state.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval HAL state
   */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
 {
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check sleep mode acknowledge flag */
+    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+    {
+      /* Sleep mode is active */
+      state = HAL_CAN_STATE_SLEEP_ACTIVE;
+    }
+    /* Check sleep mode request flag */
+    else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
+    {
+      /* Sleep mode request is pending */
+      state = HAL_CAN_STATE_SLEEP_PENDING;
+    }
+    else
+    {
+      /* Neither sleep mode request nor sleep mode acknowledge */
+    }
+  }
+
   /* Return CAN state */
-  return hcan->State;
+  return state;
 }
 
 /**
-  * @brief  Return the CAN error code
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
+  * @brief  Return the CAN error code.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
   *         the configuration information for the specified CAN.
   * @retval CAN Error Code
   */
 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
 {
+  /* Return CAN error code */
   return hcan->ErrorCode;
 }
 
 /**
-  * @}
-  */
-/**
-  * @brief  Initiates and transmits a CAN frame message.
-  * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
+  * @brief  Reset the CAN error code.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
   * @retval HAL status
   */
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
 {
-  /* Disable Transmit mailbox empty Interrupt */
-  __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX)
-  {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
-  
-  /* Transmission complete callback */ 
-  HAL_CAN_TxCpltCallback(hcan);
-  
-  return HAL_OK;
-}
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_CAN_StateTypeDef state = hcan->State;
 
-/**
-  * @brief  Receives a correct CAN frame.
-  * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.  
-  * @param  FIFONumber: Specify the FIFO number    
-  * @retval HAL status
-  * @retval None
-  */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
-  /* Get the Id */
-  hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  if (hcan->pRxMsg->IDE == CAN_ID_STD)
-  {
-    hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
-  }
-  else
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
   {
-    hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
-  }
-  
-  hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
-  /* Get the DLC */
-  hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
-  /* Get the FMI */
-  hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
-  /* Get the data field */
-  hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
-  hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
-  hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
-  hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
-  hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
-  hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
-  hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
-  hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-  /* Release the FIFO */
-  /* Release FIFO0 */
-  if (FIFONumber == CAN_FIFO0)
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
-    
-    /* Disable FIFO 0 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
-  }
-  /* Release FIFO1 */
-  else /* FIFONumber == CAN_FIFO1 */
-  {
-    __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-    
-    /* Disable FIFO 1 message pending Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_RX)
-  {   
-    /* Disable Error warning Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-    
-    /* Disable Error passive Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-    
-    /* Disable Bus-off Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-    
-    /* Disable Last error code Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-    
-    /* Disable Error Interrupt */
-    __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
-  }
-  
-  if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) 
-  {
-    /* Disable CAN state */
-    hcan->State = HAL_CAN_STATE_BUSY_TX;
+    /* Reset CAN error code */
+    hcan->ErrorCode = 0U;
   }
   else
   {
-    /* Change CAN state */
-    hcan->State = HAL_CAN_STATE_READY;
-  }
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
 
-  /* Receive complete callback */ 
-  HAL_CAN_RxCpltCallback(hcan);
+    status = HAL_ERROR;
+  }
 
-  /* Return function status */
-  return HAL_OK;
+  /* Return the status */
+  return status;
 }
 
+/**
+  * @}
+  */
+
 /**
   * @}
   */
 
 #endif /* HAL_CAN_MODULE_ENABLED */
+
 /**
   * @}
   */
 
+#endif /* CAN1 */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c
index 0e907bfe..ec8a43dc 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the CORTEX:
@@ -26,7 +24,7 @@
         function according to the following table.
     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programing manual for details in how to configure priority. 
+    (#) please refer to programming manual for details in how to configure priority. 
       
      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
          The pending IRQ priority will be managed only by the sub priority.
@@ -45,7 +43,7 @@
    (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
        is a CMSIS function that:
         (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
         (++) Resets the SysTick Counter register.
         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
         (++) Enables the SysTick Interrupt.
@@ -70,29 +68,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -142,7 +124,7 @@
 /**
   * @brief  Sets the priority grouping field (preemption priority and subpriority)
   *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length. 
+  * @param  PriorityGroup The priority grouping bits length. 
   *         This parameter can be one of the following values:
   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
   *                                    4 bits for subpriority
@@ -169,20 +151,20 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 
 /**
   * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
+  * @param  IRQn External interrupt number.
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
-  * @param  PreemptPriority: The preemption priority for the IRQn channel.
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
   *         This parameter can be a value between 0 and 15
   *         A lower priority value indicates a higher priority 
-  * @param  SubPriority: the subpriority level for the IRQ channel.
+  * @param  SubPriority the subpriority level for the IRQ channel.
   *         This parameter can be a value between 0 and 15
   *         A lower priority value indicates a higher priority.          
   * @retval None
   */
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 { 
-  uint32_t prioritygroup = 0x00;
+  uint32_t prioritygroup = 0x00U;
   
   /* Check the parameters */
   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
@@ -240,7 +222,7 @@ void HAL_NVIC_SystemReset(void)
 /**
   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
   *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
@@ -268,10 +250,50 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
   * @{
   */
 
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0U;
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged access to the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
 /**
   * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
   *                the initialization and configuration information.
   * @retval None
   */
@@ -309,8 +331,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
   }
   else
   {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
+    MPU->RBAR = 0x00U;
+    MPU->RASR = 0x00U;
   }
 }
 #endif /* __MPU_PRESENT */
@@ -327,10 +349,10 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
 
 /**
   * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number.
+  * @param  IRQn External interrupt number.
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
-  * @param   PriorityGroup: the priority grouping bits length.
+  * @param   PriorityGroup the priority grouping bits length.
   *         This parameter can be one of the following values:
   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
   *                                      4 bits for subpriority
@@ -342,8 +364,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
   *                                      1 bits for subpriority
   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
   *                                      0 bits for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
   * @retval None
   */
 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
@@ -423,7 +445,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
 
 /**
   * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
   *          This parameter can be one of the following values:
   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c
index 087080e1..4adabaa9 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c
@@ -2,59 +2,42 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   CRC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
   *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
   *
   @verbatim
-  ==============================================================================
+ ===============================================================================
                      ##### How to use this driver #####
-  ==============================================================================
+ ===============================================================================
     [..]
-      The CRC HAL driver can be used as follows:
-
-      (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
-
-      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of 
-          a 32-bit data buffer using combination of the previous CRC value
-          and the new one.
-
-      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of 
-          a new 32-bit data buffer. This function resets the CRC computation  
-          unit before starting the computation to avoid getting wrong CRC values.
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
+             (++) specify generating polynomial (peripheral default or non-default one)
+             (++) specify initialization value (peripheral default or non-default one)
+             (++) specify input data format
+             (++) specify input or output data inversion mode if any
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+             input data buffer starting with the previously computed CRC as
+             initialization value
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+             input data buffer starting with the defined initialization value
+             (default or non-default) to initiate CRC calculation
 
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -66,7 +49,8 @@
   * @{
   */
 
-/** @addtogroup CRC 
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver.
   * @{
   */
 
@@ -77,42 +61,41 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+
 /* Exported functions --------------------------------------------------------*/
 
-/** @addtogroup CRC_Exported_Functions
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
   * @{
   */
 
-/** @addtogroup CRC_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions 
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions.
  *
-@verbatim     
-  ==============================================================================
+@verbatim
+ ===============================================================================
             ##### Initialization and de-initialization functions #####
-  ==============================================================================
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the CRC according to the specified parameters 
+      (+) Initialize the CRC according to the specified parameters
           in the CRC_InitTypeDef and create the associated handle
       (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP
-      (+) DeInitialize CRC MSP 
- 
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and creates the associated handle.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
 {
   /* Check the CRC handle allocation */
-  if(hcrc == NULL)
+  if (hcrc == NULL)
   {
     return HAL_ERROR;
   }
@@ -120,34 +103,30 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
   /* Check the parameters */
   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
 
-  if(hcrc->State == HAL_CRC_STATE_RESET)
+  if (hcrc->State == HAL_CRC_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hcrc->Lock = HAL_UNLOCKED;
     /* Init the low level hardware */
     HAL_CRC_MspInit(hcrc);
   }
-  
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-   
+
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the CRC peripheral.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
+  * @brief  DeInitialize the CRC peripheral.
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 {
   /* Check the CRC handle allocation */
-  if(hcrc == NULL)
+  if (hcrc == NULL)
   {
     return HAL_ERROR;
   }
@@ -155,16 +134,28 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
   /* Check the parameters */
   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
 
+  /* Check the CRC peripheral state */
+  if (hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Reset IDR register content */
+  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
   /* DeInit the low level hardware */
   HAL_CRC_MspDeInit(hcrc);
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_RESET;
 
-  /* Release Lock */
+  /* Process unlocked */
   __HAL_UNLOCK(hcrc);
 
   /* Return function status */
@@ -173,45 +164,52 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 
 /**
   * @brief  Initializes the CRC MSP.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRC_MspInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
    */
 }
 
 /**
-  * @brief  DeInitializes the CRC MSP.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRC_MspDeInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
    */
 }
 
 /**
   * @}
-  */ 
+  */
 
-/** @addtogroup CRC_Exported_Functions_Group2
- *  @brief   Peripheral Control functions 
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief    management functions.
  *
-@verbatim  
-  ==============================================================================
+@verbatim
+ ===============================================================================
                       ##### Peripheral Control functions #####
-  ==============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Compute the 32-bit CRC value of 32-bit data buffer,
+      (+) compute the 32-bit CRC value of a 32-bit data buffer
           using combination of the previous CRC value and the new one.
-      (+) Compute the 32-bit CRC value of 32-bit data buffer,
+
+       [..]  or
+
+      (+) compute the 32-bit CRC value of a 32-bit data buffer
           independently of the previous CRC value.
 
 @endverbatim
@@ -219,106 +217,95 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
   */
 
 /**
-  * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
-  *         of the previous CRC value and the new one.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @param  pBuffer: pointer to the buffer containing the data to be computed
-  * @param  BufferLength: length of the buffer to be computed
-  * @retval 32-bit CRC
+  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer.
+  * @param  BufferLength input data buffer length (number of uint32_t words).
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
 {
-  uint32_t index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hcrc);
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
   /* Enter Data to the CRC calculator */
-  for(index = 0; index < BufferLength; index++)
+  for (index = 0U; index < BufferLength; index++)
   {
     hcrc->Instance->DR = pBuffer[index];
   }
+  temp = hcrc->Instance->DR;
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcrc);
-
   /* Return the CRC computed value */
-  return hcrc->Instance->DR;
+  return temp;
 }
 
 /**
-  * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
-  *         of the previous CRC value.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @param  pBuffer: Pointer to the buffer containing the data to be computed
-  * @param  BufferLength: Length of the buffer to be computed
-  * @retval 32-bit CRC
+  * @brief  Compute the 32-bit CRC value of a 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer.
+  * @param  BufferLength input data buffer length (number of uint32_t words).
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
 {
-  uint32_t index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hcrc); 
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_BUSY;
 
-  /* Reset CRC Calculation Unit */
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+  *  written in hcrc->Instance->DR) */
   __HAL_CRC_DR_RESET(hcrc);
 
-  /* Enter Data to the CRC calculator */
-  for(index = 0; index < BufferLength; index++)
+  /* Enter 32-bit input data to the CRC calculator */
+  for (index = 0U; index < BufferLength; index++)
   {
     hcrc->Instance->DR = pBuffer[index];
   }
+  temp = hcrc->Instance->DR;
 
   /* Change CRC peripheral state */
   hcrc->State = HAL_CRC_STATE_READY;
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcrc);
-
   /* Return the CRC computed value */
-  return hcrc->Instance->DR;
+  return temp;
 }
 
 /**
   * @}
-  */ 
+  */
 
-  
-/** @addtogroup CRC_Exported_Functions_Group3
- *  @brief   Peripheral State functions 
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ *  @brief    Peripheral State functions.
  *
-@verbatim   
-  ==============================================================================
+@verbatim
+ ===============================================================================
                       ##### Peripheral State functions #####
-  ==============================================================================  
+ ===============================================================================
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
+    This subsection permits to get in run-time the status of the peripheral.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Returns the CRC state.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
+  * @brief  Return the CRC handle state.
+  * @param  hcrc CRC handle
   * @retval HAL state
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
 {
+  /* Return CRC handle state */
   return hcrc->State;
 }
 
@@ -330,6 +317,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
   * @}
   */
 
+
 #endif /* HAL_CRC_MODULE_ENABLED */
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cryp.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cryp.c
index b4957729..d0f654ac 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cryp.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cryp.c
@@ -2,10 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_cryp.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   CRYP HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Cryptography (CRYP) peripheral:
   *           + Initialization and de-initialization functions
   *           + AES processing functions
@@ -20,16 +18,16 @@
                      ##### How to use this driver #####
   ==============================================================================
     [..]
-      The CRYP HAL driver can be used as follows:
+      The CRYP HAL driver can be used in CRYP IP as follows:
 
       (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
          (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
-         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
+         (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
              (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
              (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
              (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
-         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
-             (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
+             (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
              (+++) Configure and enable two DMA streams one for managing data transfer from
                  memory to peripheral (input stream) and another stream for managing data
                  transfer from peripheral to memory (output stream)
@@ -38,654 +36,446 @@
              (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the two DMA Streams. The output stream should have higher
                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
-    
-      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
-         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
-         (##) The key size: 128, 192 and 256. This parameter is relevant only for AES
-         (##) The encryption/decryption key. It's size depends on the algorithm
-              used for encryption/decryption
-         (##) The initialization vector (counter). It is not used ECB mode.
-    
+
+      (#)Initialize the CRYP according to the specified parameters :
+         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+         (##) The key size: 128, 192 or 256.
+         (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR.
+         (##) The initialization vector (counter). It is not used in ECB mode.
+         (##) The key buffer used for encryption/decryption.
+
       (#)Three processing (encryption/decryption) functions are available:
          (##) Polling mode: encryption and decryption APIs are blocking functions
               i.e. they process the data and wait till the processing is finished,
-              e.g. HAL_CRYP_AESCBC_Encrypt()
+              e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
          (##) Interrupt mode: encryption and decryption APIs are not blocking functions
               i.e. they process the data under interrupt,
-              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
+              e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
          (##) DMA mode: encryption and decryption APIs are not blocking functions
               i.e. the data transfer is ensured by DMA,
-              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
-    
+              e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
       (#)When the processing function is called at first time after HAL_CRYP_Init()
-         the CRYP peripheral is initialized and processes the buffer in input.
-         At second call, the processing function performs an append of the already
-         processed buffer.
-         When a new data block is to be processed, call HAL_CRYP_Init() then the
-         processing function.
-    
+         the CRYP peripheral is configured and processes the buffer in input.
+         At second call, no need to Initialize the CRYP, user have to get current configuration via
+         HAL_CRYP_GetConfig() API, then only  HAL_CRYP_SetConfig() is requested to set
+         new parametres, finally user can  start encryption/decryption.
+
        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
 
+    [..]
+      The cryptographic processor supports following standards:
+      (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
+         (##)64-bit data block processing
+         (##) chaining modes supported :
+             (+++)  Electronic Code Book(ECB)
+             (+++)  Cipher Block Chaining (CBC)
+         (##) keys length supported :64-bit, 128-bit and 192-bit.
+      (#) The advanced encryption standard (AES) supported  by CRYP1:
+         (##)128-bit data block processing
+         (##) chaining modes supported :
+             (+++)  Electronic Code Book(ECB)
+             (+++)  Cipher Block Chaining (CBC)
+             (+++)  Counter mode (CTR)
+         (##) keys length Supported :
+             (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
+
+  *** Callback registration ***
+  =============================================
+  [..]
+  The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
+  to register an interrupt callback.
+  [..]
+  Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
+    (+) InCpltCallback     :  Input FIFO transfer completed callback.
+    (+) OutCpltCallback    : Output FIFO transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CRYP MspInit.
+    (+) MspDeInitCallback  : CRYP MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+  [..]
+  Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) InCpltCallback     :  Input FIFO transfer completed callback.
+    (+) OutCpltCallback    : Output FIFO transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CRYP MspInit.
+    (+) MspDeInitCallback  : CRYP MspDeInit.
+  [..]
+  By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
+  all callbacks are set to the corresponding weak functions :
+  examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
+  keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
+  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+  in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
+  or @ref HAL_CRYP_Init() function.
+  [..]
+  When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+  
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+#if defined(CRYP)
+#ifdef HAL_CRYP_MODULE_ENABLED
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
-/** @defgroup CRYP CRYP
-  * @brief CRYP HAL module driver.
+/** @addtogroup CRYP
   * @{
   */
 
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-#if defined(STM32F215xx) || defined(STM32F217xx)
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @defgroup CRYP_Private_define CRYP Private define
+/** @addtogroup CRYP_Private_Defines
   * @{
   */
-#define CRYP_TIMEOUT_VALUE  1
+
+#define CRYP_TIMEOUT_KEYPREPARATION      82U         /*The latency of key preparation operation is 82 clock cycles.*/
+
+#define  CRYP_PHASE_READY                0x00000001U /*!< CRYP peripheral is ready for initialization. */
+#define  CRYP_PHASE_PROCESS              0x00000002U /*!< CRYP peripheral is in processing phase */
+
+#define CRYP_OPERATINGMODE_ENCRYPT       0x00000000U             /*!< Encryption mode   */
+#define CRYP_OPERATINGMODE_DECRYPT       CRYP_CR_ALGODIR         /*!< Decryption        */
+
 /**
   * @}
-  */ 
-  
+  */
+
+
 /* Private macro -------------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Macros
+  * @{
+  */
+
+#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |=  CRYP_CR_FFLUSH)
+
+
+/**
+  * @}
+  */
+
+/* Private struct -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @defgroup CRYP_Private_Functions_prototypes CRYP Private Functions prototypes
+/** @addtogroup CRYP_Private_Functions_prototypes
   * @{
-  */  
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize);
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize);
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
+  */
+
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction);
+static void CRYP_SetKey( CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+
 /**
   * @}
-  */ 
-  
-/* Private functions ---------------------------------------------------------*/
+  */
 
-/** @addtogroup CRYP_Private_Functions
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
   * @{
   */
 
 
-/**
-  * @brief  DMA CRYP Input Data process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
-     in the DMACR register */
-  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
-  
-  /* Call input data transfer complete callback */
-  HAL_CRYP_InCpltCallback(hcryp);
-}
+/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    CRYP  Initialization and Configuration functions.
+ *
+@verbatim
+  ========================================================================================
+     ##### Initialization, de-initialization and Set and Get configuration functions #####
+  ========================================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRYP
+      (+) DeInitialize the CRYP
+      (+) Initialize the CRYP MSP
+      (+) DeInitialize the CRYP MSP
+      (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
+          Parameters which are configured in This section are :
+          (++) Key size
+          (++) Data Type : 32,16, 8 or 1bit
+          (++) AlgoMode : for CRYP1 IP
+                 ECB and CBC in DES/TDES Standard
+                 ECB,CBC and CTR in AES Standard.
+      (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
 
-/**
-  * @brief  DMA CRYP Output Data process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit
-     in the DMACR register */
-  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-  
-  /* Disable CRYP */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* Change the CRYP state to ready */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Call output data transfer complete callback */
-  HAL_CRYP_OutCpltCallback(hcryp);
-}
 
-/**
-  * @brief  DMA CRYP communication error callback. 
-  * @param  hdma: DMA handle
-  * @retval None
+@endverbatim
+  * @{
   */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  hcryp->State= HAL_CRYP_STATE_READY;
-  HAL_CRYP_ErrorCallback(hcryp);
-}
 
-/**
-  * @brief  Writes the Key in Key registers. 
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Key: Pointer to Key buffer
-  * @param  KeySize: Size of Key
-  * @retval None
-  */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize)
-{
-  uint32_t keyaddr = (uint32_t)Key;
-  
-  switch(KeySize)
-  {
-  case CRYP_KEYSIZE_256B:
-    /* Key Initialisation */
-    hcryp->Instance->K0LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K0RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
-    break;
-  case CRYP_KEYSIZE_192B:
-    hcryp->Instance->K1LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K1RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
-    break;
-  case CRYP_KEYSIZE_128B:       
-    hcryp->Instance->K2LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K2RR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3LR = __REV(*(uint32_t*)(keyaddr));
-    keyaddr+=4;
-    hcryp->Instance->K3RR = __REV(*(uint32_t*)(keyaddr));
-    break;
-  default:
-    break;
-  }
-}
 
 /**
-  * @brief  Writes the InitVector/InitCounter in IV registers. 
+  * @brief  Initializes the CRYP according to the specified
+  *         parameters in the CRYP_ConfigTypeDef and creates the associated handle.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  InitVector: Pointer to InitVector/InitCounter buffer
-  * @param  IVSize: Size of the InitVector/InitCounter
-  * @retval None
+  * @retval HAL status
   */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize)
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t ivaddr = (uint32_t)InitVector;
-  
-  switch(IVSize)
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
   {
-  case CRYP_KEYSIZE_128B:
-    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
-    ivaddr+=4;
-    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
-    ivaddr+=4;
-    hcryp->Instance->IV1LR = __REV(*(uint32_t*)(ivaddr));
-    ivaddr+=4;
-    hcryp->Instance->IV1RR = __REV(*(uint32_t*)(ivaddr));
-    break;
-    /* Whatever key size 192 or 256, Init vector is written in IV0LR and IV0RR */
-  case CRYP_KEYSIZE_192B:
-    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
-    ivaddr+=4;
-    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
-    break;
-  case CRYP_KEYSIZE_256B:
-    hcryp->Instance->IV0LR = __REV(*(uint32_t*)(ivaddr));
-    ivaddr+=4;
-    hcryp->Instance->IV0RR = __REV(*(uint32_t*)(ivaddr));
-    break;
-  default:
-    break;
+    return HAL_ERROR;
   }
-}
 
-/**
-  * @brief  Process Data: Writes Input data in polling mode and read the output data
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Input: Pointer to the Input buffer
-  * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
-  * @param  Output: Pointer to the returned buffer
-  * @param  Timeout: Timeout value
-  *     * @retval None
-  */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  uint32_t i = 0;
-  uint32_t inputaddr  = (uint32_t)Input;
-  uint32_t outputaddr = (uint32_t)Output;
-  
-  for(i=0; (i < Ilength); i+=16)
+  /* Check parameters */
+  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
+  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
+  assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+  if(hcryp->State == HAL_CRYP_STATE_RESET)
   {
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
 
-    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
-    {    
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hcryp);
-        
-          return HAL_TIMEOUT;
-        }
-      }
+    hcryp->InCpltCallback  = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
+    hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback  */
+    hcryp->ErrorCallback   = HAL_CRYP_ErrorCallback;   /* Legacy weak ErrorCallback    */
+
+    if(hcryp->MspInitCallback == NULL)
+    {
+      hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit  */
     }
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
+
+    /* Init the low level hardware */
+    hcryp->MspInitCallback(hcryp);
+  }
+#else
+  if(hcryp->State == HAL_CRYP_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcryp->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_CRYP_MspInit(hcryp);
   }
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+  /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */
+  MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
+  /* Reset Error Code field */
+  hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Set the default CRYP phase */
+  hcryp->Phase = CRYP_PHASE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Process Data: Write Input data in polling mode. 
+  * @brief  De-Initializes the CRYP peripheral.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  Input: Pointer to the Input buffer
-  * @param  Ilength: Length of the Input buffer, must be a multiple of 8
-  * @param  Output: Pointer to the returned buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval None
-  */
-static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t tickstart = 0;   
-  
-  uint32_t i = 0;
-  uint32_t inputaddr  = (uint32_t)Input;
-  uint32_t outputaddr = (uint32_t)Output;
-  
-  for(i=0; (i < Ilength); i+=8)
+  /* Check the CRYP handle allocation */
+  if(hcryp == NULL)
   {
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */          
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
+    return HAL_ERROR;
   }
+
+  /* Set the default CRYP phase */
+  hcryp->Phase = CRYP_PHASE_READY;
+
+  /* Reset CrypInCount and CrypOutCount */
+  hcryp->CrypInCount = 0;
+  hcryp->CrypOutCount = 0;
+
+  /* Disable the CRYP peripheral clock */
+  __HAL_CRYP_DISABLE(hcryp);
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+  if(hcryp->MspDeInitCallback == NULL)
+  {
+    hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+  /* DeInit the low level hardware */
+  hcryp->MspDeInitCallback(hcryp);
+
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  HAL_CRYP_MspDeInit(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Set the DMA configuration and start the DMA transfer
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  * @brief  Configure the CRYP according to the specified
+  *         parameters in the CRYP_ConfigTypeDef
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  pConf: pointer to a CRYP_ConfigTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  inputaddr: address of the Input buffer
-  * @param  Size: Size of the Input buffer, must be a multiple of 16.
-  * @param  outputaddr: address of the Output buffer
-  * @retval None
+  * @retval HAL status
   */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
 {
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-  
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DR, Size/4);
-  
-  /* Enable In DMA request */
-  hcryp->Instance->DMACR = (CRYP_DMACR_DIEN);
-  
-  /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size/4);
-  
-  /* Enable Out DMA request */
-  hcryp->Instance->DMACR |= CRYP_DMACR_DOEN;
- 
+  /* Check the CRYP handle allocation */
+  if((hcryp == NULL)|| (pConf == NULL) )
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
+  assert_param(IS_CRYP_DATATYPE(pConf->DataType));
+  assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Set  CRYP parameters  */
+    hcryp->Init.DataType     = pConf->DataType;
+    hcryp->Init.pKey         = pConf->pKey;
+    hcryp->Init.Algorithm    = pConf->Algorithm;
+    hcryp->Init.KeySize      = pConf->KeySize;
+    hcryp->Init.pInitVect    = pConf->pInitVect;
+
+    /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type, AlgoMode and operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Reset Error Code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Set the default CRYP phase */
+    hcryp->Phase = CRYP_PHASE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
 }
 
 /**
-  * @brief  Sets the CRYP peripheral in DES ECB mode.
+  * @brief  Get CRYP Configuration parameters in associated handle.
+  * @param  pConf: pointer to a CRYP_ConfigTypeDef structure
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  Direction: Encryption or decryption
-  * @retval None
+  * @retval HAL status
   */
-static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf )
 {
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  /* Check the CRYP handle allocation */
+  if((hcryp == NULL)|| (pConf == NULL) )
   {
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_ECB | Direction);
-    
-    /* Set the key */
-    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
-    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
+    return HAL_ERROR;
   }
-}
 
-/**
-  * @brief  Sets the CRYP peripheral in DES CBC mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Direction: Encryption or decryption
-  * @retval None
-  */
-static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_DES_CBC | Direction);
-    
-    /* Set the key */
-    hcryp->Instance->K1LR = __REV(*(uint32_t*)(hcryp->Init.pKey));
-    hcryp->Instance->K1RR = __REV(*(uint32_t*)(hcryp->Init.pKey+4));
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-}
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
 
-/**
-  * @brief  Sets the CRYP peripheral in TDES ECB mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Direction: Encryption or decryption
-  * @retval None
-  */
-static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_ECB | Direction);
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-}
+    /* Process locked */
+    __HAL_LOCK(hcryp);
 
-/**
-  * @brief  Sets the CRYP peripheral in TDES CBC mode
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Direction: Encryption or decryption
-  * @retval None
-  */
-static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction)
-{
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Set the CRYP peripheral in AES CBC mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_TDES_CBC | Direction);
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, CRYP_KEYSIZE_192B);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_256B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-}
+    /* Get  CRYP parameters  */
+    pConf->DataType        = hcryp->Init.DataType;
+    pConf->pKey            = hcryp->Init.pKey;
+    pConf->Algorithm       = hcryp->Init.Algorithm;
+    pConf->KeySize         = hcryp->Init.KeySize ;
+    pConf->pInitVect       = hcryp->Init.pInitVect;
 
-/**
-  * @}
-  */ 
-  
- /* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRYP_Exported_Functions
-  * @{
-  */ 
-  
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRYP according to the specified parameters 
-          in the CRYP_InitTypeDef and creates the associated handle
-      (+) DeInitialize the CRYP peripheral
-      (+) Initialize the CRYP MSP
-      (+) DeInitialize CRYP MSP 
- 
-@endverbatim
-  * @{
-  */
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
 
-/**
-  * @brief  Initializes the CRYP according to the specified
-  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{ 
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
-  {
-    return HAL_ERROR;
-  }
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
 
-  /* Check the parameters */
-  assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
-  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-    
-  if(hcryp->State == HAL_CRYP_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    hcryp->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_CRYP_MspInit(hcryp);
+    /* Return function status */
+    return HAL_OK;
   }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set the key size and data type*/
-  CRYP->CR = (uint32_t) (hcryp->Init.KeySize | hcryp->Init.DataType);
-  
-  /* Reset CrypInCount and CrypOutCount */
-  hcryp->CrypInCount = 0;
-  hcryp->CrypOutCount = 0;
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Set the default CRYP phase */
-  hcryp->Phase = HAL_CRYP_PHASE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the CRYP peripheral. 
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check the CRYP handle allocation */
-  if(hcryp == NULL)
+  else
   {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
     return HAL_ERROR;
   }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set the default CRYP phase */
-  hcryp->Phase = HAL_CRYP_PHASE_READY;
-  
-  /* Reset CrypInCount and CrypOutCount */
-  hcryp->CrypInCount = 0;
-  hcryp->CrypOutCount = 0;
-  
-  /* Disable the CRYP Peripheral Clock */
-  __HAL_CRYP_DISABLE(hcryp);
-  
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_CRYP_MspDeInit(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hcryp);
-
-  /* Return function status */
-  return HAL_OK;
 }
-
 /**
   * @brief  Initializes the CRYP MSP.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
@@ -694,6 +484,9 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
   */
 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_MspInit could be implemented in the user file
    */
@@ -707,3104 +500,1967 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
   */
 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_CRYP_MspDeInit could be implemented in the user file
    */
 }
 
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions 
- *  @brief   processing functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### AES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using AES-128/192/256 using chaining modes
-      (+) Decrypt cyphertext using AES-128/192/256 using chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User CRYP Callback
+  *         To be used instead of the weak predefined callback
+  * @param hcryp cryp handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
+  *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
 {
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
+  HAL_StatusTypeDef status = HAL_OK;
 
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  if(pCallback == NULL)
   {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
 
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{  
-  /* Process Locked */
+    return HAL_ERROR;
+  }
+  /* Process locked */
   __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES ECB mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+    switch (CallbackID)
     {
-      return HAL_TIMEOUT;
+    case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+      hcryp->InCpltCallback = pCallback;
+      break;
+
+    case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+      hcryp->OutCpltCallback = pCallback;
+      break;
+
+    case HAL_CRYP_ERROR_CB_ID :
+      hcryp->ErrorCallback = pCallback;
+      break;
+
+    case HAL_CRYP_MSPINIT_CB_ID :
+      hcryp->MspInitCallback = pCallback;
+      break;
+
+    case HAL_CRYP_MSPDEINIT_CB_ID :
+      hcryp->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
     }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-   uint32_t tickstart = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
+  }
+  else if(hcryp->State == HAL_CRYP_STATE_RESET)
   {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get tick */ 
-    tickstart = HAL_GetTick();
-
-    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */          
-          __HAL_UNLOCK(hcryp);
-        
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    
-    /* Disable CRYP */
-    __HAL_CRYP_DISABLE(hcryp);
-    
-    /* Reset the ALGOMODE bits*/
-    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-    
-    /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get tick */ 
-    tickstart = HAL_GetTick();
-
-    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    
-    /* Reset the ALGOMODE bits*/
-    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-    
-    /* Set the CRYP peripheral in AES CBC decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES CTR mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Locked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {      
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Locked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t tickstart = 0;
-
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-  /* Check if initialization phase has already been performed */
-  if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-  {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get tick */ 
-    tickstart = HAL_GetTick();
-
-    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
-      {
-        /* Change state */
-        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hcryp);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Reset the ALGOMODE bits*/
-    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-    
-    /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-     
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-
-  uint32_t tickstart = 0;   
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES Key mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
-      {
-        /* Change state */
-        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hcryp);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-    
-      /* Reset the ALGOMODE bits*/
-      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-    
-      /* Set the CRYP peripheral in AES CBC decryption mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
-    
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-    
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    hcryp->pCrypOutBuffPtr += 16;
-    hcryp->CrypOutCount -= 16;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-     
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-       /* Set the phase */
-       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-     }
-     /* Set the input and output addresses and start DMA transfer */ 
-     CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-     
-     /* Process Unlocked */
-     __HAL_UNLOCK(hcryp);
-     
-     /* Return function status */
-     return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-       /* Set the phase */
-       hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t tickstart = 0;   
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-    
-    /* Set the CRYP peripheral in AES Key mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
-      {
-        /* Change state */
-        hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hcryp);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Reset the ALGOMODE bits*/
-    CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-    
-    /* Set the CRYP peripheral in AES ECB decryption mode */
-    __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR);
-    
-    /* Flush FIFO */
-    __HAL_CRYP_FIFO_FLUSH(hcryp);
-    
-     /* Set the phase */
-     hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-     
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-     /* Process Unlocked */
-     __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t tickstart = 0;   
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES Key mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_KEY | CRYP_CR_ALGODIR);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE(hcryp);
-      
-      /* Get tick */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
-      {
-        /* Check for the Timeout */
-        if((HAL_GetTick() - tickstart ) > CRYP_TIMEOUT_VALUE)
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-      
-      /* Reset the ALGOMODE bits*/
-      CRYP->CR &= (uint32_t)(~CRYP_CR_ALGOMODE);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey, hcryp->Init.KeySize);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR | CRYP_CR_ALGODIR);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect, CRYP_KEYSIZE_128B);
-      
-      /* Flush FIFO */
-      __HAL_CRYP_FIFO_FLUSH(hcryp);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-
-/**
-  * @}
-  */
-  
-/** @defgroup CRYP_Exported_Functions_Group3 DES processing functions 
- *  @brief   processing functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### DES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using DES using ECB or CBC chaining modes
-      (+) Decrypt cyphertext using ECB or CBC chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in DES ECB encryption mode */
-  CRYP_SetDESECBMode(hcryp, 0);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in DES ECB decryption mode */
-  CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in DES CBC encryption mode */
-  CRYP_SetDESCBCMode(hcryp, 0);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in DES CBC decryption mode */
-  CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using IT.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES ECB encryption mode */
-    CRYP_SetDESECBMode(hcryp, 0);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+    switch (CallbackID)
+    {
+    case HAL_CRYP_MSPINIT_CB_ID :
+      hcryp->MspInitCallback = pCallback;
+      break;
+
+    case HAL_CRYP_MSPDEINIT_CB_ID :
+      hcryp->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
   }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+  else
   {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an CRYP Callback
+  *         CRYP callabck is redirected to the weak predefined callback
+  * @param hcryp cryp handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
+  *          @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
+  *          @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hcryp);
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    switch (CallbackID)
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
+    case HAL_CRYP_INPUT_COMPLETE_CB_ID :
+      hcryp->InCpltCallback = HAL_CRYP_InCpltCallback;  /* Legacy weak  InCpltCallback  */
+      break;
+
+    case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
+      hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback;         /* Legacy weak OutCpltCallback       */
+      break;
+
+    case HAL_CRYP_ERROR_CB_ID :
+      hcryp->ErrorCallback = HAL_CRYP_ErrorCallback;           /* Legacy weak ErrorCallback        */
+      break;
+
+    case HAL_CRYP_MSPINIT_CB_ID :
+      hcryp->MspInitCallback = HAL_CRYP_MspInit;
+      break;
+
+    case HAL_CRYP_MSPDEINIT_CB_ID :
+      hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+      break;
+
+    default :
+      /* Update the error code */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
     }
   }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+  else if(hcryp->State == HAL_CRYP_STATE_RESET)
   {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+    switch (CallbackID)
     {
-      /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
+    case HAL_CRYP_MSPINIT_CB_ID :
+      hcryp->MspInitCallback = HAL_CRYP_MspInit;
+      break;
+
+    case HAL_CRYP_MSPDEINIT_CB_ID :
+      hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
+      break;
+
+    default :
+      /* Update the error code */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
     }
   }
-  
-  /* Return function status */
-  return HAL_OK;
+  else
+  {
+    /* Update the error code */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcryp);
+
+  return status;
 }
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Exported_Functions_Group2  Encrypt Decrypt functions
+ *  @brief   CRYP processing functions.
+ *
+@verbatim
+  ==============================================================================
+                      ##### Encrypt Decrypt  functions #####
+  ==============================================================================
+    [..]  This section provides API allowing to Encrypt/Decrypt Data following
+          Standard DES/TDES or AES, and Algorithm configured by the user:
+      (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
+           (++)  Electronic Code Book(ECB)
+           (++) Cipher Block Chaining (CBC)
+      (+) Standard AES  supported by CRYP1 IP , list of Algorithm supported:
+           (++) Electronic Code Book(ECB)
+           (++) Cipher Block Chaining (CBC)
+           (++) Counter mode (CTR)
+           (++) Cipher Block Chaining (CBC)
+           (++) Counter mode (CTR)
+    [..]  Three processing functions are available:
+      (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
+      (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
+      (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
+
+@endverbatim
+  * @{
+  */
+
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
+  * @brief  Encryption mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer in word.
+  * @param  Output: Pointer to the output buffer(ciphertext)
+  * @param  Timeout: Specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
+  uint32_t algo;
+  HAL_StatusTypeDef status;
+
   if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES CBC encryption mode */
-    CRYP_SetDESCBCMode(hcryp, 0);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
+      hcryp->Size = Size * 4U;
     }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+    else
     {
-      /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
+      hcryp->Size = Size;
+    }
+
+    /* Set Encryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+    /* algo get algorithm selected */
+    algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+
+      /*Set Initialization Vector (IV)*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Statrt DES/TDES encryption process */
+      status = CRYP_TDES_Process(hcryp,Timeout);
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      /* AES encryption */
+      status = CRYP_AES_Encrypt(hcryp, Timeout);
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status = HAL_ERROR;
+      break;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
       hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
     }
   }
-  
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
   /* Return function status */
-  return HAL_OK;
+  return status ;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using IT.
+  * @brief  Decryption mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer in word.
+  * @param  Output: Pointer to the output buffer(plaintext)
+  * @param  Timeout: Specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
+  HAL_StatusTypeDef status;
+  uint32_t algo;
+
   if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES ECB decryption mode */
-    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
+      hcryp->Size = Size * 4U;
     }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+    else
     {
-      /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
+      hcryp->Size = Size;
+    }
+
+    /* Set Decryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+    /* algo get algorithm selected */
+    algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+
+      /*Set Initialization Vector (IV)*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Start DES/TDES decryption process */
+      status = CRYP_TDES_Process(hcryp, Timeout);
+
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      /* AES decryption */
+      status = CRYP_AES_Decrypt(hcryp, Timeout);
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status = HAL_ERROR;
+      break;
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Change the CRYP peripheral state */
       hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
     }
   }
-  
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
+  * @brief  Encryption in interrupt mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer in word
+  * @param  Output: Pointer to the output buffer(ciphertext)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
+  uint32_t algo;
+  HAL_StatusTypeDef status;
+
   if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES CBC decryption mode */
-    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
+      hcryp->Size = Size * 4U;
     }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+    else
     {
-      /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
+      hcryp->Size = Size;
+    }
+
+    /* Set encryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+    /* algo get algorithm selected */
+    algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+      /* Set the Initialization Vector*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Enable interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+      /* Enable CRYP to start DES/TDES process*/
+      __HAL_CRYP_ENABLE(hcryp);
+
+      status = HAL_OK;
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      status = CRYP_AES_Encrypt_IT(hcryp);
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status =  HAL_ERROR;
+      break;
     }
   }
-  
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status =  HAL_ERROR;
+  }
+
   /* Return function status */
-  return HAL_OK;
+  return status ;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
+  * @brief  Decryption in itnterrupt mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer in word.
+  * @param  Output: Pointer to the output buffer(plaintext)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  uint32_t algo;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES ECB encryption mode */
-    CRYP_SetDESECBMode(hcryp, 0);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set decryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT);
+
+    /* algo get algorithm selected */
+    algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+
+      /* Set the Initialization Vector*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Enable interrupts */
+      __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+      /* Enable CRYP and start DES/TDES process*/
+      __HAL_CRYP_ENABLE(hcryp);
+
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      /* AES decryption */
+      status = CRYP_AES_Decrypt_IT(hcryp);
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status = HAL_ERROR;
+      break;
+    }
   }
   else
   {
-    return HAL_ERROR;   
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
   }
+
+  /* Return function status */
+  return status;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
+  * @brief  Encryption in DMA mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (plaintext)
+  * @param  Size: Length of the plaintext buffer in word.
+  * @param  Output: Pointer to the output buffer(ciphertext)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  uint32_t algo;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES CBC encryption mode */
-    CRYP_SetDESCBCMode(hcryp, 0);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
 
-/**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
+    /* Process locked */
     __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES ECB decryption mode */
-    CRYP_SetDESECBMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set encryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
+
+    /* algo get algorithm selected */
+    algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+
+      /* Set the Initialization Vector*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Start DMA process transfer for DES/TDES */
+      CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+      /* Set the Initialization Vector IV */
+      if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+        hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+        hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+      }
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Start DMA process transfer for AES */
+      CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status =  HAL_ERROR;
+      break;
+    }
   }
   else
   {
-    return HAL_ERROR;   
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status =  HAL_ERROR;
   }
+
+  /* Return function status */
+  return status;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
+  * @brief  Decryption in DMA mode.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @param  Input: Pointer to the input buffer (ciphertext )
+  * @param  Size: Length of the plaintext buffer in word
+  * @param  Output: Pointer to the output buffer(plaintext)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  uint32_t algo;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(hcryp->State == HAL_CRYP_STATE_READY)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
+    /* Change state Busy */
     hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in DES CBC decryption mode */
-    CRYP_SetDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /*  Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
+    hcryp->CrypInCount = 0U;
+    hcryp->CrypOutCount = 0U;
+    hcryp->pCrypInBuffPtr = Input;
+    hcryp->pCrypOutBuffPtr = Output;
+
+    /*  Calculate Size parameter in Byte*/
+    if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
+    {
+      hcryp->Size = Size * 4U;
+    }
+    else
+    {
+      hcryp->Size = Size;
+    }
+
+    /* Set decryption operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
+
+    /* algo get algorithm selected */
+    algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
+
+    switch(algo)
+    {
+    case CRYP_DES_ECB:
+    case CRYP_DES_CBC:
+    case CRYP_TDES_ECB:
+    case CRYP_TDES_CBC:
+
+      /*Set Key */
+      hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+      hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+      if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+        hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+        hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+        hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
+      }
+
+      /* Set the Initialization Vector*/
+      if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+      {
+        hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+        hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+      }
+
+      /* Flush FIFO */
+      HAL_CRYP_FIFO_FLUSH(hcryp);
+
+      /* Set the phase */
+      hcryp->Phase = CRYP_PHASE_PROCESS;
+
+      /* Start DMA process transfer for DES/TDES */
+      CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+      break;
+
+    case CRYP_AES_ECB:
+    case CRYP_AES_CBC:
+    case CRYP_AES_CTR:
+
+      /* AES decryption */
+      status = CRYP_AES_Decrypt_DMA(hcryp);
+      break;
+
+    default:
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
+      status =  HAL_ERROR;
+      break;
+    }
   }
   else
   {
-    return HAL_ERROR;   
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    status = HAL_ERROR;
   }
+
+  /* Return function status */
+  return status;
 }
 
 /**
   * @}
   */
 
-/** @defgroup CRYP_Exported_Functions_Group4 TDES processing functions 
- *  @brief   processing functions. 
+/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
+ *  @brief    CRYP IRQ handler.
  *
-@verbatim   
+@verbatim
   ==============================================================================
-                      ##### TDES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
-      (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
+                ##### CRYP IRQ handler management #####
+  ==============================================================================
+[..]  This section provides CRYP IRQ handler and callback functions.
+      (+) HAL_CRYP_IRQHandler CRYP interrupt request
+      (+) HAL_CRYP_InCpltCallback input data transfer complete callback
+      (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
+      (+) HAL_CRYP_ErrorCallback  CRYP error callback
+      (+) HAL_CRYP_GetState return the CRYP state
+      (+) HAL_CRYP_GetError return the CRYP error code
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @brief  This function handles cryptographic interrupt request.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
+  * @retval None
   */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
 {
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
   
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in TDES ECB encryption mode */
-  CRYP_SetTDESECBMode(hcryp, 0);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
+  if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0U))
   {
-    return HAL_TIMEOUT;
+    if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+    {
+      CRYP_TDES_IT(hcryp); /* DES or TDES*/
+    }
+    else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+    {
+      CRYP_AES_IT(hcryp); /*AES*/
+    }
+    else
+    {
+      /* Nothing to do */
+    }
   }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @brief  Return the CRYP error code.
+  * @param  hcryp : pointer to a CRYP_HandleTypeDef structure that contains
+  *                 the configuration information for the  CRYP IP
+  * @retval CRYP error code
+  */
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->ErrorCode;
+}
+
+/**
+  * @brief  Returns the CRYP state.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
+  *         the configuration information for CRYP module.
+  * @retval HAL state
   */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in TDES ECB decryption mode */
-  CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Cypher Data and Get Plain Data */
-  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+{
+  return hcryp->State;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
+  * @brief  Input FIFO transfer completed callback.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
+  *         the configuration information for CRYP module.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
+__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
 {
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in TDES CBC encryption mode */
-  CRYP_SetTDESCBCMode(hcryp, 0);
-  
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Plain Data and Get Cypher Data */
-  if(CRYP_ProcessData2Words(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_InCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Output FIFO transfer completed callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval None
+  */
+__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_OutCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  CRYP error callback.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval None
+  */
+ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcryp);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CRYP_ErrorCallback could be implemented in the user file
+   */
 }
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup CRYP_Private_Functions
+  * @{
+  */
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
+  * @brief  Encryption in ECB/CBC Algorithm with DES/TDES standard.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Timeout: Specify Timeout value  
+  * @param  Timeout: Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set CRYP peripheral in TDES CBC decryption mode */
-  CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-  
+
+  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint16_t incount; /* Temporary CrypInCount Value */ 
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+
   /* Enable CRYP */
   __HAL_CRYP_ENABLE(hcryp);
-  
-  /* Write Cypher Data and Get Plain Data */
-  if(CRYP_ProcessData2Words(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
+  /*Temporary CrypOutCount Value*/
+  outcount = hcryp->CrypOutCount;
+
+  /*Start processing*/
+  while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
+  {  
+    /* Temporary CrypInCount Value */ 
+    incount = hcryp->CrypInCount;   
+    /* Write plain data and get cipher data */
+    if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+    {
+      /* Write the input block in the IN FIFO */
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+    }
+
+    /* Wait for OFNE flag to be raised */
+    if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+    {
+      /* Disable the CRYP peripheral clock */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Change state & errorCode*/
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+      /*Call registered error callback*/
+      hcryp->ErrorCallback(hcryp);
+#else
+      /*Call legacy weak error callback*/
+      HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+    }
+
+    /*Temporary CrypOutCount Value*/
+    outcount = hcryp->CrypOutCount;
+
+    if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+    {
+      /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
+      temp = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      hcryp->CrypOutCount++;
+      temp = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      hcryp->CrypOutCount++;
+    }
+    /*Temporary CrypOutCount Value*/
+    outcount = hcryp->CrypOutCount;
   }
-  
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
   /* Change the CRYP state */
   hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
+  * @brief  CRYP block input/output data handling under interruption with DES/TDES standard.
+  * @note   The function is called under interruption only, once
+  *         interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  *         the configuration information for CRYP module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES ECB encryption mode */
-    CRYP_SetTDESECBMode(hcryp, 0);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+  uint32_t temp;  /* Temporary CrypOutBuff */
+
+  if(hcryp->State == HAL_CRYP_STATE_BUSY)
   {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
+    if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U))
+
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
+      /* Write input block in the IN FIFO */
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+
+      if(hcryp->CrypInCount ==  (hcryp->Size/4U))
+      {
+        /* Disable interruption */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
+        /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy weak Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
     }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+    if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U))
     {
-      /* Disable IT */
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call the Output data transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
+      /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
+      temp = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      hcryp->CrypOutCount++;
+      temp = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      hcryp->CrypOutCount++;
+      if(hcryp->CrypOutCount ==  (hcryp->Size/4U))
+      {
+        /* Disable interruption */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+        /* Disable CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+        /*Call registered Output complete callback*/
+        hcryp->OutCpltCallback(hcryp);
+#else
+        /*Call legacy weak Output complete callback*/
+        HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+      }
     }
   }
-  
-  /* Return function status */
-  return HAL_OK;
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy weak error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
+  * @brief  Encryption in ECB/CBC & CTR Algorithm with AES Standard
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout: specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES CBC encryption mode */
-    CRYP_SetTDESCBCMode(hcryp, 0);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+
+  /*  Set the Key*/
+  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
   {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
+    /* Set the Initialization Vector*/
+    hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+    hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+    hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
   }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+   /*Temporary CrypOutCount Value*/
+  outcount = hcryp->CrypOutCount;
+  
+  while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
   {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-        
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
+    /* Write plain Ddta and get cipher data */
+    CRYP_AES_ProcessData(hcryp,Timeout);
+    /*Temporary CrypOutCount Value*/
+    outcount = hcryp->CrypOutCount;
   }
-  
+
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode.
+  * @brief  Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
+
+  /*  Set the Key*/
+  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES ECB decryption mode */
-    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Enable Interrupts */
+    /* Set the Initialization Vector*/
+    hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+    hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+    hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+  }
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  if(hcryp->Size != 0U)
+  {
+    /* Enable interrupts */
     __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
+
     /* Enable CRYP */
     __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
   }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
+  else
   {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
-      __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
-      hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
   }
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pPlainData: Pointer to the plaintext buffer
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure
+  * @param  Timeout: Specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout )
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if(hcryp->State == HAL_CRYP_STATE_READY)
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+
+  /*  Key preparation for ECB/CBC */
+  if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES CBC decryption mode */
-    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
-    
+    /* change ALGOMODE to key preparation for decryption*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
+
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
     /* Enable CRYP */
     __HAL_CRYP_ENABLE(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI))
-  {
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    /* Write the Input block in the IN FIFO */
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    hcryp->Instance->DR = *(uint32_t*)(inputaddr);
-
-    hcryp->pCrypInBuffPtr += 8;
-    hcryp->CrypInCount -= 8;
-    if(hcryp->CrypInCount == 0)
-    {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-      /* Call the Input data transfer complete callback */
-      HAL_CRYP_InCpltCallback(hcryp);
-    }
-  }
-  else if(__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI))
-  {
-    outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = hcryp->Instance->DOUT;
-
-    hcryp->pCrypOutBuffPtr += 8;
-    hcryp->CrypOutCount -= 8;
-    if(hcryp->CrypOutCount == 0)
+
+    /* Wait for BUSY flag to be raised */
+    if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
     {
-      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-      /* Disable CRYP */
+      /* Disable the CRYP peripheral clock */
       __HAL_CRYP_DISABLE(hcryp);
-      /* Process Unlocked */
-      __HAL_UNLOCK(hcryp);
-      /* Change the CRYP state */
+
+      /* Change state */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
       hcryp->State = HAL_CRYP_STATE_READY;
-      /* Call Input transfer complete callback */
-      HAL_CRYP_OutCpltCallback(hcryp);
-    }
-  }
-  
-  /* Return function status */
-  return HAL_OK;
-}
 
-/**
-  * @brief  Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES ECB encryption mode */
-    CRYP_SetTDESECBMode(hcryp, 0);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+    /* Turn back to ALGOMODE of the configuration */
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
   }
-  else
+  else  /*Algorithm CTR */
   {
-    return HAL_ERROR;   
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
   }
-}
 
-/**
-  * @brief  Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  /* Set IV */
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES CBC encryption mode */
-    CRYP_SetTDESCBCMode(hcryp, 0);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+    /* Set the Initialization Vector*/
+    hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+    hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+    hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
   }
-  else
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /*Temporary CrypOutCount Value*/
+  outcount = hcryp->CrypOutCount;
+
+  while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U)))
   {
-    return HAL_ERROR;   
+    /* Write plain data and get cipher data */
+    CRYP_AES_ProcessData(hcryp,Timeout);
+    /*Temporary CrypOutCount Value*/
+    outcount = hcryp->CrypOutCount;
   }
-}
 
+  /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+
+  /* Change the CRYP state */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
 /**
-  * @brief  Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pCypherData: Pointer to the cyphertext buffer
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  __IO uint32_t count = 0U;
+
+  /*  Key preparation for ECB/CBC */
+  if (hcryp->Init.Algorithm != CRYP_AES_CTR)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES ECB decryption mode */
-    CRYP_SetTDESECBMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+    /* change ALGOMODE to key preparation for decryption*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
+
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+
+    /* Wait for BUSY flag to be raised */
+    count = CRYP_TIMEOUT_KEYPREPARATION;
+    do
+    {
+      count-- ;
+      if(count == 0U)
+      {
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+    /* Turn back to ALGOMODE of the configuration */
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
+  }
+  else  /*Algorithm CTR */
+  {
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+  }
+
+  /* Set IV */
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  {
+    /* Set the Initialization Vector*/
+    hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+    hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+    hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+  }
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+  if(hcryp->Size != 0U)
+  {
+    /* Enable interrupts */
+    __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
+
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
   }
   else
   {
-    return HAL_ERROR;   
+    /* Process locked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
   }
+  /* Return function status */
+  return HAL_OK;
 }
-
 /**
-  * @brief  Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
+  * @brief  Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 8
-  * @param  pPlainData: Pointer to the plaintext buffer
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
+static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  
-  if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS))
+  __IO uint32_t count = 0U;
+
+  /*  Key preparation for ECB/CBC */
+  if (hcryp->Init.Algorithm != CRYP_AES_CTR)
   {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set CRYP peripheral in TDES CBC decryption mode */
-    CRYP_SetTDESCBCMode(hcryp, CRYP_CR_ALGODIR);
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
+    /* change ALGOMODE to key preparation for decryption*/
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY );
+
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+    /* Enable CRYP */
+    __HAL_CRYP_ENABLE(hcryp);
+
+    /* Wait for BUSY flag to be raised */
+    count = CRYP_TIMEOUT_KEYPREPARATION;
+    do
+    {
+      count-- ;
+      if(count == 0U)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+    while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+
+    /* Turn back to ALGOMODE of the configuration */
+    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm );
+  }
+  else  /*Algorithm CTR */
+  {
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+  }
+
+  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  {
+    /* Set the Initialization Vector*/
+    hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1);
+    hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2);
+    hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3);
+  }
+  /* Set the phase */
+  hcryp->Phase = CRYP_PHASE_PROCESS;
+
+  if(hcryp->Size != 0U)
+  {
+    /* Set the input and output addresses and start DMA transfer */
+    CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
   }
   else
   {
-    return HAL_ERROR;   
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Change the CRYP state */
+    hcryp->State = HAL_CRYP_STATE_READY;
   }
+
+  /* Return function status */
+  return HAL_OK;
 }
 
+
 /**
-  * @}
+  * @brief  DMA CRYP input data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
   */
+static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
 
-/** @defgroup CRYP_Exported_Functions_Group5 DMA callback functions 
- *  @brief   DMA callback functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### DMA callback functions  #####
-  ==============================================================================  
-    [..]  This section provides DMA callback functions:
-      (+) DMA Input data transfer complete
-      (+) DMA Output data transfer complete
-      (+) DMA error
+  /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
+  in the DMACR register */
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
 
-@endverbatim
-  * @{
+  /* Call input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy weak Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA CRYP output data process complete callback.
+  * @param  hdma: DMA handle
+  * @retval None
   */
+static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
+{
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+
+  /* Disable the DMA transfer for output FIFO */
+  hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
+
+  /* Change the CRYP state to ready */
+  hcryp->State = HAL_CRYP_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcryp);
+
+    /* Disable CRYP */
+  __HAL_CRYP_DISABLE(hcryp);
+  
+  
+  /* Call output data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+  /*Call registered Output complete callback*/
+  hcryp->OutCpltCallback(hcryp);
+#else
+  /*Call legacy weak Output complete callback*/
+  HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+}
 
 /**
-  * @brief  Input FIFO transfer completed callbacks.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
+  * @brief  DMA CRYP communication error callback.
+  * @param  hdma: DMA handle
   * @retval None
   */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
+static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYP_InCpltCallback could be implemented in the user file
-   */ 
+  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+  /* Change the CRYP peripheral state */
+  hcryp->State= HAL_CRYP_STATE_READY;
+
+  /* DMA error code field */
+  hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+  /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  hcryp->ErrorCallback(hcryp);
+#else
+  /*Call legacy weak error callback*/
+  HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  Output FIFO transfer completed callbacks.
+  * @brief  Set the DMA configuration and start the DMA transfer
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
+  * @param  inputaddr: address of the input buffer
+  * @param  Size: size of the input buffer, must be a multiple of 16.
+  * @param  outputaddr: address of the output buffer
   * @retval None
   */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
+static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYP_OutCpltCallback could be implemented in the user file
-   */
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+  /* Set the DMA input error callback */
+  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+  /* Set the CRYP DMA transfer complete callback */
+  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
+
+  /* Set the DMA output error callback */
+  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
+
+  /* Enable CRYP */
+  __HAL_CRYP_ENABLE(hcryp);
+
+  /* Enable the input DMA Stream */
+  if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK)
+  {
+    /* DMA error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+    /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy weak error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);                                                                           
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+
+  /* Enable the output DMA Stream */
+  if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK)
+  {
+    /* DMA error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+
+    /* Call error callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy weak error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+  /* Enable In/Out DMA request */
+  hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
 }
 
 /**
-  * @brief  CRYP error callbacks.
+  * @brief  Process Data: Write Input data in polling mode and used in AES functions.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
+  * @param  Timeout: Specify Timeout value
   * @retval None
   */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
+static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYP_ErrorCallback could be implemented in the user file
-   */ 
+
+  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint16_t incount;  /* Temporary CrypInCount Value */
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
+  
+  /*Temporary CrypOutCount Value*/
+  incount = hcryp->CrypInCount; 
+
+  if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < ((hcryp->Size)/4U)))
+  {
+    /* Write the input block in the IN FIFO */
+    hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+    hcryp->CrypInCount++;
+    hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+    hcryp->CrypInCount++;
+    hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+    hcryp->CrypInCount++;
+    hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+    hcryp->CrypInCount++;
+  }
+
+  /* Wait for OFNE flag to be raised */
+  if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
+  {
+    /* Disable the CRYP peripheral clock */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Change state & error code*/
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy weak error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+  /*Temporary CrypOutCount Value*/
+  outcount = hcryp->CrypOutCount;
+
+  if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < ((hcryp->Size)/4U)))
+  {
+    /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
+    temp  = hcryp->Instance->DOUT;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+    hcryp->CrypOutCount++;
+    temp  = hcryp->Instance->DOUT;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+    hcryp->CrypOutCount++;
+    temp  = hcryp->Instance->DOUT;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+    hcryp->CrypOutCount++;
+    temp  = hcryp->Instance->DOUT;
+    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+    hcryp->CrypOutCount++;
+  }
 }
 
 /**
-  * @}
+  * @brief  Handle CRYP block input/output data handling under interruption.
+  * @note   The function is called under interruption only, once
+  *         interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @retval HAL status
   */
+static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
+{
+  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint16_t incount; /* Temporary CrypInCount Value */
+  uint16_t outcount;  /* Temporary CrypOutCount Value */
 
-/** @defgroup CRYP_Exported_Functions_Group6 CRYP IRQ handler management  
- *  @brief   CRYP IRQ handler.
- *
-@verbatim   
-  ==============================================================================
-                ##### CRYP IRQ handler management #####
-  ==============================================================================  
-[..]  This section provides CRYP IRQ handler function.
+  if(hcryp->State == HAL_CRYP_STATE_BUSY)
+  {
+    /*Temporary CrypOutCount Value*/
+    incount = hcryp->CrypInCount;
 
-@endverbatim
-  * @{
-  */
+    if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U)))
+    {
+      /* Write the input block in the IN FIFO */
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
+      hcryp->CrypInCount++;
+      if(hcryp->CrypInCount ==  (hcryp->Size/4U))
+      {
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+
+        /* Call the input data transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+        /*Call registered Input complete callback*/
+        hcryp->InCpltCallback(hcryp);
+#else
+        /*Call legacy weak Input complete callback*/
+        HAL_CRYP_InCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+    }
+    
+    /*Temporary CrypOutCount Value*/
+    outcount = hcryp->CrypOutCount;
+
+    if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U)))
+    {
+      /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
+      temp  = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+      hcryp->CrypOutCount++;
+      temp  = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+      hcryp->CrypOutCount++;
+      temp  = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+      hcryp->CrypOutCount++;
+      temp  = hcryp->Instance->DOUT;
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
+      hcryp->CrypOutCount++;
+      if(hcryp->CrypOutCount ==  (hcryp->Size/4U))
+      {
+        /* Disable interrupts */
+        __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
+
+        /* Change the CRYP state */
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Disable CRYP */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+
+        /* Call output transfer complete callback */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+        /*Call registered Output complete callback*/
+        hcryp->OutCpltCallback(hcryp);
+#else
+        /*Call legacy weak Output complete callback*/
+        HAL_CRYP_OutCpltCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+    /*Call registered error callback*/
+    hcryp->ErrorCallback(hcryp);
+#else
+    /*Call legacy weak error callback*/
+    HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+  }
+}
 
 /**
-  * @brief  This function handles CRYP interrupt request.
+  * @brief  Writes Key in Key registers.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
+  * @param  KeySize: Size of Key
   * @retval None
   */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
+static void CRYP_SetKey( CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
 {
-  switch(CRYP->CR & CRYP_CR_ALGOMODE_DIRECTION)
+  switch(KeySize)
   {
-  case CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT:
-    HAL_CRYP_TDESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT:
-    HAL_CRYP_TDESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT:
-    HAL_CRYP_TDESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT:
-    HAL_CRYP_TDESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT:
-    HAL_CRYP_DESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_DES_ECB_DECRYPT:
-    HAL_CRYP_DESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT:
-    HAL_CRYP_DESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_DES_CBC_DECRYPT:
-    HAL_CRYP_DESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT:
-    HAL_CRYP_AESECB_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_AES_ECB_DECRYPT:
-    HAL_CRYP_AESECB_Decrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT:
-    HAL_CRYP_AESCBC_Encrypt_IT(hcryp, NULL, 0, NULL);
-    break;
-    
-  case CRYP_CR_ALGOMODE_AES_CBC_DECRYPT:
-    HAL_CRYP_AESCBC_Decrypt_IT(hcryp, NULL, 0, NULL);
+  case CRYP_KEYSIZE_256B:
+    hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey);
+    hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1);
+    hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2);
+    hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3);
+    hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4);
+    hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5);
+    hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6);
+    hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7);
     break;
-    
-  case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT:
-    HAL_CRYP_AESCTR_Encrypt_IT(hcryp, NULL, 0, NULL);       
+  case CRYP_KEYSIZE_192B:
+    hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey);
+    hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1);
+    hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2);
+    hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3);
+    hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4);
+    hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5);
     break;
-    
-  case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT:
-    HAL_CRYP_AESCTR_Decrypt_IT(hcryp, NULL, 0, NULL);        
+  case CRYP_KEYSIZE_128B:
+    hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey);
+    hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1);
+    hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2);
+    hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3);
+
     break;
-    
   default:
     break;
   }
 }
 
 /**
-  * @}
+  * @brief  Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
+  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module.
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
   */
+static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+  uint32_t tickstart;
 
-/** @defgroup CRYP_Exported_Functions_Group7 Peripheral State functions 
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
+}
 
-@endverbatim
-  * @{
-  */
 
 /**
-  * @brief  Returns the CRYP state.
+  * @brief  Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL state
+  *         the configuration information for CRYP module.
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
   */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
+static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef  *hcryp, uint32_t Timeout)
 {
-  return hcryp->State;
+  uint32_t tickstart;
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      {
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
 }
 
+
 /**
   * @}
   */
 
 
+
 /**
   * @}
   */
 
-#endif /* STM32F215xx || STM32F217xx */
+/**
+  * @}
+  */
 
 #endif /* HAL_CRYP_MODULE_ENABLED */
+
+
 /**
   * @}
   */
-
+#endif /*  CRYP*/
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac.c
index 02b655da..9f339969 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac.c
@@ -2,172 +2,240 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
+  *         This file provides firmware functions to manage the following
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
-  *     
+  *           + Peripheral State and Errors functions
   *
-  @verbatim      
+  *
+  @verbatim
   ==============================================================================
                       ##### DAC Peripheral features #####
   ==============================================================================
-    [..]        
+    [..]
       *** DAC Channels ***
-      ====================  
-    [..]  
-    The device integrates two 12-bit Digital Analog Converters that can 
-    be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output
-      
+      ====================
+    [..]
+    STM32F2 devices integrate two 12-bit Digital Analog Converters
+
+    The 2 converters (i.e. channel1 & channel2)
+    can be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
+          peripherals (ex. timers).
+      (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
+          peripherals (ex. timers).
+
       *** DAC Triggers ***
       ====================
     [..]
     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
-    [..] 
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+    [..]
     Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
-          The used pin (GPIOx_Pin9) must be configured in input mode.
-  
+      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+          The used pin (GPIOx_PIN_9) must be configured in input mode.
+
       (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-  
+
       (#) Software using DAC_TRIGGER_SOFTWARE
-  
+
       *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
+      ===============================
+      [..]
+      Each DAC channel integrates an output buffer that can be used to
       reduce the output impedance, and to drive external loads directly
       without having to add an external operational amplifier.
-      To enable, the output buffer use  
+      To enable, the output buffer use
       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
-      [..]           
-      (@) Refer to the device datasheet for more details about output 
+      [..]
+      (@) Refer to the device datasheet for more details about output
           impedance value with and without output buffer.
-            
+
+      *** DAC connect feature ***
+      ===============================
+      [..]
+      Each DAC channel can be connected internally.
+      To connect, use
+      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
+
+      *** GPIO configurations guidelines ***
+      =====================
+      [..]
+      When a DAC channel is used (ex channel1 on PA4) and the other is not
+      (ex channel2 on PA5 is configured in Analog and disabled).
+      Channel1 may disturb channel2 as coupling effect.
+      Note that there is no coupling on channel2 as soon as channel2 is turned on.
+      Coupling on adjacent channel could be avoided as follows:
+      when unused PA5 is configured as INPUT PULL-UP or DOWN.
+      PA5 is configured in ANALOG just before it is turned on.
+
        *** DAC wave generation feature ***
-       =================================== 
-       [..]     
+       ===================================
+       [..]
        Both DAC channels can be used to generate
-         (#) Noise wave 
+         (#) Noise wave
          (#) Triangle wave
-            
+
        *** DAC data format ***
        =======================
-       [..]   
+       [..]
        The DAC data format can be:
          (#) 8-bit right alignment using DAC_ALIGN_8B_R
          (#) 12-bit left alignment using DAC_ALIGN_12B_L
          (#) 12-bit right alignment using DAC_ALIGN_12B_R
-  
-       *** DAC data value to voltage correspondence ***  
-       ================================================ 
-       [..] 
+
+       *** DAC data value to voltage correspondence ***
+       ================================================
+       [..]
        The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
+       by the following equation:
+       [..]
        DAC_OUTx = VREF+ * DOR / 4095
-       with  DOR is the Data Output Register
+       (+) with  DOR is the Data Output Register
+       [..]
           VEF+ is the input voltage reference (refer to the device datasheet)
+       [..]
         e.g. To set DAC_OUT1 to 0.7V, use
-          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-       *** DMA requests  ***
+       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+       *** DMA requests ***
        =====================
-       [..]    
-       A DMA1 request can be generated when an external trigger (but not
-       a software trigger) occurs if DMA1 requests are enabled using
-       HAL_DAC_Start_DMA()
        [..]
+       A DMA1 request can be generated when an external trigger (but not a software trigger)
+       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
        DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
-             already configured
-         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
-             already configured
-       
-    -@- For Dual mode and specific signal (Triangle and noise) generation please 
-        refer to Extension Features Driver description        
-  
-      
+      (#) DAC channel1 mapped on DMA1 Stream5 channel7
+      (#) DAC channel2 mapped on DMA1 Stream6 channel7
+
+     [..]
+    (@) For Dual mode and specific signal (Triangle and noise) generation please
+        refer to Extended Features Driver description
+
                       ##### How to use this driver #####
   ==============================================================================
-    [..]          
+    [..]
       (+) DAC APB clock must be enabled to get write access to DAC
           registers using HAL_DAC_Init()
       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
+
 
      *** Polling mode IO operation ***
      =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start()
        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
        (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
+
+     *** DMA mode IO operation ***
      ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion 
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+           of data to be transferred at each end of conversion
+           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
+       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-                    
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+    Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
+      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
+      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
+      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
+      (+) MspInitCallback         : DAC MspInit.
+      (+) MspDeInitCallback       : DAC MspdeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+    Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
+      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
+      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
+      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
+      (+) MspInitCallback         : DAC MspInit.
+      (+) MspDeInitCallback       : DAC MspdeInit.
+      (+) All Callbacks
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+      and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+      or @ref HAL_DAC_Init function.
+
+      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
      *** DAC HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DAC HAL driver.
-       
+
       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-      
+
      [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim    
+      (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
-
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -176,98 +244,115 @@
   * @{
   */
 
+#ifdef HAL_DAC_MODULE_ENABLED
+#if defined(DAC)
+
 /** @defgroup DAC DAC
   * @brief DAC driver modules
   * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
 /* Private function prototypes -----------------------------------------------*/
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
-/**
-  * @}
-  */
+/* Exported functions -------------------------------------------------------*/
 
-/* Exported functions --------------------------------------------------------*/
 /** @defgroup DAC_Exported_Functions DAC Exported Functions
   * @{
   */
 
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
   ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC. 
-      (+) De-initialize the DAC. 
-         
+      (+) Initialize and configure the DAC.
+      (+) De-initialize the DAC.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Initialize the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct and initialize the associated handle.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{ 
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
+{
   /* Check DAC handle */
-  if(hdac == NULL)
+  if (hdac == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
   /* Check the parameters */
   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-  
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {  
+
+  if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+    /* Init the DAC Callback settings */
+    hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
+    hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
+    hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
+    hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
+
+    hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
+    hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
+    hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
+    hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+    if (hdac->MspInitCallback == NULL)
+    {
+      hdac->MspInitCallback             = HAL_DAC_MspInit;
+    }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
     /* Allocate lock resource and initialize it */
     hdac->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+    /* Init the low level hardware */
+    hdac->MspInitCallback(hdac);
+#else
     /* Init the low level hardware */
     HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
   }
-  
+
   /* Initialize the DAC state*/
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Set DAC error code to none */
   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
+
   /* Initialize the DAC state*/
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
 {
   /* Check DAC handle */
-  if(hdac == NULL)
+  if (hdac == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
 
   /* Check the parameters */
@@ -276,8 +361,17 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
 
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  if (hdac->MspDeInitCallback == NULL)
+  {
+    hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hdac->MspDeInitCallback(hdac);
+#else
   /* DeInit the low level hardware */
   HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
   /* Set DAC error code to none */
   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
@@ -293,29 +387,35 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
 }
 
 /**
-  * @brief  Initializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Initialize the DAC MSP.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief  DeInitializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
+  * @brief  DeInitialize the DAC MSP.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -323,139 +423,135 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
   */
 
 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
+  *  @brief    IO operation functions
+  *
+@verbatim
   ==============================================================================
              ##### IO operation functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
       (+) Start conversion.
       (+) Stop conversion.
       (+) Start conversion and enable DMA transfer.
       (+) Stop conversion and disable DMA transfer.
       (+) Get result of conversion.
-                     
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Enable the Peripheral */
   __HAL_DAC_ENABLE(hdac, Channel);
-  
-  if(Channel == DAC_CHANNEL_1)
+
+  if (Channel == DAC_CHANNEL_1)
   {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
     /* Check if software trigger enabled */
-    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
+    if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
     {
       /* Enable the selected DAC software conversion */
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
     }
   }
   else
   {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    
     /* Check if software trigger enabled */
-    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
     {
       /* Enable the selected DAC software conversion*/
-      hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
     }
   }
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-    
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
-  
+
   /* Disable the Peripheral */
   __HAL_DAC_DISABLE(hdac, Channel);
- 
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  pData The destination peripheral Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment)
 {
-  uint32_t tmpreg = 0;
-    
+  HAL_StatusTypeDef status;
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_ALIGN(Alignment));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
 
-  if(Channel == DAC_CHANNEL_1)
+  if (Channel == DAC_CHANNEL_1)
   {
     /* Set the DMA transfer complete callback for channel1 */
     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
@@ -467,10 +563,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
 
     /* Enable the selected DAC channel1 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN1;
-    
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
     /* Case of use of channel 1 */
-    switch(Alignment)
+    switch (Alignment)
     {
       case DAC_ALIGN_12B_R:
         /* Get DHR12R1 address */
@@ -500,10 +596,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
 
     /* Enable the selected DAC channel2 DMA request */
-    hdac->Instance->CR |= DAC_CR_DMAEN2;
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
 
     /* Case of use of channel 2 */
-    switch(Alignment)
+    switch (Alignment)
     {
       case DAC_ALIGN_12B_R:
         /* Get DHR12R2 address */
@@ -521,74 +617,90 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
         break;
     }
   }
-  
+
   /* Enable the DMA Stream */
-  if(Channel == DAC_CHANNEL_1)
+  if (Channel == DAC_CHANNEL_1)
   {
     /* Enable the DAC DMA underrun interrupt */
     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
+
+   /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  }
   else
   {
     /* Enable the DAC DMA underrun interrupt */
     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-    
+
     /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
   }
-  
-  /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hdac);
-  
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Peripheral */
+    __HAL_DAC_ENABLE(hdac, Channel);
+  }
+  else
+  {
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+  }
+
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
-  HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef status;
 
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
-  
+
   /* Disable the selected DAC channel DMA request */
-   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-    
+  hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
+
   /* Disable the Peripheral */
   __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Disable the DMA Channel */
+
+  /* Disable the DMA Stream */
+
   /* Channel1 is used */
-  if(Channel == DAC_CHANNEL_1)
-  { 
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Disable the DMA Stream */
     status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
   }
   else /* Channel2 is used for */
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
+  {
+    /* Disable the DMA Stream */
+    status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
   }
 
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
+  /* Check if DMA Stream effectively disabled */
+  if (status != HAL_OK)
   {
     /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;      
+    hdac->State = HAL_DAC_STATE_ERROR;
   }
   else
   {
@@ -601,125 +713,170 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
 }
 
 /**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Handles DAC interrupt request
+  *         This function uses the interruption of DMA
+  *         underrun.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
+  * @retval None
   */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
 {
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
+  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
   {
-    return hdac->Instance->DOR1;
+    /* Check underrun flag of DAC channel 1 */
+    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+
+      /* Set DAC error code to chanel1 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
+
+      /* Disable the selected DAC channel1 DMA request */
+      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+      /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+      hdac->DMAUnderrunCallbackCh1(hdac);
+#else
+      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+    }
   }
-  else
+
+  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
   {
-    return hdac->Instance->DOR2;
+    /* Check underrun flag of DAC channel 2 */
+    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+
+      /* Set DAC error code to channel2 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
+
+      /* Disable the selected DAC channel2 DMA request */
+      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+      /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+      hdac->DMAUnderrunCallbackCh2(hdac);
+#else
+      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+    }
   }
 }
 
 /**
-  * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @retval None
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Alignment Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data Data to be loaded in the selected data holding register.
+  * @retval HAL status
   */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
 {
-  /* Check underrun channel 1 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data));
+
+  tmp = (uint32_t)hdac->Instance;
+  if (Channel == DAC_CHANNEL_1)
   {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN1;
-    
-    /* Error callback */ 
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
   }
-  /* Check underrun channel 2 flag */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+  else
   {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel2 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN2;
-    
-    /* Error callback */ 
-    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
   }
+
+  /* Set the DAC channel selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+
+  /* Return function status */
+  return HAL_OK;
 }
 
 /**
-  * @brief  Conversion complete callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Conversion complete callback in non-blocking mode for Channel1
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
    */
 }
 
 /**
   * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
    */
 }
 
 /**
   * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
    */
 }
@@ -727,111 +884,98 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
 /**
   * @}
   */
-  
+
 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
   ==============================================================================
              ##### Peripheral Control functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure channels. 
+      (+) Configure channels.
       (+) Set the specified data holding register value for DAC channel.
-      
+
 @endverbatim
   * @{
   */
 
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Returns the DAC channel data output register value */
+  if (Channel == DAC_CHANNEL_1)
+  {
+    return hdac->Instance->DOR1;
+  }
+  else
+  {
+    return hdac->Instance->DOR2;
+  }
+}
+
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  sConfig DAC configuration structure.
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
 {
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  uint32_t tmpreg1;
+  uint32_t tmpreg2;
 
   /* Check the DAC parameters */
   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
   assert_param(IS_DAC_CHANNEL(Channel));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Get the DAC CR value */
   tmpreg1 = hdac->Instance->CR;
   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
+  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
   /* Configure for the selected DAC channel: buffer output, trigger */
   /* Set TSELx and TENx bits according to DAC_Trigger value */
   /* Set BOFFx bit according to DAC_OutputBuffer value */   
   tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
   /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
+  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
   /* Write to DAC CR */
   hdac->Instance->CR = tmpreg1;
   /* Disable wave generation */
-  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
-  
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
+  /* Disable wave generation */
+  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @param  Alignment: Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{  
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
-  }
-  else
-  {
-    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
-  }
 
-  /* Set the DAC channel1 selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-  
   /* Return function status */
   return HAL_OK;
 }
@@ -841,37 +985,37 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
   */
 
 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions 
- *
-@verbatim   
+  *  @brief   Peripheral State and Errors functions
+  *
+@verbatim
   ==============================================================================
             ##### Peripheral State and Errors functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Check the DAC state.
       (+) Check the DAC Errors.
-        
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  return the DAC state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  return the DAC handle state
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL state
   */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
 {
-  /* Return DAC state */
+  /* Return DAC handle state */
   return hdac->State;
 }
 
 
 /**
   * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval DAC Error Code
   */
@@ -885,61 +1029,320 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
   */
 
 /**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DAC Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hdac DAC handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
+  *
+  * @param  pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                           pDAC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  if (hdac->State == HAL_DAC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_CH1_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_ERROR_ID :
+        hdac->ErrorCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH2_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_ERROR_ID :
+        hdac->ErrorCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = pCallback;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = pCallback;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User DAC Callback
+  *         DAC Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hdac DAC handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 tranfer Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
+  *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  if (hdac->State == HAL_DAC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_CH1_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+        break;
+      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+        break;
+      case HAL_DAC_CH1_ERROR_ID :
+        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+        break;
+      case HAL_DAC_CH1_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+        break;
+      case HAL_DAC_CH2_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+        break;
+      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+        break;
+      case HAL_DAC_CH2_ERROR_ID :
+        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+        break;
+      case HAL_DAC_CH2_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+        break;
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      case HAL_DAC_ALL_CB_ID :
+        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+  return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
 {
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvCpltCallbackCh1(hdac);
+#else
+  HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
 }
 
 /**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
 {
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvHalfCpltCallbackCh1(hdac);
+#else
+  HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+#endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
 {
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
   /* Set DAC error code to DMA error */
   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DAC_ErrorCallbackCh1(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ErrorCallbackCh1(hdac);
+#else
+  HAL_DAC_ErrorCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
 }
 
 /**
   * @}
   */
 
-#endif /* HAL_DAC_MODULE_ENABLED */
-
 /**
   * @}
   */
 
+#endif /* DAC */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac_ex.c
index c380cc2b..c2002569 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dac_ex.c
@@ -2,55 +2,42 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of DAC extension peripheral:
-  *           + Extended features functions
-  *     
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the DAC peripheral.
   *
-  @verbatim      
+  *
+  @verbatim
   ==============================================================================
                       ##### How to use this driver #####
   ==============================================================================
-    [..]          
-      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+    [..]
+     *** Dual mode IO operation ***
+     ==============================
+      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
+          Channel 1 and Channel 2.
+
+     *** Signal generation operation ***
+     ===================================
       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-   
- @endverbatim    
+
+ @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 
 /* Includes ------------------------------------------------------------------*/
@@ -60,31 +47,33 @@
   * @{
   */
 
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(DAC)
+
 /** @defgroup DACEx DACEx
-  * @brief DAC driver modules
+  * @brief DAC Extended HAL module driver
   * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup DACEx_Exported_Functions DAC Exported Functions
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
   * @{
   */
 
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- *  @brief    Extended features functions 
- *
-@verbatim   
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+  *  @brief    Extended IO operation functions
+  *
+@verbatim
   ==============================================================================
                  ##### Extended features functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
       (+) Start conversion.
       (+) Stop conversion.
@@ -92,37 +81,20 @@
       (+) Stop conversion and disable DMA transfer.
       (+) Get result of conversion.
       (+) Get result of dual mode conversion.
-                     
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0;
-  
-  tmp |= hdac->Instance->DOR1;
-  
-  tmp |= hdac->Instance->DOR2 << 16;
-  
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Select max triangle amplitude. 
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Amplitude Select max triangle amplitude.
   *          This parameter can be one of the following values:
   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -135,238 +107,312 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
-  
+
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC. 
-  * @param  Channel: The selected DAC channel. 
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
   *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
-  *          This parameter can be one of the following values: 
   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-  
+
+  /* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  * @param  Alignment Specifies the data alignment for dual channel DAC.
   *          This parameter can be one of the following values:
   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
+  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
   * @note   In dual mode, a unique register access is required to write in both
   *          DAC channels at the same time.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{  
-  uint32_t data = 0, tmp = 0;
-  
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+  uint32_t data;
+  uint32_t tmp;
+
   /* Check the parameters */
   assert_param(IS_DAC_ALIGN(Alignment));
   assert_param(IS_DAC_DATA(Data1));
   assert_param(IS_DAC_DATA(Data2));
-  
+
   /* Calculate and set dual DAC data holding register value */
   if (Alignment == DAC_ALIGN_8B_R)
   {
-    data = ((uint32_t)Data2 << 8) | Data1; 
+    data = ((uint32_t)Data2 << 8U) | Data1;
   }
   else
   {
-    data = ((uint32_t)Data2 << 16) | Data1;
+    data = ((uint32_t)Data2 << 16U) | Data1;
   }
-  
+
   tmp = (uint32_t)hdac->Instance;
   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
 
   /* Set the dual DAC selected data holding register */
   *(__IO uint32_t *)tmp = data;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @}
-  */
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Conversion complete callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
   * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @brief  DMA underrun DAC callback for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
    */
 }
 
 /**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @}
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Extended Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the last data output value of the selected DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+{
+  uint32_t tmp = 0U;
+
+  tmp |= hdac->Instance->DOR1;
+
+  tmp |= hdac->Instance->DOR2 << 16U;
+
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+  *  @brief    Extended private functions
+   * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
 {
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
 }
 
 /**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
 {
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
 {
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
   /* Set DAC error code to DMA error */
   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ErrorCallbackCh2(hdac);
+#else
+  HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
 }
 
 /**
   * @}
   */
 
-#endif /* HAL_DAC_MODULE_ENABLED */
-
 /**
   * @}
   */
 
+#endif /* DAC */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dcmi.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dcmi.c
index e71900c1..df118b05 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dcmi.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dcmi.c
@@ -2,17 +2,15 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dcmi.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   DCMI HAL module driver
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Digital Camera Interface (DCMI) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State and Error functions  
-  *           
-  @verbatim      
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
@@ -25,18 +23,18 @@
 
     (#) Program the required configuration through following parameters:
         horizontal and vertical polarity, pixel clock polarity, Capture Rate,
-        Synchronization Mode, code of the frame delimiter and data width 
+        Synchronization Mode, code of the frame delimiter and data width
         using HAL_DCMI_Init() function.
 
     (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
         register to the destination memory buffer.
 
     (#) Program the required configuration through following parameters:
-        DCMI mode, destination memory Buffer address and the data length 
+        DCMI mode, destination memory Buffer address and the data length
         and enable capture using HAL_DCMI_Start_DMA() function.
 
     (#) Optionally, configure and Enable the CROP feature to select a rectangular
-        window from the received image using HAL_DCMI_ConfigCrop() 
+        window from the received image using HAL_DCMI_ConfigCrop()
         and HAL_DCMI_EnableCROP() functions
 
     (#) The capture can be stopped using HAL_DCMI_Stop() function.
@@ -44,10 +42,10 @@
     (#) To control DCMI state you can use the function HAL_DCMI_GetState().
 
      *** DCMI HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DCMI HAL driver.
-       
+
       (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
       (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
       (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
@@ -55,40 +53,74 @@
       (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
       (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
       (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
- 
-     [..] 
+
+     [..]
        (@) You can refer to the DCMI HAL driver header file for more useful macros
-      
+
+    *** Callback registration ***
+    =============================
+
+    The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+    Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
+
+    Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
+      (+) FrameEventCallback : DCMI Frame Event.
+      (+) VsyncEventCallback : DCMI Vsync Event.
+      (+) LineEventCallback  : DCMI Line Event.
+      (+) ErrorCallback      : DCMI error.
+      (+) MspInitCallback    : DCMI MspInit.
+      (+) MspDeInitCallback  : DCMI MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the callback ID
+    and a pointer to the user callback function.
+
+    Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the callback ID.
+    This function allows to reset following callbacks:
+      (+) FrameEventCallback : DCMI Frame Event.
+      (+) VsyncEventCallback : DCMI Vsync Event.
+      (+) LineEventCallback  : DCMI Line Event.
+      (+) ErrorCallback      : DCMI error.
+      (+) MspInitCallback    : DCMI MspInit.
+      (+) MspDeInitCallback  : DCMI MspDeInit.
+
+    By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+    examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
+    and @ref  HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
+    or @ref HAL_DCMI_Init function.
+
+    When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -102,15 +134,16 @@
   */
 
 #ifdef HAL_DCMI_MODULE_ENABLED
+#if defined (DCMI)
 
-#if defined(STM32F207xx) || defined(STM32F217xx)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000)  /* 1s  */
+#define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-static void       DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void       DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
 static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
 
 /* Exported functions --------------------------------------------------------*/
@@ -120,35 +153,35 @@ static void       DCMI_DMAError(DMA_HandleTypeDef *hdma);
   */
 
 /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
-  *  @brief   Initialization and Configuration functions
-  *
-@verbatim   
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim
  ===============================================================================
                 ##### Initialization and Configuration functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Initialize and configure the DCMI
-      (+) De-initialize the DCMI 
+      (+) De-initialize the DCMI
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the DCMI according to the specified
   *         parameters in the DCMI_InitTypeDef and create the associated handle.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
-{     
+{
   /* Check the DCMI peripheral state */
-  if(hdcmi == NULL)
+  if (hdcmi == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
+
   /* Check function parameters */
   assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
   assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
@@ -159,55 +192,56 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
   assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
   assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
 
-  if(hdcmi->State == HAL_DCMI_STATE_RESET)
+  if (hdcmi->State == HAL_DCMI_STATE_RESET)
   {
-    /* Allocate lock resource and initialize it */
-    hdcmi->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
+    /* Init the DCMI Callback settings */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback  */
+    hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback  */
+    hdcmi->LineEventCallback  = HAL_DCMI_LineEventCallback;  /* Legacy weak LineEventCallback   */
+    hdcmi->ErrorCallback      = HAL_DCMI_ErrorCallback;      /* Legacy weak ErrorCallback       */
+
+    if (hdcmi->MspInitCallback == NULL)
+    {
+      /* Legacy weak MspInit Callback        */
+      hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+    }
+    /* Initialize the low level hardware (MSP) */
+    hdcmi->MspInitCallback(hdcmi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_DCMI_MspInit(hdcmi);
-  } 
-  
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
+  }
+
   /* Change the DCMI state */
-  hdcmi->State = HAL_DCMI_STATE_BUSY; 
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
   /* Configures the HS, VS, DE and PC polarity */
-  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 |
-                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  |
+  hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL  | DCMI_CR_VSPOL  | DCMI_CR_EDM_0 | \
+                           DCMI_CR_EDM_1  | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG  | \
                            DCMI_CR_ESS);
-  hdcmi->Instance->CR |=  (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
-                                     hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
-                                     hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
-                                     hdcmi->Init.JPEGMode);
 
-  if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
+  hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
+                                    hdcmi->Init.VSPolarity  | hdcmi->Init.HSPolarity  | \
+                                    hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
+                                    hdcmi->Init.JPEGMode);
+
+  if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
   {
-    DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    |
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
-                  ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
-                  ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
+    hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode)    | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
+                             ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
 
   }
 
-  /* Enable the Line interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
-
-  /* Enable the VSYNC interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
-
-  /* Enable the Frame capture complete interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
-
-  /* Enable the Synchronization error interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
-
-  /* Enable the Overflow interrupt */
-  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
-
-  /* Enable DCMI by setting DCMIEN bit */
-  __HAL_DCMI_ENABLE(hdcmi);
+  /* Enable the Line, Vsync, Error and Overrun interrupts */
+  __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
 
   /* Update error code */
   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
-  
+
   /* Initialize the DCMI state*/
   hdcmi->State  = HAL_DCMI_STATE_READY;
 
@@ -217,14 +251,24 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
 /**
   * @brief  Deinitializes the DCMI peripheral registers to their default reset
   *         values.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval HAL status
   */
+
 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
 {
-  /* DeInit the low level hardware */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  if (hdcmi->MspDeInitCallback == NULL)
+  {
+    hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+  }
+  /* De-Initialize the low level hardware (MSP) */
+  hdcmi->MspDeInitCallback(hdcmi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
   HAL_DCMI_MspDeInit(hdcmi);
+#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
 
   /* Update error code */
   hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@@ -240,25 +284,31 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
 
 /**
   * @brief  Initializes the DCMI MSP.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
-__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
+__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DeInitializes the DCMI MSP.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
-__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
+__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_MspDeInit could be implemented in the user file
    */
@@ -267,15 +317,15 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
 /**
   * @}
   */
-/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions 
-  *  @brief   IO operation functions  
-  *
-@verbatim   
+/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
+ *  @brief   IO operation functions
+ *
+@verbatim
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure destination address and data length and 
+      (+) Configure destination address and data length and
           Enables DCMI DMA request and enables DCMI capture
       (+) Stop the DCMI capture.
       (+) Handles DCMI interrupt request.
@@ -285,16 +335,16 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
   */
 
 /**
-  * @brief  Enables DCMI DMA request and enables DCMI capture  
-  * @param  hdcmi:     pointer to a DCMI_HandleTypeDef structure that contains
+  * @brief  Enables DCMI DMA request and enables DCMI capture
+  * @param  hdcmi     pointer to a DCMI_HandleTypeDef structure that contains
   *                    the configuration information for DCMI.
-  * @param  DCMI_Mode: DCMI capture mode snapshot or continuous grab.
-  * @param  pData:     The destination memory Buffer address (LCD Frame buffer).
-  * @param  Length:    The length of capture to be transferred.
+  * @param  DCMI_Mode DCMI capture mode snapshot or continuous grab.
+  * @param  pData     The destination memory Buffer address (LCD Frame buffer).
+  * @param  Length    The length of capture to be transferred.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
-{  
+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
+{
   /* Initialize the second memory address */
   uint32_t SecondMemAddress = 0;
 
@@ -307,100 +357,116 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
   /* Lock the DCMI peripheral state */
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
-  /* Check the parameters */
-  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
+  /* Enable DCMI by setting DCMIEN bit */
+  __HAL_DCMI_ENABLE(hdcmi);
 
   /* Configure the DCMI Mode */
   hdcmi->Instance->CR &= ~(DCMI_CR_CM);
-  hdcmi->Instance->CR |=  (uint32_t)(DCMI_Mode);
+  hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
 
   /* Set the DMA memory0 conversion complete callback */
-  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
+  hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
 
   /* Set the DMA error callback */
   hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
 
-  if(Length <= 0xFFFF)
+  /* Set the dma abort callback */
+  hdcmi->DMA_Handle->XferAbortCallback = NULL;
+
+  /* Reset transfer counters value */
+  hdcmi->XferCount = 0;
+  hdcmi->XferTransferNumber = 0;
+  hdcmi->XferSize = 0;
+  hdcmi->pBuffPtr = 0;
+
+  if (Length <= 0xFFFFU)
   {
     /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
+    if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
   else /* DCMI_DOUBLE_BUFFER Mode */
   {
     /* Set the DMA memory1 conversion complete callback */
-    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt; 
+    hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
 
     /* Initialize transfer parameters */
     hdcmi->XferCount = 1;
     hdcmi->XferSize = Length;
     hdcmi->pBuffPtr = pData;
-      
+
     /* Get the number of buffer */
-    while(hdcmi->XferSize > 0xFFFF)
+    while (hdcmi->XferSize > 0xFFFFU)
     {
-      hdcmi->XferSize = (hdcmi->XferSize/2);
-      hdcmi->XferCount = hdcmi->XferCount*2;
+      hdcmi->XferSize = (hdcmi->XferSize / 2U);
+      hdcmi->XferCount = hdcmi->XferCount * 2U;
     }
 
     /* Update DCMI counter  and transfer number*/
-    hdcmi->XferCount = (hdcmi->XferCount - 2);
+    hdcmi->XferCount = (hdcmi->XferCount - 2U);
     hdcmi->XferTransferNumber = hdcmi->XferCount;
 
     /* Update second memory address */
-    SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
+    SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize));
 
     /* Start DMA multi buffer transfer */
-    HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
+    if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
   }
 
   /* Enable Capture */
-  DCMI->CR |= DCMI_CR_CAPTURE;
+  hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdcmi);
 
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Disable DCMI DMA request and Disable DCMI capture  
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
-  *                the configuration information for DCMI. 
-  * @retval HAL status     
+  * @brief  Disable DCMI DMA request and Disable DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
 {
-  uint32_t tickstart = 0;
+  register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
 
   /* Lock the DCMI peripheral state */
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
-  __HAL_DCMI_DISABLE(hdcmi);
-
   /* Disable Capture */
-  DCMI->CR &= ~(DCMI_CR_CAPTURE);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
+  hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
 
   /* Check if the DCMI capture effectively disabled */
-  while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
+  do
   {
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
+    if (count-- == 0U)
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-      
       /* Update error code */
       hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
-      
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
+
+      status = HAL_TIMEOUT;
+      break;
     }
   }
+  while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+
+  /* Disable the DCMI */
+  __HAL_DCMI_DISABLE(hdcmi);
 
   /* Disable the DMA */
-  HAL_DMA_Abort(hdcmi->DMA_Handle);
+  (void)HAL_DMA_Abort(hdcmi->DMA_Handle);
 
   /* Update error code */
   hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
@@ -411,133 +477,196 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Suspend DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
+{
+  register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if (hdcmi->State == HAL_DCMI_STATE_BUSY)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
+
+    /* Disable Capture */
+    hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
+
+    /* Check if the DCMI capture effectively disabled */
+    do
+    {
+      if (count-- == 0U)
+      {
+        /* Update error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
+
+        /* Change DCMI state */
+        hdcmi->State = HAL_DCMI_STATE_READY;
+
+        status = HAL_TIMEOUT;
+        break;
+      }
+    }
+    while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Resume DCMI capture
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *                the configuration information for DCMI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
+{
+  /* Process locked */
+  __HAL_LOCK(hdcmi);
+
+  if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
+  {
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+    /* Disable Capture */
+    hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
+  }
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Handles DCMI interrupt request.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for the DCMI.
   * @retval None
   */
 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
-{  
+{
+  uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
+
   /* Synchronization error interrupt management *******************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
+  if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
-    {
-      /* Disable the Synchronization error interrupt */
-      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR); 
-
-      /* Clear the Synchronization error flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
+    /* Clear the Synchronization error flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
 
-      /* Update error code */
-      hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
 
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_ERROR;
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
+    /* Set the synchronization error callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
 
-      /* Abort the DMA Transfer */
-      HAL_DMA_Abort(hdcmi->DMA_Handle);
-      
-      /* Synchronization error Callback */
-      HAL_DCMI_ErrorCallback(hdcmi);
-    }
+    /* Abort the DMA Transfer */
+    (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
   }
   /* Overflow interrupt management ********************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET) 
+  if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
-    {
-      /* Disable the Overflow interrupt */
-      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);
+    /* Clear the Overflow flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
 
-      /* Clear the Overflow flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
-
-      /* Update error code */
-      hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
+    /* Update error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
 
-      /* Change DCMI state */
-      hdcmi->State = HAL_DCMI_STATE_ERROR;
+    /* Change DCMI state */
+    hdcmi->State = HAL_DCMI_STATE_ERROR;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
+    /* Set the overflow callback */
+    hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
 
-      /* Abort the DMA Transfer */
-      HAL_DMA_Abort(hdcmi->DMA_Handle);
-
-      /* Overflow Callback */
-      HAL_DCMI_ErrorCallback(hdcmi);
+    /* Abort the DMA Transfer */
+    if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
+    {
+      DCMI_DMAError(hdcmi->DMA_Handle);
     }
   }
   /* Line Interrupt management ************************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
+  if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
-    {
-      /* Clear the Line interrupt flag */  
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* Line interrupt Callback */
-      HAL_DCMI_LineEventCallback(hdcmi);
-    }
+    /* Clear the Line interrupt flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
+
+    /* Line interrupt Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI line event callback*/
+    hdcmi->LineEventCallback(hdcmi);
+#else
+    HAL_DCMI_LineEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
   }
   /* VSYNC interrupt management ***********************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
+  if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
-    {
-      /* Disable the VSYNC interrupt */
-      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC);   
-
-      /* Clear the VSYNC flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
-
-      /* VSYNC Callback */
-      HAL_DCMI_VsyncEventCallback(hdcmi);
-    }
+    /* Clear the VSYNC flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
+
+    /* VSYNC Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI vsync event callback*/
+    hdcmi->VsyncEventCallback(hdcmi);
+#else
+    HAL_DCMI_VsyncEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
   }
-  /* End of Frame interrupt management ****************************************/
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+  /* FRAME interrupt management ***********************************************/
+  if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
   {
-    if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
+    /* When snapshot mode, disable Vsync, Error and Overrun interrupts */
+    if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
     {
-      /* Disable the End of Frame interrupt */
-      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
+      /* Disable the Line, Vsync, Error and Overrun interrupts */
+      __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
+    }
 
-      /* Clear the End of Frame flag */
-      __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
+    /* Disable the Frame interrupt */
+    __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdcmi);
+    /* Clear the End of Frame flag */
+    __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
 
-      /* End of Frame Callback */
-      HAL_DCMI_FrameEventCallback(hdcmi);
-    }
+    /* Frame Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+    /*Call registered DCMI frame event callback*/
+    hdcmi->FrameEventCallback(hdcmi);
+#else
+    HAL_DCMI_FrameEventCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
   }
 }
 
 /**
   * @brief  Error DCMI callback.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
 __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_ErrorCallback could be implemented in the user file
    */
@@ -545,7 +674,7 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
 
 /**
   * @brief  Line Event callback.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
@@ -558,12 +687,15 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
 
 /**
   * @brief  VSYNC Event callback.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
 __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_VsyncEventCallback could be implemented in the user file
    */
@@ -571,12 +703,15 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
 
 /**
   * @brief  Frame Event callback.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval None
   */
 __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdcmi);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_DCMI_FrameEventCallback could be implemented in the user file
    */
@@ -587,15 +722,16 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
   */
 
 /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Peripheral Control functions 
-  *
-@verbatim   
+ *  @brief    Peripheral Control functions
+ *
+@verbatim
  ===============================================================================
                     ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
 [..]  This section provides functions allowing to:
       (+) Configure the CROP feature.
       (+) Enable/Disable the CROP feature.
+      (+) Set embedded synchronization delimiters unmasks.
 
 @endverbatim
   * @{
@@ -603,15 +739,15 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
 
 /**
   * @brief  Configure the DCMI CROP coordinate.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
-  * @param  X0:    DCMI window X offset
-  * @param  Y0:    DCMI window Y offset
-  * @param  XSize: DCMI Pixel per line
-  * @param  YSize: DCMI Line number
+  * @param  YSize DCMI Line number
+  * @param  XSize DCMI Pixel per line
+  * @param  X0    DCMI window X offset
+  * @param  Y0    DCMI window Y offset
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
+HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -621,13 +757,13 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
 
   /* Check the parameters */
   assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
-  assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
-  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
   assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
+  assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
 
   /* Configure CROP */
-  DCMI->CWSIZER = (XSize | (YSize << 16));
-  DCMI->CWSTRTR = (X0 | (Y0 << 16));
+  hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
+  hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
 
   /* Initialize the DCMI state*/
   hdcmi->State  = HAL_DCMI_STATE_READY;
@@ -640,11 +776,11 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
 
 /**
   * @brief  Disable the Crop feature.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
+HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -653,24 +789,24 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
   /* Disable DCMI Crop feature */
-  DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;  
+  hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
 
   /* Change the DCMI state*/
-  hdcmi->State = HAL_DCMI_STATE_READY;   
+  hdcmi->State = HAL_DCMI_STATE_READY;
 
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Enable the Crop feature.
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
+HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
 {
   /* Process Locked */
   __HAL_LOCK(hdcmi);
@@ -679,7 +815,38 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   hdcmi->State = HAL_DCMI_STATE_BUSY;
 
   /* Enable DCMI Crop feature */
-  DCMI->CR |= (uint32_t)DCMI_CR_CROP;
+  hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
+
+  /* Change the DCMI state*/
+  hdcmi->State = HAL_DCMI_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdcmi);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set embedded synchronization delimiters unmasks.
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
+  *               the configuration information for DCMI.
+  * @param  SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
+  *                    the embedded synchronization delimiters unmasks.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef  HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
+{
+  /* Process Locked */
+  __HAL_LOCK(hdcmi);
+
+  /* Lock the DCMI peripheral state */
+  hdcmi->State = HAL_DCMI_STATE_BUSY;
+
+  /* Write DCMI embedded synchronization unmask register */
+  hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
+                           ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
+                           ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
+                           ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
 
   /* Change the DCMI state*/
   hdcmi->State = HAL_DCMI_STATE_READY;
@@ -687,7 +854,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   /* Process Unlocked */
   __HAL_UNLOCK(hdcmi);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
@@ -695,43 +862,209 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
   */
 
 /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
-  *  @brief    Peripheral State functions 
-  *
-@verbatim   
+ *  @brief    Peripheral State functions
+ *
+@verbatim
  ===============================================================================
                ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Check the DCMI state.
-      (+) Get the specific DCMI error flag.  
+      (+) Get the specific DCMI error flag.
 
 @endverbatim
   * @{
-  */ 
+  */
 
 /**
   * @brief  Return the DCMI state
-  * @param  hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+  * @param  hdcmi pointer to a DCMI_HandleTypeDef structure that contains
   *                the configuration information for DCMI.
   * @retval HAL state
   */
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)  
+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
 {
   return hdcmi->State;
 }
 
 /**
-  * @brief  Return the DCMI error code
-  * @param  hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
+* @brief  Return the DCMI error code
+* @param  hdcmi  pointer to a DCMI_HandleTypeDef structure that contains
   *               the configuration information for DCMI.
-  * @retval DCMI Error Code
-  */
+* @retval DCMI Error Code
+*/
 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
 {
   return hdcmi->ErrorCode;
 }
 
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+/**
+  * @brief DCMI Callback registering
+  * @param hdcmi        pointer to a DCMI_HandleTypeDef structure that contains
+  *                     the configuration information for DCMI.
+  * @param CallbackID   dcmi Callback ID
+  * @param pCallback    pointer to DCMI_CallbackTypeDef structure
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* update the error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hdcmi->State == HAL_DCMI_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DCMI_FRAME_EVENT_CB_ID :
+          hdcmi->FrameEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_VSYNC_EVENT_CB_ID :
+          hdcmi->VsyncEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_LINE_EVENT_CB_ID :
+          hdcmi->LineEventCallback = pCallback;
+          break;
+
+        case HAL_DCMI_ERROR_CB_ID :
+          hdcmi->ErrorCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPINIT_CB_ID :
+          hdcmi->MspInitCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPDEINIT_CB_ID :
+          hdcmi->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          /* Return error status */
+          status =  HAL_ERROR;
+          break;
+      }
+    }
+    else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DCMI_MSPINIT_CB_ID :
+          hdcmi->MspInitCallback = pCallback;
+          break;
+
+        case HAL_DCMI_MSPDEINIT_CB_ID :
+          hdcmi->MspDeInitCallback = pCallback;
+          break;
+
+        default :
+          /* update the error code */
+          hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* update the error code */
+      hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief DCMI Callback Unregistering
+  * @param hdcmi       dcmi handle
+  * @param CallbackID  dcmi Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdcmi->State == HAL_DCMI_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMI_FRAME_EVENT_CB_ID :
+        hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback;  /* Legacy weak  FrameEventCallback  */
+        break;
+
+      case HAL_DCMI_VSYNC_EVENT_CB_ID :
+        hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback;  /* Legacy weak VsyncEventCallback       */
+        break;
+
+      case HAL_DCMI_LINE_EVENT_CB_ID :
+        hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback;    /* Legacy weak LineEventCallback   */
+        break;
+
+      case HAL_DCMI_ERROR_CB_ID :
+        hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback;           /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_DCMI_MSPINIT_CB_ID :
+        hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+        break;
+
+      case HAL_DCMI_MSPDEINIT_CB_ID :
+        hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+        break;
+
+      default :
+        /* update the error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdcmi->State == HAL_DCMI_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DCMI_MSPINIT_CB_ID :
+        hdcmi->MspInitCallback = HAL_DCMI_MspInit;
+        break;
+
+      case HAL_DCMI_MSPDEINIT_CB_ID :
+        hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
+        break;
+
+      default :
+        /* update the error code */
+        hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update the error code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -739,73 +1072,92 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
 /** @defgroup DCMI_Private_Functions DCMI Private Functions
   * @{
   */
-  
-  /**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
+/**
+* @brief  DMA conversion complete callback.
+* @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+*                the configuration information for the specified DMA module.
+* @retval None
+*/
+static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
 {
   uint32_t tmp = 0;
- 
-  DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hdcmi->State= HAL_DCMI_STATE_READY;
 
-  if(hdcmi->XferCount != 0)
+  DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdcmi->XferCount != 0)
   {
     /* Update memory 0 address location */
     tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
-    if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
+    if (((hdcmi->XferCount % 2) == 0) && (tmp != 0))
     {
       tmp = hdcmi->DMA_Handle->Instance->M0AR;
-      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
+      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0);
       hdcmi->XferCount--;
     }
     /* Update memory 1 address location */
-    else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+    else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
     {
       tmp = hdcmi->DMA_Handle->Instance->M1AR;
-      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
+      HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1);
       hdcmi->XferCount--;
     }
   }
   /* Update memory 0 address location */
-  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
+  else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
   {
     hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
   }
   /* Update memory 1 address location */
-  else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
+  else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
   {
     tmp = hdcmi->pBuffPtr;
-    hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
+    hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize));
     hdcmi->XferCount = hdcmi->XferTransferNumber;
   }
 
-  if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
+  /* Check if the frame is transferred */
+  if (hdcmi->XferCount == hdcmi->XferTransferNumber)
   {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdcmi);
+    /* Enable the Frame interrupt */
+    __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
 
-    /* FRAME Callback */
-    HAL_DCMI_FrameEventCallback(hdcmi);
+    /* When snapshot mode, set dcmi state to ready */
+    if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
+    {
+      hdcmi->State = HAL_DCMI_STATE_READY;
+    }
   }
 }
 
 /**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
 {
-    DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;     
-    hdcmi->State= HAL_DCMI_STATE_READY;
-    HAL_DCMI_ErrorCallback(hdcmi);
+  DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
+  {
+    /* Initialize the DCMI state*/
+    hdcmi->State = HAL_DCMI_STATE_READY;
+
+    /* Set DCMI Error Code */
+    hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
+  }
+
+  /* DCMI error Callback */
+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
+  /*Call registered DCMI error callback*/
+  hdcmi->ErrorCallback(hdcmi);
+#else
+  HAL_DCMI_ErrorCallback(hdcmi);
+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+
 }
+
 /**
   * @}
   */
@@ -813,7 +1165,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-#endif /* STM32F207xx || STM32F217xx */
+#endif /* DCMI */
 #endif /* HAL_DCMI_MODULE_ENABLED */
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c
index fb254b5b..97dd49cb 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   DMA HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -12,32 +10,36 @@
   *           + IO operation functions
   *           + Peripheral State and errors functions
   @verbatim     
-  ==============================================================================      
+  ==============================================================================
                         ##### How to use this driver #####
-  ============================================================================== 
+  ==============================================================================
   [..]
    (#) Enable and configure the peripheral to be connected to the DMA Stream
        (except for internal SRAM/FLASH memories: no initialization is 
        necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests . 
-          
-   (#) For a given Stream, program the required configuration through the following parameters:   
+       and DMA requests.
+
+   (#) For a given Stream, program the required configuration through the following parameters:
        Transfer Direction, Source and Destination data formats, 
        Circular, Normal or peripheral flow control mode, Stream Priority level, 
        Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
        Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-                     
+
+   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
      *** Polling mode IO operation ***
-     =================================   
-    [..] 
+     =================================
+    [..]
           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
-              address and destination address and the Length of data to be transferred
+              address and destination address and the Length of data to be transferred.
           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
               case a fixed Timeout can be configured by User depending from his application.
-               
-     *** Interrupt mode IO operation ***    
-     =================================== 
-    [..]     
+          (+) Use HAL_DMA_Abort() function to abort the current transfer.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
@@ -46,72 +48,51 @@
           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
               add his own function by customization of function pointer XferCpltCallback and 
-              XferErrorCallback (i.e a member of DMA handle structure). 
-    [..]                
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
      (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
          detection.
-         
-     (#) Use HAL_DMA_Abort() function to abort the current transfer
-     
+
+     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+
      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-    
+
      -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
            possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
            Half-Word data size for the peripheral to access its data register and set Word data size
            for the Memory to gain in access time. Each two half words will be packed and written in
            a single access to a Word in the Memory).
-      
+
      -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
            and Destination. In this case the Peripheral Data Size will be applied to both Source
-           and Destination.               
-  
+           and Destination.
+
      *** DMA HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DMA HAL driver.
        
       (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
-      (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
-      (+) __HAL_DMA_GET_FLAG: Get the DMA Stream pending flags.
-      (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Stream pending flags.
-      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
-      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
-     
-     [..] 
-      (@) You can refer to the DMA HAL driver header file for more useful macros  
-  
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -128,7 +109,6 @@
 #ifdef HAL_DMA_MODULE_ENABLED
 
 /* Private types -------------------------------------------------------------*/
-
 typedef struct
 {
   __IO uint32_t ISR;   /*!< DMA interrupt status register */
@@ -141,7 +121,7 @@ typedef struct
 /** @addtogroup DMA_Private_Constants
  * @{
  */
- #define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s */
+ #define HAL_TIMEOUT_DMA_ABORT    5U  /* 5 ms */
 /**
   * @}
   */
@@ -152,11 +132,12 @@ typedef struct
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
 
 /**
   * @}
   */  
-  
+
 /* Exported functions ---------------------------------------------------------*/
 /** @addtogroup DMA_Exported_Functions
   * @{
@@ -164,32 +145,34 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
 
 /** @addtogroup DMA_Exported_Functions_Group1
   *
-@verbatim   
+@verbatim
  ===============================================================================
              ##### Initialization and de-initialization functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This section provides functions allowing to initialize the DMA Stream source
     and destination addresses, incrementation and data sizes, transfer direction, 
     circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
     [..]
     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.  
+    reference manual.
 
 @endverbatim
   * @{
   */
   
 /**
-  * @brief  Initializes the DMA according to the specified
+  * @brief  Initialize the DMA according to the specified
   *         parameters in the DMA_InitTypeDef and create the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Stream.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tmp = 0;
+  uint32_t tmp = 0U;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs;
 
   /* Check the DMA peripheral state */
   if(hdma == NULL)
@@ -216,10 +199,32 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
     assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
     assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
   }
+  
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
 
   /* Change DMA peripheral state */
   hdma->State = HAL_DMA_STATE_BUSY;
-
+  
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+  
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
   /* Get the CR register value */
   tmp = hdma->Instance->CR;
 
@@ -254,11 +259,27 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   /* Prepare the DMA Stream FIFO configuration */
   tmp |= hdma->Init.FIFOMode;
 
-  /* the FIFO threshold is not used when the FIFO mode is disabled */
+  /* The FIFO threshold is not used when the FIFO mode is disabled */
   if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
   {
     /* Get the FIFO threshold */
     tmp |= hdma->Init.FIFOThreshold;
+    
+    /* Check compatibility between FIFO threshold level and size of the memory burst */
+    /* for INCR4, INCR8, INCR16 bursts */
+    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+    {
+      if (DMA_CheckFifoParam(hdma) != HAL_OK)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        return HAL_ERROR; 
+      }
+    }
   }
   
   /* Write to DMA Stream FCR */
@@ -266,11 +287,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 
   /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
      DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
-  DMA_CalcBaseAndBitshift(hdma);
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
 
   /* Initialize the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
+                                                                                     
   /* Initialize the DMA state */
   hdma->State = HAL_DMA_STATE_READY;
 
@@ -279,14 +303,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DeInitializes the DMA peripheral 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Stream.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 {
   DMA_Base_Registers *regs;
-  
+
   /* Check the DMA peripheral state */
   if(hdma == NULL)
   {
@@ -296,40 +320,52 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   /* Check the DMA peripheral state */
   if(hdma->State == HAL_DMA_STATE_BUSY)
   {
-     return HAL_ERROR;
+    /* Return error status */
+    return HAL_BUSY;
   }
 
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
   /* Disable the selected DMA Streamx */
   __HAL_DMA_DISABLE(hdma);
 
   /* Reset DMA Streamx control register */
-  hdma->Instance->CR   = 0;
+  hdma->Instance->CR   = 0U;
 
   /* Reset DMA Streamx number of data to transfer register */
-  hdma->Instance->NDTR = 0;
+  hdma->Instance->NDTR = 0U;
 
   /* Reset DMA Streamx peripheral address register */
-  hdma->Instance->PAR  = 0;
+  hdma->Instance->PAR  = 0U;
 
   /* Reset DMA Streamx memory 0 address register */
-  hdma->Instance->M0AR = 0;
+  hdma->Instance->M0AR = 0U;
   
   /* Reset DMA Streamx memory 1 address register */
-  hdma->Instance->M1AR = 0;
+  hdma->Instance->M1AR = 0U;
   
   /* Reset DMA Streamx FIFO control register */
-  hdma->Instance->FCR  = (uint32_t)0x00000021;
+  hdma->Instance->FCR  = 0x00000021U;
   
   /* Get DMA steam Base Address */  
   regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
   
+  /* Clean all callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferM1CpltCallback = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;
+
   /* Clear all interrupt flags at correct offset within the register */
-  regs->IFCR = 0x3F << hdma->StreamIndex;
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
 
-  /* Initialize the error code */
+  /* Reset the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 
-  /* Initialize the DMA state */
+  /* Reset the DMA state */
   hdma->State = HAL_DMA_STATE_RESET;
 
   /* Release Lock */
@@ -347,7 +383,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 @verbatim   
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Configure the source, destination address and data length and Start DMA transfer
       (+) Configure the source, destination address and data length and 
@@ -362,75 +398,110 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Starts the DMA Transfer.
-  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-   /* Check the parameters */
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
 
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+  /* Process locked */
+  __HAL_LOCK(hdma);
 
-  /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 
-  return HAL_OK; 
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  } 
+  return status; 
 }
 
 /**
   * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
+  HAL_StatusTypeDef status = HAL_OK;
 
-   /* Check the parameters */
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable all interrupts */
-  hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
-  hdma->Instance->FCR |= DMA_IT_FE;
-
-   /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
-} 
+ 
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }
+  
+  return status;
+}
 
 /**
   * @brief  Aborts the DMA Transfer.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                 the configuration information for the specified DMA Stream.
   *                   
   * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
@@ -442,344 +513,373 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
   */
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tickstart = 0;
-
-  /* Disable the stream */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check if the DMA Stream is effectively disabled */
-  while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  uint32_t tickstart = HAL_GetTick();
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
   {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+    hdma->Instance->FCR &= ~(DMA_IT_FE);
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
     {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
+      hdma->Instance->CR  &= ~(DMA_IT_HT);
+    }
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Check if the DMA Stream is effectively disabled */
+    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        
+        return HAL_TIMEOUT;
+      }
     }
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Change the DMA state*/
+    hdma->State = HAL_DMA_STATE_READY;
   }
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma);
+  return HAL_OK;
+}
 
-  /* Change the DMA state*/
-  hdma->State = HAL_DMA_STATE_READY;
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hdma->State = HAL_DMA_STATE_ABORT;
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+  }
 
   return HAL_OK;
 }
 
 /**
   * @brief  Polling for transfer complete.
-  * @param  hdma:          pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
   *                        the configuration information for the specified DMA Stream.
-  * @param  CompleteLevel: Specifies the DMA level complete.  
-  * @param  Timeout:       Timeout duration.
+  * @param  CompleteLevel Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
+  * @param  Timeout       Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
 {
-  uint32_t temp, tmp, tmp1, tmp2;
-  uint32_t tickstart = 0;
-
+  HAL_StatusTypeDef status = HAL_OK; 
+  uint32_t mask_cpltlevel;
+  uint32_t tickstart = HAL_GetTick(); 
+  uint32_t tmpisr;
+  
   /* calculate DMA base and stream number */
   DMA_Base_Registers *regs;
-  
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode and double buffering mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
   /* Get the level transfer complete flag */
   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
   {
     /* Transfer Complete flag */
-    temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
   }
   else
   {
     /* Half Transfer Complete flag */
-    temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
   }
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while((regs->ISR & temp) == RESET)
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
+  
+  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
   {
-    tmp  = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
-    tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
-    tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
-    if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
-    {
-      if(tmp != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-        /* Clear the transfer error flag */
-        regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-      }
-      if(tmp1 != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-        /* Clear the FIFO error flag */
-        regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-      }
-      if(tmp2 != RESET)
-      {
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-        /* Clear the Direct Mode error flag */
-        regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-      }
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-    }
-    /* Check for the Timeout */
+    /* Check for the Timeout (Not applicable in circular mode)*/
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 
         /* Process Unlocked */
         __HAL_UNLOCK(hdma);
-
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
         return HAL_TIMEOUT;
       }
     }
-  }
 
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    /* Get the ISR register value */
+    tmpisr = regs->ISR;
 
-    /* Multi_Buffering mode enabled */
-    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
     {
-      /* Current memory buffer used is Memory 0 */
-      if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_MEM0;
-      }
-      /* Current memory buffer used is Memory 1 */
-      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_MEM1;
-      }
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
     }
-    else
+    
+    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
     {
-      /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
-         are complete) */
-      hdma->State = HAL_DMA_STATE_READY_MEM0;
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      
+      /* Clear the Direct Mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
     }
+  }
+  
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      HAL_DMA_Abort(hdma);
+    
+      /* Clear the half transfer and transfer complete flags */
+      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      return HAL_ERROR;
+   }
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
+
+    hdma->State = HAL_DMA_STATE_READY;
   }
   else
   {
-    /* Clear the half transfer complete flag */
-    regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
-    /* Multi_Buffering mode enabled */
-    if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
-    {
-      /* Current memory buffer used is Memory 0 */
-      if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-      }
-      /* Current memory buffer used is Memory 1 */
-      else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
-      {
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
-      }
-    }
-    else
-    {
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-    }
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
   }
-  return HAL_OK;
+  
+  return status;
 }
 
 /**
   * @brief  Handles DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Stream.  
   * @retval None
   */
 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 {
+  uint32_t tmpisr;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
   /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs;
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
 
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
 
   /* Transfer Error Interrupt management ***************************************/
-  if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
     {
       /* Disable the transfer error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
+      hdma->Instance->CR  &= ~(DMA_IT_TE);
+      
       /* Clear the transfer error flag */
       regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-
+      
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* FIFO Error Interrupt management ******************************************/
-  if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
     {
-      /* Disable the FIFO Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
-
       /* Clear the FIFO error flag */
       regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* Direct Mode Error Interrupt management ***********************************/
-  if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
     {
-      /* Disable the direct mode Error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
-
       /* Clear the direct mode error flag */
       regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
 
       /* Update error code */
       hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      if(hdma->XferErrorCallback != NULL)
-      {
-        /* Transfer error callback */
-        hdma->XferErrorCallback(hdma);
-      }
     }
   }
   /* Half Transfer Complete Interrupt management ******************************/
-  if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
     {
+      /* Clear the half transfer complete flag */
+      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+      
       /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
       {
-        /* Clear the half transfer complete flag */
-        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
         /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
         {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
         }
         /* Current memory buffer used is Memory 1 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+        else
         {
-          /* Change DMA peripheral state */
-          hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
         }
       }
       else
       {
         /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
         {
           /* Disable the half transfer interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+        
+        if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
         }
-        /* Clear the half transfer complete flag */
-        regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-
-        /* Change DMA peripheral state */
-        hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
-      }
-
-      if(hdma->XferHalfCpltCallback != NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
       }
     }
   }
   /* Transfer Complete Interrupt management ***********************************/
-  if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
   {
     if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
     {
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
+      /* Clear the transfer complete flag */
+      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+      
+      if(HAL_DMA_STATE_ABORT == hdma->State)
       {
-        /* Clear the transfer complete flag */
-        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+        /* Disable all the transfer interrupts */
+        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+        hdma->Instance->FCR &= ~(DMA_IT_FE);
+        
+        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+        {
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
 
-        /* Current memory buffer used is Memory 1 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+        /* Clear all interrupt flags at correct offset within the register */
+        regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        if(hdma->XferAbortCallback != NULL)
+        {
+          hdma->XferAbortCallback(hdma);
+        }
+        return;
+      }
+
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
         {
           if(hdma->XferM1CpltCallback != NULL)
           {
@@ -787,8 +887,8 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
             hdma->XferM1CpltCallback(hdma);
           }
         }
-        /* Current memory buffer used is Memory 0 */
-        else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+        /* Current memory buffer used is Memory 1 */
+        else
         {
           if(hdma->XferCpltCallback != NULL)
           {
@@ -800,22 +900,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
       else
       {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
         {
           /* Disable the transfer complete interrupt */
-          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
-        }
-        /* Clear the transfer complete flag */
-        regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+          hdma->Instance->CR  &= ~(DMA_IT_TC);
 
-        /* Update error code */
-        hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
 
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY_MEM0;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+        }
 
         if(hdma->XferCpltCallback != NULL)
         {
@@ -825,6 +920,169 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       }
     }
   }
+  
+  /* manage error case */
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+
+      do
+      {
+        if (++count > timeout)
+        {
+          break;
+        }
+      }
+      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+    }
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifer
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback            pointer to private callbacsk function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                      
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifer
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
 }
 
 /**
@@ -848,7 +1106,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Stream.
   * @retval HAL state
   */
@@ -859,7 +1117,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *              the configuration information for the specified DMA Stream.
   * @retval DMA Error Code
   */
@@ -875,18 +1133,18 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-  
+
 /** @addtogroup DMA_Private_Functions
   * @{
   */
 
 /**
   * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -897,7 +1155,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
   /* Configure DMA Stream data length */
   hdma->Instance->NDTR = DataLength;
 
-  /* Peripheral to Memory */
+  /* Memory to Peripheral */
   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
   {
     /* Configure DMA Stream destination address */
@@ -906,12 +1164,12 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
     /* Configure DMA Stream source address */
     hdma->Instance->M0AR = SrcAddress;
   }
-  /* Memory to Peripheral */
+  /* Peripheral to Memory */
   else
   {
     /* Configure DMA Stream source address */
     hdma->Instance->PAR = SrcAddress;
-    
+
     /* Configure DMA Stream destination address */
     hdma->Instance->M0AR = DstAddress;
   }
@@ -919,35 +1177,122 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
 
 /**
   * @brief  Returns the DMA Stream base address depending on stream number
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream. 
   * @retval Stream base address
   */
 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
 {
-  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
+  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
   
   /* lookup table for necessary bitshift of flags within status registers */
-  static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
+  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
   hdma->StreamIndex = flagBitshiftOffset[stream_number];
   
-  if (stream_number > 3)
+  if (stream_number > 3U)
   {
     /* return pointer to HISR and HIFCR */
-    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
+    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
   }
   else
   {
     /* return pointer to LISR and LIFCR */
-    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
+    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
   }
   
   return hdma->StreamBaseAddress;
 }
+
 /**
-  * @}
-  */  
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmp = hdma->Init.FIFOThreshold;
+  
+  /* Memory Data size equal to Byte */
+  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      break;
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;   
+    default:
+      break;
+    }
+  }
   
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+    }
+  } 
+  
+  return status; 
+}
+
+/**
+  * @}
+  */
+
 #endif /* HAL_DMA_MODULE_ENABLED */
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c
index aa68fc09..53bec8e2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma_ex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_dma_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   DMA Extension HAL module driver
   *         This file provides firmware functions to manage the following 
   *         functionalities of the DMA Extension peripheral:
@@ -27,29 +25,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -87,6 +69,7 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   * @{
   */
 
+
 /** @addtogroup DMAEx_Exported_Functions_Group1
   *
 @verbatim   
@@ -104,124 +87,151 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   * @{
   */
 
+
 /**
   * @brief  Starts the multi_buffer DMA Transfer.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *         the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  /* Process Locked */
-  __HAL_LOCK(hdma);
-
-  /* Current memory buffer used is Memory 0 */
-  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
   {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
   }
-  /* Current memory buffer used is Memory 1 */
-  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+  else
   {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+    
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY; 
+      
+      /* Enable the double buffer mode */
+      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+      
+      /* Configure DMA Stream destination address */
+      hdma->Instance->M1AR = SecondMemAddress;
+      
+      /* Configure the source, destination address and the data length */
+      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+      
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_BUSY;
+    }
   }
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);  
-
-  /* Enable the double buffer mode */
-  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-
-  /* Configure DMA Stream destination address */
-  hdma->Instance->M1AR = SecondMemAddress;
-
-  /* Configure the source, destination address and the data length */
-  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the peripheral */
-  __HAL_DMA_ENABLE(hdma);
-
-  return HAL_OK;
+  return status;
 }
 
 /**
   * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *         the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
 {
-  /* Process Locked */
-  __HAL_LOCK(hdma);
-
-  /* Current memory buffer used is Memory 0 */
-  if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
   {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM0;
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
   }
-  /* Current memory buffer used is Memory 1 */
-  else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
+  
+  /* Check callback functions */
+  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
   {
-    hdma->State = HAL_DMA_STATE_BUSY_MEM1;
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    return HAL_ERROR;
   }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);  
-
-  /* Enable the Double buffer mode */
-  hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-
-  /* Configure DMA Stream destination address */
-  hdma->Instance->M1AR = SecondMemAddress;
-
-  /* Configure the source, destination address and the data length */
-  DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
-
-  /* Enable the transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
-  /* Enable the Half transfer interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
-  /* Enable the fifo Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);  
-
-  /* Enable the direct mode Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); 
-
-  /* Enable the peripheral */
-  __HAL_DMA_ENABLE(hdma); 
-
-  return HAL_OK; 
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Enable the Double buffer mode */
+    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M1AR = SecondMemAddress;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+    
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma); 
+  }
+  else
+  {     
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }  
+  return status; 
 }
 
 /**
   * @brief  Change the memory0 or memory1 address on the fly.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *         the configuration information for the specified DMA Stream.  
-  * @param  Address: The new address
-  * @param  memory: the memory to be changed, This parameter can be one of 
-  *         the following values:
-  *              MEMORY0 /
-  *              MEMORY1
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  Address    The new address
+  * @param  memory     the memory to be changed, This parameter can be one of 
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
   * @note   The MEMORY0 address can be changed only when the current transfer use
   *         MEMORY1 and the MEMORY1 address can be changed only when the current 
   *         transfer use MEMORY0.
@@ -257,11 +267,11 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
 
 /**
   * @brief  Set the DMA Transfer parameter.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *         the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_eth.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_eth.c
index 80e181c5..9a5c7229 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_eth.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_eth.c
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_eth.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   ETH HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Ethernet (ETH) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State and Errors functions
   *
   @verbatim
@@ -19,21 +17,21 @@
     [..]
       (#)Declare a ETH_HandleTypeDef handle structure, for example:
          ETH_HandleTypeDef  heth;
-        
+
       (#)Fill parameters of Init structure in heth handle
-  
-      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) 
+
+      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
 
       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
-          (##) Enable the Ethernet interface clock using 
+          (##) Enable the Ethernet interface clock using
                (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
                (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
                (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
-           
+
           (##) Initialize the related GPIO clocks
           (##) Configure Ethernet pin-out
-          (##) Configure Ethernet NVIC interrupt (IT mode)   
-    
+          (##) Configure Ethernet NVIC interrupt (IT mode)
+
       (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
           (##) HAL_ETH_DMATxDescListInit(); for Transmission process
           (##) HAL_ETH_DMARxDescListInit(); for Reception process
@@ -41,11 +39,11 @@
       (#)Enable MAC and DMA transmission and reception:
           (##) HAL_ETH_Start();
 
-      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer 
+      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
          the frame to MAC TX FIFO:
          (##) HAL_ETH_TransmitFrame();
 
-      (#)Poll for a received frame in ETH RX DMA Descriptors and get received 
+      (#)Poll for a received frame in ETH RX DMA Descriptors and get received
          frame parameters
          (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
 
@@ -53,47 +51,80 @@
          (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
 
       (#) Communicate with external PHY device:
-         (##) Read a specific register from the PHY  
+         (##) Read a specific register from the PHY
               HAL_ETH_ReadPHYRegister();
          (##) Write data to a specific RHY register:
               HAL_ETH_WritePHYRegister();
 
       (#) Configure the Ethernet MAC after ETH peripheral initialization
           HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
-      
+
       (#) Configure the Ethernet DMA after ETH peripheral initialization
           HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
 
+*** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+  Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) DMAErrorCallback : DMA Error Callback.
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) DMAErrorCallback : DMA Error Callback.
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+  or HAL_ETH_Init function.
+
+  When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -102,22 +133,23 @@
   * @{
   */
 
-/** @defgroup ETH ETH 
+/** @defgroup ETH ETH
   * @brief ETH HAL module driver
   * @{
   */
 
 #ifdef HAL_ETH_MODULE_ENABLED
 
-#if defined(STM32F207xx) || defined(STM32F217xx)
+#if defined (ETH)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @defgroup ETH_Private_Constants ETH Private Constants
   * @{
   */
-#define LINKED_STATE_TIMEOUT_VALUE          ((uint32_t)2000)  /* 2000 ms */
-#define AUTONEGO_COMPLETED_TIMEOUT_VALUE    ((uint32_t)1000)  /* 1000 ms */
+#define ETH_TIMEOUT_SWRESET                500U
+#define ETH_TIMEOUT_LINKED_STATE           5000U
+#define ETH_TIMEOUT_AUTONEGO_COMPLETED     5000U
 
 /**
   * @}
@@ -139,6 +171,10 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+static void ETH_Delay(uint32_t mdelay);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -149,10 +185,10 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
   * @{
   */
 
-/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief   Initialization and Configuration functions 
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief   Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ===============================================================================
             ##### Initialization and de-initialization functions #####
   ===============================================================================
@@ -167,216 +203,245 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
 /**
   * @brief  Initializes the Ethernet MAC and DMA according to default
   *         parameters.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
 {
-  uint32_t tmpreg1 = 0, phyreg = 0;
-  uint32_t hclk = 60000000;
-  uint32_t tickstart = 0;
+  uint32_t tmpreg1 = 0U, phyreg = 0U;
+  uint32_t hclk = 60000000U;
+  uint32_t tickstart = 0U;
   uint32_t err = ETH_SUCCESS;
-  
+
   /* Check the ETH peripheral state */
-  if(heth == NULL)
+  if (heth == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check parameters */
   assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
   assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
   assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
-  assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));  
-  
-  if(heth->State == HAL_ETH_STATE_RESET)
+  assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
+
+  if (heth->State == HAL_ETH_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     heth->Lock = HAL_UNLOCKED;
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    ETH_InitCallbacksToDefault(heth);
+
+    if (heth->MspInitCallback == NULL)
+    {
+      /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+      heth->MspInitCallback = HAL_ETH_MspInit;
+    }
+    heth->MspInitCallback(heth);
+
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
     HAL_ETH_MspInit(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
   }
-  
+
   /* Enable SYSCFG Clock */
   __HAL_RCC_SYSCFG_CLK_ENABLE();
-  
+
   /* Select MII or RMII Mode*/
   SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
   SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
-  
+
   /* Ethernet Software reset */
   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
   /* After reset all the registers holds their respective reset values */
   (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
-  
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
   /* Wait for software reset */
   while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
   {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_SWRESET)
+    {
+      heth->State = HAL_ETH_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(heth);
+
+      /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
+         not available, please check your external PHY or the IO configuration */
+      return HAL_TIMEOUT;
+    }
   }
-  
+
   /*-------------------------------- MAC Initialization ----------------------*/
   /* Get the ETHERNET MACMIIAR value */
   tmpreg1 = (heth->Instance)->MACMIIAR;
   /* Clear CSR Clock Range CR[2:0] bits */
   tmpreg1 &= ETH_MACMIIAR_CR_MASK;
-  
+
   /* Get hclk frequency value */
   hclk = HAL_RCC_GetHCLKFreq();
-  
+
   /* Set CR bits depending on hclk value */
-  if((hclk >= 20000000)&&(hclk < 35000000))
+  if ((hclk >= 20000000U) && (hclk < 35000000U))
   {
     /* CSR Clock Range between 20-35 MHz */
     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
   }
-  else if((hclk >= 35000000)&&(hclk < 60000000))
+  else if ((hclk >= 35000000U) && (hclk < 60000000U))
   {
-    /* CSR Clock Range between 35-60 MHz */ 
+    /* CSR Clock Range between 35-60 MHz */
     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
-  }  
-  else if((hclk >= 60000000)&&(hclk < 100000000))
+  }
+  else if ((hclk >= 60000000U) && (hclk < 100000000U))
   {
-    /* CSR Clock Range between 60-100 MHz */ 
+    /* CSR Clock Range between 60-100 MHz */
     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
-  }  
+  }
   else /* ((hclk >= 100000000)&&(hclk < 120000000)) */
   {
-    /* CSR Clock Range between 100-120 MHz */ 
+    /* CSR Clock Range between 100-120 MHz */
     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
   }
-  
+
   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
   (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
-  
+
   /*-------------------- PHY initialization and configuration ----------------*/
   /* Put the PHY in reset mode */
-  if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
+  if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
   {
     /* In case of write timeout */
     err = ETH_ERROR;
-    
+
     /* Config MAC and DMA */
     ETH_MACDMAConfig(heth, err);
-    
+
     /* Set the ETH peripheral state to READY */
     heth->State = HAL_ETH_STATE_READY;
-    
+
     /* Return HAL_ERROR */
     return HAL_ERROR;
   }
-  
+
   /* Delay to assure PHY reset */
   HAL_Delay(PHY_RESET_DELAY);
-  
-  if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
+
+  if ((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
   {
     /* Get tick */
     tickstart = HAL_GetTick();
-    
+
     /* We wait for linked status */
     do
     {
       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
-      
+
       /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_LINKED_STATE)
       {
         /* In case of write timeout */
         err = ETH_ERROR;
-      
+
         /* Config MAC and DMA */
         ETH_MACDMAConfig(heth, err);
-        
-        heth->State= HAL_ETH_STATE_READY;
-  
+
+        heth->State = HAL_ETH_STATE_READY;
+
         /* Process Unlocked */
         __HAL_UNLOCK(heth);
-    
+
         return HAL_TIMEOUT;
       }
-    } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
+    }
+    while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
+
 
-    
     /* Enable Auto-Negotiation */
-    if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
+    if ((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
     {
       /* In case of write timeout */
       err = ETH_ERROR;
-      
+
       /* Config MAC and DMA */
       ETH_MACDMAConfig(heth, err);
-      
+
       /* Set the ETH peripheral state to READY */
       heth->State = HAL_ETH_STATE_READY;
-      
+
       /* Return HAL_ERROR */
-      return HAL_ERROR;   
+      return HAL_ERROR;
     }
-    
+
     /* Get tick */
     tickstart = HAL_GetTick();
-    
+
     /* Wait until the auto-negotiation will be completed */
     do
     {
       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
-      
+
       /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
       {
         /* In case of write timeout */
         err = ETH_ERROR;
-      
+
         /* Config MAC and DMA */
         ETH_MACDMAConfig(heth, err);
-        
-        heth->State= HAL_ETH_STATE_READY;
-  
+
+        heth->State = HAL_ETH_STATE_READY;
+
         /* Process Unlocked */
         __HAL_UNLOCK(heth);
-    
+
         return HAL_TIMEOUT;
       }
-      
-    } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
-    
+
+    }
+    while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
+
     /* Read the result of the auto-negotiation */
-    if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
+    if ((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
     {
       /* In case of write timeout */
       err = ETH_ERROR;
-      
+
       /* Config MAC and DMA */
       ETH_MACDMAConfig(heth, err);
-      
+
       /* Set the ETH peripheral state to READY */
       heth->State = HAL_ETH_STATE_READY;
-      
+
       /* Return HAL_ERROR */
-      return HAL_ERROR;   
+      return HAL_ERROR;
     }
-    
+
     /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
-    if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
+    if ((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
     {
       /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
-      (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;  
+      (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
     }
     else
     {
       /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
-      (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;           
+      (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
     }
     /* Configure the MAC with the speed fixed by the auto-negotiation process */
-    if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
-    {  
+    if ((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
+    {
       /* Set Ethernet speed to 10M following the auto-negotiation */
-      (heth->Init).Speed = ETH_SPEED_10M; 
+      (heth->Init).Speed = ETH_SPEED_10M;
     }
     else
-    {   
-      /* Set Ethernet speed to 100M following the auto-negotiation */ 
+    {
+      /* Set Ethernet speed to 100M following the auto-negotiation */
       (heth->Init).Speed = ETH_SPEED_100M;
     }
   }
@@ -385,41 +450,41 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
     /* Check parameters */
     assert_param(IS_ETH_SPEED(heth->Init.Speed));
     assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
-    
+
     /* Set MAC Speed and Duplex Mode */
-    if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
-                                                (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
+    if (HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
+                                                 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
     {
       /* In case of write timeout */
       err = ETH_ERROR;
-      
+
       /* Config MAC and DMA */
       ETH_MACDMAConfig(heth, err);
-      
+
       /* Set the ETH peripheral state to READY */
       heth->State = HAL_ETH_STATE_READY;
-      
+
       /* Return HAL_ERROR */
       return HAL_ERROR;
-    }  
-    
+    }
+
     /* Delay to assure PHY configuration */
     HAL_Delay(PHY_CONFIG_DELAY);
   }
-  
+
   /* Config MAC and DMA */
   ETH_MACDMAConfig(heth, err);
-  
+
   /* Set ETH HAL State to Ready */
-  heth->State= HAL_ETH_STATE_READY;
-  
+  heth->State = HAL_ETH_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  De-Initializes the ETH peripheral. 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @brief  De-Initializes the ETH peripheral.
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
@@ -427,12 +492,21 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
 {
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+  if (heth->MspDeInitCallback == NULL)
+  {
+    heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+  }
+  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+  heth->MspDeInitCallback(heth);
+#else
   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
   HAL_ETH_MspDeInit(heth);
-  
+#endif
+
   /* Set ETH HAL state to Disabled */
-  heth->State= HAL_ETH_STATE_RESET;
+  heth->State = HAL_ETH_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(heth);
@@ -443,149 +517,151 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
 
 /**
   * @brief  Initializes the DMA Tx descriptors in chain mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module  
-  * @param  DMATxDescTab: Pointer to the first Tx desc list 
-  * @param  TxBuff: Pointer to the first TxBuffer list
-  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  DMATxDescTab Pointer to the first Tx desc list
+  * @param  TxBuff Pointer to the first TxBuffer list
+  * @param  TxBuffCount Number of the used Tx desc in the list
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
 {
-  uint32_t i = 0;
+  uint32_t i = 0U;
   ETH_DMADescTypeDef *dmatxdesc;
-  
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
   heth->TxDesc = DMATxDescTab;
-  
-  /* Fill each DMATxDesc descriptor with the right values */   
-  for(i=0; i < TxBuffCount; i++)
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for (i = 0U; i < TxBuffCount; i++)
   {
     /* Get the pointer on the ith member of the Tx Desc list */
     dmatxdesc = DMATxDescTab + i;
-    
+
     /* Set Second Address Chained bit */
-    dmatxdesc->Status = ETH_DMATXDESC_TCH;  
-    
+    dmatxdesc->Status = ETH_DMATXDESC_TCH;
+
     /* Set Buffer1 address pointer */
-    dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
-    
+    dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_TX_BUF_SIZE]);
+
     if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
     {
       /* Set the DMA Tx descriptors checksum insertion */
       dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
     }
-    
+
     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
-    if(i < (TxBuffCount-1))
+    if (i < (TxBuffCount - 1))
     {
       /* Set next descriptor address register with next descriptor base address */
-      dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+      dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1);
     }
     else
     {
-      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
-      dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
     }
   }
-  
+
   /* Set Transmit Descriptor List Address Register */
   (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
-  
+
   /* Set ETH HAL State to Ready */
-  heth->State= HAL_ETH_STATE_READY;
-  
+  heth->State = HAL_ETH_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the DMA Rx descriptors in chain mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module  
-  * @param  DMARxDescTab: Pointer to the first Rx desc list 
-  * @param  RxBuff: Pointer to the first RxBuffer list
-  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  DMARxDescTab Pointer to the first Rx desc list
+  * @param  RxBuff Pointer to the first RxBuffer list
+  * @param  RxBuffCount Number of the used Rx desc in the list
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
 {
-  uint32_t i = 0;
+  uint32_t i = 0U;
   ETH_DMADescTypeDef *DMARxDesc;
-  
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
-  heth->RxDesc = DMARxDescTab; 
-  
+  heth->RxDesc = DMARxDescTab;
+
   /* Fill each DMARxDesc descriptor with the right values */
-  for(i=0; i < RxBuffCount; i++)
+  for (i = 0U; i < RxBuffCount; i++)
   {
     /* Get the pointer on the ith member of the Rx Desc list */
-    DMARxDesc = DMARxDescTab+i;
-    
+    DMARxDesc = DMARxDescTab + i;
+
     /* Set Own bit of the Rx descriptor Status */
     DMARxDesc->Status = ETH_DMARXDESC_OWN;
-    
+
     /* Set Buffer1 size and Second Address Chained bit */
-    DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;  
-    
+    DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
+
     /* Set Buffer1 address pointer */
-    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
-    
-    if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_RX_BUF_SIZE]);
+
+    if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
     {
       /* Enable Ethernet DMA Rx Descriptor interrupt */
       DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
     }
-    
+
     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
-    if(i < (RxBuffCount-1))
+    if (i < (RxBuffCount - 1U))
     {
       /* Set next descriptor address register with next descriptor base address */
-      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1U);
     }
     else
     {
-      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
-      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
     }
   }
-  
+
   /* Set Receive Descriptor List Address Register */
   (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
-  
+
   /* Set ETH HAL State to Ready */
-  heth->State= HAL_ETH_STATE_READY;
-  
+  heth->State = HAL_ETH_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the ETH MSP.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_MspInit could be implemented in the user file
   */
@@ -593,28 +669,197 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
 
 /**
   * @brief  DeInitializes ETH MSP.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_MspDeInit could be implemented in the user file
   */
 }
 
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ETH Callback
+  *         To be used instead of the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(heth);
+
+  if (heth->State == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_ETH_DMA_ERROR_CB_ID :
+        heth->DMAErrorCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (heth->State == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(heth);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an ETH Callback
+  *         ETH callabck is redirected to the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID      DMA Error Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(heth);
+
+  if (heth->State == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+        break;
+
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+        break;
+
+      case HAL_ETH_DMA_ERROR_CB_ID :
+        heth->DMAErrorCallback = HAL_ETH_ErrorCallback;
+        break;
+
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (heth->State == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
+
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(heth);
+
+  return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup ETH_Exported_Functions_Group2 IO operation functions 
-  *  @brief   Data transfers functions 
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+  *  @brief   Data transfers functions
   *
-  @verbatim   
+  @verbatim
   ==============================================================================
                           ##### IO operation functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]  This section provides functions allowing to:
         (+) Transmit a frame
             HAL_ETH_TransmitFrame();
@@ -627,234 +872,234 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
             HAL_ETH_WritePHYRegister();
 
   @endverbatim
-  
+
   * @{
   */
 
 /**
-  * @brief  Sends an Ethernet frame. 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @brief  Sends an Ethernet frame.
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  FrameLength: Amount of data to be sent
+  * @param  FrameLength Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
 {
-  uint32_t bufcount = 0, size = 0, i = 0;
-  
+  uint32_t bufcount = 0U, size = 0U, i = 0U;
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
-  if (FrameLength == 0) 
+
+  if (FrameLength == 0U)
   {
     /* Set ETH HAL state to READY */
     heth->State = HAL_ETH_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(heth);
-    
-    return  HAL_ERROR;                                    
-  }  
-  
+
+    return  HAL_ERROR;
+  }
+
   /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
-  if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
-  {  
+  if (((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
+  {
     /* OWN bit set */
     heth->State = HAL_ETH_STATE_BUSY_TX;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(heth);
-    
+
     return HAL_ERROR;
   }
-  
+
   /* Get the number of needed Tx buffers for the current frame */
   if (FrameLength > ETH_TX_BUF_SIZE)
   {
-    bufcount = FrameLength/ETH_TX_BUF_SIZE;
-    if (FrameLength % ETH_TX_BUF_SIZE) 
+    bufcount = FrameLength / ETH_TX_BUF_SIZE;
+    if (FrameLength % ETH_TX_BUF_SIZE)
     {
       bufcount++;
     }
   }
-  else 
-  {  
-    bufcount = 1;
+  else
+  {
+    bufcount = 1U;
   }
-  if (bufcount == 1)
+  if (bufcount == 1U)
   {
     /* Set LAST and FIRST segment */
-    heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
+    heth->TxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
     /* Set frame size */
     heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
     heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
     /* Point to next descriptor */
-    heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
+    heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
   }
   else
   {
-    for (i=0; i< bufcount; i++)
+    for (i = 0U; i < bufcount; i++)
     {
       /* Clear FIRST and LAST segment bits */
       heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
-      
-      if (i == 0) 
+
+      if (i == 0U)
       {
         /* Setting the first segment bit */
-        heth->TxDesc->Status |= ETH_DMATXDESC_FS;  
+        heth->TxDesc->Status |= ETH_DMATXDESC_FS;
       }
-      
+
       /* Program size */
       heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
-      
-      if (i == (bufcount-1))
+
+      if (i == (bufcount - 1U))
       {
         /* Setting the last segment bit */
         heth->TxDesc->Status |= ETH_DMATXDESC_LS;
-        size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
+        size = FrameLength - (bufcount - 1U) * ETH_TX_BUF_SIZE;
         heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
       }
-      
+
       /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
       heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
       /* point to next descriptor */
       heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
     }
   }
-  
+
   /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
   if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
   {
     /* Clear TBUS ETHERNET DMA flag */
     (heth->Instance)->DMASR = ETH_DMASR_TBUS;
     /* Resume DMA transmission*/
-    (heth->Instance)->DMATPDR = 0;
+    (heth->Instance)->DMATPDR = 0U;
   }
-  
+
   /* Set ETH HAL State to Ready */
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Checks for received frames. 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @brief  Checks for received frames.
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
 {
-  uint32_t framelength = 0;
-  
+  uint32_t framelength = 0U;
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Check the ETH state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Check if segment is not owned by DMA */
   /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
-  if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
+  if (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
   {
     /* Check if last segment */
-    if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) 
+    if (((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
     {
       /* increment segment count */
       (heth->RxFrameInfos).SegCount++;
-      
+
       /* Check if last segment is first segment: one segment contains the frame */
-      if ((heth->RxFrameInfos).SegCount == 1)
+      if ((heth->RxFrameInfos).SegCount == 1U)
       {
-        (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
+        (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
       }
-      
+
       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
-      
+
       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
-      framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+      framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
       heth->RxFrameInfos.length = framelength;
-      
+
       /* Get the address of the buffer start address */
       heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
       /* point to next descriptor */
-      heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
-      
+      heth->RxDesc = (ETH_DMADescTypeDef *)((heth->RxDesc)->Buffer2NextDescAddr);
+
       /* Set HAL State to Ready */
       heth->State = HAL_ETH_STATE_READY;
-      
+
       /* Process Unlocked */
       __HAL_UNLOCK(heth);
-      
+
       /* Return function status */
       return HAL_OK;
     }
     /* Check if first segment */
-    else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
+    else if ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
     {
       (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
       (heth->RxFrameInfos).LSRxDesc = NULL;
-      (heth->RxFrameInfos).SegCount = 1;
+      (heth->RxFrameInfos).SegCount = 1U;
       /* Point to next descriptor */
-      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+      heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
     }
-    /* Check if intermediate segment */ 
+    /* Check if intermediate segment */
     else
     {
       (heth->RxFrameInfos).SegCount++;
       /* Point to next descriptor */
-      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
-    } 
+      heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
+    }
   }
-  
+
   /* Set ETH HAL State to Ready */
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
 
 /**
-  * @brief  Gets the Received frame in interrupt mode. 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @brief  Gets the Received frame in interrupt mode.
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
 {
-  uint32_t descriptorscancounter = 0;
-  
+  uint32_t descriptorscancounter = 0U;
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set ETH HAL State to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Scan descriptors owned by CPU */
   while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
   {
     /* Just for security */
     descriptorscancounter++;
-    
+
     /* Check if first segment in frame */
-    /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */  
-    if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
-    { 
+    /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
+    if ((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
+    {
       heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
-      heth->RxFrameInfos.SegCount = 1;   
+      heth->RxFrameInfos.SegCount = 1U;
       /* Point to next descriptor */
-      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
+      heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
     }
     /* Check if intermediate segment */
     /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
@@ -863,38 +1108,38 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
       /* Increment segment count */
       (heth->RxFrameInfos.SegCount)++;
       /* Point to next descriptor */
-      heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
+      heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
     }
     /* Should be last segment */
     else
-    { 
+    {
       /* Last segment */
       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
-      
+
       /* Increment segment count */
       (heth->RxFrameInfos.SegCount)++;
-      
+
       /* Check if last segment is first segment: one segment contains the frame */
-      if ((heth->RxFrameInfos.SegCount) == 1)
+      if ((heth->RxFrameInfos.SegCount) == 1U)
       {
         heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
       }
-      
+
       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
-      heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
-      
-      /* Get the address of the buffer start address */ 
-      heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
-      
-      /* Point to next descriptor */      
-      heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
-      
+      heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
+
+      /* Get the address of the buffer start address */
+      heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
+
+      /* Point to next descriptor */
+      heth->RxDesc = (ETH_DMADescTypeDef *)(heth->RxDesc->Buffer2NextDescAddr);
+
       /* Set HAL State to Ready */
       heth->State = HAL_ETH_STATE_READY;
-      
+
       /* Process Unlocked */
       __HAL_UNLOCK(heth);
-  
+
       /* Return function status */
       return HAL_OK;
     }
@@ -902,69 +1147,83 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
 
   /* Set HAL State to Ready */
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
 
 /**
   * @brief  This function handles ETH interrupt request.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
 {
   /* Frame received */
-  if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) 
+  if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
   {
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Receive complete callback*/
+    heth->RxCpltCallback(heth);
+#else
     /* Receive complete callback */
     HAL_ETH_RxCpltCallback(heth);
-    
-     /* Clear the Eth DMA Rx IT pending bits */
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    /* Clear the Eth DMA Rx IT pending bits */
     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
 
     /* Set HAL State to Ready */
     heth->State = HAL_ETH_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(heth);
 
   }
   /* Frame transmitted */
-  else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) 
+  else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
   {
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*  Call resgistered Transfer complete callback*/
+    heth->TxCpltCallback(heth);
+#else
     /* Transfer complete callback */
     HAL_ETH_TxCpltCallback(heth);
-    
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
     /* Clear the Eth DMA Tx IT pending bits */
     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
 
     /* Set HAL State to Ready */
     heth->State = HAL_ETH_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(heth);
   }
-  
+
   /* Clear the interrupt flags */
   __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
-  
+
   /* ETH DMA Error */
-  if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
+  if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
   {
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    heth->DMAErrorCallback(heth);
+#else
     /* Ethernet Error callback */
     HAL_ETH_ErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
     /* Clear the interrupt flags */
     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
-  
+
     /* Set HAL State to Ready */
     heth->State = HAL_ETH_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(heth);
   }
@@ -972,186 +1231,192 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
 
 /**
   * @brief  Tx Transfer completed callbacks.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
-  */ 
+  */
 }
 
 /**
   * @brief  Rx Transfer completed callbacks.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
-  */ 
+  */
 }
 
 /**
   * @brief  Ethernet transfer error callbacks
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
   the HAL_ETH_TxCpltCallback could be implemented in the user file
-  */ 
+  */
 }
 
 /**
   * @brief  Reads a PHY register
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module                  
-  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
-  *                This parameter can be one of the following values: 
-  *                   PHY_BCR: Transceiver Basic Control Register, 
-  *                   PHY_BSR: Transceiver Basic Status Register.   
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYReg PHY register address, is the index of one of the 32 PHY register.
+  *                This parameter can be one of the following values:
+  *                   PHY_BCR: Transceiver Basic Control Register,
+  *                   PHY_BSR: Transceiver Basic Status Register.
   *                   More PHY register could be read depending on the used PHY
-  * @param RegValue: PHY register value                  
+  * @param  RegValue PHY register value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
 {
-  uint32_t tmpreg1 = 0;     
-  uint32_t tickstart = 0;
-  
+  uint32_t tmpreg1 = 0U;
+  uint32_t tickstart = 0U;
+
   /* Check parameters */
   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
-  
+
   /* Check the ETH peripheral state */
-  if(heth->State == HAL_ETH_STATE_BUSY_RD)
+  if (heth->State == HAL_ETH_STATE_BUSY_RD)
   {
     return HAL_BUSY;
   }
   /* Set ETH HAL State to BUSY_RD */
   heth->State = HAL_ETH_STATE_BUSY_RD;
-  
+
   /* Get the ETHERNET MACMIIAR value */
   tmpreg1 = heth->Instance->MACMIIAR;
-  
+
   /* Keep only the CSR Clock Range CR[2:0] bits value */
   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-  
+
   /* Prepare the MII address register value */
-  tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
-  tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */
-  tmpreg1 &= ~ETH_MACMIIAR_MW;                                           /* Set the read mode            */
-  tmpreg1 |= ETH_MACMIIAR_MB;                                            /* Set the MII Busy bit         */
-  
+  tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
+  tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR);                /* Set the PHY register address */
+  tmpreg1 &= ~ETH_MACMIIAR_MW;                                            /* Set the read mode            */
+  tmpreg1 |= ETH_MACMIIAR_MB;                                             /* Set the MII Busy bit         */
+
   /* Write the result value into the MII Address register */
   heth->Instance->MACMIIAR = tmpreg1;
-  
+
   /* Get tick */
   tickstart = HAL_GetTick();
-  
+
   /* Check for the Busy flag */
-  while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+  while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
   {
     /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
+    if ((HAL_GetTick() - tickstart) > PHY_READ_TO)
     {
-      heth->State= HAL_ETH_STATE_READY;
-  
+      heth->State = HAL_ETH_STATE_READY;
+
       /* Process Unlocked */
       __HAL_UNLOCK(heth);
-    
+
       return HAL_TIMEOUT;
     }
-    
+
     tmpreg1 = heth->Instance->MACMIIAR;
   }
-  
+
   /* Get MACMIIDR value */
   *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
-  
+
   /* Set ETH HAL State to READY */
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Writes to a PHY register.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module  
-  * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register. 
-  *          This parameter can be one of the following values: 
-  *             PHY_BCR: Transceiver Control Register.  
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYReg PHY register address, is the index of one of the 32 PHY register.
+  *          This parameter can be one of the following values:
+  *             PHY_BCR: Transceiver Control Register.
   *             More PHY register could be written depending on the used PHY
-  * @param  RegValue: the value to write
+  * @param  RegValue the value to write
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
 {
-  uint32_t tmpreg1 = 0;
-  uint32_t tickstart = 0;
-  
+  uint32_t tmpreg1 = 0U;
+  uint32_t tickstart = 0U;
+
   /* Check parameters */
   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
-  
+
   /* Check the ETH peripheral state */
-  if(heth->State == HAL_ETH_STATE_BUSY_WR)
+  if (heth->State == HAL_ETH_STATE_BUSY_WR)
   {
     return HAL_BUSY;
   }
   /* Set ETH HAL State to BUSY_WR */
   heth->State = HAL_ETH_STATE_BUSY_WR;
-  
+
   /* Get the ETHERNET MACMIIAR value */
   tmpreg1 = heth->Instance->MACMIIAR;
-  
+
   /* Keep only the CSR Clock Range CR[2:0] bits value */
   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-  
+
   /* Prepare the MII register address value */
-  tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
-  tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */
-  tmpreg1 |= ETH_MACMIIAR_MW;                                          /* Set the write mode */
-  tmpreg1 |= ETH_MACMIIAR_MB;                                          /* Set the MII Busy bit */
-  
+  tmpreg1 |= (((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR);              /* Set the PHY register address */
+  tmpreg1 |= ETH_MACMIIAR_MW;                                           /* Set the write mode */
+  tmpreg1 |= ETH_MACMIIAR_MB;                                           /* Set the MII Busy bit */
+
   /* Give the value to the MII data register */
   heth->Instance->MACMIIDR = (uint16_t)RegValue;
-  
+
   /* Write the result value into the MII Address register */
   heth->Instance->MACMIIAR = tmpreg1;
-  
+
   /* Get tick */
   tickstart = HAL_GetTick();
-  
+
   /* Check for the Busy flag */
-  while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+  while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
   {
     /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
+    if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO)
     {
-      heth->State= HAL_ETH_STATE_READY;
-  
+      heth->State = HAL_ETH_STATE_READY;
+
       /* Process Unlocked */
       __HAL_UNLOCK(heth);
-    
+
       return HAL_TIMEOUT;
     }
-    
+
     tmpreg1 = heth->Instance->MACMIIAR;
   }
-  
+
   /* Set ETH HAL State to READY */
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Return function status */
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
@@ -1159,16 +1424,16 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
   */
 
 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
+ *  @brief    Peripheral Control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                   ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Enable MAC and DMA transmission and reception.
           HAL_ETH_Start();
-      (+) Disable MAC and DMA transmission and reception. 
+      (+) Disable MAC and DMA transmission and reception.
           HAL_ETH_Stop();
       (+) Set the MAC configuration in runtime mode
           HAL_ETH_ConfigMAC();
@@ -1177,106 +1442,106 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY
 
 @endverbatim
   * @{
-  */ 
-
- /**
-  * @brief  Enables Ethernet MAC and DMA reception/transmission 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
   */
+
+/**
+ * @brief  Enables Ethernet MAC and DMA reception/transmission
+ * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+ *         the configuration information for ETHERNET module
+ * @retval HAL status
+ */
 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
-{  
+{
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Enable transmit state machine of the MAC for transmission on the MII */
   ETH_MACTransmissionEnable(heth);
-  
+
   /* Enable receive state machine of the MAC for reception from the MII */
   ETH_MACReceptionEnable(heth);
-  
+
   /* Flush Transmit FIFO */
   ETH_FlushTransmitFIFO(heth);
-  
+
   /* Start DMA transmission */
   ETH_DMATransmissionEnable(heth);
-  
+
   /* Start DMA reception */
   ETH_DMAReceptionEnable(heth);
-  
+
   /* Set the ETH state to READY*/
-  heth->State= HAL_ETH_STATE_READY;
-  
+  heth->State = HAL_ETH_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stop Ethernet MAC and DMA reception/transmission 
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @brief  Stop Ethernet MAC and DMA reception/transmission
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
-{  
+{
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
   heth->State = HAL_ETH_STATE_BUSY;
-  
+
   /* Stop DMA transmission */
   ETH_DMATransmissionDisable(heth);
-  
+
   /* Stop DMA reception */
   ETH_DMAReceptionDisable(heth);
-  
+
   /* Disable receive state machine of the MAC for reception from the MII */
   ETH_MACReceptionDisable(heth);
-  
+
   /* Flush Transmit FIFO */
   ETH_FlushTransmitFIFO(heth);
-  
+
   /* Disable transmit state machine of the MAC for transmission on the MII */
   ETH_MACTransmissionDisable(heth);
-  
+
   /* Set the ETH state*/
   heth->State = HAL_ETH_STATE_READY;
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Set ETH MAC Configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  macconf: MAC Configuration structure  
+  * @param  macconf MAC Configuration structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
 {
-  uint32_t tmpreg1 = 0;
-  
+  uint32_t tmpreg1 = 0U;
+
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
-  heth->State= HAL_ETH_STATE_BUSY;
-  
+  heth->State = HAL_ETH_STATE_BUSY;
+
   assert_param(IS_ETH_SPEED(heth->Init.Speed));
-  assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); 
-  
+  assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
+
   if (macconf != NULL)
   {
     /* Check the parameters */
@@ -1307,139 +1572,139 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef
     assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
     assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
     assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
-    
+
     /*------------------------ ETHERNET MACCR Configuration --------------------*/
     /* Get the ETHERNET MACCR value */
     tmpreg1 = (heth->Instance)->MACCR;
     /* Clear WD, PCE, PS, TE and RE bits */
     tmpreg1 &= ETH_MACCR_CLEAR_MASK;
-    
-    tmpreg1 |= (uint32_t)(macconf->Watchdog | 
-                         macconf->Jabber | 
-                         macconf->InterFrameGap |
-                         macconf->CarrierSense |
-                         (heth->Init).Speed | 
-                         macconf->ReceiveOwn |
-                         macconf->LoopbackMode |
-                         (heth->Init).DuplexMode | 
-                         macconf->ChecksumOffload |    
-                         macconf->RetryTransmission | 
-                         macconf->AutomaticPadCRCStrip | 
-                         macconf->BackOffLimit | 
-                         macconf->DeferralCheck);
-    
+
+    tmpreg1 |= (uint32_t)(macconf->Watchdog |
+                          macconf->Jabber |
+                          macconf->InterFrameGap |
+                          macconf->CarrierSense |
+                          (heth->Init).Speed |
+                          macconf->ReceiveOwn |
+                          macconf->LoopbackMode |
+                          (heth->Init).DuplexMode |
+                          macconf->ChecksumOffload |
+                          macconf->RetryTransmission |
+                          macconf->AutomaticPadCRCStrip |
+                          macconf->BackOffLimit |
+                          macconf->DeferralCheck);
+
     /* Write to ETHERNET MACCR */
     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-    
+
     /* Wait until the write operation will be taken into account :
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1; 
-    
-    /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
-    /* Write to ETHERNET MACFFR */  
-    (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | 
+    (heth->Instance)->MACCR = tmpreg1;
+
+    /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+    /* Write to ETHERNET MACFFR */
+    (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
                                           macconf->SourceAddrFilter |
                                           macconf->PassControlFrames |
-                                          macconf->BroadcastFramesReception | 
+                                          macconf->BroadcastFramesReception |
                                           macconf->DestinationAddrFilter |
                                           macconf->PromiscuousMode |
                                           macconf->MulticastFramesFilter |
                                           macconf->UnicastFramesFilter);
-     
-     /* Wait until the write operation will be taken into account :
-     at least four TX_CLK/RX_CLK clock cycles */
-     tmpreg1 = (heth->Instance)->MACFFR;
-     HAL_Delay(ETH_REG_WRITE_DELAY);
-     (heth->Instance)->MACFFR = tmpreg1;
-     
-     /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
-     /* Write to ETHERNET MACHTHR */
-     (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
-     
-     /* Write to ETHERNET MACHTLR */
-     (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
-     /*----------------------- ETHERNET MACFCR Configuration --------------------*/
-     
-     /* Get the ETHERNET MACFCR value */  
-     tmpreg1 = (heth->Instance)->MACFCR;
-     /* Clear xx bits */
-     tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
-     
-     tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) | 
+
+    /* Wait until the write operation will be taken into account :
+    at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg1 = (heth->Instance)->MACFFR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACFFR = tmpreg1;
+
+    /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+    /* Write to ETHERNET MACHTHR */
+    (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
+
+    /* Write to ETHERNET MACHTLR */
+    (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
+    /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+
+    /* Get the ETHERNET MACFCR value */
+    tmpreg1 = (heth->Instance)->MACFCR;
+    /* Clear xx bits */
+    tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
+
+    tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
                           macconf->ZeroQuantaPause |
                           macconf->PauseLowThreshold |
-                          macconf->UnicastPauseFrameDetect | 
+                          macconf->UnicastPauseFrameDetect |
                           macconf->ReceiveFlowControl |
-                          macconf->TransmitFlowControl); 
-     
-     /* Write to ETHERNET MACFCR */
-     (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
-     
-     /* Wait until the write operation will be taken into account :
-     at least four TX_CLK/RX_CLK clock cycles */
-     tmpreg1 = (heth->Instance)->MACFCR;
-     HAL_Delay(ETH_REG_WRITE_DELAY);
-     (heth->Instance)->MACFCR = tmpreg1;
-     
-     /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
-     (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | 
-                                              macconf->VLANTagIdentifier);
-      
-      /* Wait until the write operation will be taken into account :
-      at least four TX_CLK/RX_CLK clock cycles */
-      tmpreg1 = (heth->Instance)->MACVLANTR;
-      HAL_Delay(ETH_REG_WRITE_DELAY);
-      (heth->Instance)->MACVLANTR = tmpreg1;
+                          macconf->TransmitFlowControl);
+
+    /* Write to ETHERNET MACFCR */
+    (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
+
+    /* Wait until the write operation will be taken into account :
+    at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg1 = (heth->Instance)->MACFCR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACFCR = tmpreg1;
+
+    /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+    (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
+                                             macconf->VLANTagIdentifier);
+
+    /* Wait until the write operation will be taken into account :
+    at least four TX_CLK/RX_CLK clock cycles */
+    tmpreg1 = (heth->Instance)->MACVLANTR;
+    HAL_Delay(ETH_REG_WRITE_DELAY);
+    (heth->Instance)->MACVLANTR = tmpreg1;
   }
   else /* macconf == NULL : here we just configure Speed and Duplex mode */
   {
     /*------------------------ ETHERNET MACCR Configuration --------------------*/
     /* Get the ETHERNET MACCR value */
     tmpreg1 = (heth->Instance)->MACCR;
-    
+
     /* Clear FES and DM bits */
-    tmpreg1 &= ~((uint32_t)0x00004800);
-    
+    tmpreg1 &= ~(0x00004800U);
+
     tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
-    
+
     /* Write to ETHERNET MACCR */
     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-    
+
     /* Wait until the write operation will be taken into account:
     at least four TX_CLK/RX_CLK clock cycles */
     tmpreg1 = (heth->Instance)->MACCR;
     HAL_Delay(ETH_REG_WRITE_DELAY);
     (heth->Instance)->MACCR = tmpreg1;
   }
-  
+
   /* Set the ETH state to Ready */
-  heth->State= HAL_ETH_STATE_READY;
-  
+  heth->State = HAL_ETH_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(heth);
-  
+
   /* Return function status */
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Sets ETH DMA Configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  dmaconf: DMA Configuration structure  
+  * @param  dmaconf DMA Configuration structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
 {
-  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg1 = 0U;
 
   /* Process Locked */
   __HAL_LOCK(heth);
-  
+
   /* Set the ETH peripheral state to BUSY */
-  heth->State= HAL_ETH_STATE_BUSY;
+  heth->State = HAL_ETH_STATE_BUSY;
 
   /* Check parameters */
   assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
@@ -1458,22 +1723,22 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
   assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
   assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
   assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
-  
+
   /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
   /* Get the ETHERNET DMAOMR value */
   tmpreg1 = (heth->Instance)->DMAOMR;
   /* Clear xx bits */
   tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
 
-  tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | 
-                       dmaconf->ReceiveStoreForward |
-                       dmaconf->FlushReceivedFrame |
-                       dmaconf->TransmitStoreForward | 
-                       dmaconf->TransmitThresholdControl |
-                       dmaconf->ForwardErrorFrames |
-                       dmaconf->ForwardUndersizedGoodFrames |
-                       dmaconf->ReceiveThresholdControl |
-                       dmaconf->SecondFrameOperate);
+  tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+                        dmaconf->ReceiveStoreForward |
+                        dmaconf->FlushReceivedFrame |
+                        dmaconf->TransmitStoreForward |
+                        dmaconf->TransmitThresholdControl |
+                        dmaconf->ForwardErrorFrames |
+                        dmaconf->ForwardUndersizedGoodFrames |
+                        dmaconf->ReceiveThresholdControl |
+                        dmaconf->SecondFrameOperate);
 
   /* Write to ETHERNET DMAOMR */
   (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
@@ -1485,48 +1750,48 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
   (heth->Instance)->DMAOMR = tmpreg1;
 
   /*----------------------- ETHERNET DMABMR Configuration --------------------*/
-  (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | 
-                                         dmaconf->FixedBurst |
-                                         dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
-                                         dmaconf->TxDMABurstLength |
-                                         dmaconf->EnhancedDescriptorFormat |
-                                         (dmaconf->DescriptorSkipLength << 2) |
-                                         dmaconf->DMAArbitration | 
-                                         ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
-
-   /* Wait until the write operation will be taken into account:
-      at least four TX_CLK/RX_CLK clock cycles */
-   tmpreg1 = (heth->Instance)->DMABMR;
-   HAL_Delay(ETH_REG_WRITE_DELAY);
-   (heth->Instance)->DMABMR = tmpreg1;
-
-   /* Set the ETH state to Ready */
-   heth->State= HAL_ETH_STATE_READY;
-   
-   /* Process Unlocked */
-   __HAL_UNLOCK(heth);
-   
-   /* Return function status */
-   return HAL_OK; 
+  (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
+                                        dmaconf->FixedBurst |
+                                        dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                                        dmaconf->TxDMABurstLength |
+                                        dmaconf->EnhancedDescriptorFormat |
+                                        (dmaconf->DescriptorSkipLength << 2U) |
+                                        dmaconf->DMAArbitration |
+                                        ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->DMABMR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->DMABMR = tmpreg1;
+
+  /* Set the ETH state to Ready */
+  heth->State = HAL_ETH_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(heth);
+
+  /* Return function status */
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions 
-  *  @brief   Peripheral State functions 
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
   *
-  @verbatim   
+  @verbatim
   ===============================================================================
                          ##### Peripheral State functions #####
-  ===============================================================================  
+  ===============================================================================
   [..]
-  This subsection permits to get in run-time the status of the peripheral 
+  This subsection permits to get in run-time the status of the peripheral
   and the data flow.
        (+) Get the ETH handle state:
            HAL_ETH_GetState();
-           
+
 
   @endverbatim
   * @{
@@ -1534,12 +1799,12 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef
 
 /**
   * @brief  Return the ETH HAL state
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval HAL state
   */
 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
-{  
+{
   /* Return ETH state */
   return heth->State;
 }
@@ -1547,37 +1812,37 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
-  
+
 /** @addtogroup ETH_Private_Functions
   * @{
   */
 
 /**
   * @brief  Configures Ethernet MAC and DMA with default parameters.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  err: Ethernet Init error
+  * @param  err Ethernet Init error
   * @retval HAL status
   */
 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
 {
   ETH_MACInitTypeDef macinit;
   ETH_DMAInitTypeDef dmainit;
-  uint32_t tmpreg1 = 0;
-  
+  uint32_t tmpreg1 = 0U;
+
   if (err != ETH_SUCCESS) /* Auto-negotiation failed */
   {
     /* Set Ethernet duplex mode to Full-duplex */
     (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
-    
+
     /* Set Ethernet speed to 100M */
     (heth->Init).Speed = ETH_SPEED_100M;
   }
-  
+
   /* Ethernet MAC default initialization **************************************/
   macinit.Watchdog = ETH_WATCHDOG_ENABLE;
   macinit.Jabber = ETH_JABBER_ENABLE;
@@ -1585,7 +1850,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
   macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
   macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
   macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
-  if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
+  if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
   {
     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
   }
@@ -1605,17 +1870,17 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
   macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
   macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
   macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
-  macinit.HashTableHigh = 0x0;
-  macinit.HashTableLow = 0x0;
-  macinit.PauseTime = 0x0;
+  macinit.HashTableHigh = 0x0U;
+  macinit.HashTableLow = 0x0U;
+  macinit.PauseTime = 0x0U;
   macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
   macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
   macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
   macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
   macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
   macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
-  macinit.VLANTagIdentifier = 0x0;
-  
+  macinit.VLANTagIdentifier = 0x0U;
+
   /*------------------------ ETHERNET MACCR Configuration --------------------*/
   /* Get the ETHERNET MACCR value */
   tmpreg1 = (heth->Instance)->MACCR;
@@ -1625,39 +1890,39 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
   /* Set the JD: bit according to ETH Jabber value */
   /* Set the IFG bit according to ETH InterFrameGap value */
   /* Set the DCRS bit according to ETH CarrierSense value */
-  /* Set the FES bit according to ETH Speed value */ 
-  /* Set the DO bit according to ETH ReceiveOwn value */ 
+  /* Set the FES bit according to ETH Speed value */
+  /* Set the DO bit according to ETH ReceiveOwn value */
   /* Set the LM bit according to ETH LoopbackMode value */
-  /* Set the DM bit according to ETH Mode value */ 
+  /* Set the DM bit according to ETH Mode value */
   /* Set the IPCO bit according to ETH ChecksumOffload value */
   /* Set the DR bit according to ETH RetryTransmission value */
   /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
   /* Set the BL bit according to ETH BackOffLimit value */
   /* Set the DC bit according to ETH DeferralCheck value */
-  tmpreg1 |= (uint32_t)(macinit.Watchdog | 
-                       macinit.Jabber | 
-                       macinit.InterFrameGap |
-                       macinit.CarrierSense |
-                       (heth->Init).Speed | 
-                       macinit.ReceiveOwn |
-                       macinit.LoopbackMode |
-                       (heth->Init).DuplexMode | 
-                       macinit.ChecksumOffload |    
-                       macinit.RetryTransmission | 
-                       macinit.AutomaticPadCRCStrip | 
-                       macinit.BackOffLimit | 
-                       macinit.DeferralCheck);
-  
+  tmpreg1 |= (uint32_t)(macinit.Watchdog |
+                        macinit.Jabber |
+                        macinit.InterFrameGap |
+                        macinit.CarrierSense |
+                        (heth->Init).Speed |
+                        macinit.ReceiveOwn |
+                        macinit.LoopbackMode |
+                        (heth->Init).DuplexMode |
+                        macinit.ChecksumOffload |
+                        macinit.RetryTransmission |
+                        macinit.AutomaticPadCRCStrip |
+                        macinit.BackOffLimit |
+                        macinit.DeferralCheck);
+
   /* Write to ETHERNET MACCR */
   (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-  
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
   HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACCR = tmpreg1; 
-  
-  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+  (heth->Instance)->MACCR = tmpreg1;
+
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/
   /* Set the RA bit according to ETH ReceiveAll value */
   /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
   /* Set the PCF bit according to ETH PassControlFrames value */
@@ -1666,337 +1931,365 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
   /* Set the PR bit according to ETH PromiscuousMode value */
   /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
   /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
-  /* Write to ETHERNET MACFFR */  
-  (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | 
+  /* Write to ETHERNET MACFFR */
+  (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
                                         macinit.SourceAddrFilter |
                                         macinit.PassControlFrames |
-                                        macinit.BroadcastFramesReception | 
+                                        macinit.BroadcastFramesReception |
                                         macinit.DestinationAddrFilter |
                                         macinit.PromiscuousMode |
                                         macinit.MulticastFramesFilter |
                                         macinit.UnicastFramesFilter);
-   
-   /* Wait until the write operation will be taken into account:
-      at least four TX_CLK/RX_CLK clock cycles */
-   tmpreg1 = (heth->Instance)->MACFFR;
-   HAL_Delay(ETH_REG_WRITE_DELAY);
-   (heth->Instance)->MACFFR = tmpreg1;
-   
-   /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
-   /* Write to ETHERNET MACHTHR */
-   (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
-   
-   /* Write to ETHERNET MACHTLR */
-   (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
-   /*----------------------- ETHERNET MACFCR Configuration -------------------*/
-   
-   /* Get the ETHERNET MACFCR value */  
-   tmpreg1 = (heth->Instance)->MACFCR;
-   /* Clear xx bits */
-   tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
-   
-   /* Set the PT bit according to ETH PauseTime value */
-   /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
-   /* Set the PLT bit according to ETH PauseLowThreshold value */
-   /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
-   /* Set the RFE bit according to ETH ReceiveFlowControl value */
-   /* Set the TFE bit according to ETH TransmitFlowControl value */ 
-   tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) | 
+
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->MACFFR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACFFR = tmpreg1;
+
+  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
+  /* Write to ETHERNET MACHTHR */
+  (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
+
+  /* Write to ETHERNET MACHTLR */
+  (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
+  /*----------------------- ETHERNET MACFCR Configuration -------------------*/
+
+  /* Get the ETHERNET MACFCR value */
+  tmpreg1 = (heth->Instance)->MACFCR;
+  /* Clear xx bits */
+  tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
+
+  /* Set the PT bit according to ETH PauseTime value */
+  /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
+  /* Set the PLT bit according to ETH PauseLowThreshold value */
+  /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
+  /* Set the RFE bit according to ETH ReceiveFlowControl value */
+  /* Set the TFE bit according to ETH TransmitFlowControl value */
+  tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
                         macinit.ZeroQuantaPause |
                         macinit.PauseLowThreshold |
-                        macinit.UnicastPauseFrameDetect | 
+                        macinit.UnicastPauseFrameDetect |
                         macinit.ReceiveFlowControl |
-                        macinit.TransmitFlowControl); 
-   
-   /* Write to ETHERNET MACFCR */
-   (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
-   
-   /* Wait until the write operation will be taken into account:
-   at least four TX_CLK/RX_CLK clock cycles */
-   tmpreg1 = (heth->Instance)->MACFCR;
-   HAL_Delay(ETH_REG_WRITE_DELAY);
-   (heth->Instance)->MACFCR = tmpreg1;
-   
-   /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
-   /* Set the ETV bit according to ETH VLANTagComparison value */
-   /* Set the VL bit according to ETH VLANTagIdentifier value */  
-   (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | 
-                                            macinit.VLANTagIdentifier);
-    
-    /* Wait until the write operation will be taken into account:
-       at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACVLANTR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACVLANTR = tmpreg1;
-    
-    /* Ethernet DMA default initialization ************************************/
-    dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
-    dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
-    dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
-    dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;  
-    dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
-    dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
-    dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
-    dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
-    dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
-    dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
-    dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
-    dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
-    dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
-    dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
-    dmainit.DescriptorSkipLength = 0x0;
-    dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
-    
-    /* Get the ETHERNET DMAOMR value */
-    tmpreg1 = (heth->Instance)->DMAOMR;
-    /* Clear xx bits */
-    tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
-    
-    /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
-    /* Set the RSF bit according to ETH ReceiveStoreForward value */
-    /* Set the DFF bit according to ETH FlushReceivedFrame value */
-    /* Set the TSF bit according to ETH TransmitStoreForward value */
-    /* Set the TTC bit according to ETH TransmitThresholdControl value */
-    /* Set the FEF bit according to ETH ForwardErrorFrames value */
-    /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
-    /* Set the RTC bit according to ETH ReceiveThresholdControl value */
-    /* Set the OSF bit according to ETH SecondFrameOperate value */
-    tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | 
-                         dmainit.ReceiveStoreForward |
-                         dmainit.FlushReceivedFrame |
-                         dmainit.TransmitStoreForward | 
-                         dmainit.TransmitThresholdControl |
-                         dmainit.ForwardErrorFrames |
-                         dmainit.ForwardUndersizedGoodFrames |
-                         dmainit.ReceiveThresholdControl |
-                         dmainit.SecondFrameOperate);
-    
-    /* Write to ETHERNET DMAOMR */
-    (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
-    
-    /* Wait until the write operation will be taken into account:
-       at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->DMAOMR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->DMAOMR = tmpreg1;
-    
-    /*----------------------- ETHERNET DMABMR Configuration ------------------*/
-    /* Set the AAL bit according to ETH AddressAlignedBeats value */
-    /* Set the FB bit according to ETH FixedBurst value */
-    /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
-    /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
-    /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
-    /* Set the DSL bit according to ETH DesciptorSkipLength value */
-    /* Set the PR and DA bits according to ETH DMAArbitration value */
-    (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | 
-                                          dmainit.FixedBurst |
-                                          dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
-                                          dmainit.TxDMABurstLength |
-                                          dmainit.EnhancedDescriptorFormat |
-                                          (dmainit.DescriptorSkipLength << 2) |
-                                          dmainit.DMAArbitration |
-                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
-     
-     /* Wait until the write operation will be taken into account:
-        at least four TX_CLK/RX_CLK clock cycles */
-     tmpreg1 = (heth->Instance)->DMABMR;
-     HAL_Delay(ETH_REG_WRITE_DELAY);
-     (heth->Instance)->DMABMR = tmpreg1;
-
-     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
-     {
-       /* Enable the Ethernet Rx Interrupt */
-       __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
-     }
-
-     /* Initialize MAC address in ethernet MAC */ 
-     ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
+                        macinit.TransmitFlowControl);
+
+  /* Write to ETHERNET MACFCR */
+  (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
+
+  /* Wait until the write operation will be taken into account:
+  at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->MACFCR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACFCR = tmpreg1;
+
+  /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
+  /* Set the ETV bit according to ETH VLANTagComparison value */
+  /* Set the VL bit according to ETH VLANTagIdentifier value */
+  (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
+                                           macinit.VLANTagIdentifier);
+
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->MACVLANTR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->MACVLANTR = tmpreg1;
+
+  /* Ethernet DMA default initialization ************************************/
+  dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
+  dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
+  dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
+  dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
+  dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
+  dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
+  dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
+  dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
+  dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
+  dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
+  dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
+  dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+  dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+  dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
+  dmainit.DescriptorSkipLength = 0x0U;
+  dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
+
+  /* Get the ETHERNET DMAOMR value */
+  tmpreg1 = (heth->Instance)->DMAOMR;
+  /* Clear xx bits */
+  tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
+
+  /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
+  /* Set the RSF bit according to ETH ReceiveStoreForward value */
+  /* Set the DFF bit according to ETH FlushReceivedFrame value */
+  /* Set the TSF bit according to ETH TransmitStoreForward value */
+  /* Set the TTC bit according to ETH TransmitThresholdControl value */
+  /* Set the FEF bit according to ETH ForwardErrorFrames value */
+  /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
+  /* Set the RTC bit according to ETH ReceiveThresholdControl value */
+  /* Set the OSF bit according to ETH SecondFrameOperate value */
+  tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+                        dmainit.ReceiveStoreForward |
+                        dmainit.FlushReceivedFrame |
+                        dmainit.TransmitStoreForward |
+                        dmainit.TransmitThresholdControl |
+                        dmainit.ForwardErrorFrames |
+                        dmainit.ForwardUndersizedGoodFrames |
+                        dmainit.ReceiveThresholdControl |
+                        dmainit.SecondFrameOperate);
+
+  /* Write to ETHERNET DMAOMR */
+  (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
+
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->DMAOMR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->DMAOMR = tmpreg1;
+
+  /*----------------------- ETHERNET DMABMR Configuration ------------------*/
+  /* Set the AAL bit according to ETH AddressAlignedBeats value */
+  /* Set the FB bit according to ETH FixedBurst value */
+  /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
+  /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
+  /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
+  /* Set the DSL bit according to ETH DesciptorSkipLength value */
+  /* Set the PR and DA bits according to ETH DMAArbitration value */
+  (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
+                                        dmainit.FixedBurst |
+                                        dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                                        dmainit.TxDMABurstLength |
+                                        dmainit.EnhancedDescriptorFormat |
+                                        (dmainit.DescriptorSkipLength << 2U) |
+                                        dmainit.DMAArbitration |
+                                        ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+
+  /* Wait until the write operation will be taken into account:
+     at least four TX_CLK/RX_CLK clock cycles */
+  tmpreg1 = (heth->Instance)->DMABMR;
+  HAL_Delay(ETH_REG_WRITE_DELAY);
+  (heth->Instance)->DMABMR = tmpreg1;
+
+  if ((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
+  {
+    /* Enable the Ethernet Rx Interrupt */
+    __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
+  }
+
+  /* Initialize MAC address in ethernet MAC */
+  ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
 }
 
 /**
   * @brief  Configures the selected MAC address.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  MacAddr: The MAC address to configure
+  * @param  MacAddr The MAC address to configure
   *          This parameter can be one of the following values:
-  *             @arg ETH_MAC_Address0: MAC Address0 
-  *             @arg ETH_MAC_Address1: MAC Address1 
+  *             @arg ETH_MAC_Address0: MAC Address0
+  *             @arg ETH_MAC_Address1: MAC Address1
   *             @arg ETH_MAC_Address2: MAC Address2
   *             @arg ETH_MAC_Address3: MAC Address3
-  * @param  Addr: Pointer to MAC address buffer data (6 bytes)
+  * @param  Addr Pointer to MAC address buffer data (6 bytes)
   * @retval HAL status
   */
 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
 {
   uint32_t tmpreg1;
-  
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+
   /* Check the parameters */
   assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
-  
+
   /* Calculate the selected MAC address high register */
-  tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+  tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
   /* Load the selected MAC address high register */
   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
   /* Calculate the selected MAC address low register */
-  tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
-  
+  tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
+
   /* Load the selected MAC address low register */
   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
 }
 
 /**
   * @brief  Enables the MAC transmission.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module  
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
-{ 
-  __IO uint32_t tmpreg1 = 0;
-  
+{
+  __IO uint32_t tmpreg1 = 0U;
+
   /* Enable the MAC transmission */
   (heth->Instance)->MACCR |= ETH_MACCR_TE;
-  
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
 /**
   * @brief  Disables the MAC transmission.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module  
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
-{ 
-  __IO uint32_t tmpreg1 = 0;
-  
+{
+  __IO uint32_t tmpreg1 = 0U;
+
   /* Disable the MAC transmission */
   (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
-  
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
 /**
   * @brief  Enables the MAC reception.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module   
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
-{ 
-  __IO uint32_t tmpreg1 = 0;
-  
+{
+  __IO uint32_t tmpreg1 = 0U;
+
   /* Enable the MAC reception */
   (heth->Instance)->MACCR |= ETH_MACCR_RE;
-  
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
 /**
   * @brief  Disables the MAC reception.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module   
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
-{ 
-  __IO uint32_t tmpreg1 = 0;
-  
+{
+  __IO uint32_t tmpreg1 = 0U;
+
   /* Disable the MAC reception */
-  (heth->Instance)->MACCR &= ~ETH_MACCR_RE; 
-  
+  (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->MACCR = tmpreg1;
 }
 
 /**
   * @brief  Enables the DMA transmission.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module   
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
 {
   /* Enable the DMA transmission */
-  (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;  
+  (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
 }
 
 /**
   * @brief  Disables the DMA transmission.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module   
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
-{ 
+{
   /* Disable the DMA transmission */
   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
 }
 
 /**
   * @brief  Enables the DMA reception.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module 
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
-{  
+{
   /* Enable the DMA reception */
-  (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;  
+  (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
 }
 
 /**
   * @brief  Disables the DMA reception.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module 
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
-{ 
+{
   /* Disable the DMA reception */
   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
 }
 
 /**
   * @brief  Clears the ETHERNET transmit FIFO.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
 {
-  __IO uint32_t tmpreg1 = 0;
-  
+  __IO uint32_t tmpreg1 = 0U;
+
   /* Set the Flush Transmit FIFO bit */
   (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
-  
+
   /* Wait until the write operation will be taken into account:
      at least four TX_CLK/RX_CLK clock cycles */
   tmpreg1 = (heth->Instance)->DMAOMR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
+  ETH_Delay(ETH_REG_WRITE_DELAY);
   (heth->Instance)->DMAOMR = tmpreg1;
 }
 
+/**
+  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
+  * @param  mdelay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+static void ETH_Delay(uint32_t mdelay)
+{
+  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
+  do
+  {
+    __NOP();
+  }
+  while (Delay --);
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+  /* Init the ETH Callback settings */
+  heth->TxCpltCallback       = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback   */
+  heth->RxCpltCallback       = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback   */
+  heth->DMAErrorCallback     = HAL_ETH_ErrorCallback;  /* Legacy weak DMAErrorCallback */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-#endif /* STM32F207xx || STM32F217xx */
+#endif /* ETH */
 #endif /* HAL_ETH_MODULE_ENABLED */
 /**
   * @}
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c
index bb3f7f56..0b3f21bb 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -65,32 +63,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -111,7 +93,7 @@
 /** @addtogroup FLASH_Private_Constants
   * @{
   */
-#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
+#define FLASH_TIMEOUT_VALUE       50000U   /* 50 s */
 /**
   * @}
   */         
@@ -165,10 +147,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
 
 /**
   * @brief  Program byte, halfword, word or double word at a specified address
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
   *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
   * 
   * @retval HAL_StatusTypeDef HAL Status
   */
@@ -223,10 +205,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
 
 /**
   * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
   *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
   * 
   * @retval HAL Status
   */
@@ -279,7 +261,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
   */
 void HAL_FLASH_IRQHandler(void)
 {
-  uint32_t addresstmp = 0;
+  uint32_t addresstmp = 0U;
   
   /* Check FLASH operation error flags */
   if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
@@ -289,7 +271,7 @@ void HAL_FLASH_IRQHandler(void)
     {
       /*return the faulty sector*/
       addresstmp = pFlash.Sector;
-      pFlash.Sector = 0xFFFFFFFF;
+      pFlash.Sector = 0xFFFFFFFFU;
     }
     else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
     {
@@ -324,7 +306,7 @@ void HAL_FLASH_IRQHandler(void)
       pFlash.NbSectorsToErase--;
       
       /* Check if there are still sectors to erase*/
-      if(pFlash.NbSectorsToErase != 0)
+      if(pFlash.NbSectorsToErase != 0U)
       {
         addresstmp = pFlash.Sector;
         /*Indicate user which sector has been erased*/
@@ -339,7 +321,7 @@ void HAL_FLASH_IRQHandler(void)
       {
         /*No more sectors to Erase, user callback can be called.*/
         /*Reset Sector and stop Erase sectors procedure*/
-        pFlash.Sector = addresstmp = 0xFFFFFFFF;
+        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
         pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
         
         /* Flush the caches to be sure of the data consistency */
@@ -388,7 +370,7 @@ void HAL_FLASH_IRQHandler(void)
 
 /**
   * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                  Mass Erase: Bank number which has been requested to erase
   *                  Sectors Erase: Sector which has been erased 
   *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
@@ -397,6 +379,8 @@ void HAL_FLASH_IRQHandler(void)
   */
 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
    */ 
@@ -404,7 +388,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 
 /**
   * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 Mass Erase: Bank number which has been requested to erase
   *                 Sectors Erase: Sector number which returned an error
   *                 Program: Address which was selected for data program
@@ -412,6 +396,8 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
   */
 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
    */ 
@@ -442,18 +428,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
   */
 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
 {
-  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
   {
     /* Authorize the FLASH Registers access */
-    FLASH->KEYR = FLASH_KEY1;
-    FLASH->KEYR = FLASH_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* Verify Flash is unlocked */
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+    {
+      status = HAL_ERROR;
+    }
   }
-  
-  return HAL_OK; 
+
+  return status;
 }
 
 /**
@@ -552,12 +542,12 @@ uint32_t HAL_FLASH_GetError(void)
 
 /**
   * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
+  * @param  Timeout maximum flash operationtimeout
   * @retval HAL Status
   */
 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
 { 
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
   
   /* Clear Error Code */
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
@@ -572,7 +562,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
   { 
     if(Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
       {
         return HAL_TIMEOUT;
       }
@@ -580,7 +570,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
   }
 
   /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
   {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
@@ -602,13 +592,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
 /**
   * @brief  Program a double word (64-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V and an External Vpp is present.
+  *         2.7V to 3.6V and an External Vpp in the range 7V to 9V.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
@@ -621,9 +611,16 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
   FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
   FLASH->CR |= FLASH_CR_PG;
 
-  *(__IO uint64_t*)Address = Data;
-}
+  /* Program first word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
 
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
 
 /**
   * @brief  Program word (32-bit) at a specified address.
@@ -633,8 +630,8 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
@@ -653,13 +650,13 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
 /**
   * @brief  Program a half-word (16-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
+  *         2.1V to 2.7V.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@@ -678,13 +675,13 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
 /**
   * @brief  Program byte (8-bit) at a specified address.
   * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
+  *         1.8V to 2.1V.
   *
   * @note   If an erase and a program operations are requested simultaneously,    
   *         the erase operation is performed before the program one.
   *  
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
   * @retval None
   */
 static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c
index ac75c24d..b65c9849 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Extended FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the FLASH extension peripheral:
@@ -36,32 +34,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -82,7 +64,7 @@
 /** @addtogroup FLASHEx_Private_Constants
   * @{
   */
-#define FLASH_TIMEOUT_VALUE       ((uint32_t)50000)/* 50 s */
+#define FLASH_TIMEOUT_VALUE       50000U   /* 50 s */
 /**
   * @}
   */
@@ -119,7 +101,7 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+/** @defgroup FLASHEx_Exported_Functions FLASH Exported Functions
   * @{
   */
 
@@ -139,10 +121,10 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
   */
 /**
   * @brief  Perform a mass erase or erase the specified FLASH memory sectors 
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
   * 
-  * @param[out]  SectorError: pointer to variable  that
+  * @param[out]  SectorError pointer to variable  that
   *         contains the configuration information on faulty sector in case of error 
   *         (0xFFFFFFFF means that all the sectors have been correctly erased)
   * 
@@ -151,7 +133,7 @@ extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0;
+  uint32_t index = 0U;
   
   /* Process Locked */
   __HAL_LOCK(&pFlash);
@@ -165,7 +147,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
   if(status == HAL_OK)
   {
     /*Initialization of SectorError variable*/
-    *SectorError = 0xFFFFFFFF;
+    *SectorError = 0xFFFFFFFFU;
     
     if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
     {
@@ -214,7 +196,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
 
 /**
   * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
   * 
   * @retval HAL Status
@@ -267,7 +249,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 
 /**
   * @brief   Program option bytes
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
   *         contains the configuration information for the programming.
   * 
   * @retval HAL Status
@@ -326,7 +308,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
 
 /**
   * @brief   Get the Option byte configuration
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
   *         contains the configuration information for the programming.
   * 
   * @retval None
@@ -354,9 +336,9 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 
 /**
   * @brief  Erase the specified FLASH memory sector
-  * @param  Sector: FLASH sector to erase
+  * @param  Sector FLASH sector to erase
   *         The value of this parameter depend on device used within the same series      
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
   *          This parameter can be one of the following values:
   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
   *                                  the operation will be done by byte (8-bit) 
@@ -371,7 +353,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
   */
 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
 {
-  uint32_t tmp_psize = 0;
+  uint32_t tmp_psize = 0U;
 
   /* Check the parameters */
   assert_param(IS_FLASH_SECTOR(Sector));
@@ -433,7 +415,7 @@ void FLASH_FlushCaches(void)
 
 /**
   * @brief  Mass erase of FLASH memory
-  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.  
   *          This parameter can be one of the following values:
   *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, 
   *                                  the operation will be done by byte (8-bit) 
@@ -444,25 +426,25 @@ void FLASH_FlushCaches(void)
   *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
   *                                  the operation will be done by double word (64-bit)
   * 
-  * @param  Banks: Banks to be erased
+  * @param  Banks Banks to be erased
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: Bank1 to be erased
   *
   * @retval None
   */
 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  uint32_t tmp_psize = 0;
-  
+{ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Banks);
+
   /* Check the parameters */
   assert_param(IS_VOLTAGERANGE(VoltageRange));
   assert_param(IS_FLASH_BANK(Banks));
   
   /* If the previous operation is completed, proceed to erase all sectors */
   CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= tmp_psize;
   FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT;
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);
 }
 
 /**
@@ -472,10 +454,10 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
   *         it is not possible to program or erase the flash sector i if CortexM3  
   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
   * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
+  * @param  WRPSector specifies the sector(s) to be write protected.
   *         The value of this parameter depend on device used within the same series 
   * 
-  * @param  Banks: Enable write protection on all the sectors for the specific bank
+  * @param  Banks Enable write protection on all the sectors for the specific bank
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
   *
@@ -484,7 +466,10 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Banks);
+
   /* Check the parameters */
   assert_param(IS_OB_WRP_SECTOR(WRPSector));
   assert_param(IS_FLASH_BANK(Banks));
@@ -507,10 +492,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
   *         it is not possible to program or erase the flash sector if CortexM3  
   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
   * 
-  * @param  WRPSector: specifies the sector(s) to be write protected.
+  * @param  WRPSector specifies the sector(s) to be write protected.
   *         The value of this parameter depend on device used within the same series 
   * 
-  * @param  Banks: Enable write protection on all the sectors for the specific bank
+  * @param  Banks Enable write protection on all the sectors for the specific bank
   *          This parameter can be one of the following values:
   *            @arg FLASH_BANK_1: WRP on all sectors of bank1
   *
@@ -519,7 +504,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Banks);
+
   /* Check the parameters */
   assert_param(IS_OB_WRP_SECTOR(WRPSector));
   assert_param(IS_FLASH_BANK(Banks));
@@ -537,7 +525,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
 
 /**
   * @brief  Set the read protection level.
-  * @param  Level: specifies the read protection level.
+  * @param  Level specifies the read protection level.
   *          This parameter can be one of the following values:
   *            @arg OB_RDP_LEVEL_0: No protection
   *            @arg OB_RDP_LEVEL_1: Read protection of the memory
@@ -567,15 +555,15 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
 
 /**
   * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
-  * @param  Iwdg: Selects the IWDG mode
+  * @param  Iwdg Selects the IWDG mode
   *          This parameter can be one of the following values:
   *            @arg OB_IWDG_SW: Software IWDG selected
   *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop: Reset event when entering STOP mode.
+  * @param  Stop Reset event when entering STOP mode.
   *          This parameter  can be one of the following values:
   *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
   *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby: Reset event when entering Standby mode.
+  * @param  Stdby Reset event when entering Standby mode.
   *          This parameter  can be one of the following values:
   *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
   *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
@@ -608,7 +596,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t
 
 /**
   * @brief  Set the BOR Level. 
-  * @param  Level: specifies the Option Bytes BOR Reset Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
   *          This parameter can be one of the following values:
   *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
   *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
@@ -666,13 +654,13 @@ static uint8_t FLASH_OB_GetRDP(void)
   {
     readstatus = OB_RDP_LEVEL_2;
   }
-  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
+  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))
   {
-    readstatus = OB_RDP_LEVEL_1;
+    readstatus = OB_RDP_LEVEL_0;
   }
   else 
   {
-    readstatus = OB_RDP_LEVEL_0;
+    readstatus = OB_RDP_LEVEL_1;
   }
 
   return readstatus;
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c
index f16d3498..cf8caaf3 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -95,32 +93,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -134,6 +116,13 @@
   * @{
   */
 
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+  * which may be out of array bounds [..,UNKNOWN] in following APIs:
+  * HAL_GPIO_Init
+  * HAL_GPIO_DeInit
+  */
+
 #ifdef HAL_GPIO_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
@@ -141,15 +130,15 @@
 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
   * @{
   */
-#define GPIO_MODE             ((uint32_t)0x00000003)
-#define EXTI_MODE             ((uint32_t)0x10000000)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
-#define RISING_EDGE           ((uint32_t)0x00100000)
-#define FALLING_EDGE          ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
-
-#define GPIO_NUMBER           ((uint32_t)16)
+#define GPIO_MODE             0x00000003U
+#define EXTI_MODE             0x10000000U
+#define GPIO_MODE_IT          0x00010000U
+#define GPIO_MODE_EVT         0x00020000U
+#define RISING_EDGE           0x00100000U
+#define FALLING_EDGE          0x00200000U
+#define GPIO_OUTPUT_TYPE      0x00000010U
+
+#define GPIO_NUMBER           16U
 /**
   * @}
   */
@@ -180,17 +169,16 @@
 
 /**
   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
   *         the configuration information for the specified GPIO peripheral.
   * @retval None
   */
 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 {
-  uint32_t position;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t temp = 0x00;
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t temp;
 
   /* Check the parameters */
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -199,32 +187,32 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 
   /* Configure the port pins */
-  for(position = 0; position < GPIO_NUMBER; position++)
+  while (((GPIO_Init->Pin) >> position) != 0x00u)
   {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 
-    if(iocurrent == ioposition)
+    if (iocurrent != 0x00u)
     {
       /*--------------------- GPIO Mode Configuration ------------------------*/
       /* In case of Alternate function mode selection */
       if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
       {
-        /* Check the Alternate function parameter */
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
         assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
         /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3];
-        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
-        GPIOx->AFR[position >> 3] = temp;
+        temp = GPIOx->AFR[position >> 3u];
+        temp &= ~(0xFu << ((position & 0x07u) * 4u));
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+        GPIOx->AFR[position >> 3u] = temp;
       }
 
       /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
       temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODER0 << (position * 2));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
       GPIOx->MODER = temp;
 
       /* In case of Output or Alternate function mode selection */
@@ -234,22 +222,22 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         /* Check the Speed parameter */
         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
         /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR; 
-        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-        temp |= (GPIO_Init->Speed << (position * 2));
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
+        temp |= (GPIO_Init->Speed << (position * 2u));
         GPIOx->OSPEEDR = temp;
 
         /* Configure the IO Output Type */
         temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
         GPIOx->OTYPER = temp;
       }
 
       /* Activate the Pull-up or Pull down resistor for the current IO */
       temp = GPIOx->PUPDR;
-      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-      temp |= ((GPIO_Init->Pull) << (position * 2));
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
+      temp |= ((GPIO_Init->Pull) << (position * 2u));
       GPIOx->PUPDR = temp;
 
       /*--------------------- EXTI Mode Configuration ------------------------*/
@@ -259,14 +247,14 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         /* Enable SYSCFG Clock */
         __HAL_RCC_SYSCFG_CLK_ENABLE();
 
-        temp = SYSCFG->EXTICR[position >> 2];
-        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
-        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
-        SYSCFG->EXTICR[position >> 2] = temp;
+        temp = SYSCFG->EXTICR[position >> 2u];
+        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
+        SYSCFG->EXTICR[position >> 2u] = temp;
 
         /* Clear EXTI line configuration */
         temp = EXTI->IMR;
-        temp &= ~((uint32_t)iocurrent);
+        temp &= ~(iocurrent);
         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
         {
           temp |= iocurrent;
@@ -274,7 +262,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->IMR = temp;
 
         temp = EXTI->EMR;
-        temp &= ~((uint32_t)iocurrent);
+        temp &= ~(iocurrent);
         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
         {
           temp |= iocurrent;
@@ -283,7 +271,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
         /* Clear Rising Falling edge configuration */
         temp = EXTI->RTSR;
-        temp &= ~((uint32_t)iocurrent);
+        temp &= ~(iocurrent);
         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
         {
           temp |= iocurrent;
@@ -291,7 +279,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->RTSR = temp;
 
         temp = EXTI->FTSR;
-        temp &= ~((uint32_t)iocurrent);
+        temp &= ~(iocurrent);
         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
         {
           temp |= iocurrent;
@@ -299,70 +287,74 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         EXTI->FTSR = temp;
       }
     }
+
+    position++;
   }
 }
 
 /**
   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin specifies the port bit to be written.
   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 {
-  uint32_t position;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t tmp = 0x00;
+  uint32_t position = 0x00u;
+  uint32_t iocurrent;
+  uint32_t tmp;
 
   /* Check the parameters */
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
   /* Configure the port pins */
-  for(position = 0; position < GPIO_NUMBER; position++)
+  while ((GPIO_Pin >> position) != 0x00u)
   {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (GPIO_Pin) & ioposition;
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1uL << position);
 
-    if(iocurrent == ioposition)
+    if (iocurrent != 0x00u)
     {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+
+      tmp = SYSCFG->EXTICR[position >> 2u];
+      tmp &= (0x0FuL << (4u * (position & 0x03u)));
+      if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~((uint32_t)iocurrent);
+        EXTI->EMR &= ~((uint32_t)iocurrent);
+        
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR &= ~((uint32_t)iocurrent);
+        EXTI->FTSR &= ~((uint32_t)iocurrent);
+
+        /* Configure the External Interrupt or event for the current IO */
+        tmp = 0x0FuL << (4u * (position & 0x03u));
+        SYSCFG->EXTICR[position >> 2u] &= ~tmp;
+      }
+
       /*------------------------- GPIO Mode Configuration --------------------*/
       /* Configure IO Direction in Input Floating Mode */
-      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
 
       /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+      GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
 
       /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
 
       /* Configure the default value IO Output Type */
       GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
 
       /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      tmp = SYSCFG->EXTICR[position >> 2];
-      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
-      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
-      {
-        /* Configure the External Interrupt or event for the current IO */
-        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
-        SYSCFG->EXTICR[position >> 2] &= ~tmp;
-
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-        
-        /* Clear Rising Falling edge configuration */
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-      }
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
     }
+
+    position++;
   }
 }
 
@@ -384,8 +376,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 
 /**
   * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin: specifies the port bit to read.
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin specifies the port bit to read.
   *         This parameter can be GPIO_PIN_x where x can be (0..15).
   * @retval The input port pin value.
   */
@@ -414,10 +406,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         accesses. In this way, there is no risk of an IRQ occurring between
   *         the read and the modify access.
   *
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral for all STM32F2XX devices
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral for all STM32F2XX devices
+  * @param  GPIO_Pin specifies the port bit to be written.
   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
+  * @param  PinState specifies the value to be written to the selected bit.
   *          This parameter can be one of the GPIO_PinState enum values:
   *            @arg GPIO_PIN_RESET: to clear the port pin
   *            @arg GPIO_PIN_SET: to set the port pin
@@ -435,14 +427,14 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
   }
   else
   {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
   }
 }
 
 /**
   * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral. 
-  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral. 
+  * @param  GPIO_Pin Specifies the pins to be toggled.
   * @retval None
   */
 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -450,7 +442,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
-  GPIOx->ODR ^= GPIO_Pin;
+  if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
 }
 
 /**
@@ -459,8 +458,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
   * @note   The configuration of the locked GPIO pins can no longer be modified
   *         until the next reset.
-  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
-  * @param  GPIO_Pin: specifies the port bit to be locked.
+  * @param  GPIOx where x can be (A..I) to select the GPIO peripheral for STM32F2XX family
+  * @param  GPIO_Pin specifies the port bit to be locked.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
@@ -479,10 +478,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   GPIOx->LCKR = GPIO_Pin;
   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
   GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
+  /* Read LCKK register. This read is mandatory to complete key lock sequence */
   tmp = GPIOx->LCKR;
 
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  /* read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
   {
     return HAL_OK;
   }
@@ -494,13 +494,13 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
 /**
   * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 {
   /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
   {
     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
     HAL_GPIO_EXTI_Callback(GPIO_Pin);
@@ -509,11 +509,13 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 
 /**
   * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin: Specifies the pins connected EXTI line
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
   * @retval None
   */
 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
   /* NOTE: This function Should not be modified, when the callback is needed,
            the HAL_GPIO_EXTI_Callback could be implemented in the user file
    */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hash.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hash.c
index 3b728ea9..bf28d56c 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hash.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hash.c
@@ -2,334 +2,277 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hash.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   HASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the HASH peripheral:
-  *           + Initialization and de-initialization functions
-  *           + HASH/HMAC Processing functions by algorithm using polling mode
-  *           + HASH/HMAC functions by algorithm using interrupt mode
-  *           + HASH/HMAC functions by algorithm using DMA mode
-  *           + Peripheral State functions
-  *         
+  *           + Initialization and de-initialization methods
+  *           + HASH or HMAC processing in polling mode
+  *           + HASH or HMAC processing in interrupt mode
+  *           + HASH or HMAC processing in DMA mode
+  *           + Peripheral State methods
+  *           + HASH or HMAC processing suspension/resumption
+  *
   @verbatim
-  ==============================================================================
+ ===============================================================================
                      ##### How to use this driver #####
-  ==============================================================================
+ ===============================================================================
     [..]
     The HASH HAL driver can be used as follows:
+
     (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
-        (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
-        (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
+        (##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
+        (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
             (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
             (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
-            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
-        (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
-            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
-            (+++) Configure and enable one DMA stream one for managing data transfer from
+            (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
+        (##) When resorting to DMA-based APIs  (e.g. HAL_HASH_xxx_Start_DMA())
+            (+++) Enable the DMAx interface clock using
+                   __DMAx_CLK_ENABLE()
+            (+++) Configure and enable one DMA stream to manage data transfer from
                 memory to peripheral (input stream). Managing data transfer from
-                peripheral to memory can be performed only using CPU
+                peripheral to memory can be performed only using CPU.
             (+++) Associate the initialized DMA handle to the HASH DMA handle
                 using  __HAL_LINKDMA()
             (+++) Configure the priority and enable the NVIC for the transfer complete
-                interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
-    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
-        (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
-        (##) For HMAC, the encryption key.
-        (##) For HMAC, the key size used for encryption.
-    (#)Three processing functions are available:
+                interrupt on the DMA Stream: use
+                 HAL_NVIC_SetPriority() and
+                 HAL_NVIC_EnableIRQ()
+
+    (#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
+        (##) resorts to HAL_HASH_MspInit() for low-level initialization,
+        (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
+
+    (#)Three processing schemes are available:
         (##) Polling mode: processing APIs are blocking functions
-             i.e. they process the data and wait till the digest computation is finished
-             e.g. HAL_HASH_SHA1_Start()
-        (##) Interrupt mode: encryption and decryption APIs are not blocking functions
-                i.e. they process the data under interrupt
-                e.g. HAL_HASH_SHA1_Start_IT()
+             i.e. they process the data and wait till the digest computation is finished,
+             e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
+        (##) Interrupt mode: processing APIs are not blocking functions
+                i.e. they process the data under interrupt,
+                e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
         (##) DMA mode: processing APIs are not blocking functions and the CPU is
+             not used for data transfer i.e. the data transfer is ensured by DMA,
+                e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
+                for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
+                is then required to retrieve the digest.
+
+    (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
+       initialized and processes the buffer fed in input. When the input data have all been
+       fed to the IP, the digest computation can start.
+
+    (#)Multi-buffer processing is possible in polling and DMA mode.
+        (##) In polling mode, only multi-buffer HASH processing is possible.
+             API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
+             User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as
+             well the computed digest.
+
+        (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
+              (+++) HASH processing DMA mode: processing APIs are not blocking functions and the CPU is
              not used for data transfer i.e. the data transfer is ensured by DMA
                 e.g. HAL_HASH_SHA1_Start_DMA()
-    (#)When the processing function is called at first time after HAL_HASH_Init()
-       the HASH peripheral is initialized and processes the buffer in input.
-       After that, the digest computation is started.
-       When processing multi-buffer use the accumulate function to write the
-       data in the peripheral without starting the digest computation. In last 
-       buffer use the start function to input the last buffer ans start the digest
-       computation.
-       (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
-       (##) write (n-1)th data buffer in the peripheral without starting the digest computation
-       (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
-    (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
-    (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
-       After that, call the finish function in order to get the digest value
-       e.g. HAL_HASH_SHA1_Finish()
+             (+++) HMAC processing (requires to resort to extended functions):
+             after initialization, the key and the first input buffer are entered
+             in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
+             starts step 2.
+             The following buffers are next entered with the API  HAL_HMACEx_xxx_Step2_DMA(). At this
+             point, the HMAC processing is still carrying out step 2.
+             Then, step 2 for the last input buffer and step 3 are carried out by a single call
+             to HAL_HMACEx_xxx_Step2_3_DMA().
+
+             The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
+
+
+    (#)Context swapping.
+        (##) Two APIs are available to suspend HASH or HMAC processing:
+             (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
+             (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
+
+        (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
+            to save in memory the IP context. This context can be restored afterwards
+            to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
+
+        (##) Once the HASH IP has been restored to the same configuration as that at suspension
+             time, processing can be restarted with the same API call (same API, same handle,
+             same parameters) as done before the suspension. Relevant parameters to restart at
+             the proper location are internally saved in the HASH handle.
+
     (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
 
+     *** Callback registration ***
+     ===================================
+     [..]
+      (#) The compilation define  USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callbacks.
+          Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+
+      (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+            (+) InCpltCallback    : callback for input completion.
+            (+) DgstCpltCallback  : callback for digest computation completion.
+            (+) ErrorCallback     : callback for error.
+            (+) MspInitCallback   : HASH MspInit.
+            (+) MspDeInitCallback : HASH MspDeInit.
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+      (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+          weak (surcharged) function.
+          @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (+) InCpltCallback    : callback for input completion.
+            (+) DgstCpltCallback  : callback for digest computation completion.
+            (+) ErrorCallback     : callback for error.
+            (+) MspInitCallback   : HASH MspInit.
+            (+) MspDeInitCallback : HASH MspDeInit.
+
+      (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+          examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+          Exception done for MspInit and MspDeInit callbacks that are respectively
+          reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
+          and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+          If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+          keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+          Callbacks can be registered/unregistered in READY state only.
+          Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+          in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+          during the Init/DeInit.
+          In that case first register the MspInit/MspDeInit user callbacks
+          using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
+          or @ref HAL_HASH_Init function.
+
+          When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
+          not defined, the callback registering feature is not available
+          and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
+#if defined (HASH)
 
-/** @defgroup HASH HASH
+/** @defgroup HASH  HASH
   * @brief HASH HAL module driver.
   * @{
   */
 
 #ifdef HAL_HASH_MODULE_ENABLED
 
-#if defined(STM32F215xx) || defined(STM32F217xx)
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup HASH_Private_Functions HASH Private Functions
+/** @defgroup HASH_Private_Constants HASH Private Constants
   * @{
   */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
-static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
+
+/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
+  * @{
+  */
+#define HASH_DIGEST_CALCULATION_NOT_STARTED       ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
+#define HASH_DIGEST_CALCULATION_STARTED           ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register     */
 /**
   * @}
   */
-  
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup HASH_Private_Functions
+
+/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
   * @{
   */
-
+#define HASH_NUMBER_OF_CSR_REGISTERS              54U     /*!< Number of Context Swap Registers */
 /**
-  * @brief  DMA HASH Input Data complete callback. 
-  * @param  hdma: DMA handle
-  * @retval None
+  * @}
   */
-static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
-{
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  uint32_t inputaddr = 0;
-  uint32_t buffersize = 0;
-  
-  if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
-  {
-    /* Disable the DMA transfer */
-    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-    
-    /* Change HASH peripheral state */
-    hhash->State = HAL_HASH_STATE_READY;
-    
-    /* Call Input data transfer complete callback */
-    HAL_HASH_InCpltCallback(hhash);
-  }
-  else
-  {
-    /* Increment Interrupt counter */
-    hhash->HashInCount++;
-    /* Disable the DMA transfer before starting the next transfer */
-    HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-    
-    if(hhash->HashInCount <= 2)
-    {
-      /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
-      if(hhash->HashInCount == 1)
-      {
-        inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-        buffersize = hhash->HashBuffSize;
-      }
-      /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
-      else if(hhash->HashInCount == 2)
-      {
-        inputaddr = (uint32_t)hhash->Init.pKey;
-        buffersize = hhash->Init.KeySize;
-      }
-      /* Configure the number of valid bits in last word of the message */
-      MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
-      
-      /* Set the HASH DMA transfer complete */
-      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-      
-      /* Enable the DMA In DMA Stream */
-      HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
-      
-      /* Enable DMA requests */
-      HASH->CR |= (HASH_CR_DMAE);
-    }
-    else
-    {
-      /* Disable the DMA transfer */
-      HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
-      
-      /* Reset the InCount */
-      hhash->HashInCount = 0;
-      
-      /* Change HASH peripheral state */
-      hhash->State = HAL_HASH_STATE_READY;
-      
-      /* Call Input data transfer complete callback */
-      HAL_HASH_InCpltCallback(hhash);
-    }
-  }
-}
 
+/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
+  * @{
+  */
+#define HASH_TIMEOUTVALUE                         1000U   /*!< Time-out value  */
 /**
-  * @brief  DMA HASH communication error callback. 
-  * @param  hdma: DMA handle
-  * @retval None
+  * @}
   */
-static void HASH_DMAError(DMA_HandleTypeDef *hdma)
-{
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hhash->State= HAL_HASH_STATE_READY;
-  HAL_HASH_ErrorCallback(hhash);
-}
 
+/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
+  * @{
+  */
+#define HASH_DMA_SUSPENSION_WORDS_LIMIT             20U   /*!< Number of words below which DMA suspension is aborted */
 /**
-  * @brief  Writes the input buffer in data register.
-  * @param  pInBuffer: Pointer to input buffer
-  * @param  Size: The size of input buffer
-  * @retval None
+  * @}
   */
-static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
-{
-  uint32_t buffercounter;
-  uint32_t inputaddr = (uint32_t) pInBuffer;
-  
-  for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
-  {
-    HASH->DIN = *(uint32_t*)inputaddr;
-    inputaddr+=4;
-  }
-}
 
 /**
-  * @brief  Provides the message digest result.
-  * @param  pMsgDigest: Pointer to the message digest
-  * @param  Size: The size of the message digest in bytes
-  * @retval None
+  * @}
   */
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
-{
-  uint32_t msgdigest = (uint32_t)pMsgDigest;
-  
-  switch(Size)
-  {
-  case 16:
-    /* Read the message digest */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    break;
-  case 20:
-    /* Read the message digest */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    break;
-  case 28:
-    /* Read the message digest */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    break;
-  case 32:
-    /* Read the message digest */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    msgdigest+=4;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    break;
-  default:
-    break;
-  }
-}
 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
+static void HASH_DMAError(DMA_HandleTypeDef *hdma);
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
 /**
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HASH_Exported_Functions
+/** @defgroup HASH_Exported_Functions HASH Exported Functions
   * @{
   */
-  
 
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
+/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization, configuration and call-back functions.
  *
-@verbatim    
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the HASH according to the specified parameters 
-          in the HASH_InitTypeDef and creates the associated handle.
-      (+) DeInitialize the HASH peripheral.
-      (+) Initialize the HASH MSP.
-      (+) DeInitialize HASH MSP. 
- 
+      (+) Initialize the HASH according to the specified parameters
+          in the HASH_InitTypeDef and create the associated handle
+      (+) DeInitialize the HASH peripheral
+      (+) Initialize the HASH MCU Specific Package (MSP)
+      (+) DeInitialize the HASH MSP
+
+    [..]  This section provides as well call back functions definitions for user
+          code to manage:
+      (+) Input data transfer to IP completion
+      (+) Calculated digest retrieval completion
+      (+) Error management
+
+
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the HASH according to the specified parameters in the
-            HASH_HandleTypeDef and creates the associated handle.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  Initialize the HASH according to the specified parameters in the
+            HASH_HandleTypeDef and create the associated handle.
+  * @note   Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(),
+  *         other configuration bits are set by HASH or HMAC processing APIs.
+  * @param  hhash: HASH handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
@@ -339,774 +282,576 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
   {
     return HAL_ERROR;
   }
-
+  
   /* Check the parameters */
   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
-   
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+  if (hhash->State == HAL_HASH_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhash->Lock = HAL_UNLOCKED;
+
+    /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
+    hhash->InCpltCallback =  HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
+    hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+    hhash->ErrorCallback =  HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
+    if(hhash->MspInitCallback == NULL)
+    {
+      hhash->MspInitCallback = HAL_HASH_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hhash->MspInitCallback(hhash);
+  }
+#else
   if(hhash->State == HAL_HASH_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hhash->Lock = HAL_UNLOCKED;
+
     /* Init the low level hardware */
     HAL_HASH_MspInit(hhash);
   }
-  
-  /* Change the HASH state */
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
+
+    /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Reset HashInCount, HashBuffSize and HashITCounter */
+
+  /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
   hhash->HashInCount = 0;
   hhash->HashBuffSize = 0;
   hhash->HashITCounter = 0;
-  
-  /* Set the data type */
-  HASH->CR |= (uint32_t) (hhash->Init.DataType);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Set the default HASH phase */
+  hhash->NbWordsAlreadyPushed = 0;
+  /* Reset digest calculation bridle (MDMAT bit control) */
+  hhash->DigestCalculationDisable = RESET;
+  /* Set phase to READY */
   hhash->Phase = HAL_HASH_PHASE_READY;
-  
+
+  /* Set the data type bit */
+  MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
+  /* Reset HASH handle status */
+  hhash->Status = HAL_OK;
+
+  /* Set the HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_READY;
+
+  /* Initialise the error code */
+  hhash->ErrorCode = HAL_HASH_ERROR_NONE;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the HASH peripheral.
-  * @note   This API must be called before starting a new processing. 
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  DeInitialize the HASH peripheral.
+  * @param  hhash: HASH handle.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
-{ 
+{
   /* Check the HASH handle allocation */
   if(hhash == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_BUSY;
-  
+
   /* Set the default HASH phase */
   hhash->Phase = HAL_HASH_PHASE_READY;
-  
-  /* Reset HashInCount, HashBuffSize and HashITCounter */
+
+  /* Reset HashInCount, HashITCounter and HashBuffSize */
   hhash->HashInCount = 0;
   hhash->HashBuffSize = 0;
   hhash->HashITCounter = 0;
-  
-  /* DeInit the low level hardware */
+  /* Reset digest calculation bridle (MDMAT bit control) */
+  hhash->DigestCalculationDisable = RESET;
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+    if(hhash->MspDeInitCallback == NULL)
+    {
+      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+    }
+
+    /* DeInit the low level hardware */
+    hhash->MspDeInitCallback(hhash);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
   HAL_HASH_MspDeInit(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_RESET;  
+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 
-  /* Release Lock */
-  __HAL_UNLOCK(hhash);
+
+  /* Reset HASH handle status */
+  hhash->Status = HAL_OK;
+
+  /* Set the HASH state to Ready */
+  hhash->State = HAL_HASH_STATE_RESET;
+
+  /* Initialise the error code */
+  hhash->ErrorCode = HAL_HASH_ERROR_NONE;
 
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Initializes the HASH MSP.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  Initialize the HASH MSP.
+  * @param  hhash: HASH handle.
   * @retval None
   */
 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_HASH_MspInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspInit() can be implemented in the user file.
    */
 }
 
 /**
-  * @brief  DeInitializes HASH MSP.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  DeInitialize the HASH MSP.
+  * @param  hhash: HASH handle.
   * @retval None
   */
 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_HASH_MspDeInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_MspDeInit() can be implemented in the user file.
    */
 }
 
 /**
-  * @brief  Input data transfer complete callback.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  Input data transfer complete call back.
+  * @note   HAL_HASH_InCpltCallback() is called when the complete input message
+  *         has been fed to the IP. This API is invoked only when input data are
+  *         entered under interruption or thru DMA.
+  * @param  hhash: HASH handle.
   * @retval None
   */
- __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_HASH_InCpltCallback could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_InCpltCallback() can be implemented in the user file.
+   */
 }
 
 /**
-  * @brief  Data transfer Error callback.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  Digest computation complete call back.
+  * @note   HAL_HASH_DgstCpltCallback() is used under interruption, is not
+  *         relevant with DMA.
+  * @param  hhash: HASH handle.
   * @retval None
   */
- __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_HASH_ErrorCallback could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_DgstCpltCallback() can be implemented in the user file.
+   */
 }
 
 /**
-  * @brief  Digest computation complete callback. It is used only with interrupt.
-  * @note   This callback is not relevant with DMA.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief  Error callback.
+  * @note   Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
+  *         to retrieve the error type.
+  * @param  hhash: HASH handle.
   * @retval None
   */
- __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
+__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* NOTE : This function should not be modified; when the callback is needed,
+            HAL_HASH_ErrorCallback() can be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User HASH Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hhash HASH handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+  *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+  *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+  *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+  *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hhash);
+
+  if(HAL_HASH_STATE_READY == hhash->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_HASH_INPUTCPLT_CB_ID :
+      hhash->InCpltCallback = pCallback;
+      break;
+
+    case HAL_HASH_DGSTCPLT_CB_ID :
+      hhash->DgstCpltCallback = pCallback;
+      break;
+
+    case HAL_HASH_ERROR_CB_ID :
+      hhash->ErrorCallback = pCallback;
+      break;
+
+    case HAL_HASH_MSPINIT_CB_ID :
+      hhash->MspInitCallback = pCallback;
+      break;
+
+    case HAL_HASH_MSPDEINIT_CB_ID :
+      hhash->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+     /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(HAL_HASH_STATE_RESET == hhash->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_HASH_MSPINIT_CB_ID :
+      hhash->MspInitCallback = pCallback;
+      break;
+
+    case HAL_HASH_MSPDEINIT_CB_ID :
+      hhash->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+     /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhash);
+  return status;
+}
+
+/**
+  * @brief  Unregister a HASH Callback
+  *         HASH Callback is redirected to the weak (surcharged) predefined callback
+  * @param hhash HASH handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
+  *          @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
+  *          @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
+  *          @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
+  *          @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_HASH_DgstCpltCallback could be implemented in the user file
-   */ 
+HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhash);
+
+  if(HAL_HASH_STATE_READY == hhash->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_HASH_INPUTCPLT_CB_ID :
+      hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
+      break;
+
+    case HAL_HASH_DGSTCPLT_CB_ID :
+      hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+      break;
+
+    case HAL_HASH_ERROR_CB_ID :
+      hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
+      break;
+
+    case HAL_HASH_MSPINIT_CB_ID :
+      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
+      break;
+
+    case HAL_HASH_MSPDEINIT_CB_ID :
+      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
+      break;
+
+    default :
+     /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(HAL_HASH_STATE_RESET == hhash->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_HASH_MSPINIT_CB_ID :
+      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
+      break;
+
+    case HAL_HASH_MSPDEINIT_CB_ID :
+      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
+      break;
+
+    default :
+     /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+     /* Update the error code */
+     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+     /* update return status */
+      status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhash);
+  return status;
 }
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode 
- *  @brief   processing functions using polling mode 
+/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
+ *  @brief   HASH processing functions using polling mode.
  *
-@verbatim   
+@verbatim
+ ===============================================================================
+                 ##### Polling mode HASH processing functions #####
  ===============================================================================
-              ##### HASH processing using polling mode functions#####
- ===============================================================================  
     [..]  This section provides functions allowing to calculate in polling mode
           the hash value using one of the following algorithms:
       (+) MD5
+         (++) HAL_HASH_MD5_Start()
+         (++) HAL_HASH_MD5_Accumulate()
       (+) SHA1
+         (++) HAL_HASH_SHA1_Start()
+         (++) HAL_HASH_SHA1_Accumulate()
+
+    [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
+
+    [..]  In case of multi-buffer HASH processing (a single digest is computed while
+          several buffers are fed to the IP), the user can resort to successive calls
+          to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
+          to HAL_HASH_xxx_Start().
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
-            The digest is available in pOutBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
-  *          and appending the input buffer is no more possible.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
   * @param  Timeout: Timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 16);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-   
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is multiple of 64 bytes, appending the input buffer is possible.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware
-  *          and appending the input buffer is no more possible.
+  * @brief  If not already done, initialize the HASH peripheral in MD5 mode then
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_MD5_Start().
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+{
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
-            The digest is available in pOutBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).  
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
-  * @param  Timeout: Timeout value  
+  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;   
-
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hhash->State = HAL_HASH_STATE_TIMEOUT;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 20);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
+  * @brief  If not already done, initialize the HASH peripheral in SHA1 mode then
+  *         processes pInBuffer.
+  * @note   Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed
+  *         several input buffers back-to-back to the IP that will yield a single
+  *         HASH signature once all buffers have been entered. Wrap-up of input
+  *         buffers feeding and retrieval of digest is done by a call to
+  *         HAL_HASH_SHA1_Start().
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.
+  * @note   Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start()
+  *         to read it, feeding at the same time the last input buffer to the IP.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able
+  *         to manage the ending buffer with a length in bytes not a multiple of 4.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  
-  /* Check the parameters */
-  assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
 }
 
+
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
- *  @brief   processing functions using interrupt mode. 
+/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
+ *  @brief   HASH processing functions using interrupt mode.
  *
-@verbatim   
+@verbatim
+ ===============================================================================
+                 ##### Interruption mode HASH processing functions #####
  ===============================================================================
-              ##### HASH processing using interrupt mode functions #####
- ===============================================================================  
     [..]  This section provides functions allowing to calculate in interrupt mode
           the hash value using one of the following algorithms:
       (+) MD5
+         (++) HAL_HASH_MD5_Start_IT()
       (+) SHA1
+         (++) HAL_HASH_SHA1_Start_IT()
+
+    [..]  API HAL_HASH_IRQHandler() manages each HASH interruption.
+
+    [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in
+         HMAC processing mode.
+
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
-  *         The digest is available in pOutBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).   
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+  * @brief  Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  uint32_t buffercounter;
-  uint32_t inputcounter;
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  if(hhash->State == HAL_HASH_STATE_READY)
-  {
-    /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_BUSY;
-    
-    hhash->HashInCount = Size;
-    hhash->pHashInBuffPtr = pInBuffer;
-    hhash->pHashOutBuffPtr = pOutBuffer;
-    
-    /* Check if initialization phase has already been performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Select the SHA1 mode */
-      HASH->CR |= HASH_ALGOSELECTION_MD5;
-      /* Reset the HASH processor core, so that the HASH will be ready to compute 
-         the message digest of a new message */
-      HASH->CR |= HASH_CR_INIT;
-    }
-    /* Reset interrupt counter */
-    hhash->HashITCounter = 0;
-    
-    /* Set the phase */
-    hhash->Phase = HAL_HASH_PHASE_PROCESS;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hhash);
-    
-    /* Enable Interrupts */
-    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
-  {
-    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
-    
-    if(hhash->HashInCount == 0)
-    {
-      /* Disable Interrupts */
-      HASH->IMR = 0;
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
-      /* Call digest computation complete callback */
-      HAL_HASH_DgstCpltCallback(hhash);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhash);
-      
-      /* Return function status */
-      return HAL_OK;
-    }
-  }
-  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
-  {
-    if(hhash->HashInCount >= 68)
-    {
-      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-      /* Write the Input block in the Data IN register */
-      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-        inputaddr+=4;
-      }
-      if(hhash->HashITCounter == 0)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-
-        if(hhash->HashInCount >= 68)
-        {
-          /* Decrement buffer counter */
-          hhash->HashInCount -= 68;
-          hhash->pHashInBuffPtr+= 68;
-        }
-        else
-        {
-          hhash->HashInCount = 0;
-          hhash->pHashInBuffPtr+= hhash->HashInCount;
-        }
-        /* Set Interrupt counter */
-        hhash->HashITCounter = 1;
-      }
-      else
-      {
-        /* Decrement buffer counter */
-        hhash->HashInCount -= 64;
-        hhash->pHashInBuffPtr+= 64;
-      }
-    }
-    else
-    {
-      /* Get the buffer address */
-      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-      /* Get the buffer counter */
-      inputcounter = hhash->HashInCount;
-      /* Disable Interrupts */
-      HASH->IMR &= ~(HASH_IT_DINI);
-      /* Configure the number of valid bits in last word of the message */
-      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-      
-      if((inputcounter > 4) && (inputcounter%4))
-      {
-        inputcounter = (inputcounter+4-inputcounter%4);
-      }
-      else if ((inputcounter < 4) && (inputcounter != 0))
-      {
-        inputcounter = 4;
-      }
-      /* Write the Input block in the Data IN register */
-      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-        inputaddr+=4;
-      }
-      /* Start the digest calculation */
-      __HAL_HASH_START_DIGEST();
-      /* Reset buffer counter */
-      hhash->HashInCount = 0;
-      
-      /* Call Input data transfer complete callback */
-      HAL_HASH_InCpltCallback(hhash);
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
 }
 
+
 /**
-  * @brief  Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
-  *         The digest is available in pOutBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed). 
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+  * @brief  Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  uint32_t inputaddr;
-  uint32_t outputaddr;
-  uint32_t buffercounter;
-  uint32_t inputcounter;
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  if(hhash->State == HAL_HASH_STATE_READY)
-  {
-    /* Change the HASH state */
-    hhash->State = HAL_HASH_STATE_BUSY;
-    
-    hhash->HashInCount = Size;
-    hhash->pHashInBuffPtr = pInBuffer;
-    hhash->pHashOutBuffPtr = pOutBuffer;
-    
-    /* Check if initialization phase has already been performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Select the SHA1 mode */
-      HASH->CR |= HASH_ALGOSELECTION_SHA1;
-      /* Reset the HASH processor core, so that the HASH will be ready to compute 
-         the message digest of a new message */
-      HASH->CR |= HASH_CR_INIT;
-    }
-    
-    /* Reset interrupt counter */
-    hhash->HashITCounter = 0;
-    
-    /* Set the phase */
-    hhash->Phase = HAL_HASH_PHASE_PROCESS;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hhash);
-    
-    /* Enable Interrupts */
-    HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
-  {
-    outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
-    /* Read the Output block from the Output FIFO */
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[0]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[1]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[2]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[3]);
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = __REV(HASH->HR[4]);
-    if(hhash->HashInCount == 0)
-    {
-      /* Disable Interrupts */
-      HASH->IMR = 0;
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_READY;
-      /* Call digest computation complete callback */
-      HAL_HASH_DgstCpltCallback(hhash);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhash);
-      
-      /* Return function status */
-      return HAL_OK;
-    }
-  }
-  if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
-  {
-    if(hhash->HashInCount >= 68)
-    {
-      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-      /* Write the Input block in the Data IN register */
-      for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-        inputaddr+=4;
-      }
-      if(hhash->HashITCounter == 0)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-        if(hhash->HashInCount >= 68)
-        {
-          /* Decrement buffer counter */
-          hhash->HashInCount -= 68;
-          hhash->pHashInBuffPtr+= 68;
-        }
-        else
-        {
-          hhash->HashInCount = 0;
-          hhash->pHashInBuffPtr+= hhash->HashInCount;
-        }
-        /* Set Interrupt counter */
-        hhash->HashITCounter = 1;
-      }
-      else
-      {
-        /* Decrement buffer counter */
-        hhash->HashInCount -= 64;
-        hhash->pHashInBuffPtr+= 64;
-      }
-    }
-    else
-    {
-      /* Get the buffer address */
-      inputaddr = (uint32_t)hhash->pHashInBuffPtr;
-      /* Get the buffer counter */
-      inputcounter = hhash->HashInCount;
-      /* Disable Interrupts */
-      HASH->IMR &= ~(HASH_IT_DINI);
-      /* Configure the number of valid bits in last word of the message */
-      __HAL_HASH_SET_NBVALIDBITS(inputcounter);
-      
-      if((inputcounter > 4) && (inputcounter%4))
-      {
-        inputcounter = (inputcounter+4-inputcounter%4);
-      }
-      else if ((inputcounter < 4) && (inputcounter != 0))
-      {
-        inputcounter = 4;
-      }
-      /* Write the Input block in the Data IN register */
-      for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
-      {
-        HASH->DIN = *(uint32_t*)inputaddr;
-        inputaddr+=4;
-      }
-      /* Start the digest calculation */
-      __HAL_HASH_START_DIGEST();
-      /* Reset buffer counter */
-      hhash->HashInCount = 0;
-
-      /* Call Input data transfer complete callback */
-      HAL_HASH_InCpltCallback(hhash);
-    }
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
 }
 
 /**
-  * @brief This function handles HASH interrupt request.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
+  * @brief Handle HASH interrupt request.
+  * @param hhash: HASH handle.
+  * @note  HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
+  * @note  In case of error reported during the HASH interruption processing,
+  *        HAL_HASH_ErrorCallback() API is called so that user code can
+  *        manage the error. The error type is available in hhash->Status field.
   * @retval None
   */
 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
 {
-  switch(HASH->CR & HASH_CR_ALGO)
+  hhash->Status = HASH_IT(hhash);
+  if (hhash->Status != HAL_OK)
   {
-    case HASH_ALGOSELECTION_MD5:
-       HAL_HASH_MD5_Start_IT(hhash, NULL, 0, NULL);
-    break;
-    
-    case HASH_ALGOSELECTION_SHA1:
-      HAL_HASH_SHA1_Start_IT(hhash, NULL, 0, NULL);
-    break;
-    
-    default:
-    break;
+    hhash->ErrorCode |= HAL_HASH_ERROR_IT;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+    hhash->ErrorCallback(hhash);
+#else
+    HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+    /* After error handling by code user, reset HASH handle HAL status */
+    hhash->Status = HAL_OK;
   }
 }
 
@@ -1114,738 +859,2117 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
- *  @brief   processing functions using DMA mode. 
+/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
+ *  @brief   HASH processing functions using DMA mode.
  *
-@verbatim   
+@verbatim
+ ===============================================================================
+                    ##### DMA mode HASH processing functions #####
  ===============================================================================
-              ##### HASH processing using DMA mode functions #####
- ===============================================================================  
     [..]  This section provides functions allowing to calculate in DMA mode
           the hash value using one of the following algorithms:
       (+) MD5
+         (++) HAL_HASH_MD5_Start_DMA()
+         (++) HAL_HASH_MD5_Finish()
       (+) SHA1
+         (++) HAL_HASH_SHA1_Start_DMA()
+         (++) HAL_HASH_SHA1_Finish()
+
+    [..]  When resorting to DMA mode to enter the data in the IP, user must resort
+          to  HAL_HASH_xxx_Start_DMA() then read the resulting digest with
+          HAL_HASH_xxx_Finish().
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the HASH peripheral in MD5 mode then enables DMA to
-            control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @brief  Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP.
+  * @note   Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
+  *         be called to retrieve the computed digest.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  uint32_t inputaddr  = (uint32_t)pInBuffer;
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
-  }
-   
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-    
-  /* Set the HASH DMA transfer complete callback */
-  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-  /* Set the DMA error callback */
-  hhash->hdmain->XferErrorCallback = HASH_DMAError;
-  
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-  
-  /* Enable DMA requests */
-  HASH->CR |= (HASH_CR_DMAE);
-  
-   /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
 }
 
 /**
-  * @brief  Returns the computed digest in MD5 mode
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
-  * @param  Timeout: Timeout value  
+  * @brief  Return the computed digest in MD5 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
+  *         HMAC MD5 mode.
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @param  Timeout: Timeout value.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;   
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change HASH peripheral state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 16);
-      
-  /* Change HASH peripheral state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-   /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+   return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in SHA1 mode then enables DMA to
-            control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @brief  Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
+  *         to feed the input buffer to the IP.
+  * @note   Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
+  *         be called to retrieve the computed digest.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
 {
-  uint32_t inputaddr  = (uint32_t)pInBuffer;
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute 
-       the message digest of a new message */
-    HASH->CR |= HASH_ALGOSELECTION_SHA1;
-    HASH->CR |= HASH_CR_INIT;
-  }
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Set the HASH DMA transfer complete callback */
-  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-  /* Set the DMA error callback */
-  hhash->hdmain->XferErrorCallback = HASH_DMAError;
-  
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
-  
-  /* Enable DMA requests */
-  HASH->CR |= (HASH_CR_DMAE);
-  
-   /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
 }
 
+
 /**
-  * @brief  Returns the computed digest in SHA1 mode.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.  
-  * @param  Timeout: Timeout value    
+  * @brief  Return the computed digest in SHA1 mode.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @note   HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
+  *         HMAC SHA1 mode.
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;   
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change HASH peripheral state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 20);
-  
-  /* Change HASH peripheral state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-   /* Process UnLock */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+   return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
-
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode 
- *  @brief   HMAC processing functions using polling mode . 
+/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
+ *  @brief   HMAC processing functions using polling mode.
  *
-@verbatim   
+@verbatim
+ ===============================================================================
+                 ##### Polling mode HMAC processing functions #####
  ===============================================================================
-              ##### HMAC processing using polling mode functions #####
- ===============================================================================  
     [..]  This section provides functions allowing to calculate in polling mode
           the HMAC value using one of the following algorithms:
       (+) MD5
+         (++) HAL_HMAC_MD5_Start()
       (+) SHA1
+         (++) HAL_HMAC_SHA1_Start()
+
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
-  *         then processes pInBuffer. The digest is available in pOutBuffer
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
-  * @param  Timeout: Timeout value  
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
+  * @param  Timeout: Timeout value.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;   
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Check if key size is greater than 64 bytes */
-    if(hhash->Init.KeySize > 64)
-    {
-      /* Select the HMAC MD5 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-    }
-    else
-    {
-      /* Select the HMAC MD5 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-    }
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /************************** STEP 1 ******************************************/
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /************************** STEP 2 ******************************************/
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((HAL_GetTick() - tickstart ) > Timeout)
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /************************** STEP 3 ******************************************/
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((HAL_GetTick() - tickstart ) > Timeout)
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 16);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
-  *         then processes pInBuffer. The digest is available in pOutBuffer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param   Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
-  * @param  pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
-  * @param  Timeout: Timeout value  
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
+  * @param  Timeout: Timeout value.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;   
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Check if key size is greater than 64 bytes */
-    if(hhash->Init.KeySize > 64)
-    {
-      /* Select the HMAC SHA1 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-    }
-    else
-    {
-      /* Select the HMAC SHA1 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-    }
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /************************** STEP 1 ******************************************/
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /************************** STEP 2 ******************************************/
-  /* Configure the number of valid bits in last word of the message */  
-  __HAL_HASH_SET_NBVALIDBITS(Size);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(pInBuffer, Size);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((HAL_GetTick() - tickstart ) > Timeout)
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /************************** STEP 3 ******************************************/
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Write input buffer in data register */
-  HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
-  
-  /* Start the digest calculation */
-  __HAL_HASH_START_DIGEST();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
-  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((HAL_GetTick() - tickstart ) > Timeout)
-      {
-        /* Change state */
-        hhash->State = HAL_HASH_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hhash);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /* Read the message digest */
-  HASH_GetDigest(pOutBuffer, 20);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
 }
 
 /**
   * @}
   */
 
-/** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode 
- *  @brief   HMAC processing functions using DMA mode . 
+
+/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
+ *  @brief   HMAC processing functions using interrupt mode.
  *
-@verbatim   
+@verbatim
  ===============================================================================
-                ##### HMAC processing using DMA mode functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to calculate in DMA mode
+                 ##### Interrupt mode HMAC processing functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to calculate in interrupt mode
           the HMAC value using one of the following algorithms:
       (+) MD5
+         (++) HAL_HMAC_MD5_Start_IT()
       (+) SHA1
+         (++) HAL_HMAC_SHA1_Start_IT()
 
 @endverbatim
   * @{
   */
 
+
 /**
-  * @brief  Initializes the HASH peripheral in HMAC MD5 mode
-  *         then enables DMA to control data transfer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 16 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  uint32_t inputaddr  = 0;
-  
-   /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Save buffer pointer and size in handle */
-  hhash->pHashInBuffPtr = pInBuffer;
-  hhash->HashBuffSize = Size;
-  hhash->HashInCount = 0;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Check if key size is greater than 64 bytes */
-    if(hhash->Init.KeySize > 64)
-    {
-      /* Select the HMAC MD5 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
-    }
-    else
-    {
-      /* Select the HMAC MD5 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-    }
-  }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Get the key address */
-  inputaddr = (uint32_t)(hhash->Init.pKey);
-  
-  /* Set the HASH DMA transfer complete callback */
-  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-  /* Set the DMA error callback */
-  hhash->hdmain->XferErrorCallback = HASH_DMAError;
-  
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
-  /* Enable DMA requests */
-  HASH->CR |= (HASH_CR_DMAE);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
 }
 
 /**
-  * @brief  Initializes the HASH peripheral in HMAC SHA1 mode
-  *         then enables DMA to control data transfer.
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @param  pInBuffer: Pointer to the input buffer (buffer to be hashed).
-  * @param  Size: Length of the input buffer in bytes.
-  *          If the Size is not multiple of 64 bytes, the padding is managed by hardware.
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
+  *         read the computed digest in interrupt mode.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest. Digest size is 20 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
 {
-  uint32_t inputaddr  = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hhash);
-  
-  /* Change the HASH state */
-  hhash->State = HAL_HASH_STATE_BUSY;
-  
-  /* Save buffer pointer and size in handle */
-  hhash->pHashInBuffPtr = pInBuffer;
-  hhash->HashBuffSize = Size;
-  hhash->HashInCount = 0;
-  
-  /* Check if initialization phase has already been performed */
-  if(hhash->Phase == HAL_HASH_PHASE_READY)
-  {
-    /* Check if key size is greater than 64 bytes */
-    if(hhash->Init.KeySize > 64)
+  return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
+ *  @brief   HMAC processing functions using DMA modes.
+ *
+@verbatim
+ ===============================================================================
+                 ##### DMA mode HMAC processing functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to calculate in DMA mode
+          the HMAC value using one of the following algorithms:
+      (+) MD5
+         (++) HAL_HMAC_MD5_Start_DMA()
+      (+) SHA1
+         (++) HAL_HMAC_SHA1_Start_DMA()
+
+    [..]  When resorting to DMA mode to enter the data in the IP for HMAC processing,
+          user must resort to  HAL_HMAC_xxx_Start_DMA() then read the resulting digest
+          with HAL_HASH_xxx_Finish().
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
+  *         DMA transfers to feed the key and the input buffer to the IP.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back
+  *         to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
+  *         DMA transfers to feed the key and the input buffer to the IP.
+  * @note   Once the DMA transfers are finished (indicated by hhash->State set back
+  *         to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
+  *         the computed digest.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
+ *  @brief   Peripheral State functions.
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State methods #####
+ ===============================================================================
+    [..]
+    This section permits to get in run-time the state and the peripheral handle
+    status of the peripheral:
+      (+) HAL_HASH_GetState()
+      (+) HAL_HASH_GetStatus()
+
+    [..]
+    Additionally, this subsection provides functions allowing to save and restore
+    the HASH or HMAC processing context in case of calculation suspension:
+      (+) HAL_HASH_ContextSaving()
+      (+) HAL_HASH_ContextRestoring()
+
+    [..]
+    This subsection provides functions allowing to suspend the HASH processing
+      (+) when input are fed to the IP by software
+          (++) HAL_HASH_SwFeed_ProcessSuspend()
+      (+) when input are fed to the IP by DMA
+          (++) HAL_HASH_DMAFeed_ProcessSuspend()
+
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HASH handle state.
+  * @note   The API yields the current state of the handle (BUSY, READY,...).
+  * @param  hhash: HASH handle.
+  * @retval HAL HASH state
+  */
+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+{
+  return hhash->State;
+}
+
+
+/**
+  * @brief Return the HASH HAL status.
+  * @note  The API yields the HAL status of the handle: it is the result of the
+  *        latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
+  * @param  hhash: HASH handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+{
+  return hhash->Status;
+}
+
+/**
+  * @brief  Save the HASH context in case of processing suspension.
+  * @param  hhash: HASH handle.
+  * @param  pMemBuffer: pointer to the memory buffer where the HASH context
+  *         is saved.
+  * @note   The IMR, STR, CR then all the CSR registers are saved
+  *         in that order. Only the r/w bits are read to be restored later on.
+  * @note   By default, all the context swap registers (there are
+  *         HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
+  * @note   pMemBuffer points to a buffer allocated by the user. The buffer size
+  *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
+  * @retval None
+  */
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)HASH->CSR;
+  uint32_t i;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* Save IMR register content */
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
+  mem_ptr+=4U;
+  /* Save STR register content */
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
+  mem_ptr+=4U;
+  /* Save CR register content */
+  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY);
+  mem_ptr+=4U;
+  /* By default, save all CSRs registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+  {
+    *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
+    mem_ptr+=4U;
+    csr_ptr+=4U;
+  }
+}
+
+
+/**
+  * @brief  Restore the HASH context in case of processing resumption.
+  * @param  hhash: HASH handle.
+  * @param  pMemBuffer: pointer to the memory buffer where the HASH context
+  *         is stored.
+  * @note   The IMR, STR, CR then all the CSR registers are restored
+  *         in that order. Only the r/w bits are restored.
+  * @note   By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
+  *         of those) are restored (all of them have been saved by default
+  *         beforehand).
+  * @retval None
+  */
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+{
+  uint32_t mem_ptr = (uint32_t)pMemBuffer;
+  uint32_t csr_ptr = (uint32_t)HASH->CSR;
+  uint32_t i;
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhash);
+
+  /* Restore IMR register content */
+  WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
+  mem_ptr+=4U;
+  /* Restore STR register content */
+  WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
+  mem_ptr+=4U;
+  /* Restore CR register content */
+  WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
+  mem_ptr+=4U;
+
+  /* Reset the HASH processor before restoring the Context
+  Swap Registers (CSR) */
+  __HAL_HASH_INIT();
+
+  /* By default, restore all CSR registers */
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+  {
+    WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
+    mem_ptr+=4U;
+    csr_ptr+=4U;
+  }
+}
+
+
+/**
+  * @brief  Initiate HASH processing suspension when in polling or interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   Set the handle field SuspendRequest to the appropriate value so that
+  *         the on-going HASH processing is suspended as soon as the required
+  *         conditions are met. Note that the actual suspension is carried out
+  *         by the functions HASH_WriteData() in polling mode and HASH_IT() in
+  *         interruption mode.
+  * @retval None
+  */
+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+  /* Set Handle Suspend Request field */
+  hhash->SuspendRequest = HAL_HASH_SUSPEND;
+}
+
+/**
+  * @brief  Suspend the HASH processing when in DMA mode.
+  * @param  hhash: HASH handle.
+  * @note   When suspension attempt occurs at the very end of a DMA transfer and
+  *         all the data have already been entered in the IP, hhash->State is
+  *         set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
+  *         recommended to wrap-up the processing in reading the digest as usual.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
+{
+  uint32_t tmp_remaining_DMATransferSize_inWords;
+  uint32_t tmp_initial_DMATransferSize_inWords;
+  uint32_t tmp_words_already_pushed;
+
+  if (hhash->State == HAL_HASH_STATE_READY)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+
+   /* Make sure there is enough time to suspend the processing */
+    tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+    if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
+    {
+      /* No suspension attempted since almost to the end of the transferred data. */
+      /* Best option for user code is to wrap up low priority message hashing     */
+      return HAL_ERROR;
+    }
+
+    /* Wait for DMAS to be reset */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+    {
+       return HAL_TIMEOUT;
+    }
+
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Wait for DMAS to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+    {
+       return HAL_TIMEOUT;
+    }
+    /* Disable DMA channel */
+    /* Note that the Abort function will
+      - Clear the transfer error flags
+      - Unlock
+      - Set the State
+    */
+    if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Clear DMAE bit */
+    CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+    {
+      return HAL_ERROR;
+    }
+
+    /* At this point, DMA interface is disabled and no transfer is on-going */
+    /* Retrieve from the DMA handle how many words remain to be written */
+    tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
+
+    if (tmp_remaining_DMATransferSize_inWords == 0U)
+    {
+      /* All the DMA transfer is actually done. Suspension occurred at the very end
+         of the transfer. Either the digest computation is about to start (HASH case)
+         or processing is about to move from one step to another (HMAC case).
+         In both cases, the processing can't be suspended at this point. It is
+         safer to
+         - retrieve the low priority block digest before starting the high
+           priority block processing (HASH case)
+         - re-attempt a new suspension (HMAC case)
+         */
+      return HAL_ERROR;
+    }
+    else
+    {
+
+      /* Compute how many words were supposed to be transferred by DMA */
+      tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ?  ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+
+      /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported
+        by HASH IP, correct it */
+      /* tmp_words_already_pushed reflects the number of words that were already pushed before
+         the start of DMA transfer (multi-buffer processing case) */
+      tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
+      if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U)  != HASH_NBW_PUSHED())
+      {
+        tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
+      }
+
+      /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
+      hhash->pHashInBuffPtr +=  4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
+
+      /* And store in HashInCount the remaining size to transfer (in bytes) */
+      hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
+
+    }
+
+    /* Set State as suspended */
+    hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+    return HAL_OK;
+
+  }
+}
+
+/**
+  * @brief  Return the HASH handle error code.
+  * @param  hhash: pointer to a HASH_HandleTypeDef structure.
+  * @retval HASH Error Code
+*/
+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+{
+  /* Return HASH Error Code */
+  return hhash->ErrorCode;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Private_Functions HASH Private Functions
+  * @{
+  */
+
+/**
+  * @brief DMA HASH Input Data transfer completion callback.
+  * @param hdma: DMA handle.
+  * @note  In case of HMAC processing, HASH_DMAXferCplt() initiates
+  *        the next DMA transfer for the following HMAC step.
+  * @retval None
+  */
+static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t inputaddr;
+  uint32_t buffersize;
+  HAL_StatusTypeDef status ;
+  
+  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  {
+    
+    /* Disable the DMA transfer */
+    CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
+    
+    if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
+    {
+      /* If no HMAC processing, input data transfer is now over */
+      
+      /* Change the HASH state to ready */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+      /* Call Input data transfer complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+      hhash->InCpltCallback(hhash);
+#else
+      HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+      
+    }
+    else
+    {
+      /* HMAC processing: depending on the current HMAC step and whether or
+      not multi-buffer processing is on-going, the next step is initiated
+      and MDMAT bit is set.  */
+      
+      
+      if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+      {
+        /* This is the end of HMAC processing */
+        
+        /* Change the HASH state to ready */
+        hhash->State = HAL_HASH_STATE_READY;
+        
+        /* Call Input data transfer complete call back
+        (note that the last DMA transfer was that of the key
+        for the outer HASH operation). */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+        hhash->InCpltCallback(hhash);
+#else
+        HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+        
+        return;
+      }
+      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+      {
+        inputaddr = (uint32_t)hhash->pHashMsgBuffPtr;     /* DMA transfer start address */
+        buffersize = hhash->HashBuffSize;                 /* DMA transfer size (in bytes) */
+        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
+        
+        /* In case of suspension request, save the new starting parameters */
+        hhash->HashInCount = hhash->HashBuffSize;         /* Initial DMA transfer size (in bytes) */
+        hhash->pHashInBuffPtr  = hhash->pHashMsgBuffPtr ; /* DMA transfer start address           */
+        
+        hhash->NbWordsAlreadyPushed = 0U;                  /* Reset number of words already pushed */
+      }
+      else  /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
+      {
+        if (hhash->DigestCalculationDisable != RESET)
+        {
+          /* No automatic move to Step 3 as a new message buffer will be fed to the IP
+          (case of multi-buffer HMAC processing):
+          DCAL must not be set.
+          Phase remains in Step 2, MDMAT remains set at this point.
+          Change the HASH state to ready and call Input data transfer complete call back. */
+          hhash->State = HAL_HASH_STATE_READY;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+          hhash->InCpltCallback(hhash);
+#else
+          HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+          return ;
+        }
+        else
+        {
+          /* Digest calculation is not disabled (case of single buffer input or last buffer
+          of multi-buffer HMAC processing) */
+          inputaddr = (uint32_t)hhash->Init.pKey;       /* DMA transfer start address */
+          buffersize = hhash->Init.KeySize;             /* DMA transfer size (in bytes) */
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;    /* Move phase from Step 2 to Step 3 */
+          /* In case of suspension request, save the new starting parameters */
+          hhash->HashInCount = hhash->Init.KeySize;     /* Initial size for second DMA transfer (input data) */
+          hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* address passed to DMA, now entering data message */
+          
+          hhash->NbWordsAlreadyPushed = 0U;              /* Reset number of words already pushed */
+        }
+      }
+   
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(buffersize);
+
+      /* Set the HASH DMA transfert completion call back */
+      hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+     
+      /* Enable the DMA In DMA Stream */
+    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+    
+          /* Return function status */
+      if (status != HAL_OK)
+      {
+        /* Update DAC state machine to error */
+        hhash->State = HAL_HASH_STATE_ERROR;      
+      }
+      else
+      {
+        /* Change DAC state */
+        hhash->State = HAL_HASH_STATE_READY;
+      }     
+  }
+  }
+
+  return;
+}
+
+/**
+  * @brief DMA HASH communication error callback.
+  * @param hdma: DMA handle.
+  * @note  HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
+  *        can contain user code to manage the error.
+  * @retval None
+  */
+static void HASH_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+  {
+    hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
+    /* Set HASH state to ready to prevent any blocking issue in user code
+       present in HAL_HASH_ErrorCallback() */
+    hhash->State= HAL_HASH_STATE_READY;
+    /* Set HASH handle status to error */
+    hhash->Status = HAL_ERROR;
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+    hhash->ErrorCallback(hhash);
+#else
+    HAL_HASH_ErrorCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+    /* After error handling by code user, reset HASH handle HAL status */
+    hhash->Status = HAL_OK;
+
+  }
+}
+
+/**
+  * @brief  Feed the input buffer to the HASH IP.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to input buffer.
+  * @param  Size: the size of input buffer in bytes.
+  * @note   HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
+  *         or not the HASH processing must be suspended. If this is the case, the
+  *         processing is suspended when possible and the IP feeding point reached at
+  *         suspension time is stored in the handle for resumption later on.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+{
+  uint32_t buffercounter;
+  __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+
+  for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+  {
+    /* Write input data 4 bytes at a time */
+    HASH->DIN = *(uint32_t*)inputaddr;
+    inputaddr+=4U;
+
+    /* If the suspension flag has been raised and if the processing is not about
+    to end, suspend processing */
+    if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+    {
+      /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
+      in the input buffer */
+      if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+      {
+        /* Reset SuspendRequest */
+        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+        /* Depending whether the key or the input data were fed to the IP, the feeding point
+        reached at suspension time is not saved in the same handle fields */
+        if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
+        {
+          /* Save current reading and writing locations of Input and Output buffers */
+          hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
+          /* Save the number of bytes that remain to be processed at this point */
+          hhash->HashInCount    =  Size - (buffercounter + 4U);
+        }
+        else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+        {
+          /* Save current reading and writing locations of Input and Output buffers */
+          hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
+          /* Save the number of bytes that remain to be processed at this point */
+          hhash->HashKeyCount  =  Size - (buffercounter + 4U);
+        }
+        else
+        {
+          /* Unexpected phase: unlock process and report error */
+          hhash->State = HAL_HASH_STATE_READY;
+          __HAL_UNLOCK(hhash);
+          return HAL_ERROR;
+        }
+
+        /* Set the HASH state to Suspended and exit to stop entering data */
+        hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+        return HAL_OK;
+      } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))  */
+    } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+  }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
+
+  /* At this point, all the data have been entered to the IP: exit */
+  return  HAL_OK;
+}
+
+/**
+  * @brief  Retrieve the message digest.
+  * @param  pMsgDigest: pointer to the computed digest.
+  * @param  Size: message digest size in bytes.
+  * @retval None
+  */
+static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+{
+  uint32_t msgdigest = (uint32_t)pMsgDigest;
+
+  switch(Size)
+  {
+    /* Read the message digest */
+    case 16:  /* MD5 */
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+    break;
+    case 20:  /* SHA1 */
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
+      msgdigest+=4U;
+      *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
+    break;
+    default:
+    break;
+  }
+}
+
+
+
+/**
+  * @brief  Handle HASH processing Timeout.
+  * @param  hhash: HASH handle.
+  * @param  Flag: specifies the HASH flag to check.
+  * @param  Status: the Flag status (SET or RESET).
+  * @param  Timeout: Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait until flag is set */
+  if(Status == RESET)
+  {
+    while(__HAL_HASH_GET_FLAG(Flag) == RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Set State to Ready to be able to restart later on */
+          hhash->State  = HAL_HASH_STATE_READY;
+          /* Store time out issue in handle status */
+          hhash->Status = HAL_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hhash);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  else
+  {
+    while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+    {
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Set State to Ready to be able to restart later on */
+          hhash->State  = HAL_HASH_STATE_READY;
+          /* Store time out issue in handle status */
+          hhash->Status = HAL_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hhash);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  HASH processing in interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   HASH_IT() regularly reads hhash->SuspendRequest to check whether
+  *         or not the HASH processing must be suspended. If this is the case, the
+  *         processing is suspended when possible and the IP feeding point reached at
+  *         suspension time is stored in the handle for resumption later on.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
+{
+  if (hhash->State == HAL_HASH_STATE_BUSY)
+  {
+    /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
+    if(hhash->HashITCounter == 0U)
+    {
+      /* Disable Interrupts */
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      /* HASH state set back to Ready to prevent any issue in user code
+         present in HAL_HASH_ErrorCallback() */
+      hhash->State = HAL_HASH_STATE_READY;
+      return HAL_ERROR;
+    }
+    else if (hhash->HashITCounter == 1U)
+    {
+     /* This is the first call to HASH_IT, the first input data are about to be
+        entered in the IP. A specific processing is carried out at this point to
+        start-up the processing. */
+      hhash->HashITCounter = 2U;
+    }
+    else
+    {
+      /* Cruise speed reached, HashITCounter remains equal to 3 until the end of
+        the HASH processing or the end of the current step for HMAC processing. */
+      hhash->HashITCounter = 3U;
+    }
+
+    /* If digest is ready */
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
+    {
+      /* Read the digest */
+      HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+
+      /* Disable Interrupts */
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      /* Call digest computation complete call back */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+      hhash->DgstCpltCallback(hhash);
+#else
+      HAL_HASH_DgstCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+      return HAL_OK;
+    }
+
+    /* If IP ready to accept new data */
+    if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+    {
+
+      /* If the suspension flag has been raised and if the processing is not about
+         to end, suspend processing */
+      if ( (hhash->HashInCount != 0U) &&  (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+      {
+        /* Disable Interrupts */
+        __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+
+        /* Reset SuspendRequest */
+        hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+        /* Change the HASH state */
+        hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+        return HAL_OK;
+      }
+
+      /* Enter input data in the IP thru HASH_Write_Block_Data() call and
+        check whether the digest calculation has been triggered */
+      if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
+      {
+        /* Call Input data transfer complete call back
+           (called at the end of each step for HMAC) */
+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
+        hhash->InCpltCallback(hhash);
+#else
+        HAL_HASH_InCpltCallback(hhash);
+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
+
+        if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+        {
+          /* Wait until IP is not busy anymore */
+          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+          {
+            /* Disable Interrupts */
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+            return HAL_TIMEOUT;
+          }
+          /* Initialization start for HMAC STEP 2 */
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;        /* Move phase from Step 1 to Step 2 */
+          __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
+          hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
+          hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
+          hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
+          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
+        }
+        else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+        {
+          /* Wait until IP is not busy anymore */
+          if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+          {
+            /* Disable Interrupts */
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+            return HAL_TIMEOUT;
+          }
+          /* Initialization start for HMAC STEP 3 */
+          hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;         /* Move phase from Step 2 to Step 3 */
+          __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */
+          hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */
+          hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */
+          hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
+          __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */
+        }
+        else
+        {
+          /* Nothing to do */
+        }
+      } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
+    }  /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Write a block of data in HASH IP in interruption mode.
+  * @param  hhash: HASH handle.
+  * @note   HASH_Write_Block_Data() is called under interruption by HASH_IT().
+  * @retval HAL status
+  */
+static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
+{
+  uint32_t inputaddr;
+  uint32_t buffercounter;
+  uint32_t inputcounter;
+  uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
+
+  /* If there are more than 64 bytes remaining to be entered */
+  if(hhash->HashInCount > 64U)
+  {
+    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+    /* Write the Input block in the Data IN register
+      (16 32-bit words, or 64 bytes are entered) */
+    for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      inputaddr+=4U;
+    }
+    /* If this is the start of input data entering, an additional word
+      must be entered to start up the HASH processing */
+    if(hhash->HashITCounter == 2U)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      if(hhash->HashInCount >= 68U)
+      {
+        /* There are still data waiting to be entered in the IP.
+           Decrement buffer counter and set pointer to the proper
+           memory location for the next data entering round. */
+        hhash->HashInCount -= 68U;
+        hhash->pHashInBuffPtr+= 68U;
+      }
+      else
+      {
+        /* All the input buffer has been fed to the HW. */
+        hhash->HashInCount = 0U;
+      }
+    }
+    else
+    {
+      /* 64 bytes have been entered and there are still some remaining:
+         Decrement buffer counter and set pointer to the proper
+        memory location for the next data entering round.*/
+      hhash->HashInCount -= 64U;
+      hhash->pHashInBuffPtr+= 64U;
+    }
+  }
+  else
+  {
+    /* 64 or less bytes remain to be entered. This is the last
+      data entering round. */
+
+    /* Get the buffer address */
+    inputaddr = (uint32_t)hhash->pHashInBuffPtr;
+    /* Get the buffer counter */
+    inputcounter = hhash->HashInCount;
+    /* Disable Interrupts */
+    __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
+
+    /* Write the Input block in the Data IN register */
+    for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+    {
+      HASH->DIN = *(uint32_t*)inputaddr;
+      inputaddr+=4U;
+    }
+    /* Start the Digest calculation */
+    __HAL_HASH_START_DIGEST();
+    /* Return indication that digest calculation has started:
+       this return value triggers the call to Input data transfer
+       complete call back as well as the proper transition from
+       one step to another in HMAC mode. */
+    ret = HASH_DIGEST_CALCULATION_STARTED;
+    /* Reset buffer counter */
+    hhash->HashInCount = 0;
+  }
+
+  /* Return whether or digest calculation has started */
+  return ret;
+}
+
+/**
+  * @brief  HMAC processing in polling mode.
+  * @param  hhash: HASH handle.
+  * @param  Timeout: Timeout value.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
+{
+  /* Ensure first that Phase is correct */
+  if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+  {
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+
+  /* HMAC Step 1 processing */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
+  {
+    /************************** STEP 1 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+    /* Write input buffer in Data register */
+    hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+    if (hhash->Status != HAL_OK)
+    {
+      return hhash->Status;
+    }
+
+    /* Check whether or not key entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }
+
+    /* No processing suspension at this point: set DCAL bit. */
+    __HAL_HASH_START_DIGEST();
+
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Move from Step 1 to Step 2 */
+    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
+
+  }
+
+  /* HMAC Step 2 processing.
+     After phase check, HMAC_Processing() may
+     - directly start up from this point in resumption case
+       if the same Step 2 processing was suspended previously
+    - or fall through from the Step 1 processing carried out hereabove */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+  {
+    /************************** STEP 2 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
+
+    /* Write input buffer in Data register */
+    hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
+    if (hhash->Status != HAL_OK)
+    {
+      return hhash->Status;
+    }
+
+    /* Check whether or not data entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }
+
+    /* No processing suspension at this point: set DCAL bit. */
+    __HAL_HASH_START_DIGEST();
+
+    /* Wait for BUSY flag to be cleared */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Move from Step 2 to Step 3 */
+    hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
+    /* In case Step 1 phase was suspended then resumed,
+       set again Key input buffers and size before moving to
+       next step */
+    hhash->pHashKeyBuffPtr = hhash->Init.pKey;
+    hhash->HashKeyCount    = hhash->Init.KeySize;
+  }
+
+
+ /* HMAC Step 3 processing.
+     After phase check, HMAC_Processing() may
+     - directly start up from this point in resumption case
+       if the same Step 3 processing was suspended previously
+    - or fall through from the Step 2 processing carried out hereabove */
+  if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
+  {
+    /************************** STEP 3 ******************************************/
+    /* Configure the Number of valid bits in last word of the message */
+    __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+    /* Write input buffer in Data register */
+    hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
+    if (hhash->Status != HAL_OK)
+    {
+      return hhash->Status;
+    }
+
+    /* Check whether or not key entering process has been suspended */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+
+      /* Stop right there and return function status */
+      return HAL_OK;
+    }
+
+    /* No processing suspension at this point: start the Digest calculation. */
+    __HAL_HASH_START_DIGEST();
+
+    /* Wait for DCIS flag to be set */
+     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Read the message digest */
+    HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
+  }
+
+   /* Change the HASH state */
+   hhash->State = HAL_HASH_STATE_READY;
+
+   /* Process Unlock */
+   __HAL_UNLOCK(hhash);
+
+   /* Return function status */
+   return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{
+  uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
+  uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
+  HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+
+  
+  /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  {  
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+    
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+    
+    /* Check if initialization phase has not been already performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+      
+      /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+      
+      /* Configure the number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(Size);
+      
+      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+      input parameters of HASH_WriteData() */
+      pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
+      Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
+      
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+    }
+    else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
+    {
+      /* if the IP has already been initialized, two cases are possible */
+      
+      /* Process resumption time ... */
+      if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+      {
+        /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+        to the API input parameters but to those saved beforehand by HASH_WriteData()
+        when the processing was suspended */
+        pInBuffer_tmp = hhash->pHashInBuffPtr;
+        Size_tmp = hhash->HashInCount;
+      }
+      /* ... or multi-buffer HASH processing end */
+      else
+      {
+        /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+        input parameters of HASH_WriteData() */
+        pInBuffer_tmp = pInBuffer;
+        Size_tmp = Size;
+        /* Configure the number of valid bits in last word of the message */
+        __HAL_HASH_SET_NBVALIDBITS(Size);
+      }
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+    }
+    else
+    {
+      /* Phase error */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhash);
+      
+      /* Return function status */
+      return HAL_ERROR;
+    }
+    
+    
+    /* Write input buffer in Data register */
+    hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+    if (hhash->Status != HAL_OK)
+    {
+      return hhash->Status;
+    }
+    
+    /* If the process has not been suspended, carry on to digest calculation */
+    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Start the Digest calculation */
+      __HAL_HASH_START_DIGEST();
+      
+      /* Wait for DCIS flag to be set */
+      if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      
+      /* Read the message digest */
+      HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+      
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+      
+    }
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    return HAL_OK;
+    
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  If not already done, initialize the HASH peripheral then
+  *         processes pInBuffer.
+  * @note   Field hhash->Phase of HASH handle is tested to check whether or not
+  *         the IP has already been initialized.
+  * @note   The input buffer size (in bytes) must be a multiple of 4 otherwise, the
+  *         HASH digest computation is corrupted.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes, must be a multiple of 4.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+  uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
+  uint32_t Size_tmp;  /* input data size (in bytes), input parameter of HASH_WriteData() */
+  HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+   
+  /* Make sure the input buffer size (in bytes) is a multiple of 4 */
+   assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size));
+
+  /* Initiate HASH processing in case of start or resumption */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  { 
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0U))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+     /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* If resuming the HASH processing */
+    if (hhash->State == HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
+         to the API input parameters but to those saved beforehand by HASH_WriteData()
+         when the processing was suspended */
+      pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
+      Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
+
+    }
+    else
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
+         input parameters of HASH_WriteData() */
+      pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */
+      Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */
+
+      /* Check if initialization phase has already be performed */
+      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      {
+        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+      }
+
+      /* Set the phase */
+      hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+    }
+
+    /* Write input buffer in Data register */
+    hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
+    if (hhash->Status != HAL_OK)
+    {
+      return hhash->Status;
+    }
+
+    /* If the process has not been suspended, move the state to Ready */
+    if (hhash->State != HAL_HASH_STATE_SUSPENDED)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral, next process pInBuffer then
+  *         read the computed digest in interruption mode.
+  * @note   Digest is available in pOutBuffer.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+{
+   HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+  /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  {     
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Initialize IT counter */
+    hhash->HashITCounter = 1;
+
+    /* Check if initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+
+      /* Configure the number of valid bits in last word of the message */
+     __HAL_HASH_SET_NBVALIDBITS(Size);
+
+
+      hhash->HashInCount = Size;               /* Counter used to keep track of number of data
+                                                  to be fed to the IP */
+      hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the IP at
+                                                  the next interruption */
+     /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+        the information describing where the HASH process is stopped.
+        These variables are used later on to resume the HASH processing at the
+        correct location. */
+
+      hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
+    }
+
+    /* Set the phase */
+    hhash->Phase = HAL_HASH_PHASE_PROCESS;
+
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+
+    /* Enable Interrupts */
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral then initiate a DMA transfer
+  *         to feed the input buffer to the IP.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+  uint32_t inputaddr;
+  uint32_t inputSize;
+  HAL_StatusTypeDef status ;
+  HAL_HASH_StateTypeDef State_tmp = hhash->State;
+
+   /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  { 
+    /* Check input parameters */
+    if ( (pInBuffer == NULL ) || (Size == 0U) ||
+    /* Check phase coherency. Phase must be
+       either READY (fresh start)
+       or PROCESS (multi-buffer HASH management) */
+       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* If not a resumption case */
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Check if initialization phase has already been performed.
+         If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
+         API is processing a new input data message in case of multi-buffer HASH
+         computation. */
+      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      {
+        /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+
+        /* Set the phase */
+        hhash->Phase = HAL_HASH_PHASE_PROCESS;
+      }
+
+      /* Configure the Number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(Size);
+
+      inputaddr = (uint32_t)pInBuffer;     /* DMA transfer start address   */
+      inputSize = Size;                    /* DMA transfer size (in bytes) */
+
+      /* In case of suspension request, save the starting parameters */
+      hhash->pHashInBuffPtr =  pInBuffer;  /* DMA transfer start address   */
+      hhash->HashInCount = Size;           /* DMA transfer size (in bytes) */
+
+    }
+    /* If resumption case */
+    else
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Resumption case, inputaddr and inputSize are not set to the API input parameters
+         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+         processing was suspended */
+      inputaddr = (uint32_t)hhash->pHashInBuffPtr;  /* DMA transfer start address   */
+      inputSize = hhash->HashInCount;               /* DMA transfer size (in bytes) */
+
+    }
+
+    /* Set the HASH DMA transfert complete callback */
+    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+    /* Set the DMA error callback */
+    hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+    /* Store number of words already pushed to manage proper DMA processing suspension */
+    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+    /* Enable the DMA In DMA Stream */
+    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+    
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+    
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    if (status != HAL_OK)
     {
-      /* Select the HMAC SHA1 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+      /* Update HASH state machine to error */
+      hhash->State = HAL_HASH_STATE_ERROR;      
     }
     else
     {
-      /* Select the HMAC SHA1 mode */
-      HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      /* Change HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
     }
+    
+    return status;
   }
-  
-  /* Set the phase */
-  hhash->Phase = HAL_HASH_PHASE_PROCESS;
-  
-  /* Configure the number of valid bits in last word of the message */
-  __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-  
-  /* Get the key address */
-  inputaddr = (uint32_t)(hhash->Init.pKey);
-  
-  /* Set the HASH DMA transfer complete callback */
-  hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
-  /* Set the DMA error callback */
-  hhash->hdmain->XferErrorCallback = HASH_DMAError;
-  
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
-  /* Enable DMA requests */
-  HASH->CR |= (HASH_CR_DMAE);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hhash);
-  
-  /* Return function status */
-  return HAL_OK;
+  else
+  {
+    return HAL_BUSY;
+  } 
 }
 
 /**
-  * @}
+  * @brief  Return the computed digest.
+  * @note   The API waits for DCIS to be set then reads the computed digest.
+  * @param  hhash: HASH handle.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value.
+  * @retval HAL status
   */
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+{
 
-/** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions 
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
+  if(hhash->State == HAL_HASH_STATE_READY)
+  {
+    /* Check parameter */
+    if (pOutBuffer == NULL)
+    {
+      return  HAL_ERROR;
+    }
 
-@endverbatim
-  * @{
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state to busy */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Wait for DCIS flag to be set */
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* Read the message digest */
+    HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
+
+    /* Change the HASH state to ready */
+    hhash->State = HAL_HASH_STATE_READY;
+
+    /* Process UnLock */
+    __HAL_UNLOCK(hhash);
+
+    /* Return function status */
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
+}
+
+
+/**
+  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+  *         read the computed digest.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Timeout: Timeout value.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
   */
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+{
+    HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+  
+   /* If State is ready or suspended, start or resume polling-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  { 
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Check if initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      if(hhash->Init.KeySize > 64U)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+      /* Resort to hhash internal fields to feed the IP.
+         Parameters will be updated in case of suspension to contain the proper
+         information at resumption time. */
+      hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
+      hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
+      hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
+      hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */
+      hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
+      hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */
+    }
+
+    /* Carry out HMAC processing */
+    return HMAC_Processing(hhash, Timeout);
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
 
 /**
-  * @brief return the HASH state
-  * @param  hhash: pointer to a HASH_HandleTypeDef structure that contains
-  *         the configuration information for HASH module
-  * @retval HAL state
+  * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
+  *         read the computed digest in interruption mode.
+  * @note   Digest is available in pOutBuffer.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  pOutBuffer: pointer to the computed digest.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
   */
-HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
 {
-  return hhash->State;
+    HAL_HASH_StateTypeDef State_tmp = hhash->State; 
+    
+  /* If State is ready or suspended, start or resume IT-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  { 
+    /* Check input parameters */
+    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* Change the HASH state */
+    hhash->State = HAL_HASH_STATE_BUSY;
+
+    /* Initialize IT counter */
+    hhash->HashITCounter = 1;
+
+    /* Check if initialization phase has already be performed */
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      if(hhash->Init.KeySize > 64U)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+
+      /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
+         to feed the IP whatever the HMAC step.
+         Lines below are set to start HMAC Step 1 processing where key is entered first. */
+      hhash->HashInCount     = hhash->Init.KeySize; /* Key size                      */
+      hhash->pHashInBuffPtr  = hhash->Init.pKey ;   /* Key address                   */
+
+      /* Store input and output parameters in handle fields to manage steps transition
+         or possible HMAC suspension/resumption */
+      hhash->pHashKeyBuffPtr = hhash->Init.pKey;    /* Key address                   */
+      hhash->pHashMsgBuffPtr = pInBuffer;           /* Input message address         */
+      hhash->HashBuffSize    = Size;                /* Input message size (in bytes) */
+      hhash->pHashOutBuffPtr = pOutBuffer;          /* Output digest address         */
+
+      /* Configure the number of valid bits in last word of the key */
+      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+    }
+    else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+    {
+      /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
+
+    }
+    else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      /* Restart IT-based HASH processing after Step 2 suspension */
+
+    }
+    else
+    {
+      /* Error report as phase incorrect */
+      /* Process Unlock */
+      __HAL_UNLOCK(hhash);
+      hhash->State = HAL_HASH_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Process Unlock */
+    __HAL_UNLOCK(hhash);
+
+    /* Enable Interrupts */
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+
 }
 
+
+
 /**
-  * @}
+  * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required
+  *         DMA transfers to feed the key and the input buffer to the IP.
+  * @note   Same key is used for the inner and the outer hash functions; pointer to key and
+  *         key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
+  * @note   In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
+  *         be a multiple of 4 otherwise, the HASH digest computation is corrupted.
+  *         Only the length of the last buffer of the thread doesn't have to be a
+  *         multiple of 4.
+  * @param  hhash: HASH handle.
+  * @param  pInBuffer: pointer to the input buffer (buffer to be hashed).
+  * @param  Size: length of the input buffer in bytes.
+  * @param  Algorithm: HASH algorithm.
+  * @retval HAL status
   */
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+{
+  uint32_t inputaddr;
+  uint32_t inputSize;
+  HAL_StatusTypeDef status ;
+  HAL_HASH_StateTypeDef State_tmp = hhash->State;  
+  /* If State is ready or suspended, start or resume DMA-based HASH processing */
+if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  {   
+    /* Check input parameters */
+    if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
+   /* Check phase coherency. Phase must be
+       either READY (fresh start)
+       or one of HMAC PROCESS steps (multi-buffer HASH management) */
+       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+    {
+      hhash->State = HAL_HASH_STATE_READY;
+      return  HAL_ERROR;
+    }
+
+
+    /* Process Locked */
+    __HAL_LOCK(hhash);
+
+    /* If not a case of resumption after suspension */
+    if (hhash->State == HAL_HASH_STATE_READY)
+    {
+    /* Check whether or not initialization phase has already be performed */
+    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    {
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
+      if(hhash->Init.KeySize > 64U)
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+      }
+      else
+      {
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+      }
+      /* Store input aparameters in handle fields to manage steps transition
+         or possible HMAC suspension/resumption */
+      hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
+      hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
+      hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+      hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
+      hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
+
+      /* Set DMA input parameters */
+      inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
+      inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
+
+      /* Configure the number of valid bits in last word of the key */
+      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+      /* Set the phase to Step 1 */
+      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
+    }
+      else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
+    {
+      /* Process a new input data message in case of multi-buffer HMAC processing
+        (this is not a resumption case) */
+
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Save input parameters to be able to manage possible suspension/resumption */
+        hhash->HashInCount = Size;                /* Input message address       */
+        hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
+
+      /* Set DMA input parameters */
+        inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
+        inputSize = Size;                          /* Input message size in bytes */
+
+      if (hhash->DigestCalculationDisable == RESET)
+      {
+        /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+        __HAL_HASH_SET_NBVALIDBITS(inputSize);
+      }
+    }
+      else
+      {
+        /* Phase not aligned with handle READY state */
+        __HAL_UNLOCK(hhash);
+        /* Return function status */
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+       /* Resumption case (phase may be Step 1, 2 or 3) */
+
+      /* Change the HASH state */
+      hhash->State = HAL_HASH_STATE_BUSY;
+
+      /* Set DMA input parameters at resumption location;
+         inputaddr and inputSize are not set to the API input parameters
+         but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
+         processing was suspended. */
+      inputaddr = (uint32_t)(hhash->pHashInBuffPtr);  /* Input message address       */
+      inputSize = hhash->HashInCount;                 /* Input message size in bytes */
+    }
+
 
+    /* Set the HASH DMA transfert complete callback */
+    hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
+    /* Set the DMA error callback */
+    hhash->hdmain->XferErrorCallback = HASH_DMAError;
+
+    /* Store number of words already pushed to manage proper DMA processing suspension */
+    hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
+
+    /* Enable the DMA In DMA Stream */
+    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+    /* Enable DMA requests */
+    SET_BIT(HASH->CR, HASH_CR_DMAE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhash);
+    
+    /* Return function status */
+    if (status != HAL_OK)
+    {
+      /* Update HASH state machine to error */
+      hhash->State = HAL_HASH_STATE_ERROR;
+    }
+    else
+    {
+      /* Change HASH state */
+      hhash->State = HAL_HASH_STATE_READY;
+    }
+    /* Return function status */
+    return status; 
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
 /**
   * @}
   */
-#endif /* STM32F215xx || STM32F217xx */
+
 #endif /* HAL_HASH_MODULE_ENABLED */
+
 /**
   * @}
   */
-
+#endif /*  HASH*/
 /**
   * @}
   */
 
+
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hcd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hcd.c
index 41f82123..9550e787 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hcd.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hcd.c
@@ -2,16 +2,14 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_hcd.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   HCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the USB Peripheral Controller:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
@@ -19,21 +17,21 @@
   [..]
     (#)Declare a HCD_HandleTypeDef handle structure, for example:
        HCD_HandleTypeDef  hhcd;
-        
+
     (#)Fill parameters of Init structure in HCD handle
-  
-    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) 
+
+    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
 
     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
         (##) Enable the HCD/USB Low Level interface clock using the following macros
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
              (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
-           
+
         (##) Initialize the related GPIO clocks
         (##) Configure HCD pin-out
         (##) Configure HCD NVIC interrupt
-    
+
     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
         (##) hhcd.pData = phost;
 
@@ -44,32 +42,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -78,13 +60,15 @@
   * @{
   */
 
-/** @defgroup HCD HCD 
+#ifdef HAL_HCD_MODULE_ENABLED
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
+/** @defgroup HCD HCD
   * @brief HCD HAL module driver
   * @{
   */
 
-#ifdef HAL_HCD_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -94,7 +78,7 @@
   * @{
   */
 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); 
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
 /**
@@ -106,82 +90,115 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
   * @{
   */
 
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim     
+@verbatim
  ===============================================================================
           ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
- 
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Initialize the host driver.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
-{ 
+{
+  USB_OTG_GlobalTypeDef *USBx;
+
   /* Check the HCD handle allocation */
-  if(hhcd == NULL)
+  if (hhcd == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
-  
+
+  USBx = hhcd->Instance;
+
+  if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hhcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+    hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+    hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+    hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+    hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
+
+    if (hhcd->MspInitCallback == NULL)
+    {
+      hhcd->MspInitCallback = HAL_HCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hhcd->MspInitCallback(hhcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_HCD_MspInit(hhcd);
+#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
+  }
+
   hhcd->State = HAL_HCD_STATE_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-  HAL_HCD_MspInit(hhcd);
-  
+
+  /* Disable DMA mode for FS instance */
+  if ((USBx->CID & (0x1U << 8)) == 0U)
+  {
+    hhcd->Init.dma_enable = 0U;
+  }
+
   /* Disable the Interrupts */
   __HAL_HCD_DISABLE(hhcd);
-  
+
   /* Init the Core (common init.) */
-  USB_CoreInit(hhcd->Instance, hhcd->Init);
-  
+  (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+
   /* Force Host Mode*/
-  USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
-  
+  (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+
   /* Init Host */
-  USB_HostInit(hhcd->Instance, hhcd->Init);
-  
-  hhcd->State= HAL_HCD_STATE_READY;
-  
+  (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+
+  hhcd->State = HAL_HCD_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initialize a host channel.
-  * @param  hhcd: HCD handle
-  * @param  ch_num: Channel number.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
   *         This parameter can be a value from 1 to 15
-  * @param  epnum: Endpoint number.
+  * @param  epnum Endpoint number.
   *          This parameter can be a value from 1 to 15
-  * @param  dev_address : Current device address
+  * @param  dev_address Current device address
   *          This parameter can be a value from 0 to 255
-  * @param  speed: Current device speed.
+  * @param  speed Current device speed.
   *          This parameter can be one of these values:
   *            HCD_SPEED_HIGH: High speed mode,
   *            HCD_SPEED_FULL: Full speed mode,
   *            HCD_SPEED_LOW: Low speed mode
-  * @param  ep_type: Endpoint Type.
+  * @param  ep_type Endpoint Type.
   *          This parameter can be one of these values:
   *            EP_TYPE_CTRL: Control type,
   *            EP_TYPE_ISOC: Isochronous type,
   *            EP_TYPE_BULK: Bulk type,
   *            EP_TYPE_INTR: Interrupt type
-  * @param  mps: Max Packet Size.
+  * @param  mps Max Packet Size.
   *          This parameter can be a value from 0 to32K
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,  
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
                                   uint8_t ch_num,
                                   uint8_t epnum,
                                   uint8_t dev_address,
@@ -189,94 +206,119 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
                                   uint8_t ep_type,
                                   uint16_t mps)
 {
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  __HAL_LOCK(hhcd); 
-  
+  HAL_StatusTypeDef status;
+
+  __HAL_LOCK(hhcd);
+  hhcd->hc[ch_num].do_ping = 0U;
   hhcd->hc[ch_num].dev_addr = dev_address;
   hhcd->hc[ch_num].max_packet = mps;
   hhcd->hc[ch_num].ch_num = ch_num;
   hhcd->hc[ch_num].ep_type = ep_type;
-  hhcd->hc[ch_num].ep_num = epnum & 0x7F;
-  hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+  hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    hhcd->hc[ch_num].ep_is_in = 1U;
+  }
+  else
+  {
+    hhcd->hc[ch_num].ep_is_in = 0U;
+  }
+
   hhcd->hc[ch_num].speed = speed;
-  
-  status =  USB_HC_Init(hhcd->Instance, 
+
+  status =  USB_HC_Init(hhcd->Instance,
                         ch_num,
                         epnum,
                         dev_address,
                         speed,
                         ep_type,
                         mps);
-  __HAL_UNLOCK(hhcd); 
-  
+  __HAL_UNLOCK(hhcd);
+
   return status;
 }
 
 /**
   * @brief  Halt a host channel.
-  * @param  hhcd: HCD handle
-  * @param  ch_num: Channel number.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
   *         This parameter can be a value from 1 to 15
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
-  __HAL_LOCK(hhcd);   
-  USB_HC_Halt(hhcd->Instance, ch_num);   
+
+  __HAL_LOCK(hhcd);
+  (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
   __HAL_UNLOCK(hhcd);
-  
+
   return status;
 }
 
 /**
   * @brief  DeInitialize the host driver.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
 {
   /* Check the HCD handle allocation */
-  if(hhcd == NULL)
+  if (hhcd == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   hhcd->State = HAL_HCD_STATE_BUSY;
-  
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+  if (hhcd->MspDeInitCallback == NULL)
+  {
+    hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
   /* DeInit the low level hardware */
+  hhcd->MspDeInitCallback(hhcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
   HAL_HCD_MspDeInit(hhcd);
-  
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
   __HAL_HCD_DISABLE(hhcd);
-  
-  hhcd->State = HAL_HCD_STATE_RESET; 
-  
+
+  hhcd->State = HAL_HCD_STATE_RESET;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initialize the HCD MSP.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitialize the HCD MSP.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_MspDeInit could be implemented in the user file
    */
 }
 
@@ -291,254 +333,267 @@ __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
  ===============================================================================
                       ##### IO operation functions #####
  ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USB Host Data 
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
     Transfer
-       
+
 @endverbatim
   * @{
   */
-  
-/**                                
-  * @brief  Submit a new URB for processing. 
-  * @param  hhcd: HCD handle
-  * @param  ch_num: Channel number.
+
+/**
+  * @brief  Submit a new URB for processing.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
   *         This parameter can be a value from 1 to 15
-  * @param  direction: Channel number.
+  * @param  direction Channel number.
   *          This parameter can be one of these values:
   *           0 : Output / 1 : Input
-  * @param  ep_type: Endpoint Type.
+  * @param  ep_type Endpoint Type.
   *          This parameter can be one of these values:
   *            EP_TYPE_CTRL: Control type/
   *            EP_TYPE_ISOC: Isochronous type/
   *            EP_TYPE_BULK: Bulk type/
   *            EP_TYPE_INTR: Interrupt type/
-  * @param  token: Endpoint Type.
+  * @param  token Endpoint Type.
   *          This parameter can be one of these values:
   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
-  * @param  pbuff: pointer to URB data
-  * @param  length: Length of URB data
-  * @param  do_ping: activate do ping protocol (for high speed only).
+  * @param  pbuff pointer to URB data
+  * @param  length Length of URB data
+  * @param  do_ping activate do ping protocol (for high speed only).
   *          This parameter can be one of these values:
-  *           0 : do ping inactive / 1 : do ping active 
+  *           0 : do ping inactive / 1 : do ping active
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
-                                           uint8_t ch_num, 
+                                           uint8_t ch_num,
                                            uint8_t direction,
-                                           uint8_t ep_type,  
-                                           uint8_t token, 
-                                           uint8_t* pbuff, 
+                                           uint8_t ep_type,
+                                           uint8_t token,
+                                           uint8_t *pbuff,
                                            uint16_t length,
-                                           uint8_t do_ping) 
+                                           uint8_t do_ping)
 {
   hhcd->hc[ch_num].ep_is_in = direction;
-  hhcd->hc[ch_num].ep_type  = ep_type; 
-  
-  if(token == 0)
+  hhcd->hc[ch_num].ep_type  = ep_type;
+
+  if (token == 0U)
   {
     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
+    hhcd->hc[ch_num].do_ping = do_ping;
   }
   else
   {
     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
   }
-  
+
   /* Manage Data Toggle */
-  switch(ep_type)
+  switch (ep_type)
   {
-  case EP_TYPE_CTRL:
-    if((token == 1) && (direction == 0)) /*send data */
-    {
-      if ( length == 0 )
-      { /* For Status OUT stage, Length==0, Status Out PID = 1 */
-        hhcd->hc[ch_num].toggle_out = 1;
-      }
-      
-      /* Set the Data Toggle bit as per the Flag */
-      if ( hhcd->hc[ch_num].toggle_out == 0)
-      { /* Put the PID 0 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
-      }
-      else
-      { /* Put the PID 1 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
-      }
-      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
-      {
-        hhcd->hc[ch_num].do_ping = do_ping;
-      }
-    }
-    break;
-  
-  case EP_TYPE_BULK:
-    if(direction == 0)
-    {
-      /* Set the Data Toggle bit as per the Flag */
-      if ( hhcd->hc[ch_num].toggle_out == 0)
-      { /* Put the PID 0 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
-      }
-      else
-      { /* Put the PID 1 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
-      }
-      if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
+    case EP_TYPE_CTRL:
+      if ((token == 1U) && (direction == 0U)) /*send data */
       {
-        hhcd->hc[ch_num].do_ping = do_ping;
+        if (length == 0U)
+        {
+          /* For Status OUT stage, Length==0, Status Out PID = 1 */
+          hhcd->hc[ch_num].toggle_out = 1U;
+        }
+
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
       }
-    }
-    else
-    {
-      if( hhcd->hc[ch_num].toggle_in == 0)
+      break;
+
+    case EP_TYPE_BULK:
+      if (direction == 0U)
       {
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
       }
       else
       {
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
-      }
-    }
-    
-    break;
-  case EP_TYPE_INTR:
-    if(direction == 0)
-    {
-      /* Set the Data Toggle bit as per the Flag */
-      if ( hhcd->hc[ch_num].toggle_out == 0)
-      { /* Put the PID 0 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;    
-      }
-      else
-      { /* Put the PID 1 */
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
       }
-    }
-    else
-    {
-      if( hhcd->hc[ch_num].toggle_in == 0)
+
+      break;
+    case EP_TYPE_INTR:
+      if (direction == 0U)
       {
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        /* Set the Data Toggle bit as per the Flag */
+        if (hhcd->hc[ch_num].toggle_out == 0U)
+        {
+          /* Put the PID 0 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          /* Put the PID 1 */
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
       }
       else
       {
-        hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        if (hhcd->hc[ch_num].toggle_in == 0U)
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+        }
+        else
+        {
+          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+        }
       }
-    }
-    break;
-    
-  case EP_TYPE_ISOC: 
-    hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
-    break;  
+      break;
+
+    case EP_TYPE_ISOC:
+      hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+      break;
+
+    default:
+      break;
   }
-  
+
   hhcd->hc[ch_num].xfer_buff = pbuff;
   hhcd->hc[ch_num].xfer_len  = length;
-  hhcd->hc[ch_num].urb_state =   URB_IDLE;  
-  hhcd->hc[ch_num].xfer_count = 0;
+  hhcd->hc[ch_num].urb_state = URB_IDLE;
+  hhcd->hc[ch_num].xfer_count = 0U;
   hhcd->hc[ch_num].ch_num = ch_num;
   hhcd->hc[ch_num].state = HC_IDLE;
-  
-  return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
+
+  return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
 }
 
 /**
   * @brief  Handle HCD interrupt request.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-  uint32_t i = 0 , interrupt = 0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i, interrupt;
+
   /* Ensure that we are in device mode */
   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
   {
     /* Avoid spurious interrupt */
-    if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) 
+    if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
     {
       return;
     }
-    
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
     {
       /* Incorrect mode, acknowledge the interrupt */
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
     }
-    
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
     {
       /* Incorrect mode, acknowledge the interrupt */
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
     }
-    
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
     {
       /* Incorrect mode, acknowledge the interrupt */
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
-    }   
-    
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
+    }
+
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
     {
       /* Incorrect mode, acknowledge the interrupt */
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
-    }     
-    
+    }
+
     /* Handle Host Disconnect Interrupts */
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
     {
-      
-      /* Cleanup HPRT */
-      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
-        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-      
-      /* Handle Host Port Interrupts */
-      HAL_HCD_Disconnect_Callback(hhcd);
-      USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
+
+      if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
+      {
+        /* Handle Host Port Disconnect Interrupt */
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->DisconnectCallback(hhcd);
+#else
+        HAL_HCD_Disconnect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
+        (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+      }
     }
-    
+
     /* Handle Host Port Interrupts */
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
     {
-      HCD_Port_IRQHandler (hhcd);
+      HCD_Port_IRQHandler(hhcd);
     }
-    
-    /* Handle Host SOF Interrupts */
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
+
+    /* Handle Host SOF Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
     {
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->SOFCallback(hhcd);
+#else
       HAL_HCD_SOF_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
     }
-    
-    /* Handle Host channel Interrupts */
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
+
+    /* Handle Host channel Interrupt */
+    if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
     {
       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
-      for (i = 0; i < hhcd->Init.Host_channels; i++)
+      for (i = 0U; i < hhcd->Init.Host_channels; i++)
       {
-        if (interrupt & (1 << i))
+        if ((interrupt & (1UL << (i & 0xFU))) != 0U)
         {
-          if ((USBx_HC(i)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
+          if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
           {
-            HCD_HC_IN_IRQHandler(hhcd, i);
+            HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
           }
           else
           {
-            HCD_HC_OUT_IRQHandler (hhcd, i);
+            HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
           }
         }
       }
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
-    } 
-    
+    }
+
     /* Handle Rx Queue Level Interrupts */
-    if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
+    if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
     {
       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-      
-      HCD_RXQLVL_IRQHandler (hhcd);
-      
+
+      HCD_RXQLVL_IRQHandler(hhcd);
+
       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
     }
   }
@@ -546,75 +601,395 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
 
 /**
   * @brief  SOF callback.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_HCD_SOF_Callback could be implemented in the user file
    */
 }
 
 /**
   * @brief Connection Event callback.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_HCD_Connect_Callback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Disconnection Event callback.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_HCD_Disconnect_Callback could be implemented in the user file
    */
-} 
+}
+
+/**
+  * @brief  Port Enabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Port Disabled  Event callback.
+  * @param  hhcd HCD handle
+  * @retval None
+  */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HCD_Disconnect_Callback could be implemented in the user file
+   */
+}
 
 /**
   * @brief  Notify URB state change callback.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
   * @param  urb_state:
   *          This parameter can be one of these values:
   *            URB_IDLE/
   *            URB_DONE/
   *            URB_NOTREADY/
-  *            URB_NYET/ 
-  *            URB_ERROR/  
-  *            URB_STALL/    
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL/
   * @retval None
   */
 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhcd);
+  UNUSED(chnum);
+  UNUSED(urb_state);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
    */
 }
 
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB HCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB HCD Callback
+  *         USB HCD callabck is redirected to the weak predefined callback
+  * @param  hhcd USB HCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
+  *          @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
+  *          @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
+  *          @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
+  *          @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
+  *          @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_SOF_CB_ID :
+        hhcd->SOFCallback = HAL_HCD_SOF_Callback;
+        break;
+
+      case HAL_HCD_CONNECT_CB_ID :
+        hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
+        break;
+
+      case HAL_HCD_DISCONNECT_CB_ID :
+        hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
+        break;
+
+      case HAL_HCD_PORT_ENABLED_CB_ID :
+        hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
+        break;
+
+      case HAL_HCD_PORT_DISABLED_CB_ID :
+        hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
+        break;
+
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hhcd->State == HAL_HCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HCD_MSPINIT_CB_ID :
+        hhcd->MspInitCallback = HAL_HCD_MspInit;
+        break;
+
+      case HAL_HCD_MSPDEINIT_CB_ID :
+        hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB HCD Host Channel Notify URB Change Callback
+  *         To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @param  pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB HCD Host Channel Notify URB Change Callback
+  *         USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  * @param  hhcd HCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhcd);
+
+  if (hhcd->State == HAL_HCD_STATE_READY)
+  {
+    hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhcd);
+
+  return status;
+}
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   Management functions 
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   Management functions
  *
-@verbatim 
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the HCD data 
+    This subsection provides a set of functions allowing to control the HCD data
     transfers.
 
 @endverbatim
@@ -623,35 +998,37 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t
 
 /**
   * @brief  Start the host driver.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
-{ 
-  __HAL_LOCK(hhcd); 
+{
+  __HAL_LOCK(hhcd);
   __HAL_HCD_ENABLE(hhcd);
-  USB_DriveVbus(hhcd->Instance, 1);  
-  __HAL_UNLOCK(hhcd); 
+  (void)USB_DriveVbus(hhcd->Instance, 1U);
+  __HAL_UNLOCK(hhcd);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Stop the host driver.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL status
   */
 
 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
-{ 
-  __HAL_LOCK(hhcd); 
-  USB_StopHost(hhcd->Instance);
-  __HAL_UNLOCK(hhcd); 
+{
+  __HAL_LOCK(hhcd);
+  (void)USB_StopHost(hhcd->Instance);
+  __HAL_UNLOCK(hhcd);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Reset the host port.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
@@ -663,15 +1040,15 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
   * @}
   */
 
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim 
+@verbatim
  ===============================================================================
                       ##### Peripheral State functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -680,7 +1057,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
 
 /**
   * @brief  Return the HCD handle state.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval HAL state
   */
 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@@ -690,17 +1067,17 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
 
 /**
   * @brief  Return  URB state for a channel.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
   * @retval URB state.
   *          This parameter can be one of these values:
   *            URB_IDLE/
   *            URB_DONE/
   *            URB_NOTREADY/
-  *            URB_NYET/ 
-  *            URB_ERROR/  
-  *            URB_STALL      
+  *            URB_NYET/
+  *            URB_ERROR/
+  *            URB_STALL
   */
 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
@@ -710,32 +1087,32 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
 
 /**
   * @brief  Return the last host transfer size.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
   * @retval last transfer size in byte
   */
 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
-  return hhcd->hc[chnum].xfer_count; 
+  return hhcd->hc[chnum].xfer_count;
 }
-  
+
 /**
   * @brief  Return the Host Channel state.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
   * @retval Host channel state
   *          This parameter can be one of these values:
   *            HC_IDLE/
   *            HC_XFRC/
   *            HC_HALTED/
-  *            HC_NYET/ 
-  *            HC_NAK/  
-  *            HC_STALL/ 
-  *            HC_XACTERR/  
-  *            HC_BBLERR/  
-  *            HC_DATATGLERR    
+  *            HC_NYET/
+  *            HC_NAK/
+  *            HC_STALL/
+  *            HC_XACTERR/
+  *            HC_BBLERR/
+  *            HC_DATATGLERR
   */
 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
@@ -744,7 +1121,7 @@ HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 
 /**
   * @brief  Return the current Host frame number.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval Current Host frame number
   */
 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
@@ -754,7 +1131,7 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
 
 /**
   * @brief  Return the Host enumeration speed.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval Enumeration speed
   */
 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@@ -775,418 +1152,462 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
   */
 /**
   * @brief  Handle Host Channel IN interrupt requests.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
-  * @retval None
+  * @retval none
   */
 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-  uint32_t tmpreg = 0;
-  
-  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)chnum;
+
+  uint32_t tmpreg;
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+  {
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
   {
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-  }  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
   {
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    hhcd->hc[ch_num].state = HC_STALL;
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
   }
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-    hhcd->hc[chnum].state = HC_STALL;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);    
-    USB_HC_Halt(hhcd->Instance, chnum);    
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+    hhcd->hc[ch_num].state = HC_DATATGLERR;
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
   }
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  else
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-    USB_HC_Halt(hhcd->Instance, chnum);  
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);    
-    hhcd->hc[chnum].state = HC_DATATGLERR;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
-  }    
-  
-  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+    /* ... */
+  }
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);  
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
   }
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
   {
-    
-    if (hhcd->Init.dma_enable)
+    if (hhcd->Init.dma_enable != 0U)
+    {
+      hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \
+                                    (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+    }
+
+    hhcd->hc[ch_num].state = HC_XFRC;
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+
+    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+        (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
     {
-      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
-        (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
     }
-    
-    hhcd->hc[chnum].state = HC_XFRC;
-    hhcd->hc[chnum].ErrCnt = 0;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
-    
-    
-    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
-        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
     {
-      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-      USB_HC_Halt(hhcd->Instance, chnum); 
-      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-      
+      USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[ch_num].urb_state = URB_DONE;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#else
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
     }
-    else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    else
     {
-      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
-      hhcd->hc[chnum].urb_state = URB_DONE; 
-      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+      /* ... */
     }
-    hhcd->hc[chnum].toggle_in ^= 1;
-    
+    hhcd->hc[ch_num].toggle_in ^= 1U;
+
   }
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
   {
-    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
-    
-    if(hhcd->hc[chnum].state == HC_XFRC)
+    __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+
+    if (hhcd->hc[ch_num].state == HC_XFRC)
     {
-      hhcd->hc[chnum].urb_state  = URB_DONE;      
+      hhcd->hc[ch_num].urb_state  = URB_DONE;
     }
-    
-    else if (hhcd->hc[chnum].state == HC_STALL) 
+    else if (hhcd->hc[ch_num].state == HC_STALL)
     {
-      hhcd->hc[chnum].urb_state  = URB_STALL;
-    }   
-    
-    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
-            (hhcd->hc[chnum].state == HC_DATATGLERR))
+      hhcd->hc[ch_num].urb_state  = URB_STALL;
+    }
+    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+             (hhcd->hc[ch_num].state == HC_DATATGLERR))
     {
-      if(hhcd->hc[chnum].ErrCnt++ > 3)
-      {      
-        hhcd->hc[chnum].ErrCnt = 0;
-        hhcd->hc[chnum].urb_state = URB_ERROR;
+      hhcd->hc[ch_num].ErrCnt++;
+      if (hhcd->hc[ch_num].ErrCnt > 3U)
+      {
+        hhcd->hc[ch_num].ErrCnt = 0U;
+        hhcd->hc[ch_num].urb_state = URB_ERROR;
       }
       else
       {
-        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
       }
-      
+
+      /* re-activate the channel  */
+      tmpreg = USBx_HC(ch_num)->HCCHAR;
+      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+      tmpreg |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(ch_num)->HCCHAR = tmpreg;
+    }
+    else if (hhcd->hc[ch_num].state == HC_NAK)
+    {
+      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
       /* re-activate the channel  */
-      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg = USBx_HC(ch_num)->HCCHAR;
       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
       tmpreg |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(chnum)->HCCHAR = tmpreg;
+      USBx_HC(ch_num)->HCCHAR = tmpreg;
     }
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
-    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
-  }  
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+    else
+    {
+      /* ... */
+    }
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    hhcd->hc[chnum].ErrCnt++;
-    hhcd->hc[chnum].state = HC_XACTERR;
-    USB_HC_Halt(hhcd->Instance, chnum);     
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    hhcd->hc[ch_num].ErrCnt++;
+    hhcd->hc[ch_num].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
   }
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
-  {  
-    if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+  {
+    if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
     {
-      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-      USB_HC_Halt(hhcd->Instance, chnum);  
+      hhcd->hc[ch_num].ErrCnt = 0U;
+      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
     }
-    else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
-              (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
+             (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
     {
-      /* re-activate the channel */
-      tmpreg = USBx_HC(chnum)->HCCHAR;
-      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-      tmpreg |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(chnum)->HCCHAR = tmpreg;
+      hhcd->hc[ch_num].ErrCnt = 0U;
+
+      if (hhcd->Init.dma_enable == 0U)
+      {
+        hhcd->hc[ch_num].state = HC_NAK;
+        __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+        (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      }
+    }
+    else
+    {
+      /* ... */
     }
-    hhcd->hc[chnum].state = HC_NAK;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+  }
+  else
+  {
+    /* ... */
   }
 }
 
 /**
   * @brief  Handle Host Channel OUT interrupt requests.
-  * @param  hhcd: HCD handle
-  * @param  chnum: Channel number.
+  * @param  hhcd HCD handle
+  * @param  chnum Channel number.
   *         This parameter can be a value from 1 to 15
-  * @retval None
+  * @retval none
   */
-static void HCD_HC_OUT_IRQHandler  (HCD_HandleTypeDef *hhcd, uint8_t chnum)
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
-  uint32_t tmpreg = 0;
-  
-  if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)chnum;
+  uint32_t tmpreg;
+
+  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
   {
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-  }  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
   {
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
-    
-    if( hhcd->hc[chnum].do_ping == 1)
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[ch_num].do_ping == 1U)
     {
-      hhcd->hc[chnum].state = HC_NYET;     
-      __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-      USB_HC_Halt(hhcd->Instance, chnum); 
-      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+      hhcd->hc[ch_num].do_ping = 0U;
+      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
+      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
     }
   }
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
   {
-    hhcd->hc[chnum].state = HC_NYET;
-    hhcd->hc[chnum].ErrCnt= 0;    
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);      
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
-    
-  }  
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
+    hhcd->hc[ch_num].state = HC_NYET;
+    hhcd->hc[ch_num].do_ping = 1U;
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);  
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
   }
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
   {
-      hhcd->hc[chnum].ErrCnt = 0;  
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-    USB_HC_Halt(hhcd->Instance, chnum);   
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
-    hhcd->hc[chnum].state = HC_XFRC;
-
-  }  
-
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)  
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+    hhcd->hc[ch_num].state = HC_XFRC;
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
   {
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);  
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
-    USB_HC_Halt(hhcd->Instance, chnum);   
-    hhcd->hc[chnum].state = HC_STALL;    
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    hhcd->hc[ch_num].state = HC_STALL;
   }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
+  {
+    hhcd->hc[ch_num].ErrCnt = 0U;
+    hhcd->hc[ch_num].state = HC_NAK;
 
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
-  {  
-    hhcd->hc[chnum].ErrCnt = 0;  
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);   
-    hhcd->hc[chnum].state = HC_NAK;
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-  }
+    if (hhcd->hc[ch_num].do_ping == 0U)
+    {
+      if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH)
+      {
+        hhcd->hc[ch_num].do_ping = 1U;
+      }
+    }
 
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+  }
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);      
-    hhcd->hc[chnum].state = HC_XACTERR;  
-     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    hhcd->hc[ch_num].state = HC_XACTERR;
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
   }
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(chnum); 
-    USB_HC_Halt(hhcd->Instance, chnum);      
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);    
-    hhcd->hc[chnum].state = HC_DATATGLERR;
+    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
+    hhcd->hc[ch_num].state = HC_DATATGLERR;
   }
-  
-  
-  else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
+  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
   {
-    __HAL_HCD_MASK_HALT_HC_INT(chnum); 
-    
-    if(hhcd->hc[chnum].state == HC_XFRC)
+    __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+
+    if (hhcd->hc[ch_num].state == HC_XFRC)
     {
-      hhcd->hc[chnum].urb_state  = URB_DONE;
-      if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
+      hhcd->hc[ch_num].urb_state  = URB_DONE;
+      if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
+          (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
       {
-        hhcd->hc[chnum].toggle_out ^= 1; 
-      }      
+        hhcd->hc[ch_num].toggle_out ^= 1U;
+      }
     }
-    else if (hhcd->hc[chnum].state == HC_NAK) 
+    else if (hhcd->hc[ch_num].state == HC_NAK)
     {
-      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
-    }  
-    
-    else if (hhcd->hc[chnum].state == HC_NYET) 
+      hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+    }
+    else if (hhcd->hc[ch_num].state == HC_NYET)
     {
-      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
-      hhcd->hc[chnum].do_ping = 0;
-    }   
-    
-    else if (hhcd->hc[chnum].state == HC_STALL) 
+      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
+    }
+    else if (hhcd->hc[ch_num].state == HC_STALL)
     {
-      hhcd->hc[chnum].urb_state  = URB_STALL;
-    } 
-    
-    else if((hhcd->hc[chnum].state == HC_XACTERR) ||
-            (hhcd->hc[chnum].state == HC_DATATGLERR))
+      hhcd->hc[ch_num].urb_state  = URB_STALL;
+    }
+    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
+             (hhcd->hc[ch_num].state == HC_DATATGLERR))
     {
-      if(hhcd->hc[chnum].ErrCnt++ > 3)
-      {      
-        hhcd->hc[chnum].ErrCnt = 0;
-        hhcd->hc[chnum].urb_state = URB_ERROR;
+      hhcd->hc[ch_num].ErrCnt++;
+      if (hhcd->hc[ch_num].ErrCnt > 3U)
+      {
+        hhcd->hc[ch_num].ErrCnt = 0U;
+        hhcd->hc[ch_num].urb_state = URB_ERROR;
       }
       else
       {
-        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
       }
-      
+
       /* re-activate the channel  */
-      tmpreg = USBx_HC(chnum)->HCCHAR;
+      tmpreg = USBx_HC(ch_num)->HCCHAR;
       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
       tmpreg |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(chnum)->HCCHAR = tmpreg;
+      USBx_HC(ch_num)->HCCHAR = tmpreg;
+    }
+    else
+    {
+      /* ... */
     }
-    
-    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
-    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);  
+
+    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
   }
-} 
+  else
+  {
+    /* ... */
+  }
+}
 
 /**
   * @brief  Handle Rx Queue Level interrupt requests.
-  * @param  hhcd: HCD handle
-  * @retval None
+  * @param  hhcd HCD handle
+  * @retval none
   */
 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
-  uint8_t  channelnum = 0;  
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t pktsts;
-  uint32_t pktcnt; 
-  uint32_t temp = 0;
-  uint32_t tmpreg = 0;
-  
+  uint32_t pktcnt;
+  uint32_t temp;
+  uint32_t tmpreg;
+  uint32_t ch_num;
+
   temp = hhcd->Instance->GRXSTSP;
-  channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;  
-  pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17;
-  pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4;
-  
+  ch_num = temp & USB_OTG_GRXSTSP_EPNUM;
+  pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
+  pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+
   switch (pktsts)
   {
-  case GRXSTS_PKTSTS_IN:
-    /* Read the data into the host buffer. */
-    if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void  *)0))
-    {  
-      
-      USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-      
-      /*manage multiple Xfer */
-      hhcd->hc[channelnum].xfer_buff += pktcnt;           
-      hhcd->hc[channelnum].xfer_count  += pktcnt;
-      
-      if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+    case GRXSTS_PKTSTS_IN:
+      /* Read the data into the host buffer. */
+      if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
       {
-        /* re-activate the channel when more packets are expected */
-        tmpreg = USBx_HC(channelnum)->HCCHAR;
-        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-        tmpreg |= USB_OTG_HCCHAR_CHENA;
-        USBx_HC(channelnum)->HCCHAR = tmpreg;
-        hhcd->hc[channelnum].toggle_in ^= 1;
+        (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+
+        /*manage multiple Xfer */
+        hhcd->hc[ch_num].xfer_buff += pktcnt;
+        hhcd->hc[ch_num].xfer_count  += pktcnt;
+
+        if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
+        {
+          /* re-activate the channel when more packets are expected */
+          tmpreg = USBx_HC(ch_num)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(ch_num)->HCCHAR = tmpreg;
+          hhcd->hc[ch_num].toggle_in ^= 1U;
+        }
       }
-    }
-    break;
-    
-  case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
-    break;
-  case GRXSTS_PKTSTS_IN_XFER_COMP:
-  case GRXSTS_PKTSTS_CH_HALTED:
-  default:
-    break;
+      break;
+
+    case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+      break;
+
+    case GRXSTS_PKTSTS_IN_XFER_COMP:
+    case GRXSTS_PKTSTS_CH_HALTED:
+    default:
+      break;
   }
 }
 
 /**
   * @brief  Handle Host Port interrupt requests.
-  * @param  hhcd: HCD handle
+  * @param  hhcd HCD handle
   * @retval None
   */
-static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
+static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;  
+  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
   __IO uint32_t hprt0, hprt0_dup;
-  
+
   /* Handle Host Port Interrupts */
   hprt0 = USBx_HPRT0;
   hprt0_dup = USBx_HPRT0;
-  
-  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
-                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  /* Check whether Port Connect Detected */
-  if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
-  {  
-    if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
+
+  hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
+                 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  /* Check whether Port Connect detected */
+  if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
+  {
+    if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
     {
-      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->ConnectCallback(hhcd);
+#else
       HAL_HCD_Connect_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
     }
     hprt0_dup  |= USB_OTG_HPRT_PCDET;
-    
   }
-  
+
   /* Check whether Port Enable Changed */
-  if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
+  if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
   {
     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
-    
-    if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
-    {    
-      if(hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
+
+    if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
+    {
+      if (hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
       {
         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
         {
-          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
+          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
         }
         else
         {
-          USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
         }
       }
       else
       {
-        if(hhcd->Init.speed == HCD_SPEED_FULL)
+        if (hhcd->Init.speed == HCD_SPEED_FULL)
         {
-          USBx_HOST->HFIR = (uint32_t)60000;
+          USBx_HOST->HFIR = 60000U;
         }
       }
-      HAL_HCD_Connect_Callback(hhcd);
-      
-      if(hhcd->Init.speed == HCD_SPEED_HIGH)
-      {
-        USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
-      }
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortEnabledCallback(hhcd);
+#else
+      HAL_HCD_PortEnabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+
     }
     else
     {
-      /* Cleanup HPRT */
-      USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
-        USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-      
-      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); 
-    }    
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+      hhcd->PortDisabledCallback(hhcd);
+#else
+      HAL_HCD_PortDisabled_Callback(hhcd);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+    }
   }
-  
+
   /* Check for an overcurrent */
-  if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
+  if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
   {
     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
   }
@@ -1203,7 +1624,9 @@ static void HCD_Port_IRQHandler  (HCD_HandleTypeDef *hhcd)
   * @}
   */
 
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 #endif /* HAL_HCD_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c
index 6748afab..7610867f 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c
@@ -2,15 +2,12 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
+  *           + Peripheral State, Mode and Error functions
   *
   @verbatim
   ==============================================================================
@@ -22,7 +19,7 @@
     (#) Declare a I2C_HandleTypeDef handle structure, for example:
         I2C_HandleTypeDef  hi2c;
 
-    (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
+    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
         (##) Enable the I2Cx interface clock
         (##) I2C pins configuration
             (+++) Enable the clock for the I2C GPIOs
@@ -34,103 +31,174 @@
             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
             (+++) Enable the DMAx interface clock using
             (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx Stream
+            (+++) Configure the DMA Tx or Rx stream
             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 
-                  the DMA Tx or Rx Stream
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+                  the DMA Tx or Rx stream
 
     (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
         Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
 
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 
-        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.
 
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
 
     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
 
     *** Polling mode IO operation ***
     =================================
     [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
 
     *** Polling mode IO MEM operation ***
     =====================================
     [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
 
 
     *** Interrupt mode IO operation ***
     ===================================
     [..]
-      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+
+    *** Interrupt mode or DMA mode IO sequential operation ***
+    ==========================================================
+    [..]
+      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+          when a direction change during transfer
+    [..]
+      (+) A specific option field manage the different steps of a sequential transfer
+      (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and without a final stop condition in both cases
+      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            if no direction change and with a final stop condition in both cases
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+                              without stopping the communication and so generate a restart condition.
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+                            interface.
+                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+
+      (+) Differents sequential I2C interfaces are listed below:
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
+           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
 
     *** Interrupt mode IO MEM operation ***
     =======================================
     [..]
-      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+          @ref HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+          @ref HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
 
     *** DMA mode IO operation ***
     ==============================
     [..]
-      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+          @ref HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
 
     *** DMA mode IO MEM operation ***
     =================================
     [..]
-      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
+      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+          @ref HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+          @ref HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
 
 
      *** I2C HAL driver macros list ***
@@ -138,44 +206,94 @@
      [..]
        Below the list of most used macros in I2C HAL driver.
 
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+      (+) @ref __HAL_I2C_ENABLE:     Enable the I2C peripheral
+      (+) @ref __HAL_I2C_DISABLE:    Disable the I2C peripheral
+      (+) @ref __HAL_I2C_GET_FLAG:   Checks whether the specified I2C flag is set or not
+      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) @ref __HAL_I2C_ENABLE_IT:  Enable the specified I2C interrupt
+      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+     *** Callback registration ***
+     =============================================
+    [..]
+     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     to register an interrupt callback.
+    [..]
+     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+    [..]
+     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     weak function.
+     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+       (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
+       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.
+       (+) ListenCpltCallback   : callback for end of listen mode.
+       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.
+       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.
+       (+) ErrorCallback        : callback for error detection.
+       (+) AbortCpltCallback    : callback for abort completion process.
+       (+) MspInitCallback      : callback for Msp Init.
+       (+) MspDeInitCallback    : callback for Msp DeInit.
+    [..]
+     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+    [..]
+     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     these callbacks are null (not registered beforehand).
+     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+    [..]
+     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+     or @ref HAL_I2C_Init() function.
+    [..]
+     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+
 
      [..]
        (@) You can refer to the I2C HAL driver header file for more useful macros
 
-
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -196,12 +314,21 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @addtogroup I2C_Private_Constants
+/** @addtogroup I2C_Private_Define
   * @{
-  */    
-#define I2C_TIMEOUT_FLAG          ((uint32_t)35)     /* 35 ms */
-#define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000)  /* 10 s  */
-#define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)10000)  /* 10 s  */
+  */
+#define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */
+#define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */
+#define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+
 /**
   * @}
   */
@@ -209,41 +336,56 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions
+
+/** @defgroup I2C_Private_Functions I2C Private Functions
   * @{
   */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+/* Private functions to handle DMA transfer */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
-
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
+static void I2C_ITError(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
+
+/* Private functions for I2C transfer IRQ handler */
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
+
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup I2C_Exported_Functions I2C Exported Functions
   * @{
   */
@@ -256,7 +398,7 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
               ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialize the I2Cx peripheral:
+          deinitialize the I2Cx peripheral:
 
       (+) User must Implement HAL_I2C_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
@@ -281,18 +423,18 @@ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
 
 /**
   * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and create the associated handle.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  *         in the I2C_InitTypeDef and initialize the associated handle.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
 {
-  uint32_t freqrange = 0;
-  uint32_t pclk1 = 0;
+  uint32_t freqrange;
+  uint32_t pclk1;
 
   /* Check the I2C handle allocation */
-  if(hi2c == NULL)
+  if (hi2c == NULL)
   {
     return HAL_ERROR;
   }
@@ -308,12 +450,35 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
 
-  if(hi2c->State == HAL_I2C_STATE_RESET)
+  if (hi2c->State == HAL_I2C_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hi2c->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    /* Init the I2C Callback settings */
+    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */
+    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */
+    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */
+    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */
+    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */
+    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */
+
+    if (hi2c->MspInitCallback == NULL)
+    {
+      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    hi2c->MspInitCallback(hi2c);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
 
   hi2c->State = HAL_I2C_STATE_BUSY;
@@ -324,52 +489,60 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
   /* Get PCLK1 frequency */
   pclk1 = HAL_RCC_GetPCLK1Freq();
 
+  /* Check the minimum allowed PCLK1 frequency */
+  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
+  {
+    return HAL_ERROR;
+  }
+
   /* Calculate frequency range */
   freqrange = I2C_FREQRANGE(pclk1);
 
   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
   /* Configure I2Cx: Frequency range */
-  hi2c->Instance->CR2 = freqrange;
+  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
 
   /*---------------------------- I2Cx TRISE Configuration --------------------*/
   /* Configure I2Cx: Rise Time */
-  hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
+  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
 
   /*---------------------------- I2Cx CCR Configuration ----------------------*/
   /* Configure I2Cx: Speed */
-  hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
+  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
 
   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
   /* Configure I2Cx: Generalcall and NoStretch mode */
-  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
 
   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
   /* Configure I2Cx: Own Address1 and addressing mode */
-  hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
+  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
 
   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
   /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
+  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
 
   /* Enable the selected I2C peripheral */
   __HAL_I2C_ENABLE(hi2c);
 
   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
   hi2c->State = HAL_I2C_STATE_READY;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode = HAL_I2C_MODE_NONE;
 
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the I2C peripheral.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  * @brief  DeInitialize the I2C peripheral.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
 {
   /* Check the I2C handle allocation */
-  if(hi2c == NULL)
+  if (hi2c == NULL)
   {
     return HAL_ERROR;
   }
@@ -382,12 +555,23 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
   /* Disable the I2C Peripheral Clock */
   __HAL_I2C_DISABLE(hi2c);
 
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  if (hi2c->MspDeInitCallback == NULL)
+  {
+    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  hi2c->MspDeInitCallback(hi2c);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-  hi2c->State = HAL_I2C_STATE_RESET;
+  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
+  hi2c->State         = HAL_I2C_STATE_RESET;
+  hi2c->PreviousState = I2C_STATE_NONE;
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
 
   /* Release Lock */
   __HAL_UNLOCK(hi2c);
@@ -396,36 +580,364 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
 }
 
 /**
-  * @brief I2C MSP Init.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  * @brief  Initialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
   * @retval None
   */
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_I2C_MspInit could be implemented in the user file
    */
 }
 
 /**
-  * @brief I2C MSP DeInit
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  * @brief  DeInitialize the I2C MSP.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
   * @retval None
   */
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_I2C_MspDeInit could be implemented in the user file
    */
 }
 
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User I2C Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2C Callback
+  *         I2C callback is redirected to the weak predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+        break;
+
+      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+        break;
+
+      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */
+        break;
+
+      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */
+        break;
+
+      case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */
+        break;
+
+      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */
+        break;
+
+      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */
+        break;
+
+      case HAL_I2C_ERROR_CB_ID :
+        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2C_ABORT_CB_ID :
+        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2C_STATE_RESET == hi2c->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2C_MSPINIT_CB_ID :
+        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2C_MSPDEINIT_CB_ID :
+        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  Register the Slave Address Match I2C Callback
+  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pCallback pointer to the Address Match Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Slave Address Match I2C Callback
+  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+
+  if (HAL_I2C_STATE_READY == hi2c->State)
+  {
+    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2c);
+  return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
  *  @brief   Data transfers functions
  *
 @verbatim
@@ -462,6 +974,13 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
         (++) HAL_I2C_Slave_Receive_IT()
         (++) HAL_I2C_Mem_Write_IT()
         (++) HAL_I2C_Mem_Read_IT()
+        (++) HAL_I2C_Master_Seq_Transmit_IT()
+        (++) HAL_I2C_Master_Seq_Receive_IT()
+        (++) HAL_I2C_Slave_Seq_Transmit_IT()
+        (++) HAL_I2C_Slave_Seq_Receive_IT()
+        (++) HAL_I2C_EnableListen_IT()
+        (++) HAL_I2C_DisableListen_IT()
+        (++) HAL_I2C_Master_Abort_IT()
 
     (#) No-Blocking mode functions with DMA are :
         (++) HAL_I2C_Master_Transmit_DMA()
@@ -470,15 +989,22 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
         (++) HAL_I2C_Slave_Receive_DMA()
         (++) HAL_I2C_Mem_Write_DMA()
         (++) HAL_I2C_Mem_Read_DMA()
+        (++) HAL_I2C_Master_Seq_Transmit_DMA()
+        (++) HAL_I2C_Master_Seq_Receive_DMA()
+        (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+        (++) HAL_I2C_Slave_Seq_Receive_DMA()
 
     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
         (++) HAL_I2C_MasterTxCpltCallback()
         (++) HAL_I2C_MasterRxCpltCallback()
         (++) HAL_I2C_SlaveTxCpltCallback()
         (++) HAL_I2C_SlaveRxCpltCallback()
+        (++) HAL_I2C_MemTxCpltCallback()
+        (++) HAL_I2C_MemRxCpltCallback()
+        (++) HAL_I2C_AddrCallback()
+        (++) HAL_I2C_ListenCpltCallback()
         (++) HAL_I2C_ErrorCallback()
+        (++) HAL_I2C_AbortCpltCallback()
 
 @endverbatim
   * @{
@@ -486,88 +1012,113 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
 
 /**
   * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
+    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
       }
 
       /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
 
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      /* Update counter */
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
       {
         /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+        hi2c->XferSize--;
       }
-    }
 
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
+      /* Wait until BTF flag is set */
+      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
+      }
     }
 
     /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -582,73 +1133,83 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
 
 /**
   * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
+    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
-    if(Size == 1)
+    if (hi2c->XferSize == 0U)
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 1U)
     {
       /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
       /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
     }
-    else if(Size == 2)
+    else if (hi2c->XferSize == 2U)
     {
       /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
       /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -656,105 +1217,154 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
     else
     {
       /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
     }
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
-      if(Size <= 3)
+      if (hi2c->XferSize <= 3U)
       {
         /* One byte */
-        if(Size == 1)
+        if (hi2c->XferSize == 1U)
         {
           /* Wait until RXNE flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
         /* Two bytes */
-        else if(Size == 2)
+        else if (hi2c->XferSize == 2U)
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
         /* 3 Last bytes */
         else
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
       }
       else
       {
         /* Wait until RXNE flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
         {
-          return HAL_TIMEOUT;
+          return HAL_ERROR;
         }
 
         /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
 
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
         {
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
       }
     }
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -769,95 +1379,122 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
 
 /**
   * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      return HAL_ERROR;
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
     /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
       /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        return HAL_ERROR;
       }
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
     }
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        /* Disable Address Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        return HAL_ERROR;
       }
 
       /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
 
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      /* Update counter */
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
       {
         /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+        hi2c->XferSize--;
       }
     }
 
     /* Wait until AF flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      return HAL_ERROR;
     }
 
     /* Clear AF flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
     /* Disable Address Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -872,82 +1509,112 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
 
 /**
   * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == (uint16_t)0))
     {
-      return  HAL_ERROR;
+      return HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->State       = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode        = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      return HAL_ERROR;
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
       /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        /* Disable Address Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        return HAL_ERROR;
       }
 
       /* Read data from DR */
-      (*pData++) = hi2c->Instance->DR;
-      Size--;
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
       {
         /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
       }
     }
 
     /* Wait until STOP flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      /* Disable Address Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      return HAL_ERROR;
     }
 
     /* Clear STOP flag */
     __HAL_I2C_CLEAR_STOPFLAG(hi2c);
 
     /* Disable Address Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -961,61 +1628,67 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
 }
 
 /**
-  * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  __IO uint32_t count = 0U;
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1023,7 +1696,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
     /* Note : The I2C interrupts must be enabled after unlocking current process
               to avoid the risk of I2C interrupt handle execution before current
               process unlock */
-
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
@@ -1036,96 +1708,77 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
 }
 
 /**
-  * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  __IO uint32_t count = 0U;
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      count--;
+      if (count == 0U)
       {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
+
         return HAL_ERROR;
       }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
 
-    if(hi2c->XferCount == 1)
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 2)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    /* Enable Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
     /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
 
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1139,43 +1792,48 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
 }
 
 /**
-  * @brief  Transmit in slave mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1196,43 +1854,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1253,76 +1916,137 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
 }
 
 /**
-  * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
 
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+    if (hi2c->XferSize > 0U)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
 
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferM1CpltCallback = NULL;
+      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
 
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
       {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
       }
       else
       {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
+
+        return HAL_ERROR;
       }
     }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
 
     return HAL_OK;
   }
@@ -1333,87 +2057,137 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
 }
 
 /**
-  * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
 
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
 
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+    if (hi2c->XferSize > 0U)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
 
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferM1CpltCallback = NULL;
+      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
 
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
       {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
       }
       else
       {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
 
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+        return HAL_ERROR;
+      }
     }
     else
     {
-      /* Enable Last DMA bit */
-      hi2c->Instance->CR2 |= I2C_CR2_LAST;
-    }
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
 
     return HAL_OK;
   }
@@ -1424,87 +2198,95 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
 }
 
 /**
-  * @brief  Transmit in slave mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
 
     /* Set the DMA error callback */
     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hi2c->hdmatx->XferM1CpltCallback = NULL;
+    hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+    hi2c->hdmatx->XferAbortCallback = NULL;
 
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    /* Enable the DMA stream */
+    dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
 
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    if (dmaxferstatus == HAL_OK)
     {
-      return HAL_TIMEOUT;
-    }
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-    /* If 7bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+      return HAL_OK;
     }
     else
     {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-    return HAL_OK;
+      return HAL_ERROR;
+    }
   }
   else
   {
@@ -1513,161 +2295,213 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
 }
 
 /**
-  * @brief  Receive in slave mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
 {
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  HAL_StatusTypeDef dmaxferstatus;
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      return HAL_BUSY;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
 
     /* Set the DMA error callback */
     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hi2c->hdmarx->XferM1CpltCallback = NULL;
+    hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+    hi2c->hdmarx->XferAbortCallback = NULL;
 
-    /* Enable Address Acknowledge */
-    hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    /* Enable the DMA stream */
+    dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
 
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
+    if (dmaxferstatus == HAL_OK)
     {
-      return HAL_TIMEOUT;
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      return HAL_OK;
     }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-    return HAL_OK;
+      return HAL_ERROR;
+    }
   }
   else
   {
     return HAL_BUSY;
   }
 }
+
 /**
   * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
       /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+        {
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+        return HAL_ERROR;
       }
 
       /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
 
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+      /* Update counter */
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
       {
         /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
       }
     }
 
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    /* Wait until BTF flag is set */
+    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
     }
 
     /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1682,78 +2516,88 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
 
 /**
   * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
     /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
-    if(Size == 1)
+    if (hi2c->XferSize == 0U)
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else if (hi2c->XferSize == 1U)
     {
       /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
       /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
     }
-    else if(Size == 2)
+    else if (hi2c->XferSize == 2U)
     {
       /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
       /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
       /* Clear ADDR flag */
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
@@ -1764,99 +2608,148 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
     }
 
-    while(Size > 0)
+    while (hi2c->XferSize > 0U)
     {
-      if(Size <= 3)
+      if (hi2c->XferSize <= 3U)
       {
         /* One byte */
-        if(Size== 1)
+        if (hi2c->XferSize == 1U)
         {
           /* Wait until RXNE flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
         /* Two bytes */
-        else if(Size == 2)
+        else if (hi2c->XferSize == 2U)
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
         /* 3 Last bytes */
         else
         {
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Disable Acknowledge */
-          hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
           {
-            return HAL_TIMEOUT;
+            return HAL_ERROR;
           }
 
           /* Generate Stop */
-          hi2c->Instance->CR1 |= I2C_CR1_STOP;
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
 
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
       }
       else
       {
         /* Wait until RXNE flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
         {
-          return HAL_TIMEOUT;
+          return HAL_ERROR;
         }
 
         /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
+        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
 
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+        /* Update counter */
+        hi2c->XferSize--;
+        hi2c->XferCount--;
+
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
         {
           /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+
+          /* Update counter */
+          hi2c->XferSize--;
+          hi2c->XferCount--;
         }
       }
     }
 
     hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1868,71 +2761,84 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
     return HAL_BUSY;
   }
 }
+
 /**
-  * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
 
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
     /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
 
     /* Enable EVT, BUF and ERR interrupt */
     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1946,105 +2852,90 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
 }
 
 /**
-  * @brief  Read an amount of data in no-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      count--;
+      if (count == 0U)
       {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
+
         return HAL_ERROR;
       }
-      else
-      {
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
 
-    if(hi2c->XferCount == 1)
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
-    }
-    else if(hi2c->XferCount == 2)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-      /* Enable Pos */
-      hi2c->Instance->CR1 |= I2C_CR1_POS;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+    hi2c->Devaddress  = DevAddress;
+    hi2c->Memaddress  = MemAddress;
+    hi2c->MemaddSize  = MemAddSize;
+    hi2c->EventCount  = 0U;
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      hi2c->Instance->CR1 |= I2C_CR1_ACK;
+    /* Enable Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    if (hi2c->XferSize > 0U)
+    {
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
 
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+    }
     return HAL_OK;
   }
   else
@@ -2052,81 +2943,146 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     return HAL_BUSY;
   }
 }
+
 /**
-  * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
-    }
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-    
-    /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
 
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+        return HAL_ERROR;
+      }
+    }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
 
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+    if (hi2c->XferSize > 0U)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferM1CpltCallback = NULL;
+      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
       {
+        /* Send Slave Address and Memory Address */
+        if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+        /* Enable ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        return HAL_OK;
       }
       else
       {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
+
+        return HAL_ERROR;
       }
     }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-    return HAL_OK;
+      return HAL_ERROR;
+    }
   }
   else
   {
@@ -2135,92 +3091,157 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 }
 
 /**
-  * @brief  Reads an amount of data in no-blocking mode with DMA from a specific memory address.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be read
+  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be read
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
+  /* Init tickstart for timeout management*/
+  uint32_t tickstart = HAL_GetTick();
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef dmaxferstatus;
+
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+    do
     {
-      return HAL_BUSY;
+      count--;
+      if (count == 0U)
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
+    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
-    /* Set the I2C DMA transfer complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
+    if (hi2c->XferSize > 0U)
+    {
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
 
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
 
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferM1CpltCallback = NULL;
+      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
 
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
       {
+        /* Send Slave Address and Memory Address */
+        if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+        {
+          return HAL_ERROR;
+        }
+
+        if (hi2c->XferSize == 1U)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+        else
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+        /* Enable ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
       }
       else
       {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
-        return HAL_TIMEOUT;
-      }
-    }
 
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+        return HAL_ERROR;
+      }
     }
     else
     {
-      /* Enable Last DMA bit */
-      hi2c->Instance->CR2 |= I2C_CR2_LAST;
-    }
+      /* Send Slave Address and Memory Address */
+      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+    }
 
     return HAL_OK;
   }
@@ -2233,43 +3254,56 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
 /**
   * @brief  Checks if target device is ready for communication.
   * @note   This function is used with Memory devices
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Trials: Number of trials
-  * @param  Timeout: Timeout duration
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Trials Number of trials
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
 {
-  uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
+  /* Get tick */
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t I2C_Trials = 1U;
+  FlagStatus tmp1;
+  FlagStatus tmp2;
 
-  if(hi2c->State == HAL_I2C_STATE_READY)
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
     /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
     {
       return HAL_BUSY;
     }
 
     /* Process Locked */
     __HAL_LOCK(hi2c);
-    
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
     /* Disable Pos */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 
     hi2c->State = HAL_I2C_STATE_BUSY;
     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
     do
     {
       /* Generate Start */
-      hi2c->Instance->CR1 |= I2C_CR1_START;
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
       /* Wait until SB flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
       {
-        return HAL_TIMEOUT;
+        return HAL_ERROR;
       }
 
       /* Send slave address */
@@ -2281,33 +3315,31 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 
       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-      tmp3 = hi2c->State;
-      while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
+      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
         {
           hi2c->State = HAL_I2C_STATE_TIMEOUT;
         }
         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-        tmp3 = hi2c->State;
       }
 
       hi2c->State = HAL_I2C_STATE_READY;
 
       /* Check if the ADDR flag has been set */
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
       {
         /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
         /* Clear ADDR Flag */
         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
         /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
         {
-          return HAL_TIMEOUT;
+          return HAL_ERROR;
         }
 
         hi2c->State = HAL_I2C_STATE_READY;
@@ -2320,19 +3352,22 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
       else
       {
         /* Generate Stop */
-        hi2c->Instance->CR1 |= I2C_CR1_STOP;
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
         /* Clear AF Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
         /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
         {
-          return HAL_TIMEOUT;
+          return HAL_ERROR;
         }
-
       }
-    }while(I2C_Trials++ < Trials);
+
+      /* Increment Trials */
+      I2C_Trials++;
+    }
+    while (I2C_Trials < Trials);
 
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -2348,627 +3383,2891 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 }
 
 /**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
   * @retval HAL status
   */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0;
-  /* Master mode selected */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET)
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count      = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
   {
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-      {
-        I2C_MasterTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
       {
-        I2C_MasterTransmit_BTF(hi2c);
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
       }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
     }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
-      /* RXNE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-      {
-        I2C_MasterReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
-      {
-        I2C_MasterReceive_BTF(hi2c);
-      }
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+    {
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
     }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
   }
-  /* Slave mode selected */
   else
   {
-    tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
-    tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
-    tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
-    tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
-    /* ADDR set --------------------------------------------------------------*/
-    if((tmp1 == SET) && (tmp2 == SET))
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count      = 0x00U;
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
     {
-      I2C_Slave_ADDR(hi2c);
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
     }
-    /* STOPF set --------------------------------------------------------------*/
-    else if((tmp3 == SET) && (tmp2 == SET))
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
     {
-      I2C_Slave_STOPF(hi2c);
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
     }
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    else if(tmp4 == SET)
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if (hi2c->XferSize > 0U)
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmatx->XferHalfCpltCallback = NULL;
+      hi2c->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
       {
-        I2C_SlaveTransmit_TXE(hi2c);
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+        /* Mean Previous state is same as current state */
+        if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+        {
+          /* Generate Start */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable DMA Request */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+        }
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
       }
-      /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      else
       {
-        I2C_SlaveTransmit_BTF(hi2c);
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
       }
     }
-    /* I2C in mode Receiver --------------------------------------------------*/
     else
     {
-      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
-      tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
-      tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
-      tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
-      /* RXNE set and BTF reset ----------------------------------------------*/
-      if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
-      {
-        I2C_SlaveReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((tmp3 == SET) && (tmp4 == SET))
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
       {
-        I2C_SlaveReceive_BTF(hi2c);
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
       }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable EVT, BUF and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
     }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
+  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
   * @retval HAL status
   */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
-  /* I2C Bus error interrupt occurred ----------------------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+    {
+      if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+      {
+        /* Disable Acknowledge */
+        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        /* Enable Pos */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+        /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
+        enableIT &= ~I2C_IT_BUF;
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+
+    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+    {
+      /* Generate Start */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+    to avoid the risk of I2C interrupt handle execution before current
+    process unlock */
+
+    /* Enable interrupts */
+    __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  __IO uint32_t Prev_State = 0x00U;
+  __IO uint32_t count = 0U;
+  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Check Busy Flag only if FIRST call of Master interface */
+    if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+    {
+      /* Wait until BUSY flag is reset */
+      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
+      do
+      {
+        count--;
+        if (count == 0U)
+        {
+          hi2c->PreviousState       = I2C_STATE_NONE;
+          hi2c->State               = HAL_I2C_STATE_READY;
+          hi2c->Mode                = HAL_I2C_MODE_NONE;
+          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    /* Clear Last DMA bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX;
+    hi2c->Mode      = HAL_I2C_MODE_MASTER;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+    hi2c->Devaddress  = DevAddress;
+
+    Prev_State = hi2c->PreviousState;
+
+    if (hi2c->XferSize > 0U)
+    {
+      if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
+      {
+        if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Enable Pos */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+        else
+        {
+          /* Enable Acknowledge */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+      }
+
+      /* Set the I2C DMA transfer complete callback */
+      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+      /* Set the DMA error callback */
+      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+      /* Set the unused DMA callbacks to NULL */
+      hi2c->hdmarx->XferHalfCpltCallback = NULL;
+      hi2c->hdmarx->XferAbortCallback = NULL;
+
+      /* Enable the DMA stream */
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+        /* Mean Previous state is same as current state */
+        if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+        {
+          /* Generate Start */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+          /* Update interrupt for only EVT and ERR */
+          enableIT = (I2C_IT_EVT | I2C_IT_ERR);
+        }
+        else
+        {
+          /* Update interrupt for only ERR */
+          enableIT = I2C_IT_ERR;
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+        to avoid the risk of I2C interrupt handle execution before current
+        process unlock */
+
+        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
+        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
+        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Enable DMA Request */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+        }
+
+        /* Enable EVT and ERR interrupt */
+        __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_READY;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+      /* Mean Previous state is same as current state */
+      if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
+      {
+        /* Generate Start */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+      }
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+
+      /* Enable interrupts */
+      __HAL_I2C_ENABLE_IT(hi2c, enableIT);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmatx->XferHalfCpltCallback = NULL;
+    hi2c->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the DMA stream */
+    dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      /* Enable DMA Request */
+      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Note : The I2C interrupts must be enabled after unlocking current process
+              to avoid the risk of I2C interrupt handle execution before current
+              process unlock */
+
+    /* Enable EVT, BUF and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with DMA
+  * @note   This interface allow to manage repeated start condition when a direction change during transfer
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  pData Pointer to data buffer
+  * @param  Size Amount of data to be sent
+  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+  HAL_StatusTypeDef dmaxferstatus;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+    /* and then toggle the HAL slave RX state to TX state */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmarx != NULL)
+        {
+          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA RX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+          }
+        }
+      }
+    }
+    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+      {
+        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+        /* Abort DMA Xfer if any */
+        if (hi2c->hdmatx != NULL)
+        {
+          /* Set the I2C DMA Abort callback :
+           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+          /* Abort DMA TX */
+          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+          {
+            /* Call Directly XferAbortCallback function in case of error */
+            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Disable Pos */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+
+    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
+    hi2c->Mode      = HAL_I2C_MODE_SLAVE;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+    /* Prepare transfer parameters */
+    hi2c->pBuffPtr    = pData;
+    hi2c->XferCount   = Size;
+    hi2c->XferSize    = hi2c->XferCount;
+    hi2c->XferOptions = XferOptions;
+
+    /* Set the I2C DMA transfer complete callback */
+    hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+    /* Set the DMA error callback */
+    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+    /* Set the unused DMA callbacks to NULL */
+    hi2c->hdmarx->XferHalfCpltCallback = NULL;
+    hi2c->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA stream */
+    dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+    if (dmaxferstatus == HAL_OK)
+    {
+      /* Enable Address Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      /* Enable DMA Request */
+      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Note : The I2C interrupts must be enabled after unlocking current process
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
+      /* Enable EVT and ERR interrupt */
+      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update I2C state */
+      hi2c->State     = HAL_I2C_STATE_READY;
+      hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+      /* Update I2C error code */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Enable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_READY)
+  {
+    hi2c->State = HAL_I2C_STATE_LISTEN;
+
+    /* Check if the I2C is already enabled */
+    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+    {
+      /* Enable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+    }
+
+    /* Enable Address Acknowledge */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Enable EVT and ERR interrupt */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable the Address listen mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp;
+
+  /* Disable Address listen mode only if a transfer is not ongoing */
+  if (hi2c->State == HAL_I2C_STATE_LISTEN)
+  {
+    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
+
+    /* Disable Address Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for the specified I2C.
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(DevAddress);
+
+  /* Abort Master transfer during Receive or Transmit process    */
+  if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_ABORT;
+
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    /* Generate Stop */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+    hi2c->XferCount = 0U;
+
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Wrong usage of abort function */
+    /* This function should be used only in case of abort monitored by master device */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+
+/**
+  * @brief  This function handles I2C event interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  uint32_t sr1itflags;
+  uint32_t sr2itflags               = 0U;
+  uint32_t itsources                = READ_REG(hi2c->Instance->CR2);
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  /* Master or Memory mode selected */
+  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
   {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+    sr2itflags   = READ_REG(hi2c->Instance->SR2);
+    sr1itflags   = READ_REG(hi2c->Instance->SR1);
+
+    /* Exit IRQ event until Start Bit detected in case of Other frame requested */
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
+    {
+      return;
+    }
+
+    /* SB Set ----------------------------------------------------------------*/
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      /* Convert OTHER_xxx XferOptions if any */
+      I2C_ConvertOtherXferOptions(hi2c);
+
+      I2C_Master_SB(hi2c);
+    }
+    /* ADD10 Set -------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADD10(hi2c);
+    }
+    /* ADDR Set --------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Master_ADDR(hi2c);
+    }
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
+    {
+      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
+      {
+        /* TXE set and BTF reset -----------------------------------------------*/
+        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+        {
+          I2C_MasterTransmit_TXE(hi2c);
+        }
+        /* BTF set -------------------------------------------------------------*/
+        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+        {
+          I2C_MasterTransmit_BTF(hi2c);
+        }
+        else
+        {
+          /* Do nothing */
+        }
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      /* Do not check buffer and BTF flag if a Xfer DMA is on going */
+      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
+      {
+        /* RXNE set and BTF reset -----------------------------------------------*/
+        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+        {
+          I2C_MasterReceive_RXNE(hi2c);
+        }
+        /* BTF set -------------------------------------------------------------*/
+        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+        {
+          I2C_MasterReceive_BTF(hi2c);
+        }
+        else
+        {
+          /* Do nothing */
+        }
+      }
+    }
+  }
+  /* Slave mode selected */
+  else
+  {
+    /* If an error is detected, read only SR1 register to prevent */
+    /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
+    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+    {
+      sr1itflags   = READ_REG(hi2c->Instance->SR1);
+    }
+    else
+    {
+      sr2itflags   = READ_REG(hi2c->Instance->SR2);
+      sr1itflags   = READ_REG(hi2c->Instance->SR1);
+    }
+
+    /* ADDR set --------------------------------------------------------------*/
+    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      /* Now time to read SR2, this will clear ADDR flag automatically */
+      if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+      {
+        sr2itflags   = READ_REG(hi2c->Instance->SR2);
+      }
+      I2C_Slave_ADDR(hi2c, sr2itflags);
+    }
+    /* STOPF set --------------------------------------------------------------*/
+    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+    {
+      I2C_Slave_STOPF(hi2c);
+    }
+    /* I2C in mode Transmitter -----------------------------------------------*/
+    else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+    {
+      /* TXE set and BTF reset -----------------------------------------------*/
+      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+      {
+        I2C_SlaveTransmit_TXE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+      {
+        I2C_SlaveTransmit_BTF(hi2c);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+    /* I2C in mode Receiver --------------------------------------------------*/
+    else
+    {
+      /* RXNE set and BTF reset ----------------------------------------------*/
+      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
+      {
+        I2C_SlaveReceive_RXNE(hi2c);
+      }
+      /* BTF set -------------------------------------------------------------*/
+      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
+      {
+        I2C_SlaveReceive_BTF(hi2c);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  This function handles I2C error interrupt request.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+  HAL_I2C_ModeTypeDef tmp1;
+  uint32_t tmp2;
+  HAL_I2C_StateTypeDef tmp3;
+  uint32_t tmp4;
+  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
+  uint32_t error      = HAL_I2C_ERROR_NONE;
+
+  /* I2C Bus error interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+  }
+
+  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+  }
+
+  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    tmp1 = hi2c->Mode;
+    tmp2 = hi2c->XferCount;
+    tmp3 = hi2c->State;
+    tmp4 = hi2c->PreviousState;
+    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
+        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
+         ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
+    {
+      I2C_Slave_AF(hi2c);
+    }
+    else
+    {
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      error |= HAL_I2C_ERROR_AF;
+
+      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+      if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+    }
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
+  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
+  {
+    error |= HAL_I2C_ERROR_OVR;
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+  }
+
+  /* Call the Error Callback in case of Error detected -----------------------*/
+  if (error != HAL_I2C_ERROR_NONE)
+  {
+    hi2c->ErrorCode |= error;
+    I2C_ITError(hi2c);
+  }
+}
+
+/**
+  * @brief  Master Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Master Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
+   */
+}
+
+/** @brief  Slave Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Slave Address Match callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+  UNUSED(TransferDirection);
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Listen Complete callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Memory Tx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemTxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Memory Rx Transfer completed callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_MemRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C error callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  I2C abort callback.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ *  @brief   Peripheral State, Mode and Error functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State, Mode and Error functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the I2C handle state.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL state
+  */
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+{
+  /* Return I2C handle state */
+  return hi2c->State;
+}
+
+/**
+  * @brief  Returns the I2C Master, Slave, Memory or no mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval HAL mode
+  */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->Mode;
+}
+
+/**
+  * @brief  Return the I2C error code.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *              the configuration information for the specified I2C.
+  * @retval I2C Error Code
+  */
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+{
+  return hi2c->ErrorCode;
+}
+
+/**
+  * @}
+  */
 
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Handle TXE flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
-  /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
   {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+    /* Call TxCpltCallback() directly if no stop mode is set */
+    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+    {
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
-  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterTxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else /* Generate Stop condition then Call TxCpltCallback() */
+    {
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MemTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+           ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
   {
-    tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL);
-    tmp2 = hi2c->XferCount;
-    tmp3 = hi2c->State;
-    if((tmp1 == RESET) && (tmp2 == 0) && (tmp3 == HAL_I2C_STATE_BUSY_TX))
+    if (hi2c->XferCount == 0U)
     {
-      I2C_Slave_AF(hi2c);
+      /* Disable BUF interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
     }
     else
     {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      /* Clear AF flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        if (hi2c->EventCount == 0U)
+        {
+          /* If Memory address size is 8Bit */
+          if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+          {
+            /* Send Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+            hi2c->EventCount += 2U;
+          }
+          /* If Memory address size is 16Bit */
+          else
+          {
+            /* Send MSB of Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+
+            hi2c->EventCount++;
+          }
+        }
+        else if (hi2c->EventCount == 1U)
+        {
+          /* Send LSB of Memory Address */
+          hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+          hi2c->EventCount++;
+        }
+        else if (hi2c->EventCount == 2U)
+        {
+          if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+          {
+            /* Generate Restart */
+            hi2c->Instance->CR1 |= I2C_CR1_START;
+          }
+          else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+          {
+            /* Write data to DR */
+            hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+            /* Increment Buffer pointer */
+            hi2c->pBuffPtr++;
+
+            /* Update counter */
+            hi2c->XferCount--;
+          }
+          else
+          {
+            /* Do nothing */
+          }
+        }
+        else
+        {
+          /* Do nothing */
+        }
+      }
+      else
+      {
+        /* Write data to DR */
+        hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hi2c->pBuffPtr++;
+
+        /* Update counter */
+        hi2c->XferCount--;
+      }
     }
   }
+  else
+  {
+    /* Do nothing */
+  }
+}
 
-  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
-  tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
-  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
-  if((tmp1 == SET) && (tmp2 == SET))
+/**
+  * @brief  Handle BTF flag for Master transmitter
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
   {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+    if (hi2c->XferCount != 0U)
+    {
+      /* Write data to DR */
+      hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+    else
+    {
+      /* Call TxCpltCallback() directly if no stop mode is set */
+      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+      {
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterTxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else /* Generate Stop condition then Call TxCpltCallback() */
+      {
+        /* Disable EVT, BUF and ERR interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+
+        if (hi2c->Mode == HAL_I2C_MODE_MEM)
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MemTxCpltCallback(hi2c);
+#else
+          HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+        else
+        {
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->MasterTxCpltCallback(hi2c);
+#else
+          HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+        }
+      }
+    }
   }
+}
 
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+/**
+  * @brief  Handle RXNE flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @retval None
+  */
+static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+{
+  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
   {
-    hi2c->State = HAL_I2C_STATE_READY;
-    
-    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
-    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
-    
-    HAL_I2C_ErrorCallback(hi2c);
+    uint32_t tmp;
+
+    tmp = hi2c->XferCount;
+    if (tmp > 3U)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+
+      if (hi2c->XferCount == (uint16_t)3)
+      {
+        /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
+        on BTF subroutine */
+        /* Disable BUF interrupt */
+        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+      }
+    }
+    else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* Disable EVT, BUF and ERR interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+
+      hi2c->State = HAL_I2C_STATE_READY;
+
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MemRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      /* Do nothing */
+    }
   }
 }
 
 /**
-  * @brief  Master Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle BTF flag for Master receiver
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
- __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  if (hi2c->XferCount == 4U)
+  {
+    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+       on BTF subroutine if there is a reception delay between N-1 and N byte */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+  else if (hi2c->XferCount == 3U)
+  {
+    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
+       on BTF subroutine if there is a reception delay between N-1 and N byte */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+    if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
+  else if (hi2c->XferCount == 2U)
+  {
+    /* Prepare next transfer or stop current transfer */
+    if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+    else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
+    {
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
+    else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+    if (hi2c->Mode == HAL_I2C_MODE_MEM)
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->PreviousState = I2C_STATE_NONE;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MemRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->MasterRxCpltCallback(hi2c);
+#else
+      HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
 }
 
 /**
-  * @brief  Master Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle SB flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  if (hi2c->Mode == HAL_I2C_MODE_MEM)
+  {
+    if (hi2c->EventCount == 0U)
+    {
+      /* Send slave address */
+      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+    }
+    else
+    {
+      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+    }
+  }
+  else
+  {
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+    {
+      /* Send slave 7 Bits address */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+      }
+      else
+      {
+        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+      }
+
+      if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+      {
+        if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
+        {
+          /* Enable DMA Request */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+        }
+      }
+    }
+    else
+    {
+      if (hi2c->EventCount == 0U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
+      }
+      else if (hi2c->EventCount == 1U)
+      {
+        /* Send header of slave address */
+        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
+      }
+      else
+      {
+        /* Do nothing */
+      }
+    }
+  }
 }
 
-/** @brief  Slave Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+/**
+  * @brief  Handle ADD10 flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
- __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  /* Send slave address */
+  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
+
+  if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
+  {
+    if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
+    {
+      /* Enable DMA Request */
+      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+    }
+  }
 }
 
 /**
-  * @brief  Slave Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle ADDR flag for Master
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_ModeTypeDef CurrentMode       = hi2c->Mode;
+  uint32_t CurrentXferOptions           = hi2c->XferOptions;
+  uint32_t Prev_State                   = hi2c->PreviousState;
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+  {
+    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    }
+    else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+    {
+      /* Clear ADDR flag */
+      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+      /* Generate Restart */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+
+      hi2c->EventCount++;
+    }
+    else
+    {
+      if (hi2c->XferCount == 0U)
+      {
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      else if (hi2c->XferCount == 1U)
+      {
+        if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+          {
+            /* Disable Acknowledge */
+            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+            /* Clear ADDR flag */
+            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+          }
+          else
+          {
+            /* Clear ADDR flag */
+            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+            /* Generate Stop */
+            SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+          }
+        }
+        /* Prepare next transfer or stop current transfer */
+        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+                 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
+        {
+          if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
+          {
+            /* Disable Acknowledge */
+            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+          }
+          else
+          {
+            /* Enable Acknowledge */
+            SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+          }
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+        }
+        else
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+          /* Generate Stop */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+        }
+      }
+      else if (hi2c->XferCount == 2U)
+      {
+        if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
+        {
+          /* Disable Acknowledge */
+          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+          /* Enable Pos */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+        }
+        else
+        {
+          /* Enable Acknowledge */
+          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+        }
+
+        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+      else
+      {
+        /* Enable Acknowledge */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
+        {
+          /* Enable Last DMA bit */
+          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+        }
+
+        /* Clear ADDR flag */
+        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+      }
+
+      /* Reset Event counter  */
+      hi2c->EventCount = 0U;
+    }
+  }
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+  }
 }
 
 /**
-  * @brief  Memory Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle TXE flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
- __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  if (hi2c->XferCount != 0U)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+
+    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+    {
+      /* Last Byte is received, disable Interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveTxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
 }
 
 /**
-  * @brief  Memory Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle BTF flag for Slave transmitter
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_TxCpltCallback could be implemented in the user file
-   */
+  if (hi2c->XferCount != 0U)
+  {
+    /* Write data to DR */
+    hi2c->Instance->DR = *hi2c->pBuffPtr;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
 }
 
 /**
-  * @brief  I2C error callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle RXNE flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
   * @retval None
   */
- __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
 
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
+  if (hi2c->XferCount != 0U)
+  {
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-@endverbatim
-  * @{
-  */
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
 
-/**
-  * @brief  Returns the I2C state.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->State;
-}
+    /* Update counter */
+    hi2c->XferCount--;
 
-/**
-  * @brief  Return the I2C error code
-  * @param  hi2c : pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
+    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+    {
+      /* Last Byte is received, disable Interrupt */
+      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+  }
 }
 
 /**
-  * @}
-  */
-
-/**
-  * @brief  Handle TXE flag for Master
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle BTF flag for Slave receiver
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @retval HAL status
+  * @retval None
   */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
+static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
 {
-  /* Write data to DR */
-  hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-  hi2c->XferCount--;
-
-  if(hi2c->XferCount == 0)
+  if (hi2c->XferCount != 0U)
   {
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-  }
+    /* Read data from DR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-  return HAL_OK;
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    /* Update counter */
+    hi2c->XferCount--;
+  }
 }
 
 /**
-  * @brief  Handle BTF flag for Master transmitter
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle ADD flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @retval HAL status
+  * @param  IT2Flags Interrupt2 flags to handle.
+  * @retval None
   */
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
 {
-  if(hi2c->XferCount != 0)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  else
-  {
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
+  uint16_t SlaveAddrCode;
 
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+  {
+    /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
+    __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
 
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
+    /* Transfer Direction requested by Master */
+    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
     {
-      hi2c->State = HAL_I2C_STATE_READY;
+      TransferDirection = I2C_DIRECTION_TRANSMIT;
+    }
 
-      HAL_I2C_MemTxCpltCallback(hi2c);
+    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
+    {
+      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
     }
     else
     {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterTxCpltCallback(hi2c);
+      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
     }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#else
+    HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Clear ADDR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
   }
-  return HAL_OK;
 }
 
 /**
-  * @brief  Handle RXNE flag for Master
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @brief  Handle STOPF flag for Slave
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @retval HAL status
+  * @retval None
   */
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
 {
-  uint32_t tmp = 0;
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  /* Disable EVT, BUF and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-  tmp = hi2c->XferCount;
-  if(tmp > 3)
+  /* Clear STOPF flag */
+  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+
+  /* Disable Acknowledge */
+  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+  /* If a DMA is ongoing, Update handle size context */
+  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
   {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+    if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+    {
+      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));
+
+      if (hi2c->XferCount != 0U)
+      {
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      }
+
+      /* Disable, stop the current DMA */
+      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Abort DMA Xfer if any */
+      if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+        hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+        /* Abort DMA RX */
+        if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+        }
+      }
+    }
+    else
+    {
+      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));
+
+      if (hi2c->XferCount != 0U)
+      {
+        /* Set ErrorCode corresponding to a Non-Acknowledge */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+      }
+
+      /* Disable, stop the current DMA */
+      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+
+      /* Abort DMA Xfer if any */
+      if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+      {
+        /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+        hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+        /* Abort DMA TX */
+        if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+        {
+          /* Call Directly XferAbortCallback function in case of error */
+          hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+        }
+      }
+    }
   }
-  else if((tmp == 2) || (tmp == 3))
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
   {
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      /* Update counter */
+      hi2c->XferCount--;
+    }
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    }
   }
-  else
-  {
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c);
+  }
+  else
+  {
+    if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
 
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
     {
+      hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+      hi2c->PreviousState = I2C_STATE_NONE;
       hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MemRxCpltCallback(hi2c);
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+
+      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->ListenCpltCallback(hi2c);
+#else
+      HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
     }
     else
     {
-      hi2c->State = HAL_I2C_STATE_READY;
+      if ((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+      {
+        hi2c->PreviousState = I2C_STATE_NONE;
+        hi2c->State = HAL_I2C_STATE_READY;
+        hi2c->Mode = HAL_I2C_MODE_NONE;
 
-      HAL_I2C_MasterRxCpltCallback(hi2c);
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->SlaveRxCpltCallback(hi2c);
+#else
+        HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
     }
   }
-  return HAL_OK;
 }
 
 /**
-  * @brief  Handle BTF flag for Master receiver
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @retval HAL status
+  * @retval None
   */
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
+static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
 {
-  if(hi2c->XferCount == 3)
-  {
-    /* Disable Acknowledge */
-    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
 
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  else if(hi2c->XferCount == 2)
+  if (((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+      (CurrentState == HAL_I2C_STATE_LISTEN))
   {
-    /* Generate Stop */
-    hi2c->Instance->CR1 |= I2C_CR1_STOP;
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
+  {
+    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
 
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
 
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
+    /* Clear AF flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
+    /* Disable Acknowledge */
+    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
   else
   {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+    /* Clear AF flag only */
+    /* State Listen, but XferOptions == FIRST or NEXT */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
   }
-  return HAL_OK;
 }
 
 /**
-  * @brief  Handle TXE flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
+  * @brief  I2C interrupts error process
+  * @param  hi2c I2C handle.
+  * @retval None
   */
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
+static void I2C_ITError(I2C_HandleTypeDef *hi2c)
 {
-  if(hi2c->XferCount != 0)
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+
+  if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
   {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
+    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+    hi2c->Instance->CR1 &= ~I2C_CR1_POS;
   }
-  return HAL_OK;
-}
 
-/**
-  * @brief  Handle BTF flag for Slave transmitter
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
+  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
   {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
+    /* keep HAL_I2C_STATE_LISTEN */
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State = HAL_I2C_STATE_LISTEN;
   }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
+  else
   {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+    }
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
   }
-  return HAL_OK;
-}
 
-/**
-  * @brief  Handle BTF flag for Slave receiver
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
+  /* Abort DMA transfer */
+  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
   {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
+    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
 
-/**
-  * @brief  Handle ADD flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
-{
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
+    {
+      /* Set the DMA Abort callback :
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
 
-  return HAL_OK;
-}
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+      {
+        /* Disable I2C peripheral to prevent dummy data in buffer */
+        __HAL_I2C_DISABLE(hi2c);
 
-/**
-  * @brief  Handle STOPF flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
-{
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+        hi2c->State = HAL_I2C_STATE_READY;
 
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+      }
+    }
+    else
+    {
+      /* Set the DMA Abort callback :
+      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
 
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+      {
+        /* Store Last receive data if any */
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+        {
+          /* Read data from DR */
+          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-  hi2c->State = HAL_I2C_STATE_READY;
+          /* Increment Buffer pointer */
+          hi2c->pBuffPtr++;
+        }
 
-  HAL_I2C_SlaveRxCpltCallback(hi2c);
+        /* Disable I2C peripheral to prevent dummy data in buffer */
+        __HAL_I2C_DISABLE(hi2c);
 
-  return HAL_OK;
-}
+        hi2c->State = HAL_I2C_STATE_READY;
 
-/**
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
-{
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+      }
+    }
+  }
+  else if (hi2c->State == HAL_I2C_STATE_ABORT)
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 
-  /* Clear AF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+    }
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    /* Disable I2C peripheral to prevent dummy data in buffer */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Store Last receive data if any */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+    {
+      /* Read data from DR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
 
-  HAL_I2C_SlaveTxCpltCallback(hi2c);
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+    }
 
-  return HAL_OK;
+    /* Call user error callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+  /* STOP Flag is not set after a NACK reception */
+  /* So may inform upper layer that listen phase is stopped */
+  /* during NACK error treatment */
+  CurrentState = hi2c->State;
+  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
+  {
+    /* Disable EVT, BUF and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+    hi2c->PreviousState = I2C_STATE_NONE;
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ListenCpltCallback(hi2c);
+#else
+    HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
 }
 
 /**
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Timeout: Timeout duration
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
-  /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+  /* Generate Start condition if first transfer */
+  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+  {
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+  {
+    /* Generate ReStart */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else
+  {
+    /* Do nothing */
+  }
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    return HAL_ERROR;
   }
 
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
   {
     /* Send slave address */
     hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
@@ -2979,16 +6278,9 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
 
     /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
     /* Send slave address */
@@ -2996,16 +6288,9 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
   }
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
+    return HAL_ERROR;
   }
 
   return HAL_OK;
@@ -3013,27 +6298,45 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
 
 /**
   * @brief  Master sends target device address for read request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Timeout: Timeout duration
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
 {
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  uint32_t CurrentXferOptions = hi2c->XferOptions;
+
   /* Enable Acknowledge */
-  hi2c->Instance->CR1 |= I2C_CR1_ACK;
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-  /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
+  /* Generate Start condition if first transfer */
+  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+  {
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+  {
+    /* Generate ReStart */
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+  }
+  else
+  {
+    /* Do nothing */
+  }
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    return HAL_ERROR;
   }
 
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
   {
     /* Send slave address */
     hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
@@ -3044,44 +6347,30 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
 
     /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
     /* Send slave address */
     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
 
     /* Wait until ADDR flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
     {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
 
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
     /* Generate Restart */
-    hi2c->Instance->CR1 |= I2C_CR1_START;
+    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
     /* Wait until SB flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      return HAL_ERROR;
     }
 
     /* Send header of slave address */
@@ -3089,16 +6378,9 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
   }
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
+    return HAL_ERROR;
   }
 
   return HAL_OK;
@@ -3106,52 +6388,52 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
 
 /**
   * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    return HAL_ERROR;
   }
 
   /* Send slave address */
   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
+    return HAL_ERROR;
   }
 
   /* Clear ADDR flag */
   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
   }
 
   /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
   {
     /* Send Memory Address */
     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3163,9 +6445,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
     }
 
     /* Send LSB of Memory Address */
@@ -3177,55 +6464,55 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
 
 /**
   * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
+  * @param  DevAddress Target device address: The device 7 bits address value
+  *         in datasheet must be shifted to the left before calling the interface
+  * @param  MemAddress Internal memory address
+  * @param  MemAddSize Size of internal memory address
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
 {
   /* Enable Acknowledge */
-  hi2c->Instance->CR1 |= I2C_CR1_ACK;
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
   /* Generate Start */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    return HAL_ERROR;
   }
 
   /* Send slave address */
   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
+    return HAL_ERROR;
   }
 
   /* Clear ADDR flag */
   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
   }
 
   /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
   {
     /* Send Memory Address */
     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3237,9 +6524,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
 
     /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
     {
-      return HAL_TIMEOUT;
+      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+      {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+      }
+      return HAL_ERROR;
     }
 
     /* Send LSB of Memory Address */
@@ -3247,367 +6539,496 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
   }
 
   /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
+    return HAL_ERROR;
   }
 
   /* Generate Restart */
-  hi2c->Instance->CR1 |= I2C_CR1_START;
+  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 
   /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
   {
-    return HAL_TIMEOUT;
+    return HAL_ERROR;
   }
 
   /* Send slave address */
   hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
 
   /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
   {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
+    return HAL_ERROR;
   }
 
   return HAL_OK;
 }
 
 /**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  hdma: DMA handle
+  * @brief  DMA I2C process complete callback.
+  * @param  hdma DMA handle
   * @retval None
   */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
+  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;
+  uint32_t CurrentXferOptions       = hi2c->XferOptions;
 
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+  /* Disable EVT and ERR interrupt */
+  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
 
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+  /* Clear Complete callback */
+  hi2c->hdmatx->XferCpltCallback = NULL;
+  hi2c->hdmarx->XferCpltCallback = NULL;
 
-  hi2c->XferCount = 0;
+  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
+  {
+    /* Disable DMA Request */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->XferCount = 0U;
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
+    if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveTxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
+    {
+      /* Set state at HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->SlaveRxCpltCallback(hi2c);
+#else
+      HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Do nothing */
+    }
+
+    /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
+    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
   }
-  else
+  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
+  else if (hi2c->Mode != HAL_I2C_MODE_NONE)
   {
-    HAL_I2C_MasterTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+    if (hi2c->XferCount == (uint16_t)1)
+    {
+      /* Disable Acknowledge */
+      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+    }
 
-  /* Wait until AF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
+    /* Disable EVT and ERR interrupt */
+    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
 
-  /* Clear AF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    /* Prepare next transfer or stop current transfer */
+    if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+    }
 
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+    /* Disable Last DMA */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
 
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+    /* Disable DMA Request */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
 
-  hi2c->XferCount = 0;
+    hi2c->XferCount = 0U;
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    /* Check if Errors has been detected during transfer */
+    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+    {
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+      hi2c->ErrorCallback(hi2c);
+#else
+      HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
+      if (hi2c->Mode == HAL_I2C_MODE_MEM)
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_NONE;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MemRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hi2c->Mode = HAL_I2C_MODE_NONE;
+        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+        hi2c->MasterRxCpltCallback(hi2c);
+#else
+        HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+      }
+    }
   }
   else
   {
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
+    /* Do nothing */
   }
 }
 
 /**
-  * @brief  DMA I2C master receive process complete callback
-  * @param  hdma: DMA handle
+  * @brief  DMA I2C communication error callback.
+  * @param  hdma DMA handle
   * @retval None
   */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-  
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+  /* Clear Complete callback */
+  hi2c->hdmatx->XferCpltCallback = NULL;
+  hi2c->hdmarx->XferCpltCallback = NULL;
 
-  /* Disable Last DMA */
-  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+  /* Ignore DMA FIFO error */
+  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+  {
+    /* Disable Acknowledge */
+    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
 
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+    hi2c->XferCount = 0U;
 
-  hi2c->XferCount = 0;
+    hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->Mode = HAL_I2C_MODE_NONE;
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
     HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
 }
 
 /**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  hdma: DMA handle
+  * @brief DMA I2C communication abort callback
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
   * @retval None
   */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
-  /* Wait until STOPF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
+  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
 
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
+  /* Clear Complete callback */
+  hi2c->hdmatx->XferCpltCallback = NULL;
+  hi2c->hdmarx->XferCpltCallback = NULL;
 
-  /* Disable Address Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+  /* Disable Acknowledge */
+  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
 
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+  hi2c->XferCount = 0U;
 
-  hi2c->XferCount = 0;
+  /* Reset XferAbortCallback */
+  hi2c->hdmatx->XferAbortCallback = NULL;
+  hi2c->hdmarx->XferAbortCallback = NULL;
 
-  hi2c->State = HAL_I2C_STATE_READY;
+  /* Disable I2C peripheral to prevent dummy data in buffer */
+  __HAL_I2C_DISABLE(hi2c);
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+  /* Check if come from abort from user */
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
   {
-    HAL_I2C_ErrorCallback(hi2c);
+    hi2c->State         = HAL_I2C_STATE_READY;
+    hi2c->Mode          = HAL_I2C_MODE_NONE;
+    hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
   else
   {
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
+    if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+    {
+      /* Renable I2C peripheral */
+      __HAL_I2C_ENABLE(hi2c);
+
+      /* Enable Acknowledge */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+
+      /* keep HAL_I2C_STATE_LISTEN */
+      hi2c->PreviousState = I2C_STATE_NONE;
+      hi2c->State = HAL_I2C_STATE_LISTEN;
+    }
+    else
+    {
+      hi2c->State = HAL_I2C_STATE_READY;
+      hi2c->Mode = HAL_I2C_MODE_NONE;
+    }
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
   }
 }
 
 /**
-  * @brief  DMA I2C Memory Write process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
   */
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
+  /* Wait until flag is set */
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
   {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
-
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
-
-  hi2c->XferCount = 0;
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState     = I2C_STATE_NONE;
+        hi2c->State             = HAL_I2C_STATE_READY;
+        hi2c->Mode              = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
 
-  hi2c->State = HAL_I2C_STATE_READY;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemTxCpltCallback(hi2c);
+        return HAL_ERROR;
+      }
+    }
   }
+  return HAL_OK;
 }
 
 /**
-  * @brief  DMA I2C Memory Read process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
+  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag specifies the I2C flag to check.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
   */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+  {
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    {
+      /* Generate Stop */
+      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-  
-  /* Generate Stop */
-  hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      /* Clear AF Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
-  /* Disable Last DMA */
-  hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
 
-  /* Disable DMA Request */
-  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-  hi2c->XferCount = 0;
+      return HAL_ERROR;
+    }
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemRxCpltCallback(hi2c);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+    }
   }
+  return HAL_OK;
 }
 
 /**
-  * @brief  DMA I2C communication error callback.
-  * @param  hdma: DMA handle
-  * @retval None
+  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
   */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Acknowledge */
-  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
-
-  hi2c->XferCount = 0;
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+  {
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
 
-  hi2c->State = HAL_I2C_STATE_READY;
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
 
-  HAL_I2C_ErrorCallback(hi2c);
+        return HAL_ERROR;
+      }
+    }
+  }
+  return HAL_OK;
 }
 
 /**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag: specifies the I2C flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
   {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
+        hi2c->PreviousState       = I2C_STATE_NONE;
+        hi2c->State               = HAL_I2C_STATE_READY;
+        hi2c->Mode                = HAL_I2C_MODE_NONE;
+        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
 
-          return HAL_TIMEOUT;
-        }
+        return HAL_ERROR;
       }
     }
   }
-  else
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
   {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
+    /* Check if a NACK is detected */
+    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
+      return HAL_ERROR;
+    }
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-          return HAL_TIMEOUT;
-        }
-      }
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+
+      return HAL_ERROR;
     }
   }
   return HAL_OK;
 }
 
 /**
-  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag: specifies the I2C flag to check.
-  * @param  Timeout: Timeout duration
+  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
 
-  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
   {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+    /* Check if a STOPF is detected */
+    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
     {
-      /* Generate Stop */
-      hi2c->Instance->CR1 |= I2C_CR1_STOP;
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
-      /* Clear AF Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-      hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -3616,28 +7037,81 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD
     }
 
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hi2c->State= HAL_I2C_STATE_READY;
+      hi2c->PreviousState       = I2C_STATE_NONE;
+      hi2c->State               = HAL_I2C_STATE_READY;
+      hi2c->Mode                = HAL_I2C_MODE_NONE;
+      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
 
-        return HAL_TIMEOUT;
-      }
+      return HAL_ERROR;
     }
   }
   return HAL_OK;
 }
 
+/**
+  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
+{
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  {
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    hi2c->PreviousState       = I2C_STATE_NONE;
+    hi2c->State               = HAL_I2C_STATE_READY;
+    hi2c->Mode                = HAL_I2C_MODE_NONE;
+    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+  /* if user set XferOptions to I2C_OTHER_FRAME            */
+  /* it request implicitly to generate a restart condition */
+  /* set XferOptions to I2C_FIRST_FRAME                    */
+  if (hi2c->XferOptions == I2C_OTHER_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_FRAME;
+  }
+  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+  /* it request implicitly to generate a restart condition    */
+  /* then generate a stop condition at the end of transfer    */
+  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */
+  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+  {
+    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+
 /**
   * @}
   */
 
 #endif /* HAL_I2C_MODULE_ENABLED */
-
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2s.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2s.c
index 1159b7b2..4d583a32 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2s.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2s.c
@@ -2,10 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
@@ -16,10 +14,10 @@
  ===============================================================================
  [..]
     The I2S HAL driver can be used as follow:
-    
+
     (#) Declare a I2S_HandleTypeDef handle structure.
     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.                      
+        (##) Enable the SPIx interface clock.
         (##) I2S pins configuration:
             (+++) Enable the clock for the I2S GPIOs.
             (+++) Configure these I2S pins as alternate function pull-up.
@@ -29,74 +27,74 @@
             (+++) Enable the NVIC I2S IRQ handle.
         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
              and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Configure the DMA Tx/Rx Stream/Channel.
             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
-                DMA Tx/Rx Stream.
-  
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+                  DMA Tx/Rx Stream/Channel.
+
    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
        using HAL_I2S_Init() function.
 
-   -@- The specific I2S interrupts (Transmission complete interrupt, 
+   -@- The specific I2S interrupts (Transmission complete interrupt,
        RXNE interrupt and Error Interrupts) will be managed using the macros
-       __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
+       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
    -@- Make sure that either:
-        (+@) I2S PLL is configured or 
-        (+@) External clock source is configured after setting correctly 
-             the define constant EXTERNAL_CLOCK_VALUE in the stm32f2xx_hal_conf.h file. 
-             
-   (#) Three operation modes are available within this driver :
-  
+        (+@) I2S PLL clock is configured or
+        (+@) External clock source is configured after setting correctly
+             the define constant EXTERNAL_CLOCK_VALUE in the stm32f2xx_hal_conf.h file.
+
+    (#) Three mode of operations are available within this driver :
+
    *** Polling mode IO operation ***
    =================================
-   [..]    
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 
+   [..]
+     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-   
+
    *** Interrupt mode IO operation ***
    ===================================
-   [..]    
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+   [..]
+     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_I2S_ErrorCallback
 
    *** DMA mode IO operation ***
    ==============================
-   [..] 
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
+   [..]
+     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
+     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
+     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_I2S_ErrorCallback
      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
 
    *** I2S HAL driver macros list ***
-   =============================================
+   ===================================
    [..]
-     Below the list of most used macros in USART HAL driver.
-       
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 
+     Below the list of most used macros in I2S HAL driver.
+
+      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
@@ -105,40 +103,84 @@
     [..]
       (@) You can refer to the I2S HAL driver header file for more useful macros
 
+   *** I2S HAL driver macros list ***
+   ===================================
+   [..]
+       Callback registration:
+
+      (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+          allows the user to configure dynamically the driver callbacks.
+          Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+          Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+            (++) TxCpltCallback        : I2S Tx Completed callback
+            (++) RxCpltCallback        : I2S Rx Completed callback
+            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
+            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (++) ErrorCallback         : I2S Error callback
+            (++) MspInitCallback       : I2S Msp Init callback
+            (++) MspDeInitCallback     : I2S Msp DeInit callback
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+
+      (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+          weak function.
+          HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (++) TxCpltCallback        : I2S Tx Completed callback
+            (++) RxCpltCallback        : I2S Rx Completed callback
+            (++) TxHalfCpltCallback    : I2S Tx Half Completed callback
+            (++) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (++) ErrorCallback         : I2S Error callback
+            (++) MspInitCallback       : I2S Msp Init callback
+            (++) MspDeInitCallback     : I2S Msp DeInit callback
+
+       [..]
+       By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+       all callbacks are set to the corresponding weak functions:
+       examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+       Exception done for MspInit and MspDeInit functions that are
+       reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+       these callbacks are null (not registered beforehand).
+       If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+       [..]
+       Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+       Exception done MspInit/MspDeInit functions that can be registered/unregistered
+       in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+       Then, the user first registers the MspInit/MspDeInit user callbacks
+       using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+       or HAL_I2S_Init() function.
+
+       [..]
+       When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+       not defined, the callback registering feature is not available
+       and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+#ifdef HAL_I2S_MODULE_ENABLED
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
@@ -148,79 +190,82 @@
   * @{
   */
 
-#ifdef HAL_I2S_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2S_Private_Functions
+/** @defgroup I2S_Private_Functions I2S Private Functions
   * @{
   */
-static void              I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void              I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 
-static void              I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void              I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void              I2S_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
+static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
+static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+                                                        uint32_t Timeout);
 /**
   * @}
   */
-  
-/* Exported functions --------------------------------------------------------*/
+
+/* Exported functions ---------------------------------------------------------*/
+
 /** @defgroup I2S_Exported_Functions I2S Exported Functions
   * @{
   */
 
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim     
+/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
+    [..]  This subsection provides a set of functions allowing to initialize and
           de-initialize the I2Sx peripheral in simplex mode:
 
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures 
+      (+) User must Implement HAL_I2S_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 
-      (+) Call the function HAL_I2S_Init() to configure the selected device with 
+      (+) Call the function HAL_I2S_Init() to configure the selected device with
           the selected configuration:
         (++) Mode
-        (++) Standard 
+        (++) Standard
         (++) Data Format
         (++) MCLK Output
         (++) Audio frequency
         (++) Polarity
 
-      (+) Call the function HAL_I2S_DeInit() to restore the default configuration 
-          of the selected I2Sx peripheral. 
-@endverbatim
+     (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+          of the selected I2Sx peripheral.
+  @endverbatim
   * @{
   */
 
 /**
-  * @brief Initializes the I2S according to the specified parameters 
+  * @brief  Initializes the I2S according to the specified parameters
   *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
-__weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 {
-  uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0, i2sclk = 0;
-  
+  uint32_t i2sdiv;
+  uint32_t i2sodd;
+  uint32_t packetlength;
+  uint32_t tmp;
+  uint32_t i2sclk;
+
   /* Check the I2S handle allocation */
-  if(hi2s == NULL)
+  if (hi2s == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the I2S parameters */
   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
@@ -228,47 +273,73 @@ __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
+  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
   assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
-  
-  if(hi2s->State == HAL_I2S_STATE_RESET)
+
+  if (hi2s->State == HAL_I2S_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hi2s->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+    /* Init the I2S Callback settings */
+    hi2s->TxCpltCallback       = HAL_I2S_TxCpltCallback;          /* Legacy weak TxCpltCallback       */
+    hi2s->RxCpltCallback       = HAL_I2S_RxCpltCallback;          /* Legacy weak RxCpltCallback       */
+    hi2s->TxHalfCpltCallback   = HAL_I2S_TxHalfCpltCallback;      /* Legacy weak TxHalfCpltCallback   */
+    hi2s->RxHalfCpltCallback   = HAL_I2S_RxHalfCpltCallback;      /* Legacy weak RxHalfCpltCallback   */
+    hi2s->ErrorCallback        = HAL_I2S_ErrorCallback;           /* Legacy weak ErrorCallback        */
+
+    if (hi2s->MspInitCallback == NULL)
+    {
+      hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    hi2s->MspInitCallback(hi2s);
+#else
     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
     HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
   }
-  
+
   hi2s->State = HAL_I2S_STATE_BUSY;
-  
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
-                               SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
-                               SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); 
-  hi2s->Instance->I2SPR = 0x0002;
 
-  /* Get the I2SCFGR register value */
-  tmpreg = hi2s->Instance->I2SCFGR;
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+                                      SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+                                      SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+  hi2s->Instance->I2SPR = 0x0002U;
 
-  /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
+  /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
   /* If the requested audio frequency is not the default, compute the prescaler */
-  if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
+  if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
   {
-    /* Check the frame length (For the Prescaler computing) *******************/
-    if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+    /* Check the frame length (For the Prescaler computing) ********************/
+    if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 16U;
+    }
+    else
     {
       /* Packet length is 32 bits */
-      packetlength = 2;
+      packetlength = 32U;
     }
 
-    /* Get I2S source Clock frequency  ****************************************/
-    /* If an external I2S clock has to be used, the specific define should be set  
+    /* I2S standard */
+    if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
+    {
+      /* In I2S standard packet lenght is multiplied by 2 */
+      packetlength = packetlength * 2U;
+    }
+
+    /* If an external I2S clock has to be used, the specific define should be set
     in the project configuration or in the stm32f2xx_conf.h file */
-    if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
+    if (hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
     {
       /* Set external clock as I2S clock source */
-      if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
+      if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0U)
       {
         RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
       }
@@ -277,23 +348,23 @@ __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
       i2sclk = EXTERNAL_CLOCK_VALUE;
     }
     else
-    { 
+    {
       /* Check if PLLI2S is enabled or Not */
-      if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
+      if ((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
       {
-        hi2s->State= HAL_I2S_STATE_READY;
-        
+        hi2s->State = HAL_I2S_STATE_READY;
+
         return HAL_ERROR;
       }
 
       /* Set PLLI2S as I2S clock source */
-      if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
+      if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0U)
       {
         RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
       }
 
       /* Get the PLLM value */
-      if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+      if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
       {
         /* Get the I2S source clock value */
         i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
@@ -303,78 +374,121 @@ __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
         /* Get the I2S source clock value */
         i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
       }
-      i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
-      i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
+      i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U));
+      i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U));
     }
-
     /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+    if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
     {
       /* MCLK output is enabled */
-      tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+      if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+      {
+        tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+      }
+      else
+      {
+        tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+      }
     }
     else
     {
       /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+      tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
     }
 
     /* Remove the flatting point */
-    tmp = tmp / 10;  
+    tmp = tmp / 10U;
 
     /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1);
+    i2sodd = (uint32_t)(tmp & (uint32_t)1U);
 
     /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+    i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
 
     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t) (i2sodd << 8);
+    i2sodd = (uint32_t)(i2sodd << 8U);
+  }
+  else
+  {
+    /* Set the default values */
+    i2sdiv = 2U;
+    i2sodd = 0U;
   }
 
   /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if((i2sdiv < 2) || (i2sdiv > 0xFF))
+  if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
   {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
+    /* Set the error code and execute error callback*/
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+    return  HAL_ERROR;
   }
-  
+
+  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
   /* Write to SPIx I2SPR register the computed value */
   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-  
-  /* Configure the I2S with the I2S_InitStruct values */
-  tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-  
-  /* Write to SPIx I2SCFGR */  
-  hi2s->Instance->I2SCFGR = tmpreg;
+
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  /* And configure the I2S with the I2S_InitStruct values                      */
+  MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+                                       SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+                                       SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+                                       SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD), \
+             (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+              hi2s->Init.Standard | hi2s->Init.DataFormat | \
+              hi2s->Init.CPOL));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+  if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
+  {
+    /* Write to SPIx I2SCFGR */
+    SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+  }
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State= HAL_I2S_STATE_READY;
-  
+  hi2s->State     = HAL_I2S_STATE_READY;
+
   return HAL_OK;
 }
-           
+
 /**
-  * @brief DeInitializes the I2S peripheral 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief DeInitializes the I2S peripheral
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
 {
   /* Check the I2S handle allocation */
-  if(hi2s == NULL)
+  if (hi2s == NULL)
   {
     return HAL_ERROR;
   }
-  
+
+  /* Check the parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
+
   hi2s->State = HAL_I2S_STATE_BUSY;
-  
+
+  /* Disable the I2S Peripheral Clock */
+  __HAL_I2S_DISABLE(hi2s);
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  if (hi2s->MspDeInitCallback == NULL)
+  {
+    hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  hi2s->MspDeInitCallback(hi2s);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
   HAL_I2S_MspDeInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 
   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State = HAL_I2S_STATE_RESET;
+  hi2s->State     = HAL_I2S_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(hi2s);
@@ -384,58 +498,257 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
 
 /**
   * @brief I2S MSP Init
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief I2S MSP DeInit
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_MspDeInit could be implemented in the user file
-   */ 
+   */
+}
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User I2S Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2S.
+  * @param  CallbackID ID of the callback to be registered
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hi2s);
+
+  if (HAL_I2S_STATE_READY == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_TX_COMPLETE_CB_ID :
+        hi2s->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_RX_COMPLETE_CB_ID :
+        hi2s->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+        hi2s->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+        hi2s->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_I2S_ERROR_CB_ID :
+        hi2s->ErrorCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2S_STATE_RESET == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = pCallback;
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2s);
+  return status;
+}
+
+/**
+  * @brief  Unregister an I2S Callback
+  *         I2S callback is redirected to the weak predefined callback
+  * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2S.
+  * @param  CallbackID ID of the callback to be unregistered
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hi2s);
+
+  if (HAL_I2S_STATE_READY == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_TX_COMPLETE_CB_ID :
+        hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback;                /* Legacy weak TxCpltCallback       */
+        break;
+
+      case HAL_I2S_RX_COMPLETE_CB_ID :
+        hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback;                /* Legacy weak RxCpltCallback       */
+        break;
+
+      case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+        hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback   */
+        break;
+
+      case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+        hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback   */
+        break;
+
+      case HAL_I2S_ERROR_CB_ID :
+        hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_I2S_STATE_RESET == hi2s->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_I2S_MSPINIT_CB_ID :
+        hi2s->MspInitCallback = HAL_I2S_MspInit;                      /* Legacy weak MspInit              */
+        break;
+
+      case HAL_I2S_MSPDEINIT_CB_ID :
+        hi2s->MspDeInitCallback = HAL_I2S_MspDeInit;                  /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hi2s);
+  return status;
 }
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- *  @brief    Data transfers functions  
- *
-@verbatim   
+  *  @brief Data transfers functions
+  *
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
  ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to manage the I2S data 
+    This subsection provides a set of functions allowing to manage the I2S data
     transfers.
 
     (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
-            The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode : The communication is performed using Interrupts 
+       (++) Blocking mode : The communication is performed in the polling mode.
+            The status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) No-Blocking mode : The communication is performed using Interrupts
             or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
+            The end of the data processing will be indicated through the
+            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
 
     (#) Blocking mode functions are :
         (++) HAL_I2S_Transmit()
         (++) HAL_I2S_Receive()
-        
+
     (#) No-Blocking mode functions with Interrupt are :
         (++) HAL_I2S_Transmit_IT()
         (++) HAL_I2S_Receive_IT()
@@ -454,742 +767,815 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
   */
 
 /**
-  * @brief Transmit an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Transmit an amount of data in blocking mode
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param  Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @param  Timeout Timeout duration
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t tmp1 = 0;
-  if((pData == NULL ) || (Size == 0)) 
+  uint32_t tmpreg_cfgr;
+
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2;
-      hi2s->TxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-   
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-    
-    while(hi2s->TxXferCount > 0)
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr = pData;
+
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+  {
+    hi2s->TxXferSize = (Size << 1U);
+    hi2s->TxXferCount = (Size << 1U);
+  }
+  else
+  {
+    hi2s->TxXferSize = Size;
+    hi2s->TxXferCount = Size;
+  }
+
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR;
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Wait until TXE flag is set */
+  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+  {
+    /* Set the error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+    hi2s->State = HAL_I2S_STATE_READY;
+    __HAL_UNLOCK(hi2s);
+    return HAL_ERROR;
+  }
+
+  while (hi2s->TxXferCount > 0U)
+  {
+    hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+    hi2s->pTxBuffPtr++;
+    hi2s->TxXferCount--;
+
+    /* Wait until TXE flag is set */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
     {
-      hi2s->Instance->DR = (*pData++);
-      hi2s->TxXferCount--;   
-      /* Wait until TXE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_ERROR;
     }
-     
-    /* Check if Slave mode is selected */
-    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+
+    /* Check if an underrun occurs */
+    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
     {
-      /* Wait until Busy flag is reset */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
+      /* Clear underrun flag */
+      __HAL_I2S_CLEAR_UDRFLAG(hi2s);
 
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+    }
   }
-  else
+
+  /* Check if Slave mode is selected */
+  if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+      || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
   {
-    return HAL_BUSY;
+    /* Wait until Busy flag is reset */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+    {
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_ERROR;
+    }
   }
+
+  hi2s->State = HAL_I2S_STATE_READY;
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Receive an amount of data in blocking mode 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Receive an amount of data in blocking mode
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *       in continuous way and as the I2S is not disabled at the end of the I2S transaction.
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @param  Timeout Timeout duration
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @note   In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+  *         in continuous way and as the I2S is not disabled at the end of the I2S transaction.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint32_t tmp1 = 0;
-  if((pData == NULL ) || (Size == 0)) 
+  uint32_t tmpreg_cfgr;
+
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2;
-      hi2s->RxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
 
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
 
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr = pData;
+
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+  {
+    hi2s->RxXferSize = (Size << 1U);
+    hi2s->RxXferCount = (Size << 1U);
+  }
+  else
+  {
+    hi2s->RxXferSize = Size;
+    hi2s->RxXferCount = Size;
+  }
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  /* Check if Master Receiver mode is selected */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+  {
+    /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+    access to the SPI_SR register. */
+    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+  }
+
+  /* Receive data */
+  while (hi2s->RxXferCount > 0U)
+  {
+    /* Wait until RXNE flag is set */
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
     {
-      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+      hi2s->State = HAL_I2S_STATE_READY;
+      __HAL_UNLOCK(hi2s);
+      return HAL_ERROR;
     }
 
-    /* Receive data */
-    while(hi2s->RxXferCount > 0)
+    (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+    hi2s->pRxBuffPtr++;
+    hi2s->RxXferCount--;
+
+    /* Check if an overrun occurs */
+    if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
     {
-      /* Wait until RXNE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
+      /* Clear overrun flag */
+      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
 
-      (*pData++) = hi2s->Instance->DR;
-      hi2s->RxXferCount--;
+      /* Set the error code */
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
     }
-
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
   }
+
+  hi2s->State = HAL_I2S_STATE_READY;
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
+  * @param  pData a 16-bit pointer to data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 {
-  uint32_t tmp1 = 0;
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
+  uint32_t tmpreg_cfgr;
 
-    hi2s->pTxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
 
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2;
-      hi2s->TxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
 
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
 
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr = pData;
 
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+  {
+    hi2s->TxXferSize = (Size << 1U);
+    hi2s->TxXferCount = (Size << 1U);
   }
   else
   {
-    return HAL_BUSY;
+    hi2s->TxXferSize = Size;
+    hi2s->TxXferCount = Size;
+  }
+
+  /* Enable TXE and ERR interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
   }
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 
-  * between Master and Slave otherwise the I2S interrupt should be optimized. 
+  * @param  pData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
+  * @note   It is recommended to use DMA for the I2S receiver to avoid de-synchronization
+  * between Master and Slave otherwise the I2S interrupt should be optimized.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 {
-  uint32_t tmp1 = 0;
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
+  uint32_t tmpreg_cfgr;
 
-    hi2s->pRxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+  if ((pData == NULL) || (Size == 0U))
+  {
+    return  HAL_ERROR;
+  }
 
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2;
-      hi2s->RxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
 
-    /* Process Unlocked */
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
     __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
+    return HAL_BUSY;
   }
 
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr = pData;
+
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+  {
+    hi2s->RxXferSize = (Size << 1U);
+    hi2s->RxXferCount = (Size << 1U);
+  }
   else
   {
-    return HAL_BUSY; 
-  } 
+    hi2s->RxXferSize = Size;
+    hi2s->RxXferCount = Size;
+  }
+
+  /* Enable RXNE and ERR interrupt */
+  __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+  /* Check if the I2S is already enabled */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
+  }
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Transmit an amount of data in non-blocking mode with DMA
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
+  * @param  pData a 16-bit pointer to the Transmit data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 {
-  uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  if((pData == NULL) || (Size == 0)) 
+  uint32_t tmpreg_cfgr;
+
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {  
-    hi2s->pTxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = Size*2;
-      hi2s->TxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
 
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
 
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_TX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pTxBuffPtr = pData;
 
-    /* Set the I2S Tx DMA Half transfer complete callback */
-    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
 
-    /* Set the I2S Tx DMA transfer complete callback */
-    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+  {
+    hi2s->TxXferSize = (Size << 1U);
+    hi2s->TxXferCount = (Size << 1U);
+  }
+  else
+  {
+    hi2s->TxXferSize = Size;
+    hi2s->TxXferCount = Size;
+  }
 
-    /* Set the DMA error callback */
-    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+  /* Set the I2S Tx DMA Half transfer complete callback */
+  hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
 
-    /* Enable the Tx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+  /* Set the I2S Tx DMA transfer complete callback */
+  hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
 
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
+  /* Set the DMA error callback */
+  hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
 
-     /* Check if the I2S Tx request is already enabled */ 
-    if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
-    {
-      /* Enable Tx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-    }
+  /* Enable the Tx DMA Stream/Channel */
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
+                                 (uint32_t)hi2s->pTxBuffPtr,
+                                 (uint32_t)&hi2s->Instance->DR,
+                                 hi2s->TxXferSize))
+  {
+    /* Update SPI error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
 
-    /* Process Unlocked */
     __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
+    return HAL_ERROR;
   }
-  else
+
+  /* Check if the I2S is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
   {
-    return HAL_BUSY;
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
   }
+
+  /* Check if the I2S Tx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+  {
+    /* Enable Tx DMA Request */
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+  }
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Receive an amount of data in non-blocking mode with DMA 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Receive an amount of data in non-blocking mode with DMA
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
+  * @param  pData a 16-bit pointer to the Receive data buffer.
+  * @param  Size number of data sample to be sent:
+  * @note   When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+  *         configuration phase, the Size parameter means the number of 16-bit data length
+  *         in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+  *         the Size parameter means the number of 16-bit data length.
+  * @note   The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+  *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 {
-  uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  if((pData == NULL) || (Size == 0))
+  uint32_t tmpreg_cfgr;
+
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if(hi2s->State == HAL_I2S_STATE_READY)
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    __HAL_UNLOCK(hi2s);
+    return HAL_BUSY;
+  }
+
+  /* Set state and reset error code */
+  hi2s->State = HAL_I2S_STATE_BUSY_RX;
+  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+  hi2s->pRxBuffPtr = pData;
+
+  tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+  if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
   {
-    hi2s->pRxBuffPtr = pData;
-    tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
-    if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = Size*2;
-      hi2s->RxXferCount = Size*2;
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-    
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    
-    /* Set the I2S Rx DMA Half transfer complete callback */
-    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-    
-    /* Set the I2S Rx DMA transfer complete callback */
-    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-    
-    /* Set the DMA error callback */
-    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-    
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-    
-    /* Enable the Rx DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
+    hi2s->RxXferSize = (Size << 1U);
+    hi2s->RxXferCount = (Size << 1U);
+  }
+  else
+  {
+    hi2s->RxXferSize = Size;
+    hi2s->RxXferCount = Size;
+  }
 
-     /* Check if the I2S Rx request is already enabled */ 
-    if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
-    {
-      /* Enable Rx DMA Request */  
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-    }
+  /* Set the I2S Rx DMA Half transfer complete callback */
+  hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+  /* Set the I2S Rx DMA transfer complete callback */
+  hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+  /* Set the DMA error callback */
+  hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+  /* Check if Master Receiver mode is selected */
+  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+  {
+    /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+    access to the SPI_SR register. */
+    __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+  }
+
+  /* Enable the Rx DMA Stream/Channel */
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
+                                 hi2s->RxXferSize))
+  {
+    /* Update SPI error code */
+    SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+    hi2s->State = HAL_I2S_STATE_READY;
 
-    /* Process Unlocked */
     __HAL_UNLOCK(hi2s);
+    return HAL_ERROR;
+  }
 
-    return HAL_OK;
+  /* Check if the I2S is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+  {
+    /* Enable I2S peripheral */
+    __HAL_I2S_ENABLE(hi2s);
   }
-  else
+
+  /* Check if the I2S Rx request is already enabled */
+  if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
   {
-    return HAL_BUSY;
+    /* Enable Rx DMA Request */
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
   }
+
+  __HAL_UNLOCK(hi2s);
+  return HAL_OK;
 }
 
 /**
-  * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Pauses the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
-__weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
 {
   /* Process Locked */
   __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+
+  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
   {
     /* Disable the I2S DMA Tx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
   }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
   {
     /* Disable the I2S DMA Rx request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
   }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+  else
   {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Disable the I2S DMA Tx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    }
-    else
-    {
-      /* Disable the I2S DMA Rx request */
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
+    /* nothing to do */
   }
 
   /* Process Unlocked */
   __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Resumes the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
-__weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
 {
   /* Process Locked */
   __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+
+  if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
   {
     /* Enable the I2S DMA Tx request */
-    hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
   }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
   {
     /* Enable the I2S DMA Rx request */
-    hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
   }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
+  else
   {
-    if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
-    {
-      /* Enable the I2S DMA Tx request */
-      hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
-    }
-    else
-    {
-      /* Enable the I2S DMA Rx request */
-      hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
-    }
+    /* nothing to do */
   }
 
   /* If the I2S peripheral is still not enabled, enable it */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+  if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
   {
-    /* Enable I2S peripheral */    
+    /* Enable I2S peripheral */
     __HAL_I2S_ENABLE(hi2s);
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hi2s);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Stops the audio DMA Stream/Channel playing from the Media.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL status
   */
-__weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
 {
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+     when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+     */
+
   /* Disable the I2S Tx/Rx DMA requests */
-  hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
-  hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
+  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
 
-  /* Abort the I2S DMA Stream tx */
-  if(hi2s->hdmatx != NULL)
+  /* Abort the I2S DMA tx Stream/Channel */
+  if (hi2s->hdmatx != NULL)
   {
-    HAL_DMA_Abort(hi2s->hdmatx);
+    /* Disable the I2S DMA tx Stream/Channel */
+    if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+    {
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
   }
-  /* Abort the I2S DMA Stream rx */
-  if(hi2s->hdmarx != NULL)
+
+  /* Abort the I2S DMA rx Stream/Channel */
+  if (hi2s->hdmarx != NULL)
   {
-    HAL_DMA_Abort(hi2s->hdmarx);
+    /* Disable the I2S DMA rx Stream/Channel */
+    if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+    {
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
   }
 
   /* Disable I2S peripheral */
   __HAL_I2S_DISABLE(hi2s);
-  
+
   hi2s->State = HAL_I2S_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
+
+  return errorcode;
 }
 
 /**
   * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
-__weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{  
-  uint32_t tmp1 = 0, tmp2 = 0; 
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+  uint32_t itsource = hi2s->Instance->CR2;
+  uint32_t itflag   = hi2s->Instance->SR;
+
+  /* I2S in mode Receiver ------------------------------------------------*/
+  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
+      (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
+  {
+    I2S_Receive_IT(hi2s);
+    return;
+  }
+
+  /* I2S in mode Tramitter -----------------------------------------------*/
+  if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
+  {
+    I2S_Transmit_IT(hi2s);
+    return;
+  }
 
-    if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+  /* I2S interrupt error -------------------------------------------------*/
+  if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
+  {
+    /* I2S Overrun error interrupt occurred ---------------------------------*/
+    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
     {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
-      /* I2S in mode Receiver ------------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Receive_IT(hi2s);
-      }
+      /* Disable RXNE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
 
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Overrun error interrupt occurred ---------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
-      }
+      /* Set the error code and execute error callback*/
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
     }
 
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+    /* I2S Underrun error interrupt occurred --------------------------------*/
+    if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
     {
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
-      /* I2S in mode Transmitter -----------------------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        I2S_Transmit_IT(hi2s);
-      }
+      /* Disable TXE and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
 
-      tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
-      tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
-      /* I2S Underrun error interrupt occurred --------------------------------*/
-      if((tmp1 != RESET) && (tmp2 != RESET))
-      {
-        __HAL_I2S_CLEAR_UDRFLAG(hi2s);
-        hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+      /* Set the error code and execute error callback*/
+      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
     }
-  }
 
-  /* Call the Error call Back in case of Errors */
-  if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
-  {
-    /* Set the I2S state ready to be able to start again the process */
-    hi2s->State= HAL_I2S_STATE_READY;
+    /* Set the I2S State ready */
+    hi2s->State = HAL_I2S_STATE_READY;
+
+    /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+    hi2s->ErrorCallback(hi2s);
+#else
     HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
   }
 }
 
 /**
-  * @brief Tx Transfer Half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Tx Transfer Half completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief Tx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Tx Transfer completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief Rx Transfer half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Rx Transfer half completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
+            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief Rx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Rx Transfer completed callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_RxCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief I2S error callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  I2S error callbacks
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval None
   */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_I2S_ErrorCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions 
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
   *  @brief   Peripheral State functions
-@verbatim   
+  *
+@verbatim
  ===============================================================================
                       ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -1198,7 +1584,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
 
 /**
   * @brief  Return the I2S state
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval HAL state
   */
@@ -1209,7 +1595,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
 
 /**
   * @brief  Return the I2S error code
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
   * @retval I2S Error Code
   */
@@ -1222,260 +1608,215 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
   */
 
 /**
-  * @brief DMA I2S transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @}
+  */
+
+/** @addtogroup I2S_Private_Functions I2S Private Functions
+  * @{
+  */
+/**
+  * @brief  DMA I2S transmit process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-  {
-    hi2s->TxXferCount = 0;
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
+  {
     /* Disable Tx DMA Request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
 
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->RxXferCount == 0)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY; 
-    }
+    hi2s->TxXferCount = 0U;
+    hi2s->State = HAL_I2S_STATE_READY;
   }
+  /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->TxCpltCallback(hi2s);
+#else
   HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA I2S transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA I2S transmit process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
+  /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->TxHalfCpltCallback(hi2s);
+#else
   HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA I2S receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA I2S receive process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
   {
     /* Disable Rx DMA Request */
-    hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    hi2s->RxXferCount = 0;
-    if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
-    {
-      if(hi2s->TxXferCount == 0)
-      {
-        hi2s->State = HAL_I2S_STATE_READY;
-      }
-    }
-    else
-    {
-      hi2s->State = HAL_I2S_STATE_READY; 
-    }
+    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+    hi2s->RxXferCount = 0U;
+    hi2s->State = HAL_I2S_STATE_READY;
   }
-  HAL_I2S_RxCpltCallback(hi2s); 
+  /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->RxCpltCallback(hi2s);
+#else
+  HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA I2S receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA I2S receive process half complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_RxHalfCpltCallback(hi2s); 
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->RxHalfCpltCallback(hi2s);
+#else
+  HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA I2S communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief  DMA I2S communication error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
 
-  hi2s->TxXferCount = 0;
-  hi2s->RxXferCount = 0;
+  /* Disable Rx and Tx DMA Request */
+  CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+  hi2s->TxXferCount = 0U;
+  hi2s->RxXferCount = 0U;
 
-  hi2s->State= HAL_I2S_STATE_READY;
+  hi2s->State = HAL_I2S_STATE_READY;
 
-  hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+  /* Set the error code and execute error callback*/
+  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+  /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+  hi2s->ErrorCallback(hi2s);
+#else
   HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @retval HAL status
+  * @retval None
   */
-static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
+static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
 {
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    /* Transmit data */
-    hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-
-    hi2s->TxXferCount--;	
-    
-    if(hi2s->TxXferCount == 0)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-      
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-      HAL_I2S_TxCpltCallback(hi2s);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-    }
+  /* Transmit data */
+  hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+  hi2s->pTxBuffPtr++;
+  hi2s->TxXferCount--;
 
-    return HAL_OK;
-  }
-  
-  else
+  if (hi2s->TxXferCount == 0U)
   {
-    return HAL_BUSY;
+    /* Disable TXE and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+    hi2s->State = HAL_I2S_STATE_READY;
+    /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+    hi2s->TxCpltCallback(hi2s);
+#else
+    HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
   }
 }
 
 /**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @retval HAL status
+  * @retval None
   */
-static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
+static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
 {
-  if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Process Locked */
-    __HAL_LOCK(hi2s);
-
-    /* Receive data */
-    (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-
-    hi2s->RxXferCount--;
-
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-
-    if(hi2s->RxXferCount == 0)
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
-
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
+  /* Receive data */
+  (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+  hi2s->pRxBuffPtr++;
+  hi2s->RxXferCount--;
 
-      HAL_I2S_RxCpltCallback(hi2s);
-    }
-    else
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2s);
-    }
-
-    return HAL_OK; 
-  }
-  else
+  if (hi2s->RxXferCount == 0U)
   {
-    return HAL_BUSY; 
-  } 
+    /* Disable RXNE and ERR interrupt */
+    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+    hi2s->State = HAL_I2S_STATE_READY;
+    /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+    hi2s->RxCpltCallback(hi2s);
+#else
+    HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+  }
 }
 
 /**
-  * @brief This function handles I2S Communication Timeout.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
+  * @brief  This function handles I2S Communication Timeout.
+  * @param  hi2s pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param Flag: Flag checked
-  * @param Status: Value of the flag expected
-  * @param Timeout: Duration of the timeout
+  * @param  Flag Flag checked
+  * @param  State Value of the flag expected
+  * @param  Timeout Duration of the timeout
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+                                                       uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-  
+  uint32_t tickstart;
+
   /* Get tick */
   tickstart = HAL_GetTick();
-  
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
 
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
+  /* Wait until flag is set to status*/
+  while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
   {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if(Timeout != HAL_MAX_DELAY)
+      if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
+        /* Set the I2S State ready */
+        hi2s->State = HAL_I2S_STATE_READY;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2s);
 
-          return HAL_TIMEOUT;
-        }
+        return HAL_TIMEOUT;
       }
     }
   }
@@ -1485,8 +1826,7 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
 /**
   * @}
   */
-  
-#endif /* HAL_I2S_MODULE_ENABLED */
+
 /**
   * @}
   */
@@ -1495,4 +1835,6 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
   * @}
   */
 
+#endif /* HAL_I2S_MODULE_ENABLED */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c
index d919ac01..c31e6978 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_irda.c
@@ -2,28 +2,26 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   IRDA HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the IrDA SIR ENDEC block (IrDA):
-  *           + Initialization and de-initialization methods
-  *           + IO operation methods
-  *           + Peripheral Control methods
-  *
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
   [..]
     The IRDA HAL driver can be used as follows:
-    
-    (#) Declare a IRDA_HandleTypeDef handle structure.
+
+    (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
         (##) Enable the USARTx interface clock.
         (##) IRDA pins configuration:
             (+++) Enable the clock for the IRDA GPIOs.
-            (+++) Configure these IRDA pins as alternate function pull-up.
+            (+++) Configure IRDA pins as alternate function pull-up.
         (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
              and HAL_IRDA_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
@@ -32,97 +30,173 @@
              and HAL_IRDA_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx stream.
             (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx stream.
             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+            (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
+                  (used for last byte sending completion detection in DMA non circular mode)
 
-    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler 
+    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
         and Mode(Receiver/Transmitter) in the hirda Init structure.
 
     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-            by calling the customized HAL_IRDA_MspInit() API.
-    -@@- The specific IRDA interrupts (Transmission complete interrupt, 
-        RXNE interrupt and Error Interrupts) will be managed using the macros
-        __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-        
+             by calling the customized HAL_IRDA_MspInit() API.
+
+         -@@- The specific IRDA interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
     (#) Three operation modes are available within this driver :
-             
+
     *** Polling mode IO operation ***
     =================================
-    [..]    
-      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() 
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-       
-    *** Interrupt mode IO operation ***    
+
+    *** Interrupt mode IO operation ***
     ===================================
-    [..]    
-      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() 
-      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
+    [..]
+      (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
+      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() 
-      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
-           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
-      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
+      (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
+      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
 
-    *** DMA mode IO operation ***    
+    *** DMA mode IO operation ***
     =============================
     [..]
-      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() 
-      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
+      (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+      (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
+      (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() 
-      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
-           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
-      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
-           add his own code by customization of function pointer HAL_IRDA_ErrorCallback    
+      (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+      (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
+      (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
+           add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+      (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+           add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+      (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
+      (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
+      (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
 
     *** IRDA HAL driver macros list ***
     ===================================
     [..]
       Below the list of most used macros in IRDA HAL driver.
-       
-     (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral 
-     (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral     
-     (+) __HAL_IRDA_GET_FLAG : Checks whether the specified IRDA flag is set or not
-     (+) __HAL_IRDA_CLEAR_FLAG : Clears the specified IRDA pending flag
-     (+) __HAL_IRDA_ENABLE_IT: Enables the specified IRDA interrupt
-     (+) __HAL_IRDA_DISABLE_IT: Disables the specified IRDA interrupt
-      
+
+       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
+       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
+       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
+       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
+       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
+
+    [..]
      (@) You can refer to the IRDA HAL driver header file for more useful macros
 
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+      The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+    [..]
+      Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
+      Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+       (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+       (+) TxCpltCallback            : Tx Complete Callback.
+       (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+       (+) RxCpltCallback            : Rx Complete Callback.
+       (+) ErrorCallback             : Error Callback.
+       (+) AbortCpltCallback         : Abort Complete Callback.
+       (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+       (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+       (+) MspInitCallback           : IRDA MspInit.
+       (+) MspDeInitCallback         : IRDA MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+    [..]
+      Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function.
+      @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+      and the Callback ID.
+      This function allows to reset following callbacks:
+       (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+       (+) TxCpltCallback            : Tx Complete Callback.
+       (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+       (+) RxCpltCallback            : Rx Complete Callback.
+       (+) ErrorCallback             : Error Callback.
+       (+) AbortCpltCallback         : Abort Complete Callback.
+       (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+       (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+       (+) MspInitCallback           : IRDA MspInit.
+       (+) MspDeInitCallback         : IRDA MspDeInit.
+
+    [..]
+      By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+      all callbacks are set to the corresponding weak (surcharged) functions:
+      examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+      Exception done for MspInit and MspDeInit functions that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
+      and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+      Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+      Exception done MspInit/MspDeInit that can be registered/unregistered
+      in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+      MspInit/DeInit callbacks can be used during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
+      or @ref HAL_IRDA_Init() function.
+
+    [..]
+      When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available
+      and weak (surcharged) callbacks are used.
+
   @endverbatim
+     [..]
+       (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           the possible IRDA frame formats are as listed in the following table:
+    +-------------------------------------------------------------+
+    |   M bit |  PCE bit  |            IRDA frame                 |
+    |---------------------|---------------------------------------|
+    |    0    |    0      |    | SB | 8 bit data | 1 STB |        |
+    |---------|-----------|---------------------------------------|
+    |    0    |    1      |    | SB | 7 bit data | PB | 1 STB |   |
+    |---------|-----------|---------------------------------------|
+    |    1    |    0      |    | SB | 9 bit data | 1 STB |        |
+    |---------|-----------|---------------------------------------|
+    |    1    |    1      |    | SB | 8 bit data | PB | 1 STB |   |
+    +-------------------------------------------------------------+
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -140,20 +214,17 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Constants
-  * @{
-  */
-#define IRDA_TIMEOUT_VALUE  22000
-/**
-  * @}
-  */
+/* Private constants ---------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /** @addtogroup IRDA_Private_Functions
   * @{
   */
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
@@ -162,36 +233,44 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
 /**
   * @}
   */
+
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
   * @{
   */
 
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-@verbatim 
+@verbatim
 
-===============================================================================
+  ==============================================================================
             ##### Initialization and Configuration functions #####
- ===============================================================================  
+  ==============================================================================
     [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
-    in IrDA mode.
-      (+) For the asynchronous mode only these parameters can be configured: 
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous IrDA mode.
+      (+) For the asynchronous mode only these parameters can be configured:
         (++) BaudRate
-        (++) WordLength 
+        (++) WordLength
         (++) Parity: If the parity is enabled, then the MSB bit of the data written
              in the data register is transmitted but is changed by the parity bit.
              Depending on the frame length defined by the M bit (8-bits or 9-bits),
              please refer to Reference manual for possible IRDA frame formats.
         (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
              not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
-             specification specifies a minimum of 10 ms delay between transmission and 
+             specification specifies a minimum of 10 ms delay between transmission and
              reception (IrDA is a half duplex protocol).
         (++) Mode: Receiver/transmitter modes
         (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
@@ -206,92 +285,116 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda,
 /**
   * @brief  Initializes the IRDA mode according to the specified
   *         parameters in the IRDA_InitTypeDef and create the associated handle.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
 {
   /* Check the IRDA handle allocation */
-  if(hirda == NULL)
+  if (hirda == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the IRDA instance parameters */
   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
   /* Check the IRDA mode parameter in the IRDA handle */
-  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); 
-  
-  if(hirda->State == HAL_IRDA_STATE_RESET)
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
+
+  if (hirda->gState == HAL_IRDA_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hirda->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+    IRDA_InitCallbacksToDefault(hirda);
+
+    if (hirda->MspInitCallback == NULL)
+    {
+      hirda->MspInitCallback = HAL_IRDA_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hirda->MspInitCallback(hirda);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
   }
-  
-  hirda->State = HAL_IRDA_STATE_BUSY;
-  
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
   /* Disable the IRDA peripheral */
   __HAL_IRDA_DISABLE(hirda);
-  
+
   /* Set the IRDA communication parameters */
   IRDA_SetConfig(hirda);
-  
-  /* In IrDA mode, the following bits must be kept cleared: 
-     - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-     - SCEN and HDSEL bits in the USART_CR3 register.*/
-  hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
-  hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
-  
+
+  /* In IrDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
+  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+
   /* Enable the IRDA peripheral */
   __HAL_IRDA_ENABLE(hirda);
-  
+
   /* Set the prescaler */
   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-  
+
   /* Configure the IrDA mode */
   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
-  
+
   /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-  hirda->Instance->CR3 |= USART_CR3_IREN;
-  
+  SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
+
   /* Initialize the IRDA state*/
   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-  hirda->State= HAL_IRDA_STATE_READY;
-  
+  hirda->gState = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the IRDA peripheral 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  DeInitializes the IRDA peripheral
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
 {
   /* Check the IRDA handle allocation */
-  if(hirda == NULL)
+  if (hirda == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance)); 
-  
-  hirda->State = HAL_IRDA_STATE_BUSY;
-  
+  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+
+  hirda->gState = HAL_IRDA_STATE_BUSY;
+
   /* Disable the Peripheral */
   __HAL_IRDA_DISABLE(hirda);
-  
+
+  /* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+  if (hirda->MspDeInitCallback == NULL)
+  {
+    hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+  }
   /* DeInit the low level hardware */
+  hirda->MspDeInitCallback(hirda);
+#else
   HAL_IRDA_MspDeInit(hirda);
-  
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
 
-  hirda->State = HAL_IRDA_STATE_RESET; 
+  hirda->gState = HAL_IRDA_STATE_RESET;
+  hirda->RxState = HAL_IRDA_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(hirda);
@@ -301,66 +404,310 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
 
 /**
   * @brief  IRDA MSP Init.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_MspInit could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspInit can be implemented in the user file
+   */
 }
 
 /**
   * @brief  IRDA MSP DeInit.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_IRDA_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User IRDA Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hirda irda handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hirda);
+
+  if (hirda->gState == HAL_IRDA_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+        hirda->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_TX_COMPLETE_CB_ID :
+        hirda->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+        hirda->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_RX_COMPLETE_CB_ID :
+        hirda->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ERROR_CB_ID :
+        hirda->ErrorCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+        hirda->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hirda->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hirda->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hirda->gState == HAL_IRDA_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = pCallback;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hirda);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an IRDA callback
+  *         IRDA callback is redirected to the weak predefined callback
+  * @param  hirda irda handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_MspDeInit could be implemented in the user file
-   */ 
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hirda);
+
+  if (HAL_IRDA_STATE_READY == hirda->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+        hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_IRDA_TX_COMPLETE_CB_ID :
+        hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+        hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_IRDA_RX_COMPLETE_CB_ID :
+        hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_IRDA_ERROR_CB_ID :
+        hirda->ErrorCallback = HAL_IRDA_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+        hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = HAL_IRDA_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_IRDA_STATE_RESET == hirda->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_IRDA_MSPINIT_CB_ID :
+        hirda->MspInitCallback = HAL_IRDA_MspInit;
+        break;
+
+      case HAL_IRDA_MSPDEINIT_CB_ID :
+        hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hirda);
+
+  return status;
 }
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions 
-  *  @brief   IRDA Transmit/Receive functions 
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+  *  @brief   IRDA Transmit and Receive functions
   *
-@verbatim   
- ===============================================================================
+@verbatim
+  ==============================================================================
                       ##### IO operation functions #####
- ===============================================================================  
-    This subsection provides a set of functions allowing to manage the IRDA data transfers.
+  ==============================================================================
     [..]
+    This subsection provides a set of functions allowing to manage the IRDA data transfers.
     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
-    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
     While receiving data, transmission should be avoided as the data to be transmitted
     could be corrupted.
 
     (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode: The communication is performed using Interrupts 
-           or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the 
-           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when 
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, these API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
-           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks 
-           will be executed respectively at the end of the transmit or Receive process
+           The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the Transmit or Receive process
            The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
 
-    (#) Blocking mode API's are :
+    (#) Blocking mode APIs are :
         (++) HAL_IRDA_Transmit()
-        (++) HAL_IRDA_Receive() 
-        
+        (++) HAL_IRDA_Receive()
+
     (#) Non Blocking mode APIs with Interrupt are :
         (++) HAL_IRDA_Transmit_IT()
         (++) HAL_IRDA_Receive_IT()
@@ -369,173 +716,197 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
     (#) Non Blocking mode functions with DMA are :
         (++) HAL_IRDA_Transmit_DMA()
         (++) HAL_IRDA_Receive_DMA()
+        (++) HAL_IRDA_DMAPause()
+        (++) HAL_IRDA_DMAResume()
+        (++) HAL_IRDA_DMAStop()
 
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+    (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+        (++) HAL_IRDA_TxHalfCpltCallback()
         (++) HAL_IRDA_TxCpltCallback()
+        (++) HAL_IRDA_RxHalfCpltCallback()
         (++) HAL_IRDA_RxCpltCallback()
         (++) HAL_IRDA_ErrorCallback()
 
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_IRDA_Abort()
+        (+) HAL_IRDA_AbortTransmit()
+        (+) HAL_IRDA_AbortReceive()
+        (+) HAL_IRDA_Abort_IT()
+        (+) HAL_IRDA_AbortTransmit_IT()
+        (+) HAL_IRDA_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_IRDA_AbortCpltCallback()
+        (+) HAL_IRDA_AbortTransmitCpltCallback()
+        (+) HAL_IRDA_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+        (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+            to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+            Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+            and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+            If user wants to abort it, Abort services should be called by user.
+        (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+            This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+            Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Specify timeout value  
+  * @brief Sends an amount of data in blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Specify timeout value.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State; 
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-   
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
-    while(hirda->TxXferCount > 0)
+    while (hirda->TxXferCount > 0U)
     {
       hirda->TxXferCount--;
-      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+      if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pData;
+        tmp = (uint16_t *) pData;
         hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        if (hirda->Init.Parity == IRDA_PARITY_NONE)
         {
-          pData +=2;
+          pData += 2U;
         }
         else
         {
-          pData +=1;
+          pData += 1U;
         }
-      } 
+      }
       else
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
         hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
       }
     }
-    
-    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-    
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-    else
+
+    if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     {
-      hirda->State = HAL_IRDA_STATE_READY;
+      return HAL_TIMEOUT;
     }
-    
+
+    /* At end of Tx process, restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receive an amount of data in blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Specify timeout value    
+  * @brief Receive an amount of data in blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Specify timeout value
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{ 
-  uint16_t* tmp;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State; 
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+{
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
     hirda->RxXferSize = Size;
     hirda->RxXferCount = Size;
+
     /* Check the remain data to be received */
-    while(hirda->RxXferCount > 0)
+    while (hirda->RxXferCount > 0U)
     {
       hirda->RxXferCount--;
-      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+
+      if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pData ;
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        tmp = (uint16_t *) pData ;
+        if (hirda->Init.Parity == IRDA_PARITY_NONE)
         {
           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
-           pData +=2;
+          pData += 2U;
         }
         else
         {
           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
-          pData +=1;
+          pData += 1U;
         }
-      } 
+      }
       else
       {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
+        if (hirda->Init.Parity == IRDA_PARITY_NONE)
         {
           *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
         }
@@ -545,567 +916,1117 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
         }
       }
     }
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_READY;
-    }
-    
+
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Send an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief Send an amount of data in non blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
 {
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State;   
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pTxBuffPtr = pData;
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    
-   /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
 
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hirda);
 
     /* Enable the IRDA Transmit Data Register Empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
-    
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
+  * @brief Receive an amount of data in non blocking mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
 {
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State;   
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pRxBuffPtr = pData;
     hirda->RxXferSize = Size;
     hirda->RxXferCount = Size;
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-    
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
 
-    /* Enable the IRDA Data Register not empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); 
+    /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
 
-    /* Enable the IRDA Parity Error Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+    /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
 
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-    
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Sends an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief Send an amount of data in DMA mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the sent data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State;   
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
+
+  /* Check that a Tx process is not already ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pTxBuffPtr = pData;
     hirda->TxXferSize = Size;
     hirda->TxXferCount = Size;
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
     /* Set the IRDA DMA transfer complete callback */
     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-    
+
     /* Set the IRDA DMA half transfer complete callback */
     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-    
+
     /* Set the DMA error callback */
     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-    
-    /* Enable the IRDA transmit DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
-    
+
+    /* Set the DMA abort callback */
+    hirda->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the IRDA transmit DMA stream */
+    tmp = (uint32_t *)&pData;
+    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size);
+
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    hirda->Instance->CR3 |= USART_CR3_DMAT;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
+  * @brief Receives an amount of data in DMA mode.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of u16. In this case, Size must reflect the number
+  *        of u16 available through pData.
+  * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *              the configuration information for the specified IRDA module.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
   * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State; 
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
+
+  /* Check that a Rx process is not already ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(hirda);
-    
+
     hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;   
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE; 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-    
+    hirda->RxXferSize = Size;
+
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+    hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
     /* Set the IRDA DMA transfer complete callback */
     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-    
+
     /* Set the IRDA DMA half transfer complete callback */
     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-    
+
     /* Set the DMA error callback */
     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-    
-    /* Enable the DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    hirda->Instance->CR3 |= USART_CR3_DMAR;
-    
+
+    /* Set the DMA abort callback */
+    hirda->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA stream */
+    tmp = (uint32_t *)&pData;
+    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t *)tmp, Size);
+
+    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+    __HAL_IRDA_CLEAR_OREFLAG(hirda);
+
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
-    
+
+    /* Enable the IRDA Parity Error Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+    in the USART CR3 register */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
-    
+
 /**
   * @brief Pauses the DMA Transfer.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
 {
+  uint32_t dmarequest = 0x00U;
+
   /* Process Locked */
   __HAL_LOCK(hirda);
-  
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
-  {
-    /* Disable the UART DMA Tx request */
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-  }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Disable the UART DMA Rx request */
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-  else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
   {
-    /* Disable the UART DMA Tx & Rx requests */
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-    hirda->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+    /* Disable the IRDA DMA Tx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
   }
-  else
+
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
   {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-  
-    return HAL_ERROR; 
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the IRDA DMA Rx request */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hirda);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief Resumes the DMA Transfer.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
 {
   /* Process Locked */
   __HAL_LOCK(hirda);
-  
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
   {
-    /* Enable the UART DMA Tx request */
-    hirda->Instance->CR3 |= USART_CR3_DMAT;
+    /* Enable the IRDA DMA Tx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
   }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer */
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    /* Enable the UART DMA Rx request */
-    hirda->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
   {
     /* Clear the Overrun flag before resuming the Rx transfer */
     __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    /* Enable the UART DMA Tx & Rx request */
-    hirda->Instance->CR3 |= USART_CR3_DMAT;
-    hirda->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-  
-    return HAL_ERROR; 
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the IRDA DMA Rx request */
+    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
   }
 
   /* Process Unlocked */
   __HAL_UNLOCK(hirda);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief Stops the DMA Transfer.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+     to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-
-  /* Disable the UART Tx/Rx DMA requests */
-  hirda->Instance->CR3 &= ~USART_CR3_DMAT;
-  hirda->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  /* Abort the UART DMA tx Stream */
-  if(hirda->hdmatx != NULL)
+     and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+  */
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
   {
-    HAL_DMA_Abort(hirda->hdmatx);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel */
+    if (hirda->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
+    IRDA_EndTxTransfer(hirda);
   }
-  /* Abort the UART DMA rx Stream */
-  if(hirda->hdmarx != NULL)
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
   {
-    HAL_DMA_Abort(hirda->hdmarx);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel */
+    if (hirda->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+    IRDA_EndRxTransfer(hirda);
   }
-  
-  hirda->State = HAL_IRDA_STATE_READY;
 
   return HAL_OK;
 }
 
 /**
-  * @brief  This function handles IRDA interrupt request.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
 {
-  uint32_t  tmp1 = 0, tmp2 =0;
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
-  /* IRDA parity error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_PEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_PE; 
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA frame error interrupt occurred --------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_FEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_FE; 
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA noise error interrupt occurred --------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_NEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_NE; 
+
+  /* Reset Tx and Rx transfer counters */
+  hirda->TxXferCount = 0x00U;
+  hirda->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Restore hirda->RxState and hirda->gState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmatx);
+    }
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA Over-Run interrupt occurred -----------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; 
+
+  /* Reset Tx transfer counter */
+  hirda->TxXferCount = 0x00U;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hirda->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hirda->RxXferCount = 0x00U;
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (hirda->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+    {
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (hirda->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+    {
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+    }
+    else
+    {
+      hirda->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at IRDA level */
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* IRDA Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        hirda->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* IRDA Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        hirda->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (AbortCplt == 0x01U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hirda->TxXferCount = 0x00U;
+    hirda->RxXferCount = 0x00U;
+
+    /* Reset ErrorCode */
+    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+    /* Restore hirda->gState and hirda->RxState to Ready */
+    hirda->gState  = HAL_IRDA_STATE_READY;
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    hirda->AbortCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
   }
 
-  /* Call the Error call Back in case of Errors */
-  if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable IRDA Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the IRDA DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmatx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+        hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hirda->TxXferCount = 0x00U;
+
+      /* Restore hirda->gState to Ready */
+      hirda->gState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      hirda->AbortTransmitCpltCallback(hirda);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hirda->TxXferCount = 0x00U;
+
+    /* Restore hirda->gState to Ready */
+    hirda->gState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    hirda->AbortTransmitCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hirda IRDA handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the IRDA DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (hirda->hdmarx != NULL)
+    {
+      /* Set the IRDA DMA Abort callback :
+         will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+      hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+        hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hirda->RxXferCount = 0x00U;
+
+      /* Restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      hirda->AbortReceiveCpltCallback(hirda);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+    }
+  }
+  else
   {
-    /* Set the IRDA state ready to be able to start again the process */
-    hirda->State = HAL_IRDA_STATE_READY;
-    HAL_IRDA_ErrorCallback(hirda);
+    /* Reset Rx transfer counter */
+    hirda->RxXferCount = 0x00U;
+
+    /* Restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    hirda->AbortReceiveCpltCallback(hirda);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
   }
 
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
-  /* IRDA in mode Receiver ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    IRDA_Receive_IT(hirda);
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles IRDA interrupt request.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
+{
+  uint32_t isrflags   = READ_REG(hirda->Instance->SR);
+  uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
+  uint32_t cr3its     = READ_REG(hirda->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if (errorflags == RESET)
+  {
+    /* IRDA in mode Receiver -----------------------------------------------*/
+    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      IRDA_Receive_IT(hirda);
+      return;
+    }
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
+
+  /* If some errors occur */
+  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* IRDA parity error interrupt occurred -------------------------------*/
+    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+    }
+
+    /* IRDA noise error interrupt occurred --------------------------------*/
+    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+    }
+
+    /* IRDA frame error interrupt occurred --------------------------------*/
+    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+    }
+
+    /* IRDA Over-Run interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+    }
+    /* Call IRDA Error Call back function if need be -----------------------*/
+    if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+    {
+      /* IRDA in mode Receiver ---------------------------------------------*/
+      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        IRDA_Receive_IT(hirda);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+      if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the IRDA state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        IRDA_EndRxTransfer(hirda);
+
+        /* Disable the IRDA DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the IRDA DMA Rx channel */
+          if (hirda->hdmarx != NULL)
+          {
+            /* Set the IRDA DMA Abort callback :
+            will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+            hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+            }
+          }
+          else
+          {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+            /* Call registered user error callback */
+            hirda->ErrorCallback(hirda);
+#else
+            /* Call legacy weak user error callback */
+            HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+          }
+        }
+        else
+        {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+          /* Call registered user error callback */
+          hirda->ErrorCallback(hirda);
+#else
+          /* Call legacy weak user error callback */
+          HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+        /* Call registered user error callback */
+        hirda->ErrorCallback(hirda);
+#else
+        /* Call legacy weak user error callback */
+        HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+
+        hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
   /* IRDA in mode Transmitter ------------------------------------------------*/
-  if((tmp1 != RESET) &&(tmp2 != RESET))
+  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     IRDA_Transmit_IT(hirda);
+    return;
   }
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
-  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+
+  /* IRDA in mode Transmitter end --------------------------------------------*/
+  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     IRDA_EndTransmit_IT(hirda);
-  }   
+    return;
+  }
 }
 
 /**
-  * @brief  Tx Transfer complete callbacks.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Tx Transfer complete callback.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_TxCpltCallback could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+   */
 }
 
 /**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_IRDA_TxHalfCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
    */
 }
 
 /**
-  * @brief  Rx Transfer complete callbacks.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Rx Transfer complete callback.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_RxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxCpltCallback can be implemented in the user file.
    */
 }
 
 /**
-  * @brief  Rx Half Transfer complete callbacks.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Rx Half Transfer complete callback.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_RxHalfCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
    */
 }
 
 /**
-  * @brief IRDA error callbacks.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  IRDA error callback.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IRDA_ErrorCallback could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Transmit Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  IRDA Abort Receive Complete callback.
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA module.
+  * @retval None
+  */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hirda);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   IRDA State and Errors functions 
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   IRDA State and Errors functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                   ##### Peripheral State and Errors functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection provides a set of functions allowing to return the State of IrDA 
+    This subsection provides a set of functions allowing to return the State of IrDA
     communication process and also return Peripheral Errors occurred during communication process
      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
-     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication. 
-     
+     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Returns the IRDA state.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
+  * @brief  Return the IRDA state.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA.
   * @retval HAL state
   */
 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
 {
-  return hirda->State;
+  uint32_t temp1 = 0x00U, temp2 = 0x00U;
+  temp1 = hirda->gState;
+  temp2 = hirda->RxState;
+
+  return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
 }
 
 /**
-  * @brief  Return the IARDA error code
-  * @param  hirda : pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Return the IRDA error code
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *              the configuration information for the specified IRDA.
   * @retval IRDA Error Code
   */
@@ -1117,216 +2038,449 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
 /**
   * @}
   */
-  
+
+/**
+  * @}
+  */
+
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+  * @{
+  */
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  hirda IRDA handle.
+  * @retval none
+  */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+  /* Init the IRDA Callback settings */
+  hirda->TxHalfCpltCallback        = HAL_IRDA_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  hirda->TxCpltCallback            = HAL_IRDA_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  hirda->RxHalfCpltCallback        = HAL_IRDA_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  hirda->RxCpltCallback            = HAL_IRDA_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  hirda->ErrorCallback             = HAL_IRDA_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  hirda->AbortCpltCallback         = HAL_IRDA_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  hirda->AbortReceiveCpltCallback  = HAL_IRDA_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
 /**
-  * @brief  DMA IRDA transmit process complete callback. 
-  * @param  hdma : DMA handle
+  * @brief  DMA IRDA transmit process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA.
   * @retval None
   */
 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    hirda->TxXferCount = 0;
+    hirda->TxXferCount = 0U;
 
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
        in the IRDA CR3 register */
-    hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
 
-    /* Enable the IRDA Transmit Complete Interrupt */    
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+    /* Enable the IRDA Transmit Complete Interrupt */
+    SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
   }
   /* DMA Circular mode */
   else
   {
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx complete callback */
+    hirda->TxCpltCallback(hirda);
+#else
+    /* Call legacy weak Tx complete callback */
     HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
   }
 }
 
 /**
-  * @brief DMA IRDA receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief DMA IRDA receive process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA.
   * @retval None
   */
 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_IRDA_TxHalfCpltCallback(hirda); 
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx Half complete callback */
+  hirda->TxHalfCpltCallback(hirda);
+#else
+  /* Call legacy weak Tx complete callback */
+  HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
 }
 
 /**
-  * @brief  DMA IRDA receive process complete callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA IRDA receive process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA.
   * @retval None
   */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
   /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    hirda->RxXferCount = 0;
+    hirda->RxXferCount = 0U;
 
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
        in the IRDA CR3 register */
-    hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
 
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_READY;
-    }
+    /* At end of Rx process, restore hirda->RxState to Ready */
+    hirda->RxState = HAL_IRDA_STATE_READY;
   }
 
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx complete callback */
+  hirda->RxCpltCallback(hirda);
+#else
+  /* Call legacy weak Rx complete callback */
   HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA IRDA receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief DMA IRDA receive process half complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA.
   * @retval None
   */
 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_IRDA_RxHalfCpltCallback(hirda); 
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx Half complete callback*/
+  hirda->RxHalfCpltCallback(hirda);
+#else
+  /* Call legacy weak Rx Half complete callback */
+  HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
 }
 
 /**
-  * @brief  DMA IRDA communication error callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA IRDA communication error callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA.
   * @retval None
   */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)   
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
 {
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  hirda->RxXferCount = 0;
-  hirda->TxXferCount = 0;
-  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; 
-  hirda->State= HAL_IRDA_STATE_READY;
-  
+  uint32_t dmarequest = 0x00U;
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Stop IRDA DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+  if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+  {
+    hirda->TxXferCount = 0U;
+    IRDA_EndTxTransfer(hirda);
+  }
+
+  /* Stop IRDA DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+  if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+  {
+    hirda->RxXferCount = 0U;
+    IRDA_EndRxTransfer(hirda);
+  }
+
+  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hirda->ErrorCallback(hirda);
+#else
+  /* Call legacy weak user error callback */
   HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
 }
 
 /**
   * @brief  This function handles IRDA Communication Timeout.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  Flag: specifies the IRDA flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+  *                the configuration information for the specified IRDA.
+  * @param  Flag specifies the IRDA flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
   /* Wait until flag is set */
-  if(Status == RESET)
-  {    
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+  while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-        
-          hirda->State= HAL_IRDA_STATE_READY;
-        
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
-        
-          return HAL_TIMEOUT;
-        }
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+        hirda->gState  = HAL_IRDA_STATE_READY;
+        hirda->RxState = HAL_IRDA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hirda);
+
+        return HAL_TIMEOUT;
       }
     }
   }
-  else
+  return HAL_OK;
+}
+
+/**
+  * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+  * @param  hirda IRDA handle.
+  * @retval None
+  */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
+  * @param  hirda IRDA handle.
+  * @retval None
+  */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+/**
+  * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  hirda->RxXferCount = 0x00U;
+  hirda->TxXferCount = 0x00U;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hirda->ErrorCallback(hirda);
+#else
+  /* Call legacy weak user error callback */
+  HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hirda->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hirda->hdmarx != NULL)
   {
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
+    if (hirda->hdmarx->XferAbortCallback != NULL)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-          hirda->State= HAL_IRDA_STATE_READY;
-        
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
-        
-          return HAL_TIMEOUT;
-        }
-      }
+      return;
     }
   }
-  return HAL_OK;      
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0x00U;
+  hirda->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hirda->AbortCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
 }
 
- /**
-  * @brief  Send an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hirda->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (hirda->hdmatx != NULL)
+  {
+    if (hirda->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hirda->TxXferCount = 0x00U;
+  hirda->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+  /* Restore hirda->gState and hirda->RxState to Ready */
+  hirda->gState  = HAL_IRDA_STATE_READY;
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hirda->AbortCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
   */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hirda->TxXferCount = 0x00U;
+
+  /* Restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  hirda->AbortTransmitCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
+  *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  hirda->RxXferCount = 0x00U;
+
+  /* Restore hirda->RxState to Ready */
+  hirda->RxState = HAL_IRDA_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  hirda->AbortReceiveCpltCallback(hirda);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+}
+
+/**
+ * @brief  Send an amount of data in non blocking mode.
+ * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
+ *                the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
 {
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
+  uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
   {
-    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+    if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) hirda->pTxBuffPtr;
+      tmp = (uint16_t *) hirda->pTxBuffPtr;
       hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      if (hirda->Init.Parity == IRDA_PARITY_NONE)
       {
-        hirda->pTxBuffPtr += 2;
+        hirda->pTxBuffPtr += 2U;
       }
       else
       {
-        hirda->pTxBuffPtr += 1;
+        hirda->pTxBuffPtr += 1U;
       }
-    } 
+    }
     else
     {
       hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
     }
-    
-    if(--hirda->TxXferCount == 0)
+
+    if (--hirda->TxXferCount == 0U)
     {
       /* Disable the IRDA Transmit Data Register Empty Interrupt */
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-      
-      /* Enable the IRDA Transmit Complete Interrupt */    
-      __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the IRDA Transmit Complete Interrupt */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
     }
 
     return HAL_OK;
@@ -1339,155 +2493,155 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
 
 /**
   * @brief  Wraps up transmission in non blocking mode.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
 {
-  /* Disable the IRDA Transmit Complete Interrupt */    
-  __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-  {
-    hirda->State = HAL_IRDA_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+  /* Disable the IRDA Transmit Complete Interrupt */
+  CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
 
-    hirda->State = HAL_IRDA_STATE_READY;
-  }
-  
+  /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+  /* Tx process is ended, restore hirda->gState to Ready */
+  hirda->gState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx complete callback */
+  hirda->TxCpltCallback(hirda);
+#else
+  /* Call legacy weak Tx complete callback */
   HAL_IRDA_TxCpltCallback(hirda);
-  
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Receives an amount of data in non blocking mode.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
 {
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hirda->State;  
-  if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
+  uint16_t *tmp;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
   {
-    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
+    uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
+    if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) hirda->pRxBuffPtr;
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      tmp = (uint16_t *) hirda->pRxBuffPtr;
+      if (hirda->Init.Parity == IRDA_PARITY_NONE)
       {
-        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
-        hirda->pRxBuffPtr += 2;
+        *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
+        hirda->pRxBuffPtr += 2U;
       }
       else
       {
-        *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
-        hirda->pRxBuffPtr += 1;
+        *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
+        hirda->pRxBuffPtr += 1U;
       }
-    } 
+    }
     else
     {
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
+      if (hirda->Init.Parity == IRDA_PARITY_NONE)
       {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
+        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
       }
       else
       {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
+        *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
       }
     }
-    
-    if(--hirda->RxXferCount == 0)
+
+    if (--hirda->RxXferCount == 0U)
     {
+      /* Disable the IRDA Data Register not empty Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
 
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-      
-      if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-      {
-        hirda->State = HAL_IRDA_STATE_BUSY_TX;
-      }
-      else
-      {
-        /* Disable the IRDA Parity Error Interrupt */
-        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-        
-        /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-        
-        hirda->State = HAL_IRDA_STATE_READY;
-      }
+      /* Disable the IRDA Parity Error Interrupt */
+      CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+      /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+      CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore hirda->RxState to Ready */
+      hirda->RxState = HAL_IRDA_STATE_READY;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx complete callback */
+      hirda->RxCpltCallback(hirda);
+#else
+      /* Call legacy weak Rx complete callback */
       HAL_IRDA_RxCpltCallback(hirda);
-      
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
       return HAL_OK;
     }
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Configures the IRDA peripheral. 
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
+  * @brief  Configures the IRDA peripheral.
+  * @param  hirda  Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
 {
-  uint32_t tmpreg = 0x00;
-  
+  uint32_t pclk;
+
   /* Check the parameters */
   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));  
+  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
   assert_param(IS_IRDA_MODE(hirda->Init.Mode));
-  
-  /*-------------------------- IRDA CR2 Configuration ------------------------*/
+  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
+
+  /*-------------------------- USART CR2 Configuration ------------------------*/
   /* Clear STOP[13:12] bits */
-  hirda->Instance->CR2 &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-  
+  CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
+
   /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = hirda->Instance->CR1;
-  
   /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-    USART_CR1_RE));
-  
-  /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to hirda->Init.WordLength value 
+  CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE));
+
+  /* Configure the USART Word Length, Parity and mode:
+     Set the M bits according to hirda->Init.WordLength value
      Set PCE and PS bits according to hirda->Init.Parity value
      Set TE and RE bits according to hirda->Init.Mode value */
-  tmpreg |= (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode;
-  
   /* Write to USART CR1 */
-  hirda->Instance->CR1 = (uint32_t)tmpreg;
-  
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  SET_BIT(hirda->Instance->CR1, (hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode));
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Clear CTSE and RTSE bits */
-  hirda->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-  
+  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((hirda->Instance == USART1) || (hirda->Instance == USART6))
   {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK2Freq();
+    SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
   }
   else
   {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK1Freq();
+    SET_BIT(hirda->Instance->BRR, IRDA_BRR(pclk, hirda->Init.BaudRate));
   }
 }
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_iwdg.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_iwdg.c
index 33bdf533..91788bd8 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_iwdg.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_iwdg.c
@@ -2,112 +2,86 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   IWDG HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Independent Watchdog (IWDG) peripheral:
-  *           + Initialization and Configuration functions
+  *           + Initialization and Start functions
   *           + IO operation functions
-  *           + Peripheral State functions
-  *         
-  @verbatim 
+  *
+  @verbatim
   ==============================================================================
-                    ##### IWDG Specific features #####
+                    ##### IWDG Generic features #####
   ==============================================================================
-    [..] 
+  [..]
     (+) The IWDG can be started by either software or hardware (configurable
-         through option byte).
-    
-    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
-         thus stays active even if the main clock fails.
-         Once the IWDG is started, the LSI is forced ON and cannot be disabled
-         (LSI cannot be disabled too), and the counter starts counting down from 
-         the reset value of 0xFFF. When it reaches the end of count value (0x000)
-         a system reset is generated.
-
-    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
-         watchdog generates an MCU reset when the counter reaches 0.          
- 
+        through option byte).
+
+    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+        if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both can not be 
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is 
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+        prevented.
+
     (+) The IWDG is implemented in the VDD voltage domain that is still functional
-         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
-         reset occurs.
+        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
 
-    (+) Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+    (+) Debug mode : When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
          The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx
          devices provide the capability to measure the LSI frequency (LSI clock
          connected internally to TIM5 CH4 input capture). The measured value
          can be used to have an IWDG timeout with an acceptable accuracy.
 
-
                      ##### How to use this driver #####
   ==============================================================================
-    [..]
-    If Window option is disabled
-      (+) Use IWDG using HAL_IWDG_Init() function to :
-         (++) Enable write access to IWDG_PR, IWDG_RLR.
-         (++) Configure the IWDG prescaler, counter reload value.
-              This reload value will be loaded in the IWDG counter each time the counter
-              is reloaded, then the IWDG will start counting down from this value.
-    [..]
-      (+) Use IWDG using HAL_IWDG_Start() function to:
-          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
-          (++) Start the IWDG, when the IWDG is used in software mode (no need 
-               to enable the LSI, it will be enabled by hardware).
-      (+) Then the application program must refresh the IWDG counter at regular
-          intervals during normal operation to prevent an MCU reset, using
-          HAL_IWDG_Refresh() function.
-    [..] 
-    if Window option is enabled:
-      
-      (+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
-      (+) Use IWDG using HAL_IWDG_Init() function to :
-         (++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-         (++) Configure the IWDG prescaler, reload value and window value.
-      (+) Then the application program must refresh the IWDG counter at regular
-          intervals during normal operation to prevent an MCU reset, using
-          HAL_IWDG_Refresh() function.  
-     
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts downcounting.
+      (+) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
+      (+) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (+) wait for status flags to be reset"
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
      *** IWDG HAL driver macros list ***
      ====================================
      [..]
-       Below the list of most used macros in IWDG HAL driver.
-       
+       Below the list of most used macros in IWDG HAL driver:
       (+) __HAL_IWDG_START: Enable the IWDG peripheral
-      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register    
-      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
 
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -116,57 +90,63 @@
   * @{
   */
 
-/** @defgroup IWDG IWDG
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
   * @brief IWDG HAL module driver.
   * @{
   */
 
-#ifdef HAL_IWDG_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
- /** @addtogroup IWDG_Private_Constants
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-#define IWDG_TIMEOUT_FLAG          ((uint32_t)1000)     /* 1 s */
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
+   higher prescaler (256), and according to HSI variation, we need to wait at
+   least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT            48U
 /**
   * @}
   */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+
+/** @addtogroup IWDG_Exported_Functions
   * @{
   */
 
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
+/** @addtogroup IWDG_Exported_Functions_Group1
+  * @brief    Initialization and Start functions.
+  *
+@verbatim
  ===============================================================================
-          ##### Initialization and de-initialization functions #####
+          ##### Initialization and Start functions #####
  ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the IWDG according to the specified parameters 
-          in the IWDG_InitTypeDef and create the associated handle
-      (+) Initialize the IWDG MSP
-      (+) DeInitialize IWDG MSP 
- 
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the IWDG according to the specified
-  *         parameters in the IWDG_InitTypeDef and creates the associated handle.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  * @brief  Initialize the IWDG according to the specified parameters in the
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
   *                the configuration information for the specified IWDG module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
 {
+  uint32_t tickstart;
+
   /* Check the IWDG handle allocation */
   if(hiwdg == NULL)
   {
@@ -176,137 +156,33 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
   /* Check the parameters */
   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
-  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); 
-  
-  if(hiwdg->State == HAL_IWDG_STATE_RESET)
-  {  
-    /* Allocate lock resource and initialize it */
-    hiwdg->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_IWDG_MspInit(hiwdg);
-  }
-  
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;  
-  
-  /* Enable write access to IWDG_PR and IWDG_RLR registers */  
-  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-  
-  /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
-  MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
-  MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
- 
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the IWDG MSP.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval None
-  */
-__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IWDG_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions  
- *  @brief   IO operation functions  
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start the IWDG.
-      (+) Refresh the IWDG.
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hiwdg); 
-  
-    /* Change IWDG peripheral state */  
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
-
-  /* Start the IWDG peripheral */
+  /* Enable IWDG. LSI is turned on automaticaly */
   __HAL_IWDG_START(hiwdg);
-  
-    /* Reload IWDG counter with value defined in the RLR register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-  
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
 
-/**
-  * @brief  Refreshes the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
-  uint32_t tickstart = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hiwdg);
+  /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
 
-    /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
 
+  /* Check pending flag, if previous update not done, return timeout */
   tickstart = HAL_GetTick();
 
-  /* Wait until RVU flag is RESET */
-  while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+  /* Wait for register to be updated */
+  while(hiwdg->Instance->SR != 0x00u)
   {
-    if((HAL_GetTick() - tickstart ) > IWDG_TIMEOUT_FLAG)
+    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
     {
-      /* Set IWDG state */
-      hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
-
-       /* Process unlocked */
-      __HAL_UNLOCK(hiwdg);
-
       return HAL_TIMEOUT;
     }
   }
-  
+
   /* Reload IWDG counter with value defined in the reload register */
   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-    
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -315,30 +191,33 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
   * @}
   */
 
-/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
+/** @addtogroup IWDG_Exported_Functions_Group2
+  * @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
  ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Returns the IWDG state.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
   *                the configuration information for the specified IWDG module.
-  * @retval HAL state
+  * @retval HAL status
   */
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
 {
-  return hiwdg->State;
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_msp_template.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_msp_template.c
index 1c816000..d806e3b9 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_msp_template.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_msp_template.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_msp_template.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   HAL MSP module.
   *          This file template is located in the HAL folder and should be copied 
   *          to the user folder.
@@ -13,39 +11,20 @@
                      ##### How to use this driver #####
  ===============================================================================
     [..]
-    This file is generated automatically by STM32CubeMX and eventually modified 
-    by the user
-
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -75,10 +54,7 @@
   * @retval None
   */
 void HAL_MspInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */ 
+{ 
 }
 
 /**
@@ -87,9 +63,6 @@ void HAL_MspInit(void)
   */
 void HAL_MspDeInit(void)
 {
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */
 }
 
 /**
@@ -98,9 +71,6 @@ void HAL_MspDeInit(void)
   */
 void HAL_PPP_MspInit(void)
 {
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */ 
 }
 
 /**
@@ -109,9 +79,6 @@ void HAL_PPP_MspInit(void)
   */
 void HAL_PPP_MspDeInit(void)
 {
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nand.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nand.c
index 7adf41a5..1958af38 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nand.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nand.c
@@ -2,175 +2,196 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nand.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   NAND HAL module driver.
-  *          This file provides a generic firmware to drive NAND memories mounted 
+  *          This file provides a generic firmware to drive NAND memories mounted
   *          as external device.
-  *         
+  *
   @verbatim
   ==============================================================================
                          ##### How to use this driver #####
   ==============================================================================
     [..]
-      This driver is a generic layered driver which contains a set of APIs used to 
-      control NAND flash memories. It uses the FSMC layer functions to interface 
+      This driver is a generic layered driver which contains a set of APIs used to
+      control NAND flash memories. It uses the FSMC layer functions to interface
       with NAND devices. This driver is used as follows:
-    
-      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() 
+
+      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
           with control and timing parameters for both common and attribute spaces.
-            
+
       (+) Read NAND flash memory maker and device IDs using the function
-          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef 
-          structure declared by the function caller. 
-        
+          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
+          structure declared by the function caller.
+
       (+) Access NAND flash memory by read/write operations using the functions
-          HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
-          to read/write page(s)/spare area(s). These functions use specific device 
-          information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef 
+          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
+          to read/write page(s)/spare area(s). These functions use specific device
+          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
           structure. The read/write address information is contained by the Nand_Address_Typedef
           structure passed as parameter.
-        
+
       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
-        
+
       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
-          The erase block address information is contained in the Nand_Address_Typedef 
+          The erase block address information is contained in the Nand_Address_Typedef
           structure passed as parameter.
-    
+
       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
-        
+
       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
-          feature or the function HAL_NAND_GetECC() to get the ECC correction code. 
-       
+          feature or the function HAL_NAND_GetECC() to get the ECC correction code.
+
       (+) You can monitor the NAND device HAL state by calling the function
-          HAL_NAND_GetState()  
+          HAL_NAND_GetState()
 
     [..]
       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
-          If a NAND flash device contains different operations and/or implementations, 
+          If a NAND flash device contains different operations and/or implementations,
           it should be implemented separately.
 
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : NAND MspInit.
+        (+) MspDeInitCallback  : NAND MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : NAND MspInit.
+        (+) MspDeInitCallback  : NAND MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
+      and @ref  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
+      or @ref HAL_NAND_Init function.
+
+      When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
-
 #ifdef HAL_NAND_MODULE_ENABLED
 
-
-/** @defgroup NAND NAND 
+/** @defgroup NAND NAND
   * @brief NAND HAL module driver
   * @{
   */
 
 /* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/    
-/** @defgroup NAND_Private_Macros NAND Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
+/* Private Constants ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
 /** @defgroup NAND_Exported_Functions NAND Exported Functions
   * @{
   */
-    
-/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
+
+/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
             ##### NAND Initialization and de-initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to initialize/de-initialize
     the NAND memory
-  
+
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Perform NAND memory Initialization sequence
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  ComSpace_Timing: pointer to Common space timing structure
-  * @param  AttSpace_Timing: pointer to Attribute space timing structure
+  * @param  ComSpace_Timing pointer to Common space timing structure
+  * @param  AttSpace_Timing pointer to Attribute space timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
 {
   /* Check the NAND handle state */
-  if(hnand == NULL)
+  if (hnand == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
 
-  if(hnand->State == HAL_NAND_STATE_RESET)
+  if (hnand->State == HAL_NAND_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hnand->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    if(hnand->MspInitCallback == NULL)
+    {
+      hnand->MspInitCallback = HAL_NAND_MspInit;
+    }
+    hnand->ItCallback = HAL_NAND_ITCallback;
+
+    /* Init the low level hardware */
+    hnand->MspInitCallback(hnand);
+#else
     /* Initialize the low level hardware (MSP) */
     HAL_NAND_MspInit(hnand);
-  } 
+#endif
+  }
 
   /* Initialize NAND control Interface */
-  FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
-  
-  /* Initialize NAND common space timing Interface */  
-  FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
-  
-  /* Initialize NAND attribute space timing Interface */  
-  FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
-  
+  (void)FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
+
+  /* Initialize NAND common space timing Interface */
+  (void)FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
+
+  /* Initialize NAND attribute space timing Interface */
+  (void)FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
+
   /* Enable the NAND device */
   __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
   
@@ -182,17 +203,27 @@ HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing
 
 /**
   * @brief  Perform NAND memory De-Initialization sequence
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)  
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
 {
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+  if(hnand->MspDeInitCallback == NULL)
+  {
+    hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hnand->MspDeInitCallback(hnand);
+#else
   /* Initialize the low level hardware (MSP) */
   HAL_NAND_MspDeInit(hnand);
+#endif
 
   /* Configure the NAND registers with their reset values */
-  FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
+  (void)FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
 
   /* Reset the NAND controller state */
   hnand->State = HAL_NAND_STATE_RESET;
@@ -205,737 +236,1651 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
 
 /**
   * @brief  NAND MSP Init
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval None
   */
 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  NAND MSP DeInit
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval None
   */
 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 
 /**
   * @brief  This function handles NAND device interrupt request.
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL status
 */
 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
 {
   /* Check NAND interrupt Rising edge flag */
-  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
+  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
   {
     /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
     HAL_NAND_ITCallback(hnand);
-  
+#endif
+
     /* Clear NAND interrupt Rising edge pending bit */
     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
   }
-  
+
   /* Check NAND interrupt Level flag */
-  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
+  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
   {
     /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
     HAL_NAND_ITCallback(hnand);
-  
+#endif
+
     /* Clear NAND interrupt Level pending bit */
     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
   }
 
   /* Check NAND interrupt Falling edge flag */
-  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
+  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
   {
     /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
     HAL_NAND_ITCallback(hnand);
-  
+#endif
+
     /* Clear NAND interrupt Falling edge pending bit */
     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
   }
-  
+
   /* Check NAND interrupt FIFO empty flag */
-  if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
+  if (__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
   {
     /* NAND interrupt callback*/
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+    hnand->ItCallback(hnand);
+#else
     HAL_NAND_ITCallback(hnand);
-  
+#endif
+
     /* Clear NAND interrupt FIFO empty pending bit */
     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
-  }  
+  }
 
 }
 
 /**
   * @brief  NAND interrupt feature callback
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval None
   */
 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnand);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NAND_ITCallback could be implemented in the user file
    */
 }
- 
+
 /**
   * @}
   */
-  
-
-
 
-/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
+/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
                     ##### NAND Input and Output functions #####
   ==============================================================================
-  [..]  
-    This section provides functions allowing to use and control the NAND 
+  [..]
+    This section provides functions allowing to use and control the NAND
     memory
-  
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Read the NAND memory electronic signature
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pNAND_ID: NAND ID structure
+  * @param  pNAND_ID NAND ID structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
 {
   __IO uint32_t data = 0;
-  uint32_t deviceaddress = 0;
+  __IO uint32_t data1 = 0;
+  uint32_t deviceAddress;
 
-  /* Process Locked */
-  __HAL_LOCK(hnand);  
-  
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    deviceaddress = NAND_DEVICE1;
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* Send Read ID command sequence */
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_READID;
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
+    __DSB();
+
+    /* Read the electronic signature from NAND flash */
+    if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
+    {
+      data = *(__IO uint32_t *)deviceAddress;
+
+      /* Return the data read */
+      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
+      pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
+      pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
+      pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
+    }
+    else
+    {
+      data = *(__IO uint32_t *)deviceAddress;
+      data1 = *((__IO uint32_t *)deviceAddress + 4);
+
+      /* Return the data read */
+      pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
+      pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
+      pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
+      pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
   }
   else
   {
-    deviceaddress = NAND_DEVICE2;
+    return HAL_ERROR;
   }
-  
-  /* Update the NAND controller state */ 
-  hnand->State = HAL_NAND_STATE_BUSY;
-  
-  /* Send Read ID command sequence */   
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
 
-  /* Read the electronic signature from NAND flash */  
-  data = *(__IO uint32_t *)deviceaddress;
-  
-  /* Return the data read */
-  pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
-  pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
-  pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
-  pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
-  
-  /* Update the NAND controller state */ 
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
-   
   return HAL_OK;
 }
 
 /**
   * @brief  NAND memory reset
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
 {
-  uint32_t deviceaddress = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hnand);
+  uint32_t deviceAddress;
 
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    deviceaddress = NAND_DEVICE1;
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* Send NAND reset command */
+    *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
   }
   else
   {
-    deviceaddress = NAND_DEVICE2;
-  }  
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_BUSY; 
-  
-  /* Send NAND reset command */  
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
+    return HAL_ERROR;
+  }
 
   return HAL_OK;
 
 }
-  
+
 /**
-  * @brief  Read Page(s) from NAND memory block 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Configure the device: Enter the physical parameters of the device
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pAddress : pointer to NAND address structure
-  * @param  pBuffer : pointer to destination read buffer
-  * @param  NumPageToRead : number of pages to read from block 
+  * @param  pDeviceConfig  pointer to NAND_DeviceConfigTypeDef structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
-{   
-  __IO uint32_t index  = 0;
-  uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
-  NAND_AddressTypeDef nandaddress;
-  uint32_t addressoffset = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnand); 
-  
-  /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
-  {
-    deviceaddress = NAND_DEVICE1;
-  }
-  else
-  {
-    deviceaddress = NAND_DEVICE2;
-  }
-
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_BUSY;
-  
-  /* Save the content of pAddress as it will be modified */
-  nandaddress.Block     = pAddress->Block;
-  nandaddress.Page      = pAddress->Page;
-  nandaddress.Zone      = pAddress->Zone;
-
-  /* Page(s) read loop */  
-  while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
-  {     
-    /* update the buffer size */
-    size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
-    
-    /* Get the address offset */
-    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-    
-    /* Send read page command sequence */
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-   
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; 
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-  
-    /* for 512 and 1 GB devices, 4th cycle is required */
-    if(hnand->Info.BlockNbr >= 1024)
-    {
-      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
-    }
-  
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
-      
-    /* Get Data into Buffer */    
-    for(index = size; index != 0; index--)
-    {
-      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
-    }
-    
-    /* Increment read pages number */
-    numpagesread++;
-    
-    /* Decrement pages to read */
-    NumPageToRead--;
-    
-    /* Increment the NAND address */
-    addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
-  }
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+  hnand->Config.PageSize           = pDeviceConfig->PageSize;
+  hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
+  hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
+  hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
+  hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
+  hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
+  hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
 
   return HAL_OK;
-
 }
 
 /**
-  * @brief  Write Page(s) to NAND memory block 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Read Page(s) from NAND memory block (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pAddress : pointer to NAND address structure
-  * @param  pBuffer : pointer to source buffer to write  
-  * @param  NumPageToWrite  : number of pages to write to block 
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to destination read buffer
+  * @param  NumPageToRead  number of pages to read from block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
 {
-  __IO uint32_t index   = 0;
-  uint32_t tickstart = 0;
-  uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
-  NAND_AddressTypeDef nandaddress;
-  uint32_t addressoffset = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnand);  
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
+  uint8_t * buff = pBuffer;
 
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    deviceaddress = NAND_DEVICE1;
+    return HAL_BUSY;
   }
-  else
-  {
-    deviceaddress = NAND_DEVICE2;
-  }
-  
-  /* Update the NAND controller state */ 
-  hnand->State = HAL_NAND_STATE_BUSY;
-  
-  /* Save the content of pAddress as it will be modified */
-  nandaddress.Block     = pAddress->Block;
-  nandaddress.Page      = pAddress->Page;
-  nandaddress.Zone      = pAddress->Zone;
-    
-  /* Page(s) write loop */
-  while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    /* update the buffer size */
-    size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
-    
-    /* Get the address offset */
-    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-    
-    /* Send write page command sequence */
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;  
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-  
-    /* for 512 and 1 GB devices, 4th cycle is required */     
-    if(hnand->Info.BlockNbr >= 1024)
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
     {
-      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+      deviceAddress = NAND_DEVICE1;
     }
-  
-    /* Write data to memory */
-    for(index = size; index != 0; index--)
+    else
     {
-      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+      deviceAddress = NAND_DEVICE2;
     }
-   
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    /* Read status until NAND is ready */
-    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) read loop */
+    while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
     {
-      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+      /* Send read page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
       {
-        return HAL_TIMEOUT; 
+        *buff = *(uint8_t *)deviceAddress;
+        buff++;
       }
+
+      /* Increment read pages number */
+      numPagesRead++;
+
+      /* Decrement pages to read */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
     }
- 
-    /* Increment written pages number */
-    numpageswritten++;
-    
-    /* Decrement pages to write */
-    NumPageToWrite--;
-    
-    /* Increment the NAND address */
-    addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
   }
-  
-  /* Update the NAND controller state */ 
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
-  
+  else
+  {
+    return HAL_ERROR;
+  }
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Read Spare area(s) from NAND memory 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Read Page(s) from NAND memory block (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pAddress : pointer to NAND address structure
-  * @param  pBuffer: pointer to source buffer to write  
-  * @param  NumSpareAreaToRead: Number of spare area to read  
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to destination read buffer. pBuffer should be 16bits aligned
+  * @param  NumPageToRead  number of pages to read from block
   * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+  */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
 {
-  __IO uint32_t index   = 0; 
-  uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
-  NAND_AddressTypeDef nandaddress;
-  uint32_t addressoffset = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnand);  
-  
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
+  uint16_t * buff = pBuffer;
+
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    deviceaddress = NAND_DEVICE1;
+    return HAL_BUSY;
   }
-  else
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    deviceaddress = NAND_DEVICE2;
-  }
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_BUSY;
-  
-  /* Save the content of pAddress as it will be modified */
-  nandaddress.Block     = pAddress->Block;
-  nandaddress.Page      = pAddress->Page;
-  nandaddress.Zone      = pAddress->Zone;
-  
-  /* Spare area(s) read loop */ 
-  while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
-  {     
-    /* update the buffer size */
-    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
-
-    /* Get the address offset */
-    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-    
-    /* Send read spare area command sequence */     
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; 
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-  
-    /* for 512 and 1 GB devices, 4th cycle is required */    
-    if(hnand->Info.BlockNbr >= 1024)
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
     {
-      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
-    } 
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
 
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
-    
-    /* Get Data into Buffer */
-    for (index = size ;index != 0; index--)
+    /* Page(s) read loop */
+    while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
     {
-      *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+      /* Send read page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *buff = *(uint16_t *)deviceAddress;
+        buff++;
+      }
+
+      /* Increment read pages number */
+      numPagesRead++;
+
+      /* Decrement pages to read */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
     }
-    
-    /* Increment read spare areas number */
-    num_spare_area_read++;
-    
-    /* Decrement spare areas to read */
-    NumSpareAreaToRead--;
-    
-    /* Increment the NAND address */
-    addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
   }
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
-  * @brief  Write Spare area(s) to NAND memory 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Write Page(s) to NAND memory block (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pAddress : pointer to NAND address structure
-  * @param  pBuffer : pointer to source buffer to write  
-  * @param  NumSpareAreaTowrite  : number of spare areas to write to block
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write
+  * @param  NumPageToWrite   number of pages to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
 {
-  __IO uint32_t index = 0;
-  uint32_t tickstart = 0;
-  uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
-  NAND_AddressTypeDef nandaddress;
-  uint32_t addressoffset = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hnand); 
-  
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
+  uint8_t * buff = pBuffer;
+
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
-  {
-    deviceaddress = NAND_DEVICE1;
-  }
-  else
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    deviceaddress = NAND_DEVICE2;
+    return HAL_BUSY;
   }
-  
-  /* Update the FSMC_NAND controller state */
-  hnand->State = HAL_NAND_STATE_BUSY;  
-  
-  /* Save the content of pAddress as it will be modified */
-  nandaddress.Block     = pAddress->Block;
-  nandaddress.Page      = pAddress->Page;
-  nandaddress.Zone      = pAddress->Zone;
-  
-  /* Spare area(s) write loop */
-  while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    /* update the buffer size */
-    size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
-
-    /* Get the address offset */
-    addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-    
-    /* Send write Spare area command sequence */
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;  
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-  
-    /* for 512 and 1 GB devices, 4th cycle is required */     
-    if(hnand->Info.BlockNbr >= 1024)
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
     {
-      *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+      deviceAddress = NAND_DEVICE1;
     }
-  
-    /* Write data to memory */
-    for(; index < size; index++)
+    else
     {
-      *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
+      deviceAddress = NAND_DEVICE2;
     }
-   
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
-    
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    /* Read status until NAND is ready */
-    while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) write loop */
+    while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
     {
-      if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+      /* Send write page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *(__IO uint8_t *)deviceAddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
       {
-        return HAL_TIMEOUT; 
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
       }
+
+      /* Increment written pages number */
+      numPagesWritten++;
+
+      /* Decrement pages to write */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
     }
 
-    /* Increment written spare areas number */
-    num_spare_area_written++;
-    
-    /* Decrement spare areas to write */
-    NumSpareAreaTowrite--;
-    
-    /* Increment the NAND address */
-    addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
-  }
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
 
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_READY;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);
-    
   return HAL_OK;
 }
 
 /**
-  * @brief  NAND memory Block erase 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Write Page(s) to NAND memory block (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  pAddress : pointer to NAND address structure
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned
+  * @param  NumPageToWrite   number of pages to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
 {
-  uint32_t deviceaddress = 0;
-  uint32_t tickstart = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnand);
-  
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
+  uint16_t * buff = pBuffer;
+
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    deviceaddress = NAND_DEVICE1;
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Page(s) write loop */
+    while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Send write page command sequence */
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+      __DSB();
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+      __DSB();
+
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.PageSize; index++)
+      {
+        *(__IO uint16_t *)deviceAddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Increment written pages number */
+      numPagesWritten++;
+
+      /* Decrement pages to write */
+      nbpages--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
   }
   else
   {
-    deviceaddress = NAND_DEVICE2;
+    return HAL_ERROR;
   }
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_BUSY;  
-  
-  /* Send Erase block command sequence */
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
 
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-  
-  /* for 512 and 1 GB devices, 4th cycle is required */     
-  if(hnand->Info.BlockNbr >= 1024)
+  return HAL_OK;
+}
+
+/**
+  * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer pointer to source buffer to write
+  * @param  NumSpareAreaToRead Number of spare area to read
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
+  uint8_t * buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-  }  
-    
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; 
-  
-  /* Update the NAND controller state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Read status until NAND is ready */
-  while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
     {
-      /* Process unlocked */
-      __HAL_UNLOCK(hnand);    
-  
-      return HAL_TIMEOUT; 
-    } 
-  }    
- 
-  /* Process unlocked */
-  __HAL_UNLOCK(hnand);    
-  
-  return HAL_OK;  
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnAddress = COLUMN_ADDRESS(hnand);
+
+    /* Spare area(s) read loop */
+    while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *buff = *(uint8_t *)deviceAddress;
+        buff++;
+      }
+
+      /* Increment read spare areas number */
+      numSpareAreaRead++;
+
+      /* Decrement spare areas to read */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  NAND memory read status 
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @retval NAND status
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+  * @param  NumSpareAreaToRead Number of spare area to read
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
+  uint16_t * buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+    /* Spare area(s) read loop */
+    while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send read spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+      __DSB();
+
+      if (hnand->Config.ExtraCommandEnable == ENABLE)
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Read status until NAND is ready */
+        while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+        {
+          if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+          {
+            /* Update the NAND controller state */
+            hnand->State = HAL_NAND_STATE_ERROR;
+
+            /* Process unlocked */
+            __HAL_UNLOCK(hnand);
+
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Go back to read mode */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
+        __DSB();
+      }
+
+      /* Get Data into Buffer */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *buff = *(uint16_t *)deviceAddress;
+        buff++;
+      }
+
+      /* Increment read spare areas number */
+      numSpareAreaRead++;
+
+      /* Decrement spare areas to read */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write
+  * @param  NumSpareAreaTowrite   number of spare areas to write to block
+  * @retval HAL status
   */
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
 {
-  uint32_t data = 0;
-  uint32_t deviceaddress = 0;
-  
-  /* Identify the device address */
-  if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
+  uint8_t * buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    deviceaddress = NAND_DEVICE1;
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* Page address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnAddress = COLUMN_ADDRESS(hnand);
+
+    /* Spare area(s) write loop */
+    while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *(__IO uint8_t *)deviceAddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Increment written spare areas number */
+      numSpareAreaWritten++;
+
+      /* Decrement spare areas to write */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
   }
   else
   {
-    deviceaddress = NAND_DEVICE2;
-  } 
+    return HAL_ERROR;
+  }
 
-  /* Send Read status operation command */
-  *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
-  
-  /* Read status register data */
-  data = *(__IO uint8_t *)deviceaddress;
+  return HAL_OK;
+}
 
-  /* Return the status */
-  if((data & NAND_ERROR) == NAND_ERROR)
+/**
+  * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @param  pBuffer  pointer to source buffer to write. pBuffer should be 16bits aligned.
+  * @param  NumSpareAreaTowrite   number of spare areas to write to block
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+  uint32_t index;
+  uint32_t tickstart;
+  uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
+  uint16_t * buff = pBuffer;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-    return NAND_ERROR;
-  } 
-  else if((data & NAND_READY) == NAND_READY)
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
   {
-    return NAND_READY;
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      deviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      deviceAddress = NAND_DEVICE2;
+    }
+
+    /* NAND raw address calculation */
+    nandAddress = ARRAY_ADDRESS(pAddress, hnand);
+
+    /* Column in page address */
+    columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+    /* Spare area(s) write loop */
+    while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+    {
+      /* Cards with page size <= 512 bytes */
+      if ((hnand->Config.PageSize) <= 512U)
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+      else /* (hnand->Config.PageSize) > 512 */
+      {
+        /* Send write Spare area command sequence */
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
+        __DSB();
+        *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
+        __DSB();
+
+        if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+        }
+        else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+        {
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
+          __DSB();
+          *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
+          __DSB();
+        }
+      }
+
+      /* Write data to memory */
+      for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
+      {
+        *(__IO uint16_t *)deviceAddress = *buff;
+        buff++;
+        __DSB();
+      }
+
+      *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+      __DSB();
+
+      /* Get tick */
+      tickstart = HAL_GetTick();
+
+      /* Read status until NAND is ready */
+      while (HAL_NAND_Read_Status(hnand) != NAND_READY)
+      {
+        if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
+        {
+          /* Update the NAND controller state */
+          hnand->State = HAL_NAND_STATE_ERROR;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hnand);
+
+          return HAL_TIMEOUT;
+        }
+      }
+
+      /* Increment written spare areas number */
+      numSpareAreaWritten++;
+
+      /* Decrement spare areas to write */
+      nbspare--;
+
+      /* Increment the NAND address */
+      nandAddress = (uint32_t)(nandAddress + 1U);
+    }
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  NAND memory Block erase
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @param  pAddress  pointer to NAND address structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+{
+  uint32_t DeviceAddress;
+
+  /* Check the NAND controller state */
+  if (hnand->State == HAL_NAND_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnand);
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      DeviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      DeviceAddress = NAND_DEVICE2;
+    }
+
+    /* Send Erase block command sequence */
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+    __DSB();
+
+    *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
+    __DSB();
+
+    /* Update the NAND controller state */
+    hnand->State = HAL_NAND_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnand);
+  }
+  else
+  {
+    return HAL_ERROR;
   }
 
-  return NAND_BUSY; 
+  return HAL_OK;
 }
 
 /**
   * @brief  Increment the NAND memory address
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param pAddress: pointer to NAND address structure
+  * @param pAddress pointer to NAND address structure
   * @retval The new status of the increment address operation. It can be:
   *           - NAND_VALID_ADDRESS: When the new address is valid address
   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
@@ -943,155 +1888,310 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 {
   uint32_t status = NAND_VALID_ADDRESS;
- 
+
   /* Increment page address */
   pAddress->Page++;
 
   /* Check NAND address is valid */
-  if(pAddress->Page == hnand->Info.BlockSize)
+  if (pAddress->Page == hnand->Config.BlockSize)
   {
     pAddress->Page = 0;
     pAddress->Block++;
-    
-    if(pAddress->Block == hnand->Info.ZoneSize)
+
+    if (pAddress->Block == hnand->Config.PlaneSize)
     {
       pAddress->Block = 0;
-      pAddress->Zone++;
+      pAddress->Plane++;
 
-      if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+      if (pAddress->Plane == (hnand->Config.PlaneNbr))
       {
         status = NAND_INVALID_ADDRESS;
       }
     }
-  } 
-  
+  }
+
   return (status);
 }
+
+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User NAND Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hnand : NAND handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
+  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
+  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hnand);
+
+  if(hnand->State == HAL_NAND_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case HAL_NAND_MSP_INIT_CB_ID :
+      hnand->MspInitCallback = pCallback;
+      break;
+    case HAL_NAND_MSP_DEINIT_CB_ID :
+      hnand->MspDeInitCallback = pCallback;
+      break;
+    case HAL_NAND_IT_CB_ID :
+      hnand->ItCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(hnand->State == HAL_NAND_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_NAND_MSP_INIT_CB_ID :
+      hnand->MspInitCallback = pCallback;
+      break;
+    case HAL_NAND_MSP_DEINIT_CB_ID :
+      hnand->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnand);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User NAND Callback
+  *         NAND Callback is redirected to the weak (surcharged) predefined callback
+  * @param hnand : NAND handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NAND_MSP_INIT_CB_ID       NAND MspInit callback ID
+  *          @arg @ref HAL_NAND_MSP_DEINIT_CB_ID     NAND MspDeInit callback ID
+  *          @arg @ref HAL_NAND_IT_CB_ID             NAND IT callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hnand);
+
+  if(hnand->State == HAL_NAND_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case HAL_NAND_MSP_INIT_CB_ID :
+      hnand->MspInitCallback = HAL_NAND_MspInit;
+      break;
+    case HAL_NAND_MSP_DEINIT_CB_ID :
+      hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+      break;
+    case HAL_NAND_IT_CB_ID :
+      hnand->ItCallback = HAL_NAND_ITCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(hnand->State == HAL_NAND_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_NAND_MSP_INIT_CB_ID :
+      hnand->MspInitCallback = HAL_NAND_MspInit;
+      break;
+    case HAL_NAND_MSP_DEINIT_CB_ID :
+      hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hnand);
+  return status;
+}
+#endif
+
 /**
   * @}
   */
 
-/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   management functions 
+/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   management functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                          ##### NAND Control functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control dynamically
     the NAND interface.
 
 @endverbatim
   * @{
-  */ 
+  */
+
 
-    
 /**
   * @brief  Enables dynamically NAND ECC feature.
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL status
-  */    
+  */
 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
 {
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Enable ECC feature */
+    (void)FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
   }
 
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_BUSY;
-   
-  /* Enable ECC feature */
-  FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
-  
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
   return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically FSMC_NAND ECC feature.
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL status
-  */  
+  */
 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
 {
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
 
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_BUSY;
-    
-  /* Disable ECC feature */
-  FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
-  
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_READY;
-  
-  return HAL_OK;  
+    /* Disable ECC feature */
+    (void)FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically NAND ECC feature.
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
-  * @param  ECCval: pointer to ECC value 
-  * @param  Timeout: maximum timeout to wait    
+  * @param  ECCval pointer to ECC value
+  * @param  Timeout maximum timeout to wait
   * @retval HAL status
   */
 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
 {
-  HAL_StatusTypeDef status = HAL_OK;
-  
+  HAL_StatusTypeDef status;
+
   /* Check the NAND controller state */
-  if(hnand->State == HAL_NAND_STATE_BUSY)
+  if (hnand->State == HAL_NAND_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
+  else if (hnand->State == HAL_NAND_STATE_READY)
+  {
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_BUSY;
+
+    /* Get NAND ECC value */
+    status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
+
+    /* Update the NAND state */
+    hnand->State = HAL_NAND_STATE_READY;
+  }
+  else
+  {
+    return HAL_ERROR;
   }
-  
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_BUSY;  
-   
-  /* Get NAND ECC value */
-  status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
-  
-  /* Update the NAND state */
-  hnand->State = HAL_NAND_STATE_READY;
 
-  return status;  
+  return status;
 }
 
 /**
   * @}
   */
-  
-    
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
+
+
+/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                          ##### NAND State functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection permits to get in run-time the status of the NAND controller 
+    This subsection permits to get in run-time the status of the NAND controller
     and the data flow.
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  return the NAND state
-  * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
   *                the configuration information for NAND module.
   * @retval HAL state
   */
@@ -1100,9 +2200,52 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
   return hnand->State;
 }
 
+/**
+  * @brief  NAND memory read status
+  * @param  hnand pointer to a NAND_HandleTypeDef structure that contains
+  *                the configuration information for NAND module.
+  * @retval NAND status
+  */
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+{
+  uint32_t data;
+  uint32_t DeviceAddress;
+  UNUSED(hnand);
+
+  /* Identify the device address */
+    if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+    {
+      DeviceAddress = NAND_DEVICE1;
+    }
+    else
+    {
+      DeviceAddress = NAND_DEVICE2;
+    }
+
+  /* Send Read status operation command */
+  *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
+
+  /* Read status register data */
+  data = *(__IO uint8_t *)DeviceAddress;
+
+  /* Return the status */
+  if ((data & NAND_ERROR) == NAND_ERROR)
+  {
+    return NAND_ERROR;
+  }
+  else if ((data & NAND_READY) == NAND_READY)
+  {
+    return NAND_READY;
+  }
+  else
+  {
+    return NAND_BUSY;
+  }
+}
+
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
@@ -1118,4 +2261,5 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
   * @}
   */
 
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nor.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nor.c
index 0eb21a28..014ed2be 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nor.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nor.c
@@ -2,101 +2,125 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   NOR HAL module driver.
-  *          This file provides a generic firmware to drive NOR memories mounted 
+  *          This file provides a generic firmware to drive NOR memories mounted
   *          as external device.
-  *         
+  *
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
-  ==============================================================================       
+  ==============================================================================
     [..]
-      This driver is a generic layered driver which contains a set of APIs used to 
-      control NOR flash memories. It uses the FSMC layer functions to interface 
+      This driver is a generic layered driver which contains a set of APIs used to
+      control NOR flash memories. It uses the FSMC layer functions to interface
       with NOR devices. This driver is used as follows:
-    
-      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() 
+
+      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
           with control and timing parameters for both normal and extended mode.
-            
+
       (+) Read NOR flash memory manufacturer code and device IDs using the function
-          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef 
-          structure declared by the function caller. 
-        
+          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
+          structure declared by the function caller.
+
       (+) Access NOR flash memory by read/write data unit operations using the functions
           HAL_NOR_Read(), HAL_NOR_Program().
-        
-      (+) Perform NOR flash erase block/chip operations using the functions 
+
+      (+) Perform NOR flash erase block/chip operations using the functions
           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-        
+
       (+) Read the NOR flash CFI (common flash interface) IDs using the function
           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
           structure declared by the function caller.
-        
+
       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
-          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
-       
+          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
+
       (+) You can monitor the NOR device HAL state by calling the function
-          HAL_NOR_GetState() 
+          HAL_NOR_GetState()
     [..]
      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
-         If a NOR flash device contains different operations and/or implementations, 
+         If a NOR flash device contains different operations and/or implementations,
          it should be implemented separately.
 
      *** NOR HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in NOR HAL driver.
-       
+
       (+) NOR_WRITE : NOR memory write data to specified address
 
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
+      and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
+      or @ref HAL_NOR_Init function.
+
+      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
+#ifdef HAL_NOR_MODULE_ENABLED
+
 /** @defgroup NOR NOR
   * @brief NOR driver modules
   * @{
   */
-#ifdef HAL_NOR_MODULE_ENABLED
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-      
+
 /** @defgroup NOR_Private_Defines NOR Private Defines
   * @{
   */
@@ -133,86 +157,128 @@
 /**
   * @}
   */
-      
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Variables NOR Private Variables
+  * @{
+  */
+
+static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
+
+/**
+  * @}
+  */
+
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup NOR_Exported_Functions NOR Exported Functions
   * @{
   */
 
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
+/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
            ##### NOR Initialization and de_initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to initialize/de-initialize
     the NOR memory
-  
+
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Perform the NOR memory Initialization sequence
-  * @param  hnor: pointer to the NOR handle
-  * @param  Timing: pointer to NOR control timing structure 
-  * @param  ExtTiming: pointer to NOR extended mode timing structure    
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Timing pointer to NOR control timing structure
+  * @param  ExtTiming pointer to NOR extended mode timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
 {
   /* Check the NOR handle parameter */
-  if(hnor == NULL)
+  if (hnor == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
-  if(hnor->State == HAL_NOR_STATE_RESET)
+
+  if (hnor->State == HAL_NOR_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hnor->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+    if(hnor->MspInitCallback == NULL)
+    {
+      hnor->MspInitCallback = HAL_NOR_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hnor->MspInitCallback(hnor);
+#else
     /* Initialize the low level hardware (MSP) */
     HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
   }
-  
+
   /* Initialize NOR control Interface */
-  FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+  (void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
 
   /* Initialize NOR timing Interface */
-  FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); 
+  (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
 
   /* Initialize NOR extended mode timing Interface */
-  FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+  (void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
 
   /* Enable the NORSRAM device */
   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
 
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY; 
-  
+  /* Initialize NOR Memory Data Width*/
+  if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_8B;
+  }
+  else
+  {
+    uwNORMemoryDataWidth = NOR_MEMORY_16B;
+  }
+
+  /* Initialize the NOR controller state */
+  hnor->State = HAL_NOR_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Perform NOR memory De-Initialization sequence
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
 {
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+  if(hnor->MspDeInitCallback == NULL)
+  {
+    hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hnor->MspDeInitCallback(hnor);
+#else
   /* De-Initialize the low level hardware (MSP) */
   HAL_NOR_MspDeInit(hnor);
- 
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+
   /* Configure the NOR registers with their reset values */
-  FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-  
-  /* Update the NOR controller state */
+  (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+
+  /* Reset the NOR controller state */
   hnor->State = HAL_NOR_STATE_RESET;
 
   /* Release Lock */
@@ -223,613 +289,802 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  NOR MSP Init
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval None
   */
 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  NOR MSP DeInit
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval None
   */
 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief  NOR BSP Wait for Ready/Busy signal
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @brief  NOR MSP Wait for Ready/Busy signal
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  Timeout: Maximum timeout value
+  * @param  Timeout Maximum timeout value
   * @retval None
   */
 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hnor);
+  UNUSED(Timeout);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_BspWait could be implemented in the user file
-   */ 
+            the HAL_NOR_MspWait could be implemented in the user file
+   */
 }
-  
+
 /**
   * @}
   */
 
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
+/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
                 ##### NOR Input and Output functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to use and control the NOR memory
-  
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Read NOR flash IDs
-  * @param  hnor: pointer to the NOR handle
-  * @param  pNOR_ID : pointer to NOR ID structure
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_ID  pointer to NOR ID structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+    return HAL_BUSY;
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
   {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read ID command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+    /* Read the NOR IDs */
+    pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+    pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+    pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+    pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
   }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }  
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read ID command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
 
-  /* Read the NOR IDs */
-  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
-  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
-  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
-  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);   
-  
   return HAL_OK;
 }
 
 /**
   * @brief  Returns the NOR memory to Read mode.
-  * @param  hnor: pointer to the NOR handle
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
 {
-  uint32_t deviceaddress = 0;  
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+    return HAL_BUSY;
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
   {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
   }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }  
-  
-  NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
 
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);   
-  
   return HAL_OK;
 }
 
 /**
-  * @brief  Read data from NOR memory 
-  * @param  hnor: pointer to the NOR handle
-  * @param  pAddress: pointer to Device address
-  * @param  pData : pointer to read data  
+  * @brief  Read data from NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress pointer to Device address
+  * @param  pData  pointer to read data
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+    return HAL_BUSY;
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
   {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read data command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+
+    /* Read the data */
+    *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
   }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  } 
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
-  NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
 
-  /* Read the data */
- *pData = *(__IO uint32_t *)(uint32_t)pAddress;
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
-  * @brief  Program data to NOR memory 
-  * @param  hnor: pointer to the NOR handle
-  * @param  pAddress: Device address
-  * @param  pData : pointer to the data to write   
+  * @brief  Program data to NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pAddress Device address
+  * @param  pData  pointer to the data to write
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if (hnor->State == HAL_NOR_STATE_READY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send program data command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+    /* Write the data */
+    NOR_WRITE(pAddress, *pData);
+
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
   }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  } 
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send program data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
 
-  /* Write the data */
-  NOR_WRITE(pAddress, *pData);
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Reads a half-word buffer from the NOR memory.
-  * @param  hnor: pointer to the NOR handle
-  * @param  uwAddress: NOR memory internal address to read from.
-  * @param  pData: pointer to the buffer that receives the data read from the 
+  * @param  hnor pointer to the NOR handle
+  * @param  uwAddress NOR memory internal address to read from.
+  * @param  pData pointer to the buffer that receives the data read from the
   *         NOR memory.
-  * @param  uwBufferSize : number of Half word to read.
+  * @param  uwBufferSize  number of Half word to read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
+  uint16_t *data = pData;
+  HAL_NOR_StateTypeDef state;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read data command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+
+    /* Read buffer */
+    while (size > 0U)
+    {
+      *data = *(__IO uint16_t *)address;
+      data++;
+      address += 2U;
+      size--;
+    }
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
   }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }  
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);  
-  NOR_WRITE(uwAddress, 0x00F0);
-  
-  /* Read buffer */
-  while( uwBufferSize > 0) 
-  {
-    *pData++ = *(__IO uint16_t *)uwAddress;
-    uwAddress += 2;
-    uwBufferSize--;
-  } 
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Writes a half-word buffer to the NOR memory. This function must be used 
-            only with S29GL128P NOR memory. 
-  * @param  hnor: pointer to the NOR handle
-  * @param  uwAddress: NOR memory internal start write address 
-  * @param  pData: pointer to source data buffer. 
-  * @param  uwBufferSize: Size of the buffer to write
+  * @brief  Writes a half-word buffer to the NOR memory. This function must be used
+            only with S29GL128P NOR memory.
+  * @param  hnor pointer to the NOR handle
+  * @param  uwAddress NOR memory internal start write address
+  * @param  pData pointer to source data buffer.
+  * @param  uwBufferSize Size of the buffer to write
   * @retval HAL status
-  */ 
+  */
 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
 {
-  uint16_t * p_currentaddress = (uint16_t *)NULL;
-  uint16_t * p_endaddress = (uint16_t *)NULL;
-  uint32_t lastloadedaddress = 0, deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint16_t *p_currentaddress;
+  const uint16_t *p_endaddress;
+  uint16_t *data = pData;
+  uint32_t lastloadedaddress, deviceaddress;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_BUSY;
   }
-  else /* FSMC_NORSRAM_BANK4 */
+  else if (hnor->State == HAL_NOR_STATE_READY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }  
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Initialize variables */
-  p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
-  p_endaddress      = p_currentaddress + (uwBufferSize-1);
-  lastloadedaddress = (uint32_t)(uwAddress);
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Initialize variables */
+    p_currentaddress  = (uint16_t *)(uwAddress);
+    p_endaddress      = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
+    lastloadedaddress = uwAddress;
 
-  /* Issue unlock command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); 
+    /* Issue unlock command sequence */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
 
-  /* Write Buffer Load Command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); 
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); 
+    /* Write Buffer Load Command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
 
-  /* Load Data into NOR Buffer */
-  while(p_currentaddress <= p_endaddress)
+    /* Load Data into NOR Buffer */
+    while (p_currentaddress <= p_endaddress)
+    {
+      /* Store last loaded address & data value (for polling) */
+      lastloadedaddress = (uint32_t)p_currentaddress;
+
+      NOR_WRITE(p_currentaddress, *data);
+
+      data++;
+      p_currentaddress ++;
+    }
+
+    NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
   {
-    /* Store last loaded address & data value (for polling) */
-     lastloadedaddress = (uint32_t)p_currentaddress;
- 
-    NOR_WRITE(p_currentaddress, *pData++);
-    
-    p_currentaddress ++; 
+    return HAL_ERROR;
   }
 
-  NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK; 
-  
+  return HAL_OK;
+
 }
 
 /**
-  * @brief  Erase the specified block of the NOR memory 
-  * @param  hnor: pointer to the NOR handle
-  * @param  BlockAddress : Block to erase address 
-  * @param  Address: Device address
+  * @brief  Erase the specified block of the NOR memory
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  BlockAddress  Block to erase address
+  * @param  Address Device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
 {
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
 
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if (hnor->State == HAL_NOR_STATE_READY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send block erase command sequence */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+    NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS4;
+    return HAL_ERROR;
   }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send block erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-  NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
 
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
   return HAL_OK;
- 
+
 }
 
 /**
   * @brief  Erase the entire NOR chip.
-  * @param  hnor: pointer to the NOR handle
-  * @param  Address : Device address  
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address  Device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+  UNUSED(Address);
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if (hnor->State == HAL_NOR_STATE_READY)
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send NOR chip erase command sequence */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS4;
+    return HAL_ERROR;
   }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;  
-    
-  /* Send NOR chip erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);  
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-  
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Read NOR flash CFI IDs
-  * @param  hnor: pointer to the NOR handle
-  * @param  pNOR_CFI : pointer to NOR CFI IDs structure  
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  pNOR_CFI  pointer to NOR CFI IDs structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
 {
-  uint32_t deviceaddress = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
+  uint32_t deviceaddress;
+  HAL_NOR_StateTypeDef state;
+
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  state = hnor->State;
+  if (state == HAL_NOR_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
   {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+
+    /* Send read CFI query command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+    /* read the NOR CFI information */
+    pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+    pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+    pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+    pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+
+    /* Check the NOR controller state */
+    hnor->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    return HAL_ERROR;
   }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+
+  return HAL_OK;
+}
+
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User NOR Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+
+  if(pCallback == NULL)
   {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hnor);
+
+  state = hnor->State;
+  if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+    case HAL_NOR_MSP_INIT_CB_ID :
+      hnor->MspInitCallback = pCallback;
+      break;
+    case HAL_NOR_MSP_DEINIT_CB_ID :
+      hnor->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
   }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
   {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }  
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read CFI query command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    /* update return status */
+    status =  HAL_ERROR;
+  }
 
-  /* read the NOR CFI information */
-  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
-  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
-  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
-  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
+  /* Release Lock */
+  __HAL_UNLOCK(hnor);
+  return status;
+}
 
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
+/**
+  * @brief  Unregister a User NOR Callback
+  *         NOR Callback is redirected to the weak (surcharged) predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+
+  /* Process locked */
+  __HAL_LOCK(hnor);
+
+  state = hnor->State;
+  if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+    case HAL_NOR_MSP_INIT_CB_ID :
+      hnor->MspInitCallback = HAL_NOR_MspInit;
+      break;
+    case HAL_NOR_MSP_DEINIT_CB_ID :
+      hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
   __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;
+  return status;
 }
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
 
 /**
   * @}
   */
-  
-/** @defgroup NOR_Exported_Functions_Group3 Control functions 
- *  @brief   management functions 
+
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
+ *  @brief   management functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                         ##### NOR Control functions #####
   ==============================================================================
@@ -840,76 +1095,98 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Enables dynamically NOR write operation.
-  * @param  hnor: pointer to the NOR handle
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
 {
-  /* Process Locked */
-  __HAL_LOCK(hnor);
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_PROTECTED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
 
-  /* Enable write operation */
-  FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); 
-  
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor); 
-  
-  return HAL_OK;  
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Enable write operation */
+    (void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically NOR write operation.
-  * @param  hnor: pointer to the NOR handle
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
 {
-  /* Process Locked */
-  __HAL_LOCK(hnor);
+  /* Check the NOR controller state */
+  if(hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+
+    /* Disable write operation */
+    (void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_PROTECTED;
 
-  /* Update the SRAM controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-    
-  /* Disable write operation */
-  FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); 
-  
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_PROTECTED;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor); 
-  
-  return HAL_OK;  
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @}
-  */  
-  
-/** @defgroup NOR_Exported_Functions_Group4 State functions 
- *  @brief   Peripheral State functions 
+  */
+
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                       ##### NOR State functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection permits to get in run-time the status of the NOR controller 
+    This subsection permits to get in run-time the status of the NOR controller
     and the data flow.
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  return the NOR controller state
-  * @param  hnor: pointer to the NOR handle
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
   * @retval NOR controller state
   */
 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
@@ -919,63 +1196,64 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  Returns the NOR operation status.
-  * @param  hnor: pointer to the NOR handle  
-  * @param  Address: Device address
-  * @param  Timeout: NOR programming Timeout
-  * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  *                the configuration information for NOR module.
+  * @param  Address Device address
+  * @param  Timeout NOR programming Timeout
+  * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
   *         or HAL_NOR_STATUS_TIMEOUT
   */
 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{ 
+{
   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
-  uint16_t tmpSR1 = 0, tmpSR2 = 0;
-  uint32_t tickstart = 0;
+  uint16_t tmpSR1, tmpSR2;
+  uint32_t tickstart;
 
   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
   HAL_NOR_MspWait(hnor, Timeout);
-  
+
   /* Get the NOR memory operation status -------------------------------------*/
-  
+
   /* Get tick */
   tickstart = HAL_GetTick();
-  while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
+  while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
   {
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
-        status = HAL_NOR_STATUS_TIMEOUT; 
-      } 
-    } 
+        status = HAL_NOR_STATUS_TIMEOUT;
+      }
+    }
 
     /* Read NOR status register (DQ6 and DQ5) */
     tmpSR1 = *(__IO uint16_t *)Address;
     tmpSR2 = *(__IO uint16_t *)Address;
 
     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-    if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) 
+    if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
     {
       return HAL_NOR_STATUS_SUCCESS ;
     }
-    
-    if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+
+    if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
     {
       status = HAL_NOR_STATUS_ONGOING;
     }
-    
+
     tmpSR1 = *(__IO uint16_t *)Address;
     tmpSR2 = *(__IO uint16_t *)Address;
 
     /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-    if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) 
+    if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
     {
       return HAL_NOR_STATUS_SUCCESS;
     }
-    if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+    if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
     {
       return HAL_NOR_STATUS_ERROR;
-    } 
+    }
   }
 
   /* Return the operation status */
@@ -985,19 +1263,20 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
 /**
   * @}
   */
-  
 
 /**
   * @}
   */
 
-#endif /* HAL_NOR_MODULE_ENABLED */
 /**
   * @}
   */
 
+#endif /* HAL_NOR_MODULE_ENABLED */
+
 /**
   * @}
   */
 
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pccard.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pccard.c
index 4d29ae72..cb3e7752 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pccard.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pccard.c
@@ -2,110 +2,133 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pccard.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   PCCARD HAL module driver.
-  *          This file provides a generic firmware to drive PCCARD memories mounted 
+  *          This file provides a generic firmware to drive PCCARD memories mounted
   *          as external device.
-  *         
+  *
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
- ===============================================================================  
+ ===============================================================================
    [..]
-     This driver is a generic layered driver which contains a set of APIs used to 
-     control PCCARD/compact flash memories. It uses the FSMC layer functions 
+     This driver is a generic layered driver which contains a set of APIs used to
+      control PCCARD/compact flash memories. It uses the FSMC layer functions
      to interface with PCCARD devices. This driver is used for:
-    
-    (+) PCCARD/Compact Flash memory configuration sequence using the function 
+
+    (+) PCCARD/Compact Flash memory configuration sequence using the function
         HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for
         both common and attribute spaces.
-            
+
     (+) Read PCCARD/Compact Flash memory maker and device IDs using the function
         HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in
-        the CompactFlash_ID structure declared by the function caller. 
-        
+        the CompactFlash_ID structure declared by the function caller.
+
     (+) Access PCCARD/Compact Flash memory by read/write operations using the functions
-        HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() - 
-        HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector. 
-        
+        HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() -
+        HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector.
+
     (+) Perform PCCARD/Compact Flash Reset chip operation using the function
         HAL_PCCARD_Reset()/HAL_CF_Reset.
-        
-    (+) Perform PCCARD/Compact Flash erase sector operation using the function 
+
+    (+) Perform PCCARD/Compact Flash erase sector operation using the function
         HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector.
-    
+
     (+) Read the PCCARD/Compact Flash status operation using the function
         HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus().
-     
+
     (+) You can monitor the PCCARD/Compact Flash  device HAL state by calling
         the function HAL_PCCARD_GetState()/HAL_CF_GetState()
-        
+
    [..]
-     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash 
-         operations. If a PCCARD/Compact Flash device contains different operations 
+     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
+         operations. If a PCCARD/Compact Flash device contains different operations
          and/or implementations, it should be implemented separately.
-   
+
+      *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions @ref HAL_PCCARD_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : PCCARD MspInit.
+        (+) MspDeInitCallback  : PCCARD MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function @ref HAL_PCCARD_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : PCCARD MspInit.
+        (+) MspDeInitCallback  : PCCARD MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the @ref HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_PCCARD_Init
+      and @ref  HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_PCCARD_Init and @ref HAL_PCCARD_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_PCCARD_RegisterCallback before calling @ref HAL_PCCARD_DeInit
+      or @ref HAL_PCCARD_Init function.
+
+      When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
-/** @defgroup PCCARD PCCARD  
+
+/** @defgroup PCCARD PCCARD
   * @brief PCCARD HAL module driver
   * @{
   */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-    
+
 /** @defgroup PCCARD_Private_Defines PCCARD Private Defines
   * @{
   */
-#define PCCARD_TIMEOUT_READ_ID                 (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_READ_WRITE_SECTOR       (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_ERASE_SECTOR            (uint32_t)0x00000400
-#define PCCARD_TIMEOUT_STATUS                  (uint32_t)0x01000000
+#define PCCARD_TIMEOUT_READ_ID                 0x0000FFFFU
+#define PCCARD_TIMEOUT_READ_WRITE_SECTOR       0x0000FFFFU
+#define PCCARD_TIMEOUT_ERASE_SECTOR            0x00000400U
+#define PCCARD_TIMEOUT_STATUS                  0x01000000U
 
 #define PCCARD_STATUS_OK                       (uint8_t)0x58
 #define PCCARD_STATUS_WRITE_OK                 (uint8_t)0x50
 /**
   * @}
-  */ 
-    
+  */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function ----------------------------------------------------------*/
@@ -114,226 +137,250 @@
   * @{
   */
 
-/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
+/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
           ##### PCCARD Initialization and de-initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to initialize/de-initialize
     the PCCARD memory
-  
+
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Perform the PCCARD memory Initialization sequence
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
-  * @param  ComSpaceTiming: Common space timing structure
-  * @param  AttSpaceTiming: Attribute space timing structure
-  * @param  IOSpaceTiming: IO space timing structure     
+  * @param  ComSpaceTiming Common space timing structure
+  * @param  AttSpaceTiming Attribute space timing structure
+  * @param  IOSpaceTiming IO space timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
 {
   /* Check the PCCARD controller state */
-  if(hpccard == NULL)
+  if (hpccard == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
-  if(hpccard->State == HAL_PCCARD_STATE_RESET)
-  {  
+
+  if (hpccard->State == HAL_PCCARD_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hpccard->Lock = HAL_UNLOCKED;
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+    if(hpccard->MspInitCallback == NULL)
+    {
+      hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+    }
+    hpccard->ItCallback = HAL_PCCARD_ITCallback;
+
+    /* Init the low level hardware */
+    hpccard->MspInitCallback(hpccard);
+#else
     /* Initialize the low level hardware (MSP) */
     HAL_PCCARD_MspInit(hpccard);
+#endif
   }
-  
+
   /* Initialize the PCCARD state */
-  hpccard->State = HAL_PCCARD_STATE_BUSY;    
+  hpccard->State = HAL_PCCARD_STATE_BUSY;
 
   /* Initialize PCCARD control Interface */
   FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
-  
+
   /* Init PCCARD common space timing Interface */
   FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
-  
-  /* Init PCCARD attribute space timing Interface */  
+
+  /* Init PCCARD attribute space timing Interface */
   FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
-  
-  /* Init PCCARD IO space timing Interface */  
+
+  /* Init PCCARD IO space timing Interface */
   FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
-  
+
   /* Enable the PCCARD device */
-  __FSMC_PCCARD_ENABLE(hpccard->Instance); 
-  
+  __FSMC_PCCARD_ENABLE(hpccard->Instance);
+
   /* Update the PCCARD state */
-  hpccard->State = HAL_PCCARD_STATE_READY;  
-  
+  hpccard->State = HAL_PCCARD_STATE_READY;
+
   return HAL_OK;
 
 }
 
 /**
   * @brief  Perform the PCCARD memory De-initialization sequence
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval HAL status
   */
 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
 {
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+  if(hpccard->MspDeInitCallback == NULL)
+  {
+    hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hpccard->MspDeInitCallback(hpccard);
+#else
   /* De-Initialize the low level hardware (MSP) */
   HAL_PCCARD_MspDeInit(hpccard);
-   
+#endif
+
   /* Configure the PCCARD registers with their reset values */
   FSMC_PCCARD_DeInit(hpccard->Instance);
-  
+
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(hpccard);
 
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
   * @brief  PCCARD MSP Init
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval None
   */
 __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpccard);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCCARD_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  PCCARD MSP DeInit
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval None
   */
 __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpccard);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCCARD_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
+/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions
+  * @brief    Input Output and memory control functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
                     ##### PCCARD Input and Output functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to use and control the PCCARD memory
-  
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Read Compact Flash's ID.
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
-  * @param  CompactFlash_ID: Compact flash ID structure.  
-  * @param  pStatus: pointer to compact flash status         
+  * @param  CompactFlash_ID Compact flash ID structure.
+  * @param  pStatus pointer to compact flash status
   * @retval HAL status
-  *   
-  */ 
+  *
+  */
 HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
 {
-  uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
+  uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
   uint8_t status = 0;
-  
+
   /* Process Locked */
-  __HAL_LOCK(hpccard);  
-  
+  __HAL_LOCK(hpccard);
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
+
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_BUSY;
- 
 
- 
   /* Initialize the PCCARD status */
-  *pStatus = PCCARD_READY;  
-  
+  *pStatus = PCCARD_READY;
+
   /* Send the Identify Command */
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)  = 0xECEC;
-    
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)  = (uint16_t)0xECEC;
+
   /* Read PCCARD IDs and timeout treatment */
-  do 
+  do
   {
-     /* Read the PCCARD status */
-     status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-     
-     timeout--;
-  }while((status != PCCARD_STATUS_OK) && timeout); 
-  
-  if(timeout == 0)
+    /* Read the PCCARD status */
+    status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
+
+    timeout--;
+  }
+  while ((status != PCCARD_STATUS_OK) && timeout);
+
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
   }
   else
   {
-     /* Read PCCARD ID bytes */
-    for(index = 0; index < 16; index++)
+    /* Read PCCARD ID bytes */
+    for (index = 0U; index < 16U; index++)
     {
       CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
-    }    
+    }
   }
-  
+
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_READY;
-  
+
   /* Process unlocked */
-  __HAL_UNLOCK(hpccard);  
-  
+  __HAL_UNLOCK(hpccard);
+
   return HAL_OK;
 }
-   
+
 /**
   * @brief  Read sector from PCCARD memory
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
-  * @param  pBuffer: pointer to destination read buffer
-  * @param  SectorAddress: Sector address to read
-  * @param  pStatus: pointer to PCCARD status
+  * @param  pBuffer pointer to destination read buffer
+  * @param  SectorAddress Sector address to read
+  * @param  pStatus pointer to PCCARD status
   * @retval HAL status
-  */    
+  */
 HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
 {
-  uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+  uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
   uint8_t status = 0;
 
   /* Process Locked */
   __HAL_LOCK(hpccard);
-  
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  
+
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_BUSY;
 
@@ -341,22 +388,23 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
   *pStatus = PCCARD_READY;
 
   /* Set the parameters to write a sector */
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0xE4A0;  
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0xE4A0;
 
   do
   {
     /* wait till the Status = 0x80 */
     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
-  }while((status == 0x80) && timeout);
-  
-  if(timeout == 0)
+  }
+  while ((status == 0x80U) && timeout);
+
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
   }
-  
+
   timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR;
 
   do
@@ -364,77 +412,79 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
     /* wait till the Status = PCCARD_STATUS_OK */
     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
-  }while((status != PCCARD_STATUS_OK) && timeout);
-  
-  if(timeout == 0)
+  }
+  while ((status != PCCARD_STATUS_OK) && timeout);
+
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
   }
-  
+
   /* Read bytes */
-  for(; index < PCCARD_SECTOR_SIZE; index++)
+  for (; index < PCCARD_SECTOR_SIZE; index++)
   {
     *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
-  } 
+  }
 
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hpccard);
-      
+
   return HAL_OK;
 }
 
 
 /**
   * @brief  Write sector to PCCARD memory
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
-  * @param  pBuffer: pointer to source write buffer
-  * @param  SectorAddress: Sector address to write
-  * @param  pStatus: pointer to PCCARD status
+  * @param  pBuffer pointer to source write buffer
+  * @param  SectorAddress Sector address to write
+  * @param  pStatus pointer to PCCARD status
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus)
 {
-  uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0;
+  uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U;
   uint8_t status = 0;
 
   /* Process Locked */
-  __HAL_LOCK(hpccard);  
-  
+  __HAL_LOCK(hpccard);
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-   
+
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_BUSY;
-    
+
   /* Initialize PCCARD status */
-  *pStatus = PCCARD_READY;  
-    
+  *pStatus = PCCARD_READY;
+
   /* Set the parameters to write a sector */
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
-  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000;
+  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0x30A0;
-  
+
   do
   {
     /* Wait till the Status = PCCARD_STATUS_OK */
     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
-  }while((status != PCCARD_STATUS_OK) && timeout);
-  
-  if(timeout == 0)
+  }
+  while ((status != PCCARD_STATUS_OK) && timeout);
+
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
   }
-  
+
   /* Write bytes */
-  for(; index < PCCARD_SECTOR_SIZE; index++)
+  for (; index < PCCARD_SECTOR_SIZE; index++)
   {
     *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
   }
@@ -444,51 +494,52 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
     /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
-  }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
+  }
+  while ((status != PCCARD_STATUS_WRITE_OK) && timeout);
 
-  if(timeout == 0)
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
-  }  
+  }
 
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_READY;
-  
+
   /* Process unlocked */
-  __HAL_UNLOCK(hpccard);  
-  
+  __HAL_UNLOCK(hpccard);
+
   return HAL_OK;
 }
 
 
 /**
-  * @brief  Erase sector from PCCARD memory 
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @brief  Erase sector from PCCARD memory
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
-  * @param  SectorAddress: Sector address to erase
-  * @param  pStatus: pointer to PCCARD status
+  * @param  SectorAddress Sector address to erase
+  * @param  pStatus pointer to PCCARD status
   * @retval HAL status
   */
 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
 {
   uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR;
   uint8_t status = 0;
-  
+
   /* Process Locked */
-  __HAL_LOCK(hpccard);  
-  
+  __HAL_LOCK(hpccard);
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
 
   /* Update the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_BUSY;
-  
-  /* Initialize PCCARD status */ 
+
+  /* Initialize PCCARD status */
   *pStatus = PCCARD_READY;
-    
+
   /* Set the parameters to write a sector */
   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW)  = 0x00;
   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
@@ -496,45 +547,45 @@ HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16
   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = 0x01;
   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD)     = 0xA0;
   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = ATA_ERASE_SECTOR_CMD;
-  
+
   /* wait till the PCCARD is ready */
   status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-  
-  while((status != PCCARD_STATUS_WRITE_OK) && timeout)
+
+  while ((status != PCCARD_STATUS_WRITE_OK) && timeout)
   {
     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
-  } 
-  
-  if(timeout == 0)
+  }
+
+  if (timeout == 0U)
   {
     *pStatus = PCCARD_TIMEOUT_ERROR;
   }
-  
+
   /* Check the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_READY;
-  
+
   /* Process unlocked */
-  __HAL_UNLOCK(hpccard);   
-  
+  __HAL_UNLOCK(hpccard);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Reset the PCCARD memory 
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @brief  Reset the PCCARD memory
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
 {
   /* Process Locked */
-  __HAL_LOCK(hpccard);  
-  
+  __HAL_LOCK(hpccard);
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
 
   /* Provide a SW reset and Read and verify the:
@@ -546,196 +597,351 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
 
   /* Check the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_BUSY;
-  
-  *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01;
-    
+
+  *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
+
   /* Check the PCCARD controller state */
   hpccard->State = HAL_PCCARD_STATE_READY;
-  
+
   /* Process unlocked */
-  __HAL_UNLOCK(hpccard);  
-  
+  __HAL_UNLOCK(hpccard);
+
   return HAL_OK;
 }
 
 /**
   * @brief  This function handles PCCARD device interrupt request.
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval HAL status
 */
 void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
 {
   /* Check PCCARD interrupt Rising edge flag */
-  if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
+  if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
   {
     /* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+    hpccard->ItCallback(hpccard);
+#else
     HAL_PCCARD_ITCallback(hpccard);
-  
+#endif
+
     /* Clear PCCARD interrupt Rising edge pending bit */
     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
   }
-  
+
   /* Check PCCARD interrupt Level flag */
-  if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
+  if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
   {
     /* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+    hpccard->ItCallback(hpccard);
+#else
     HAL_PCCARD_ITCallback(hpccard);
-  
+#endif
+
     /* Clear PCCARD interrupt Level pending bit */
     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
   }
 
   /* Check PCCARD interrupt Falling edge flag */
-  if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
+  if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
   {
     /* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+    hpccard->ItCallback(hpccard);
+#else
     HAL_PCCARD_ITCallback(hpccard);
-  
+#endif
+
     /* Clear PCCARD interrupt Falling edge pending bit */
     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
   }
-  
+
   /* Check PCCARD interrupt FIFO empty flag */
-  if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
+  if (__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
   {
     /* PCCARD interrupt callback*/
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+    hpccard->ItCallback(hpccard);
+#else
     HAL_PCCARD_ITCallback(hpccard);
-  
+#endif
+
     /* Clear PCCARD interrupt FIFO empty pending bit */
     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
-  }  
+  }
 }
 
 /**
   * @brief  PCCARD interrupt feature callback
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval None
   */
 __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpccard);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_PCCARD_ITCallback could be implemented in the user file
    */
 }
-  
+
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User PCCARD Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hpccard : PCCARD handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_PCCARD_MSP_INIT_CB_ID       PCCARD MspInit callback ID
+  *          @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID     PCCARD MspDeInit callback ID
+  *          @arg @ref HAL_PCCARD_IT_CB_ID             PCCARD IT callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpccard);
+
+  if(hpccard->State == HAL_PCCARD_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case HAL_PCCARD_MSP_INIT_CB_ID :
+      hpccard->MspInitCallback = pCallback;
+      break;
+    case HAL_PCCARD_MSP_DEINIT_CB_ID :
+      hpccard->MspDeInitCallback = pCallback;
+      break;
+    case HAL_PCCARD_IT_CB_ID :
+      hpccard->ItCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(hpccard->State == HAL_PCCARD_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_PCCARD_MSP_INIT_CB_ID :
+      hpccard->MspInitCallback = pCallback;
+      break;
+    case HAL_PCCARD_MSP_DEINIT_CB_ID :
+      hpccard->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpccard);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User PCCARD Callback
+  *         PCCARD Callback is redirected to the weak (surcharged) predefined callback
+  * @param hpccard : PCCARD handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_PCCARD_MSP_INIT_CB_ID       PCCARD MspInit callback ID
+  *          @arg @ref HAL_PCCARD_MSP_DEINIT_CB_ID     PCCARD MspDeInit callback ID
+  *          @arg @ref HAL_PCCARD_IT_CB_ID             PCCARD IT callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpccard);
+
+  if(hpccard->State == HAL_PCCARD_STATE_READY)
+  {
+    switch (CallbackId)
+    {
+    case HAL_PCCARD_MSP_INIT_CB_ID :
+      hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+      break;
+    case HAL_PCCARD_MSP_DEINIT_CB_ID :
+      hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+      break;
+    case HAL_PCCARD_IT_CB_ID :
+      hpccard->ItCallback = HAL_PCCARD_ITCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(hpccard->State == HAL_PCCARD_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_PCCARD_MSP_INIT_CB_ID :
+      hpccard->MspInitCallback = HAL_PCCARD_MspInit;
+      break;
+    case HAL_PCCARD_MSP_DEINIT_CB_ID :
+      hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpccard);
+  return status;
+}
+#endif
+
 /**
   * @}
   */
 
-/** @defgroup PCCARD_Exported_Functions_Group3 State functions 
- *  @brief   Peripheral State functions 
+/** @defgroup PCCARD_Exported_Functions_Group3 State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                       ##### PCCARD State functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection permits to get in run-time the status of the PCCARD controller 
+    This subsection permits to get in run-time the status of the PCCARD controller
     and the data flow.
 
 @endverbatim
   * @{
-  */ 
-  
+  */
+
 /**
   * @brief  return the PCCARD controller state
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
   *                the configuration information for PCCARD module.
   * @retval HAL state
   */
 HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
 {
   return hpccard->State;
-}  
- 
+}
+
 /**
   * @brief  Get the compact flash memory status
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
-  *                the configuration information for PCCARD module.       
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
   * @retval New status of the PCCARD operation. This parameter can be:
-  *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate 
+  *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
   *            a Timeout error
-  *          - CompactFlash_READY: when memory is ready for the next operation          
+  *          - CompactFlash_READY: when memory is ready for the next operation
   */
 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
 {
-  uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0;  
-  
+  uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U;
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_PCCARD_STATUS_ONGOING;
+    return HAL_PCCARD_STATUS_ONGOING;
   }
 
   status_pccard =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
-  
-  while((status_pccard == PCCARD_BUSY) && timeout)
+
+  while ((status_pccard == PCCARD_BUSY) && timeout)
   {
     status_pccard =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
     timeout--;
   }
 
-  if(timeout == 0)
-  {          
-    status_pccard =  PCCARD_TIMEOUT_ERROR;      
-  }   
+  if (timeout == 0U)
+  {
+    status_pccard =  PCCARD_TIMEOUT_ERROR;
+  }
 
   /* Return the operation status */
-  return (HAL_PCCARD_StatusTypeDef) status_pccard;      
+  return (HAL_PCCARD_StatusTypeDef) status_pccard;
 }
-  
+
 /**
   * @brief  Reads the Compact Flash memory status using the Read status command
-  * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
-  *                the configuration information for PCCARD module.      
+  * @param  hpccard pointer to a PCCARD_HandleTypeDef structure that contains
+  *                the configuration information for PCCARD module.
   * @retval The status of the Compact Flash memory. This parameter can be:
   *          - CompactFlash_BUSY: when memory is busy
-  *          - CompactFlash_READY: when memory is ready for the next operation    
-  *          - CompactFlash_ERROR: when the previous operation generates error                
+  *          - CompactFlash_READY: when memory is ready for the next operation
+  *          - CompactFlash_ERROR: when the previous operation generates error
   */
 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
 {
-  uint8_t data = 0, status_pccard = PCCARD_BUSY;
-  
+  uint8_t data = 0U, status_pccard = PCCARD_BUSY;
+
   /* Check the PCCARD controller state */
-  if(hpccard->State == HAL_PCCARD_STATE_BUSY)
+  if (hpccard->State == HAL_PCCARD_STATE_BUSY)
   {
-     return HAL_PCCARD_STATUS_ONGOING;
-  } 
+    return HAL_PCCARD_STATUS_ONGOING;
+  }
 
   /* Read status operation */
   data =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
 
-  if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
+  if ((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
   {
     status_pccard = PCCARD_TIMEOUT_ERROR;
-  } 
-  else if((data & PCCARD_READY) == PCCARD_READY)
+  }
+  else if ((data & PCCARD_READY) == PCCARD_READY)
   {
     status_pccard = PCCARD_READY;
   }
-  
+
   return (HAL_PCCARD_StatusTypeDef) status_pccard;
-}  
- 
+}
+
 /**
   * @}
   */
-  
+
 /**
   * @}
   */
 
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
 /**
   * @}
   */
 
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 /**
   * @}
   */
 
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd.c
index 69f309d6..8097858d 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd.c
@@ -2,16 +2,14 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the USB Peripheral Controller:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
@@ -21,20 +19,20 @@
 
      (#) Declare a PCD_HandleTypeDef handle structure, for example:
          PCD_HandleTypeDef  hpcd;
-        
+
      (#) Fill parameters of Init structure in HCD handle
-  
-     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) 
+
+     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
 
      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using 
+         (##) Enable the PCD/USB Low Level interface clock using
               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
               (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
-           
+
          (##) Initialize the related GPIO clocks
          (##) Configure PCD pin-out
          (##) Configure PCD NVIC interrupt
-    
+
      (#)Associate the Upper USB device stack to the HAL PCD Driver:
          (##) hpcd.pData = pdev;
 
@@ -45,32 +43,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -86,13 +68,15 @@
 
 #ifdef HAL_PCD_MODULE_ENABLED
 
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup PCD_Private_Macros PCD Private Macros
   * @{
-  */ 
+  */
 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
 /**
@@ -103,7 +87,11 @@
 /** @defgroup PCD_Private_Functions PCD Private Functions
   * @{
   */
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 /**
   * @}
   */
@@ -113,15 +101,15 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
   * @{
   */
 
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim 
+@verbatim
  ===============================================================================
             ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
- 
+
 @endverbatim
   * @{
   */
@@ -129,593 +117,1274 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
 /**
   * @brief  Initializes the PCD according to the specified
   *         parameters in the PCD_InitTypeDef and initialize the associated handle.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{ 
-  uint32_t i = 0;
-  
+{
+  USB_OTG_GlobalTypeDef *USBx;
+  uint8_t i;
+
   /* Check the PCD handle allocation */
-  if(hpcd == NULL)
+  if (hpcd == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
 
+  USBx = hpcd->Instance;
+
+  if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hpcd->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->SOFCallback = HAL_PCD_SOFCallback;
+    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+    hpcd->ResetCallback = HAL_PCD_ResetCallback;
+    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+
+    if (hpcd->MspInitCallback == NULL)
+    {
+      hpcd->MspInitCallback = HAL_PCD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hpcd->MspInitCallback(hpcd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
+  }
+
   hpcd->State = HAL_PCD_STATE_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-  HAL_PCD_MspInit(hpcd);
+
+  /* Disable DMA mode for FS instance */
+  if ((USBx->CID & (0x1U << 8)) == 0U)
+  {
+    hpcd->Init.dma_enable = 0U;
+  }
 
   /* Disable the Interrupts */
- __HAL_PCD_DISABLE(hpcd);
- 
- /*Init the Core (common init.) */
- USB_CoreInit(hpcd->Instance, hpcd->Init);
- 
- /* Force Device Mode*/
- USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
- 
- /* Init endpoints structures */
- for (i = 0; i < 15 ; i++)
- {
-   /* Init ep structure */
-   hpcd->IN_ep[i].is_in = 1;
-   hpcd->IN_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->IN_ep[i].type = EP_TYPE_CTRL;
-   hpcd->IN_ep[i].maxpacket =  0;
-   hpcd->IN_ep[i].xfer_buff = 0;
-   hpcd->IN_ep[i].xfer_len = 0;
- }
- 
- for (i = 0; i < 15 ; i++)
- {
-   hpcd->OUT_ep[i].is_in = 0;
-   hpcd->OUT_ep[i].num = i;
-   hpcd->IN_ep[i].tx_fifo_num = i;
-   /* Control until ep is activated */
-   hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
-   hpcd->OUT_ep[i].maxpacket = 0;
-   hpcd->OUT_ep[i].xfer_buff = 0;
-   hpcd->OUT_ep[i].xfer_len = 0;
-   
-   hpcd->Instance->DIEPTXF[i] = 0;
- }
- 
- /* Init Device */
- USB_DevInit(hpcd->Instance, hpcd->Init);
- 
- hpcd->State= HAL_PCD_STATE_READY;
- 
- USB_DevDisconnect (hpcd->Instance);  
- return HAL_OK;
+  __HAL_PCD_DISABLE(hpcd);
+
+  /*Init the Core (common init.) */
+  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  /* Force Device Mode*/
+  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+
+  /* Init endpoints structures */
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    /* Init ep structure */
+    hpcd->IN_ep[i].is_in = 1U;
+    hpcd->IN_ep[i].num = i;
+    hpcd->IN_ep[i].tx_fifo_num = i;
+    /* Control until ep is activated */
+    hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+    hpcd->IN_ep[i].maxpacket = 0U;
+    hpcd->IN_ep[i].xfer_buff = 0U;
+    hpcd->IN_ep[i].xfer_len = 0U;
+  }
+
+  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+  {
+    hpcd->OUT_ep[i].is_in = 0U;
+    hpcd->OUT_ep[i].num = i;
+    /* Control until ep is activated */
+    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+    hpcd->OUT_ep[i].maxpacket = 0U;
+    hpcd->OUT_ep[i].xfer_buff = 0U;
+    hpcd->OUT_ep[i].xfer_len = 0U;
+  }
+
+  /* Init Device */
+  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
+
+  hpcd->USB_Address = 0U;
+  hpcd->State = HAL_PCD_STATE_READY;
+  (void)USB_DevDisconnect(hpcd->Instance);
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the PCD peripheral. 
-  * @param  hpcd: PCD handle
+  * @brief  DeInitializes the PCD peripheral.
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
 {
   /* Check the PCD handle allocation */
-  if(hpcd == NULL)
+  if (hpcd == NULL)
   {
     return HAL_ERROR;
   }
 
   hpcd->State = HAL_PCD_STATE_BUSY;
-  
+
   /* Stop Device */
-  HAL_PCD_Stop(hpcd);
-    
+  (void)HAL_PCD_Stop(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  if (hpcd->MspDeInitCallback == NULL)
+  {
+    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
   /* DeInit the low level hardware */
+  hpcd->MspDeInitCallback(hpcd);
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
   HAL_PCD_MspDeInit(hpcd);
-  
-  hpcd->State = HAL_PCD_STATE_RESET; 
-  
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  hpcd->State = HAL_PCD_STATE_RESET;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_MspDeInit could be implemented in the user file
    */
 }
 
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User USB PCD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = pCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = pCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = pCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = pCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = pCallback;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Unregister an USB PCD Callback
+  *         USB PCD callabck is redirected to the weak predefined callback
+  * @param  hpcd USB PCD handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  /* Setup Legacy weak Callbacks  */
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_SOF_CB_ID :
+        hpcd->SOFCallback = HAL_PCD_SOFCallback;
+        break;
+
+      case HAL_PCD_SETUPSTAGE_CB_ID :
+        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+        break;
+
+      case HAL_PCD_RESET_CB_ID :
+        hpcd->ResetCallback = HAL_PCD_ResetCallback;
+        break;
+
+      case HAL_PCD_SUSPEND_CB_ID :
+        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+        break;
+
+      case HAL_PCD_RESUME_CB_ID :
+        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+        break;
+
+      case HAL_PCD_CONNECT_CB_ID :
+        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+        break;
+
+      case HAL_PCD_DISCONNECT_CB_ID :
+        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+        break;
+
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hpcd->State == HAL_PCD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_PCD_MSPINIT_CB_ID :
+        hpcd->MspInitCallback = HAL_PCD_MspInit;
+        break;
+
+      case HAL_PCD_MSPDEINIT_CB_ID :
+        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data OUT Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data OUT Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Data IN Stage Callback
+  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Data IN Stage Callback
+  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso OUT incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso OUT incomplete Callback
+  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  Register USB PCD Iso IN incomplete Callback
+  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the USB PCD Iso IN incomplete Callback
+  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hpcd);
+
+  if (hpcd->State == HAL_PCD_STATE_READY)
+  {
+    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hpcd);
+
+  return status;
+}
+
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions 
- *  @brief   Data transfers functions 
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Data transfers functions
  *
-@verbatim 
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to manage the PCD data 
+    This subsection provides a set of functions allowing to manage the PCD data
     transfers.
 
 @endverbatim
   * @{
   */
-  
+
 /**
-  * @brief  Start The USB OTG Device.
-  * @param  hpcd: PCD handle
+  * @brief  Start the USB device
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect (hpcd->Instance);  
+{
+  __HAL_LOCK(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
   __HAL_PCD_ENABLE(hpcd);
-  __HAL_UNLOCK(hpcd); 
+  __HAL_UNLOCK(hpcd);
   return HAL_OK;
 }
 
-/**
-  * @brief  Stop The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  __HAL_PCD_DISABLE(hpcd);
-  USB_StopDevice(hpcd->Instance);
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
+/**
+  * @brief  Stop the USB device.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
+{
+  __HAL_LOCK(hpcd);
+  __HAL_PCD_DISABLE(hpcd);
+
+  if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+  {
+    __HAL_UNLOCK(hpcd);
+    return HAL_ERROR;
+  }
+
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
+
   return HAL_OK;
 }
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /**
   * @brief  Handles PCD interrupt request.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 {
   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-  uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
-  uint32_t fifoemptymsk = 0, temp = 0;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i, ep_intr, epint, epnum;
+  uint32_t fifoemptymsk, temp;
   USB_OTG_EPTypeDef *ep;
-    
+
   /* ensure that we are in device mode */
   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
   {
     /* avoid spurious interrupt */
-    if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) 
+    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
     {
       return;
     }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
     {
-     /* incorrect mode, acknowledge the interrupt */
+      /* incorrect mode, acknowledge the interrupt */
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
     }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
     {
-      epnum = 0;
-      
+      epnum = 0U;
+
       /* Read in the device interrupt bits */
       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-      
-      while ( ep_intr )
+
+      while (ep_intr != 0U)
       {
-        if (ep_intr & 0x1)
+        if ((ep_intr & 0x1U) != 0U)
         {
-          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-          
-          if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
+          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
+
+          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
           {
             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-            
-            if(hpcd->Init.dma_enable == 1)
-            {
-              hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); 
-              hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;            
-            }
-            
-            HAL_PCD_DataOutStageCallback(hpcd, epnum);
-            if(hpcd->Init.dma_enable == 1)
-            {
-              if((epnum == 0) && (hpcd->OUT_ep[epnum].xfer_len == 0))
-              {
-                 /* this is ZLP, so prepare EP0 for next setup */
-                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
-              }              
-            }
+            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
           }
-          
-          if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
+
+          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
           {
-            /* Inform the upper layer that a setup packet is available */
-            HAL_PCD_SetupStageCallback(hpcd);
+            /* Class B setup phase done for previous decoded setup */
+            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
           }
-          
-          if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
+
+          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
           {
             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
           }
+
+          /* Clear Status Phase Received interrupt */
+          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+          {
+            if (hpcd->Init.dma_enable == 1U)
+            {
+              (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+            }
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+          }
+
+          /* Clear OUT NAK interrupt */
+          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
+          {
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
+          }
         }
         epnum++;
-        ep_intr >>= 1;
+        ep_intr >>= 1U;
       }
     }
-    
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
+
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
     {
       /* Read in the device interrupt bits */
       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-      
-      epnum = 0;
-      
-      while ( ep_intr )
+
+      epnum = 0U;
+
+      while (ep_intr != 0U)
       {
-        if (ep_intr & 0x1) /* In ITR */
+        if ((ep_intr & 0x1U) != 0U) /* In ITR */
         {
-          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
+          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
 
-           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
+          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
           {
-            fifoemptymsk = 0x1 << epnum;
+            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-            
+
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-            
-            if (hpcd->Init.dma_enable == 1)
+
+            if (hpcd->Init.dma_enable == 1U)
             {
-              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; 
+              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
             }
-                                      
-            HAL_PCD_DataInStageCallback(hpcd, epnum);
 
-            if (hpcd->Init.dma_enable == 1)
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
+#else
+            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+            if (hpcd->Init.dma_enable == 1U)
             {
               /* this is ZLP, so prepare EP0 for next setup */
-              if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0))
+              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
               {
                 /* prepare to rx more setup packets */
-                USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
+                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
               }
-            }           
+            }
           }
-           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
+          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
           {
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
           }
-          if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
+          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
           {
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
           }
-          if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
+          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
           {
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
           }
-          if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
+          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
           {
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
-          }       
-          if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
+          }
+          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
           {
-            PCD_WriteEmptyTxFifo(hpcd , epnum);
+            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);
           }
         }
         epnum++;
-        ep_intr >>= 1;
+        ep_intr >>= 1U;
       }
     }
-    
+
     /* Handle Resume Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
-    {    
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
+    {
       /* Clear the Remote Wake-up Signaling */
       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
 
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ResumeCallback(hpcd);
+#else
       HAL_PCD_ResumeCallback(hpcd);
-      
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
     }
-    
+
     /* Handle Suspend Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
     {
-      if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
       {
-        
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->SuspendCallback(hpcd);
+#else
         HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
       }
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
     }
-
     /* Handle Reset Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
     {
-      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; 
-      USB_FlushTxFifo(hpcd->Instance ,  0 );
-      
-      for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
+
+      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
       {
-        USBx_INEP(i)->DIEPINT = 0xFF;
-        USBx_OUTEP(i)->DOEPINT = 0xFF;
+        USBx_INEP(i)->DIEPINT = 0xFB7FU;
+        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
+        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
       }
-      USBx_DEVICE->DAINT = 0xFFFFFFFF;
-      USBx_DEVICE->DAINTMSK |= 0x10001;
-      
-      if(hpcd->Init.use_dedicated_ep1)
+      USBx_DEVICE->DAINTMSK |= 0x10001U;
+
+      if (hpcd->Init.use_dedicated_ep1 != 0U)
       {
-        USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); 
-        USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);  
+        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
+                                   USB_OTG_DOEPMSK_XFRCM |
+                                   USB_OTG_DOEPMSK_EPDM;
+
+        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
+                                  USB_OTG_DIEPMSK_XFRCM |
+                                  USB_OTG_DIEPMSK_EPDM;
       }
       else
       {
-        USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
-        USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
+                                USB_OTG_DOEPMSK_XFRCM |
+                                USB_OTG_DOEPMSK_EPDM |
+                                USB_OTG_DOEPMSK_OTEPSPRM |
+                                USB_OTG_DOEPMSK_NAKM;
+
+        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
+                                USB_OTG_DIEPMSK_XFRCM |
+                                USB_OTG_DIEPMSK_EPDM;
       }
-      
+
       /* Set Default Address to 0 */
       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-      
+
       /* setup EP0 to receive SETUP packets */
-      USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-        
+      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
+                             (uint8_t *)hpcd->Setup);
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
     }
-    
+
     /* Handle Enumeration done Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
     {
-      USB_ActivateSetup(hpcd->Instance);
-      hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-      
-      if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_HIGH;
-        hpcd->Init.ep0_mps          = USB_OTG_HS_MAX_PACKET_SIZE ;    
-        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
-      }
-      else
-      {
-        hpcd->Init.speed            = USB_OTG_SPEED_FULL;
-        hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;  
-        hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
-      }
-      
+      (void)USB_ActivateSetup(hpcd->Instance);
+      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
+
+      /* Set USB Turnaround time */
+      (void)USB_SetTurnaroundTime(hpcd->Instance,
+                                  HAL_RCC_GetHCLKFreq(),
+                                  (uint8_t)hpcd->Init.speed);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ResetCallback(hpcd);
+#else
       HAL_PCD_ResetCallback(hpcd);
-      
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
     }
 
     /* Handle RxQLevel Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
     {
       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-      
+
       temp = USBx->GRXSTSP;
-      
+
       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-      
-      if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+
+      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
       {
-        if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
+        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
         {
-          USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
+          (void)USB_ReadPacket(USBx, ep->xfer_buff,
+                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+
           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
         }
       }
       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
       {
-        USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
+        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
       }
+      else
+      {
+        /* ... */
+      }
       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
     }
-    
+
     /* Handle SOF Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
     {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SOFCallback(hpcd);
+#else
       HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
     }
-    
+
     /* Handle Incomplete ISO IN Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
     {
-      HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
+      /* Keep application checking the corresponding Iso IN endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
-    } 
-    
+    }
+
     /* Handle Incomplete ISO OUT Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
     {
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
+      /* Keep application checking the corresponding Iso OUT endpoint
+      causing the incomplete Interrupt */
+      epnum = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
-    } 
-    
+    }
+
     /* Handle Connection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
     {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->ConnectCallback(hpcd);
+#else
       HAL_PCD_ConnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
-    } 
-    
+    }
+
     /* Handle Disconnection event Interrupt */
-    if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
     {
       temp = hpcd->Instance->GOTGINT;
-      
-      if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+
+      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
       {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DisconnectCallback(hpcd);
+#else
         HAL_PCD_DisconnectCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
       }
       hpcd->Instance->GOTGINT |= temp;
     }
   }
 }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
 
 /**
   * @brief  Data OUT stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number  
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_DataOutStageCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
-  * @brief  Data IN stage callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @brief  Data IN stage callback
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_DataInStageCallback could be implemented in the user file
-   */ 
+   */
 }
 /**
-  * @brief  Setup stage callback.
-  * @param  hpcd: PCD handle
+  * @brief  Setup stage callback
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_SetupStageCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  USB Start Of Frame callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_SOFCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  USB Reset callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_ResetCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Suspend event callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_SuspendCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Resume event callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_ResumeCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Incomplete ISO OUT callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Incomplete ISO IN callback.
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number  
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval None
   */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(epnum);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Connection event callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_ConnectCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Disconnection event callback.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval None
   */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_PCD_DisconnectCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -725,12 +1394,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
  *  @brief   management functions
  *
-@verbatim 
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the PCD data 
+    This subsection provides a set of functions allowing to control the PCD data
     transfers.
 
 @endverbatim
@@ -738,342 +1407,340 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
   */
 
 /**
-  * @brief  Connect the USB device.
-  * @param  hpcd: PCD handle
+  * @brief  Connect the USB device
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
 {
-  __HAL_LOCK(hpcd); 
-  USB_DevConnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
+  __HAL_LOCK(hpcd);
+  (void)USB_DevConnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
   return HAL_OK;
 }
 
 /**
   * @brief  Disconnect the USB device.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
 {
-  __HAL_LOCK(hpcd); 
-  USB_DevDisconnect(hpcd->Instance);
-  __HAL_UNLOCK(hpcd); 
+  __HAL_LOCK(hpcd);
+  (void)USB_DevDisconnect(hpcd->Instance);
+  __HAL_UNLOCK(hpcd);
   return HAL_OK;
 }
 
 /**
-  * @brief  Set the USB Device address. 
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
+  * @brief  Set the USB Device address.
+  * @param  hpcd PCD handle
+  * @param  address new device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
 {
-  __HAL_LOCK(hpcd); 
-  USB_SetDevAddress(hpcd->Instance, address);
-  __HAL_UNLOCK(hpcd);   
+  __HAL_LOCK(hpcd);
+  hpcd->USB_Address = address;
+  (void)USB_SetDevAddress(hpcd->Instance, address);
+  __HAL_UNLOCK(hpcd);
   return HAL_OK;
 }
 /**
   * @brief  Open and configure an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packet size
-  * @param  ep_type: endpoint type   
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  ep_mps endpoint max packet size
+  * @param  ep_type endpoint type
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
 {
   HAL_StatusTypeDef  ret = HAL_OK;
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
   {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
   }
   else
   {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
   }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
+
+  ep->num = ep_addr & EP_ADDR_MSK;
   ep->maxpacket = ep_mps;
   ep->type = ep_type;
-  if (ep->is_in)
+
+  if (ep->is_in != 0U)
   {
     /* Assign a Tx FIFO */
     ep->tx_fifo_num = ep->num;
   }
   /* Set initial data PID. */
-  if (ep_type == EP_TYPE_BULK )
+  if (ep_type == EP_TYPE_BULK)
   {
-    ep->data_pid_start = 0;
+    ep->data_pid_start = 0U;
   }
-  
-  __HAL_LOCK(hpcd); 
-  USB_ActivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
+
+  __HAL_LOCK(hpcd);
+  (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
   return ret;
 }
 
-
 /**
   * @brief  Deactivate an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{  
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
+{
+  PCD_EPTypeDef *ep;
+
+  if ((ep_addr & 0x80U) == 0x80U)
   {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
   }
   else
   {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
   }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
-  
-  __HAL_LOCK(hpcd); 
-  USB_DeactivateEndpoint(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd);   
+  ep->num   = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
   return HAL_OK;
 }
 
 
 /**
-  * @brief  Receive an amount of data.  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer   
-  * @param  len: amount of data to be received
+  * @brief  Receive an amount of data.
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the reception buffer
+  * @param  len amount of data to be received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
 {
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
   /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
+  ep->xfer_buff = pBuf;
   ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 0;
-  ep->num = ep_addr & 0x7F;
-  
-  if (hpcd->Init.dma_enable == 1)
+  ep->xfer_count = 0U;
+  ep->is_in = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
   {
-    ep->dma_addr = (uint32_t)pBuf;  
+    ep->dma_addr = (uint32_t)pBuf;
   }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7F) == 0 )
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
   {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
   }
   else
   {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
   }
-  __HAL_UNLOCK(hpcd); 
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Get Received Data Size.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @brief  Get Received Data Size
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval Data Size
   */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 {
-  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
 }
 /**
-  * @brief  Send an amount of data.  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer   
-  * @param  len: amount of data to be sent
+  * @brief  Send an amount of data
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
+  * @param  pBuf pointer to the transmission buffer
+  * @param  len amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
 {
-  USB_OTG_EPTypeDef *ep;
-  
-  ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  
+  PCD_EPTypeDef *ep;
+
+  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
   /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
+  ep->xfer_buff = pBuf;
   ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 1;
-  ep->num = ep_addr & 0x7F;
-  
-  if (hpcd->Init.dma_enable == 1)
+  ep->xfer_count = 0U;
+  ep->is_in = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  if (hpcd->Init.dma_enable == 1U)
   {
-    ep->dma_addr = (uint32_t)pBuf;  
+    ep->dma_addr = (uint32_t)pBuf;
   }
-  
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x7F) == 0 )
+
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
   {
-    USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
   }
   else
   {
-    USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
   }
-  
-  __HAL_UNLOCK(hpcd);
-     
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Set a STALL condition over an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @brief  Set a STALL condition over an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 {
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80 & ep_addr) == 0x80)
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+  {
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
   {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
   }
   else
   {
     ep = &hpcd->OUT_ep[ep_addr];
+    ep->is_in = 0U;
   }
-  
-  ep->is_stall = 1;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPSetStall(hpcd->Instance , ep);
-  if((ep_addr & 0x7F) == 0)
+
+  ep->is_stall = 1U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+
+  (void)USB_EPSetStall(hpcd->Instance, ep);
+  if ((ep_addr & EP_ADDR_MSK) == 0U)
   {
-    USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
+    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
   }
-  __HAL_UNLOCK(hpcd); 
-  
+  __HAL_UNLOCK(hpcd);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Clear a STALL condition over in an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @brief  Clear a STALL condition over in an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 {
-  USB_OTG_EPTypeDef *ep;
-  
-  if ((0x80 & ep_addr) == 0x80)
+  PCD_EPTypeDef *ep;
+
+  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
   {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
+    return HAL_ERROR;
+  }
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 1U;
   }
   else
   {
-    ep = &hpcd->OUT_ep[ep_addr];
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+    ep->is_in = 0U;
   }
-  
-  ep->is_stall = 0;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  __HAL_LOCK(hpcd); 
-  USB_EPClearStall(hpcd->Instance , ep);
-  __HAL_UNLOCK(hpcd); 
-    
+
+  ep->is_stall = 0U;
+  ep->num = ep_addr & EP_ADDR_MSK;
+
+  __HAL_LOCK(hpcd);
+  (void)USB_EPClearStall(hpcd->Instance, ep);
+  __HAL_UNLOCK(hpcd);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Flush an endpoint.
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
+  * @brief  Flush an endpoint
+  * @param  hpcd PCD handle
+  * @param  ep_addr endpoint address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
 {
-  __HAL_LOCK(hpcd); 
-  
-  if ((ep_addr & 0x80) == 0x80)
+  __HAL_LOCK(hpcd);
+
+  if ((ep_addr & 0x80U) == 0x80U)
   {
-    USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
   }
   else
   {
-    USB_FlushRxFifo(hpcd->Instance);
+    (void)USB_FlushRxFifo(hpcd->Instance);
   }
-  
-  __HAL_UNLOCK(hpcd); 
-    
+
+  __HAL_UNLOCK(hpcd);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
+  * @brief  Activate remote wakeup signalling
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-    
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
-  {
-    /* Activate Remote wakeup signaling */
-    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
-  }
-  return HAL_OK;  
+  return (USB_ActivateRemoteWakeup(hpcd->Instance));
 }
 
 /**
   * @brief  De-activate remote wakeup signalling.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
-  
-  /* De-activate Remote wakeup signaling */
-  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
-  return HAL_OK;  
+  return (USB_DeActivateRemoteWakeup(hpcd->Instance));
 }
+
 /**
   * @}
   */
-  
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions 
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
  *  @brief   Peripheral State functions
  *
-@verbatim  
+@verbatim
  ===============================================================================
                       ##### Peripheral State functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -1082,13 +1749,14 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
 
 /**
   * @brief  Return the PCD handle state.
-  * @param  hpcd: PCD handle
+  * @param  hpcd PCD handle
   * @retval HAL state
   */
 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
 {
   return hpcd->State;
 }
+
 /**
   * @}
   */
@@ -1101,66 +1769,231 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
 /** @addtogroup PCD_Private_Functions
   * @{
   */
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /**
   * @brief  Check FIFO for the next packet to be loaded.
-  * @param  hpcd: PCD handle
-  * @param  epnum : endpoint number   
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
   * @retval HAL status
   */
 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
 {
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
   USB_OTG_EPTypeDef *ep;
-  int32_t len = 0;
+  uint32_t len;
   uint32_t len32b;
-  uint32_t fifoemptymsk = 0;
+  uint32_t fifoemptymsk;
 
   ep = &hpcd->IN_ep[epnum];
+
+  if (ep->xfer_count > ep->xfer_len)
+  {
+    return HAL_ERROR;
+  }
+
   len = ep->xfer_len - ep->xfer_count;
-  
+
   if (len > ep->maxpacket)
   {
     len = ep->maxpacket;
   }
-  
-  
-  len32b = (len + 3) / 4;
- 
-  while  ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
-          ep->xfer_count < ep->xfer_len &&
-            ep->xfer_len != 0)
+
+  len32b = (len + 3U) / 4U;
+
+  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
+         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
   {
     /* Write the FIFO */
     len = ep->xfer_len - ep->xfer_count;
-    
+
     if (len > ep->maxpacket)
     {
       len = ep->maxpacket;
     }
-    len32b = (len + 3) / 4;
-    
-    USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); 
-    
+    len32b = (len + 3U) / 4U;
+
+    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
+                          (uint8_t)hpcd->Init.dma_enable);
+
     ep->xfer_buff  += len;
     ep->xfer_count += len;
   }
-  
-  if(len <= 0)
+
+  if (ep->xfer_len <= ep->xfer_count)
   {
-    fifoemptymsk = 0x1 << epnum;
+    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
-    
   }
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
 
+
 /**
-  * @}
+  * @brief  process EP OUT transfer complete interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+
+      /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->SetupStageCallback(hpcd);
+#else
+      HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+      (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
+    }
+    else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+    }
+    else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        /* out data packet received over EP0 */
+        hpcd->OUT_ep[epnum].xfer_count =
+          hpcd->OUT_ep[epnum].maxpacket -
+          (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+
+        hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+        if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+        {
+          /* this is ZLP, so prepare EP0 for next setup */
+          (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+        }
+      }
+    }
+    else
+    {
+      /* ... */
+    }
+  }
+  else
+  {
+    if (gSNPSiD == USB_OTG_CORE_ID_310A)
+    {
+      /* StupPktRcvd = 1 this is a setup packet */
+      if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
+      {
+        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+      }
+      else
+      {
+        if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
+        {
+          CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
+        }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
+#else
+      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  process EP OUT setup packet received interrupt.
+  * @param  hpcd PCD handle
+  * @param  epnum endpoint number
+  * @retval HAL status
   */
+static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
+
+  if (hpcd->Init.dma_enable == 1U)
+  {
+    /* StupPktRcvd = 1 pending setup packet int */
+    if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
+        ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+    }
+  }
+  else
+  {
+    if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
+        ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
+    {
+      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
+    }
+  }
+
+  /* Inform the upper layer that a setup packet is available */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+  hpcd->SetupStageCallback(hpcd);
+#else
+  HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+  if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
+  {
+    (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+  }
 
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 #endif /* HAL_PCD_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd_ex.c
index 78c551ae..9ee9d0f8 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd_ex.c
@@ -2,42 +2,24 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
   *          functionalities of the USB Peripheral Controller:
   *           + Extended features functions
   *
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -50,8 +32,10 @@
   * @brief PCD Extended HAL module driver
   * @{
   */
+
 #ifdef HAL_PCD_MODULE_ENABLED
 
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -59,89 +43,125 @@
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
-/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
   * @{
   */
 
 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
-  * @brief    PCDEx control functions 
-  *
-@verbatim  
+  * @brief    PCDEx control functions
+ *
+@verbatim
  ===============================================================================
                  ##### Extended features functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Update FIFO configuration
 
 @endverbatim
   * @{
   */
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /**
   * @brief  Set Tx FIFO
-  * @param  hpcd: PCD handle
-  * @param  fifo: The number of Tx fifo
-  * @param  size: Fifo size
+  * @param  hpcd PCD handle
+  * @param  fifo The number of Tx fifo
+  * @param  size Fifo size
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
 {
-  uint8_t i = 0;
-  uint32_t Tx_Offset = 0;
+  uint8_t i;
+  uint32_t Tx_Offset;
 
   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
-      When a TxFIFO is not used, the Configuration should be as follows: 
+      When a TxFIFO is not used, the Configuration should be as follows:
           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
          --> Txm can use the space allocated for Txn.
          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
          --> Txn should be configured with the minimum space of 16 words
-     The FIFO is used optimally when used TxFIFOs are allocated in the top 
+     The FIFO is used optimally when used TxFIFOs are allocated in the top
          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
-  
+
   Tx_Offset = hpcd->Instance->GRXFSIZ;
-  
-  if(fifo == 0)
+
+  if (fifo == 0U)
   {
-    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
   }
   else
   {
     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
-    for (i = 0; i < (fifo - 1); i++)
+    for (i = 0U; i < (fifo - 1U); i++)
     {
       Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
     }
-    
+
     /* Multiply Tx_Size by 2 to get higher performance */
-    hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);    
+    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
   }
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Set Rx FIFO
-  * @param  hpcd: PCD handle
-  * @param  size: Size of Rx fifo
+  * @param  hpcd PCD handle
+  * @param  size Size of Rx fifo
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
 {
   hpcd->Instance->GRXFSIZ = size;
-  
+
   return HAL_OK;
 }
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 /**
-  * @}
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
   */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
 
 /**
   * @}
   */
 
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 #endif /* HAL_PCD_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c
index 3b293201..eda81c66 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Power Controller (PWR) peripheral:
@@ -13,32 +11,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -63,10 +45,10 @@
 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
   * @{
   */     
-#define PVD_MODE_IT               ((uint32_t)0x00010000)
-#define PVD_MODE_EVT              ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)
+#define PVD_MODE_IT               0x00010000U
+#define PVD_MODE_EVT              0x00020000U
+#define PVD_RISING_EDGE           0x00000001U
+#define PVD_FALLING_EDGE          0x00000002U
 /**
   * @}
   */
@@ -258,7 +240,7 @@ void HAL_PWR_DisableBkUpAccess(void)
 
 /**
   * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
   *        information for the PVD.
   * @note Refer to the electrical characteristics of your device datasheet for
   *         more details about the voltage threshold corresponding to each 
@@ -324,7 +306,7 @@ void HAL_PWR_DisablePVD(void)
 
 /**
   * @brief Enables the Wake-up PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
   *         This parameter can be one of the following values:
   *           @arg PWR_WAKEUP_PIN1
   * @retval None
@@ -340,7 +322,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
 
 /**
   * @brief Disables the Wake-up PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
   *         This parameter can be one of the following values:
   *           @arg PWR_WAKEUP_PIN1
   * @retval None
@@ -362,13 +344,13 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
   * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
   *       systick interrupt when used as time base for Timeout 
   *                
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
+  * @param Regulator Specifies the regulator state in SLEEP mode.
   *            This parameter can be one of the following values:
   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
   * @note This parameter is not used for the STM32F2 family and is kept as parameter
   *       just to maintain compatibility with the lower power families.
-  * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
+  * @param  SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
   *          This parameter can be one of the following values:
   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
@@ -376,6 +358,9 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
   */
 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
   /* Check the parameters */
   assert_param(IS_PWR_REGULATOR(Regulator));
   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
@@ -407,11 +392,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
   *         startup delay is incurred when waking up from Stop mode. 
   *         By keeping the internal regulator ON during Stop mode, the consumption 
   *         is higher although the startup time is reduced.    
-  * @param Regulator: Specifies the regulator state in Stop mode.
+  * @param  Regulator Specifies the regulator state in Stop mode.
   *          This parameter can be one of the following values:
   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+  * @param  STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
   *          This parameter can be one of the following values:
   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c
index 4546ac35..941e7f09 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr_ex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of PWR extension peripheral:           
@@ -12,32 +10,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -58,7 +40,7 @@
 /** @addtogroup PWREx_Private_Constants
   * @{
   */    
-#define PWR_BKPREG_TIMEOUT_VALUE     1000
+#define PWR_BKPREG_TIMEOUT_VALUE     1000U
 /**
   * @}
   */
@@ -68,7 +50,7 @@
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+/** @defgroup PWREx_Exported_Functions PWR Exported Functions
   *  @{
   */
 
@@ -124,7 +106,7 @@
   */
 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
 
@@ -148,7 +130,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
   */
 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c
index c5f94420..66ac9802 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c
@@ -2,21 +2,19 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
   *           + Initialization and de-initialization functions
   *           + Peripheral Control functions
-  *       
-  @verbatim                
+  *
+  @verbatim
   ==============================================================================
                       ##### RCC specific features #####
   ==============================================================================
-    [..]  
-      After reset the device is running from Internal High Speed oscillator 
-      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
       and I-Cache are disabled, and all peripherals are off except internal
       SRAM, Flash and JTAG.
       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
@@ -24,12 +22,12 @@
       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
       (+) All GPIOs are in input floating state, except the JTAG pins which
           are assigned to be used for debug purpose.
-    
-    [..]          
-      Once the device started from reset, the user application has to:        
+
+    [..]
+      Once the device started from reset, the user application has to:
       (+) Configure the clock source to be used to drive the System clock
           (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings  
+      (+) Configure the System clock frequency and Flash settings
       (+) Configure the AHB and APB busses prescalers
       (+) Enable the clock for the peripheral(s) to be used
       (+) Configure the clock source(s) for peripherals which clocks are not
@@ -37,53 +35,35 @@
 
                       ##### RCC Limitations #####
   ==============================================================================
-    [..]  
-      A delay between an RCC peripheral clock enable and the effective peripheral 
-      enabling should be taken into account in order to manage the peripheral read/write 
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
       from/to registers.
       (+) This delay depends on the peripheral mapping.
-      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle 
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
           after the clock enable bit is set on the hardware register
-      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle 
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
           after the clock enable bit is set on the hardware register
 
-    [..]  
-      Possible Workarounds:
-      (#) Enable the peripheral clock sometimes before the peripheral read/write 
-          register is required.
-      (#) For AHB peripheral, insert two dummy read to the peripheral register.
-      (#) For APB peripheral, insert a dummy read to the peripheral register.
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
 
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -104,12 +84,12 @@
 /** @addtogroup RCC_Private_Constants
   * @{
   */
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
+#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s */
 
 /* Private macro -------------------------------------------------------------*/
 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
 #define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8 
+#define MCO1_PIN              GPIO_PIN_8
 
 #define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
 #define MCO2_GPIO_PORT         GPIOC
@@ -121,12 +101,10 @@
 /* Private variables ---------------------------------------------------------*/
 /** @defgroup RCC_Private_Variables RCC Private Variables
   * @{
-  */    
-const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+  */
 /**
   * @}
   */
-
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
@@ -134,16 +112,16 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
   *  @{
   */
 
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
  ===============================================================================
            ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]
       This section provides functions allowing to configure the internal/external oscillators
-      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
        and APB2).
 
     [..] Internal/external clock and PLL configuration
@@ -156,7 +134,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
          (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
              through the PLL as System clock source. Can be used also as RTC clock source.
 
-         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
 
          (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
            (++) The first output is used to generate the high speed system clock (up to 120 MHz)
@@ -164,10 +142,10 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
                 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
 
          (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-             and if a HSE clock failure occurs(HSE used directly or through PLL as System 
+             and if a HSE clock failure occurs(HSE used directly or through PLL as System
              clock source), the System clocks automatically switched to HSI and an interrupt
-             is generated if enabled. The interrupt is linked to the Cortex-M3 NMI 
-             (Non-Maskable Interrupt) exception vector.   
+             is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
+             (Non-Maskable Interrupt) exception vector.
 
          (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
              clock (through a configurable prescaler) on PA8 pin.
@@ -175,54 +153,54 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
          (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
              clock (through a configurable prescaler) on PC9 pin.
 
-    [..] System, AHB and APB busses clocks configuration  
+    [..] System, AHB and APB busses clocks configuration
          (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
              HSE and PLL.
-             The AHB clock (HCLK) is derived from System clock through configurable 
-             prescaler and used to clock the CPU, memory and peripherals mapped 
-             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
-             from AHB clock through configurable prescalers and used to clock 
-             the peripherals mapped on these busses. You can use 
-             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.  
+             The AHB clock (HCLK) is derived from System clock through configurable
+             prescaler and used to clock the CPU, memory and peripherals mapped
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+             from AHB clock through configurable prescalers and used to clock
+             the peripherals mapped on these busses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
 
          -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
            (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
-                from an external clock mapped on the I2S_CKIN pin. 
+                from an external clock mapped on the I2S_CKIN pin.
                 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
            (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
                 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
-                macros to configure this clock. 
+                macros to configure this clock.
            (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
                 to work correctly, while the SDIO require a frequency equal or lower than
                 to 48. This clock is derived of the main PLL through PLLQ divider.
            (+@) IWDG clock which is always the LSI clock.
-       
+
          (#) For the stm32f2xx devices, the maximum
-             frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. 
+             frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
              Depending on the device voltage range, the maximum frequency should
              be adapted accordingly:
- +-------------------------------------------------------------------------------------+     
+ +-------------------------------------------------------------------------------------+
  | Latency       |                HCLK clock frequency (MHz)                           |
- |               |---------------------------------------------------------------------|     
+ |               |---------------------------------------------------------------------|
  |               | voltage range  | voltage range  | voltage range   | voltage range   |
  |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
- |---------------|----------------|----------------|-----------------|-----------------|              
+ |---------------|----------------|----------------|-----------------|-----------------|
  |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
- |---------------|----------------|----------------|-----------------|-----------------|   
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
- |---------------|----------------|----------------|-----------------|-----------------|   
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  |
+ |---------------|----------------|----------------|-----------------|-----------------|
  |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
- |---------------|----------------|----------------|-----------------|-----------------| 
+ |---------------|----------------|----------------|-----------------|-----------------|
  |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
- |---------------|----------------|----------------|-----------------|-----------------| 
+ |---------------|----------------|----------------|-----------------|-----------------|
  |4WS(5CPU cycle)|      NA        |96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
- |---------------|----------------|----------------|-----------------|-----------------| 
- |5WS(6CPU cycle)|      NA        |      NA        |90 < HCLK <= 108 |80 < HCLK <= 96  | 
- |---------------|----------------|----------------|-----------------|-----------------| 
- |6WS(7CPU cycle)|      NA        |      NA        |108 < HCLK <= 120|96 < HCLK <= 112 | 
- |---------------|----------------|----------------|-----------------|-----------------| 
- |7WS(8CPU cycle)|      NA        |      NA        |       NA        |112 < HCLK <= 120| 
- +-------------------------------------------------------------------------------------+    
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|      NA        |      NA        |90 < HCLK <= 108 |80 < HCLK <= 96  |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)|      NA        |      NA        |108 < HCLK <= 120|96 < HCLK <= 112 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |7WS(8CPU cycle)|      NA        |      NA        |       NA        |112 < HCLK <= 120|
+ +-------------------------------------------------------------------------------------+
 @endverbatim
   * @{
   */
@@ -236,57 +214,151 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7,
   *            - CSS, MCO1 and MCO2 OFF
   *            - All interrupts disabled
   * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks  
-  *            - LSI, LSE and RTC clocks 
-  * @retval None
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
   */
-void HAL_RCC_DeInit(void)
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
 {
-  /* Set HSION bit */
-  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); 
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Reset HSEON, CSSON, PLLON, PLLI2S */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); 
-  
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); 
-  
-  /* Reset PLLI2SCFGR register */
-  CLEAR_REG(RCC->PLLI2SCFGR);
-  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-  
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-  
+  uint32_t tickstart;
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[4:0] bits to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Reset CFGR register (HSI is selected as system clock source) */
+  RCC->CFGR = 0x00000000u;
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear CR register in 3 steps: first to clear HSEON, HSEBYP and CSSON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Second step is to clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Once PLL is OFF, reset PLLCFGR register to default value */
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Third step is to clear PLLI2SON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Once PLLI2S is OFF, reset PLLI2SCFGR register to default value */
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+
   /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR); 
+  RCC->CIR = 0x00000000u;
+
+  /* Clear all flags */
+  RCC->CSR = 0xFFFFFFFFu;
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
 }
 
 /**
   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
   *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
   *         contains the configuration information for the RCC Oscillators.
   * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
-  uint32_t tickstart = 0;  
- 
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/ 
+  /*------------------------------- HSE Configuration ------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
@@ -296,42 +368,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till HSE is disabled */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }       
-      }
-      
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-      
+
       /* Check the HSE State */
       if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
       {
-        /* Get Start Tick*/
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
-      
-        /* Wait till HSE is ready */  
+
+        /* Wait till HSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          } 
+          }
         }
       }
       else
       {
-        /* Get Start Tick*/
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
 
         /* Wait till HSE is bypassed or disabled */
@@ -340,7 +397,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          } 
+          }
         }
       }
     }
@@ -351,9 +408,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    
+
     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
     {
       /* When HSI is used as system clock it will not disabled */
@@ -364,7 +421,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       /* Otherwise, just the calibration is allowed */
       else
       {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
       }
     }
@@ -376,19 +433,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
 
-        /* Get Start Tick*/
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
 
-        /* Wait till HSI is ready */  
+        /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          }       
-        } 
-                
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
       }
       else
@@ -396,17 +453,17 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
 
-        /* Get Start Tick*/
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
-      
-        /* Wait till HSI is ready */  
+
+        /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
         {
           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          } 
-        } 
+          }
+        }
       }
     }
   }
@@ -421,106 +478,110 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
-      
-      /* Get Start Tick*/
+
+      /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
+
       /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
-        } 
+        }
       }
     }
     else
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
-      
-      /* Get Start Tick*/
+
+      /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
+
+      /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
-        }       
-      } 
+        }
+      }
     }
   }
-  /*------------------------------ LSE Configuration -------------------------*/ 
+  /*------------------------------ LSE Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
   {
+    FlagStatus       pwrclkchanged = RESET;
+
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-    
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-    
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
     /* Enable write access to Backup domain */
     PWR->CR |= PWR_CR_DBP;
-    
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
     {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
       {
-        return HAL_TIMEOUT;
-      }      
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
     }
-    
-    /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-    
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-    
-    /* Wait till LSE is ready */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }    
-    } 
-    
+
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
     /* Check the LSE State */
     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
     {
-      /* Get Start Tick*/
+      /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
+
+      /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
-        }       
+        }
       }
     }
     else
     {
-      /* Get Start Tick*/
+      /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
+
+      /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
-        }       
+        }
       }
     }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
   }
   /*-------------------------------- PLL Configuration -----------------------*/
   /* Check the parameters */
@@ -529,7 +590,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     /* Check if the PLL is used as system clock or not */
     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    { 
+    {
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
       {
         /* Check the parameters */
@@ -538,52 +599,52 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-      
+
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
-        
-        /* Get Start Tick*/
+
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
+
+        /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
-        }        
+        }
 
         /* Configure the main PLL clock source, multiplication and division factors. */
-        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
-                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
-                                 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN))             | \
-                                 (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
-                                 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
+        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                              | \
+                                RCC_OscInitStruct->PLL.PLLM                                                    | \
+                                (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN))                | \
+                                (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
+                                (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
 
-        /* Get Start Tick*/
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
+
+        /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          } 
+          }
         }
       }
       else
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 
-        /* Get Start Tick*/
+
+        /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
+
+        /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -595,32 +656,50 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     }
     else
     {
-      return HAL_ERROR;
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        uint32_t pllcfgr = RCC->PLLCFGR;
+      
+        if((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+           (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
+           ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
+           (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
+           (READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
+        {
+          return HAL_ERROR;
+        }
+      }
     }
   }
   return HAL_OK;
 }
- 
+
 /**
-  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified 
+  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
   *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
   *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency: FLASH Latency, this parameter depend on device selected
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  * @param  FLatency FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
   *
   * @note   The HSI is used (enabled by hardware) as system clock source after
   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
   *         of failure of the HSE used directly or indirectly as system clock
   *         (if the Clock Security System CSS is enabled).
-  *           
+  *
   * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         clock source is ready (clock stable after startup delay or PLL locked).
   *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready. 
-  *           
+  *         occur when the clock source will be ready.
+  *
   * @note   Depending on the device voltage range, the software has to set correctly
   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
   *         (for more details refer to section above "Initialization/de-initialization functions")
@@ -628,211 +707,137 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   */
 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 {
-  uint32_t tickstart = 0;   
- 
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
   assert_param(IS_FLASH_LATENCY(FLatency));
- 
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
-    must be correctly programmed according to the frequency of the CPU clock 
-    (HCLK) and the supply voltage of the device. */
-  
-  /* Increasing the CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
-  {    
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+     must be correctly programmed according to the frequency of the CPU clock
+     (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
-    
+
     /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+       memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
     {
       return HAL_ERROR;
     }
+  }
 
-    /*-------------------------- HCLK Configuration --------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    /* Set the highest APBx dividers in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
     {
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
     }
 
-    /*------------------------- SYSCLK Configuration ---------------------------*/ 
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-    {    
-      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-      
-      /* HSE is selected as System Clock Source */
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        /* Check the HSE ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* PLL is selected as System Clock Source */
-      else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK))
-      {
-        /* Check the PLL ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* HSI is selected as System Clock Source */
-      else
-      {
-        /* Check the HSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3U));
+    }
 
-      __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }    
+    /* Set the new HCLK clock divider */
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
   }
-  /* Decreasing the CPU frequency */
-  else
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
   {
-    /*-------------------------- HCLK Configuration --------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-    {
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-    }
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 
-    /*------------------------- SYSCLK Configuration -------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-    {    
-      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-      
-      /* HSE is selected as System Clock Source */
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        /* Check the HSE ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* PLL is selected as System Clock Source */
-      else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK))
-      {
-        /* Check the PLL ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* HSI is selected as System Clock Source */
-      else
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
       {
-        /* Check the HSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
-      __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    }
+    /* PLL is selected as System Clock Source */
+    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      /* Check the PLL ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
+        return HAL_ERROR;
       }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
       {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          } 
-        }
+        return HAL_ERROR;
       }
-      else
+    }
+
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
       {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
+        return HAL_TIMEOUT;
       }
     }
-    
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
-    
+
     /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+       memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
     {
       return HAL_ERROR;
     }
- }
+  }
 
-  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
   }
-  
-  /*-------------------------- PCLK2 Configuration ---------------------------*/ 
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
   }
 
-  /* Configure the source of time base considering new system clocks settings*/
-  HAL_InitTick (TICK_INT_PRIORITY);
-  
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+
+  /* Configure the source of time base considering new system clocks settings */
+  HAL_InitTick (uwTickPrio);
+
   return HAL_OK;
 }
 
@@ -840,17 +845,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   * @}
   */
 
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   RCC clocks control functions 
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
+    This subsection provides a set of functions allowing to control the RCC Clocks
     frequencies.
-      
+
 @endverbatim
   * @{
   */
@@ -858,11 +863,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 /**
   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
   * @note   PA8/PC9 should be configured in alternate function mode.
-  * @param  RCC_MCOx: specifies the output direction for the clock source.
+  * @param  RCC_MCOx specifies the output direction for the clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
-  * @param  RCC_MCOSource: specifies the clock source to output.
+  * @param  RCC_MCOSource specifies the clock source to output.
   *          This parameter can be one of the following values:
   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
@@ -872,7 +877,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  RCC_MCODiv: specifies the MCOx prescaler.
+  * @param  RCC_MCODiv specifies the MCOx prescaler.
   *          This parameter can be one of the following values:
   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
@@ -891,28 +896,28 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
   if(RCC_MCOx == RCC_MCO1)
   {
     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-    
+
     /* MCO1 Clock Enable */
     __MCO1_CLK_ENABLE();
-    
-    /* Configure the MCO1 pin in alternate function mode */    
+
+    /* Configure the MCO1 pin in alternate function mode */
     GPIO_InitStruct.Pin = MCO1_PIN;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-    
+
     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
   }
   else
   {
     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-    
+
     /* MCO2 Clock Enable */
     __MCO2_CLK_ENABLE();
-    
+
     /* Configure the MCO2 pin in alternate function mode */
     GPIO_InitStruct.Pin = MCO2_PIN;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -920,9 +925,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
     GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-    
+
     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
   }
 }
 
@@ -931,8 +936,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
   *         is automatically disabled and an interrupt is generated to inform the
   *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
-  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.  
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
   * @retval None
   */
 void HAL_RCC_EnableCSS(void)
@@ -951,14 +956,14 @@ void HAL_RCC_DisableCSS(void)
 
 /**
   * @brief  Returns the SYSCLK frequency
-  *        
-  * @note   The system frequency computed by this function is not the real 
-  *         frequency in the chip. It is calculated based on the predefined 
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
   *         constant and the selected clock source:
   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
   * @note     (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
   *               16 MHz) but the real value may vary depending on the variations
   *               in voltage and temperature.
@@ -966,23 +971,23 @@ void HAL_RCC_DisableCSS(void)
   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
   *                frequency of the crystal used. Otherwise, this function may
   *                have wrong result.
-  *                  
+  *
   * @note   The result of this function could be not correct when using fractional
   *         value for HSE crystal.
-  *           
-  * @note   This function can be used by the user application to compute the 
+  *
+  * @note   This function can be used by the user application to compute the
   *         baudrate for the communication peripherals or configure other parameters.
-  *           
+  *
   * @note   Each time SYSCLK changes, this function must be called to update the
   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *         
-  *               
+  *
+  *
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
-  uint32_t pllm = 0, pllvco = 0, pllp = 0;
-  uint32_t sysclockfreq = 0;
+  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
+  uint32_t sysclockfreq = 0U;
 
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (RCC->CFGR & RCC_CFGR_SWS)
@@ -1005,15 +1010,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
       {
         /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
       }
       else
       {
         /* HSI used as PLL clock source */
-        pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));    
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
       }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
-      
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
       sysclockfreq = pllvco/pllp;
       break;
     }
@@ -1027,34 +1032,33 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
 }
 
 /**
-  * @brief  Returns the HCLK frequency     
+  * @brief  Returns the HCLK frequency
   * @note   Each time HCLK changes, this function must be called to update the
   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated within this function
   * @retval HCLK frequency
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
   return SystemCoreClock;
 }
 
 /**
-  * @brief  Returns the PCLK1 frequency     
+  * @brief  Returns the PCLK1 frequency
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
   */
 uint32_t HAL_RCC_GetPCLK1Freq(void)
-{  
+{
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
 }
 
 /**
-  * @brief  Returns the PCLK2 frequency     
+  * @brief  Returns the PCLK2 frequency
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK2 frequency
@@ -1062,13 +1066,13 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
 uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-} 
+  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+}
 
 /**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
+  * @brief  Configures the RCC_OscInitStruct according to the internal
   * RCC configuration registers.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that 
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
   * will be configured.
   * @retval None
   */
@@ -1076,7 +1080,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
   /* Set all possible values for the Oscillator type parameter ---------------*/
   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-  
+
   /* Get the HSE configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
   {
@@ -1090,7 +1094,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
   }
-  
+
   /* Get the HSI configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
   {
@@ -1100,9 +1104,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
   }
-  
+
   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-  
+
   /* Get the LSE configuration -----------------------------------------------*/
   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
   {
@@ -1116,7 +1120,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
   }
-  
+
   /* Get the LSI configuration -----------------------------------------------*/
   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
   {
@@ -1126,7 +1130,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
   }
-  
+
   /* Get the PLL configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
   {
@@ -1139,37 +1143,37 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
 }
 
 /**
-  * @brief  Configures the RCC_ClkInitStruct according to the internal 
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
   * RCC configuration registers.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that 
+  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
   * will be configured.
-  * @param  pFLatency: Pointer on the Flash Latency.
+  * @param  pFLatency Pointer on the Flash Latency.
   * @retval None
   */
 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
 {
   /* Set all possible values for the Clock type parameter --------------------*/
   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-   
-  /* Get the SYSCLK configuration --------------------------------------------*/ 
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-  
-  /* Get the HCLK configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 
-  
-  /* Get the APB1 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
-  
-  /* Get the APB2 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-  
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/   
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 }
 
 /**
@@ -1198,7 +1202,7 @@ __weak void HAL_RCC_CSSCallback(void)
 {
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RCC_CSSCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c
index e8a23263..528b6ad4 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   Extension RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
@@ -12,32 +10,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -75,7 +57,7 @@
 @verbatim   
  ===============================================================================
                 ##### Extended Peripheral Control functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides a set of functions allowing to control the RCC Clocks 
     frequencies.
@@ -92,7 +74,7 @@
 /**
   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
   *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
   *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
   *         
   * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case 
@@ -103,8 +85,8 @@
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
-  uint32_t tickstart = 0;
-  uint32_t tmpreg1 = 0;
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
     
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@@ -151,9 +133,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
   /*--------------------------------------------------------------------------*/
   
-  /*----------------------------- RTC configuration --------------------------*/
+  /*---------------------------- RTC configuration ---------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {    
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+    
     /* Enable Power Clock*/
     __HAL_RCC_PWR_CLK_ENABLE();
     
@@ -168,10 +153,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
-      }      
+      }
     }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */
-    if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
     {
       /* Store the content of BDCR register before the reset of Backup Domain */
       tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -180,8 +166,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = tmpreg1;
-      /* Wait for LSERDY if LSE was enabled */
-      if(HAL_IS_BIT_SET(tmpreg1, RCC_BDCR_LSERDY))
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
       {
         /* Get tick */
         tickstart = HAL_GetTick();
@@ -195,8 +182,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
           }
         }
       }
-      __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
     }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
   }
   /*--------------------------------------------------------------------------*/
 
@@ -206,7 +193,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 /**
   * @brief  Configures the RCC_OscInitStruct according to the internal 
   * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that 
   * will be configured.
   * @retval None
   */
@@ -217,7 +204,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   /* Set all possible values for the extended clock type parameter------------*/
   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
   
-  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
   PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
   PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
   
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rng.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rng.c
index ff629841..5e54018b 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rng.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rng.c
@@ -2,15 +2,13 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rng.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   RNG HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Random Number Generator (RNG) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
+  *           + Initialization and configuration functions
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -18,43 +16,81 @@
   [..]
       The RNG HAL driver can be used as follows:
 
-      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro 
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
           in HAL_RNG_MspInit().
       (#) Activate the RNG peripheral using HAL_RNG_Init() function.
-      (#) Wait until the 32 bit Random Number Generator contains a valid 
-          random data using (polling/interrupt) mode.   
+      (#) Wait until the 32 bit Random Number Generator contains a valid
+          random data using (polling/interrupt) mode.
       (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
-  
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
+    Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+
+    [..]
+    For specific callback ReadyDataCallback, use dedicated register callbacks:
+    respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+
+    [..]
+    By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    example @ref HAL_RNG_ErrorCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
+    and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
+    or @ref HAL_RNG_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -63,24 +99,26 @@
   * @{
   */
 
-/** @addtogroup RNG 
+#if defined (RNG)
+
+/** @addtogroup RNG
+  * @brief RNG HAL module driver.
   * @{
   */
 
 #ifdef HAL_RNG_MODULE_ENABLED
 
-
 /* Private types -------------------------------------------------------------*/
 /* Private defines -----------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNG_Private_Constants
+/** @defgroup RNG_Private_Constants RNG Private Constants
   * @{
   */
-#define RNG_TIMEOUT_VALUE     2
+#define RNG_TIMEOUT_VALUE     2U
 /**
   * @}
-  */ 
+  */
 /* Private macros ------------------------------------------------------------*/
 /* Private functions prototypes ----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -91,18 +129,18 @@
   */
 
 /** @addtogroup RNG_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions
+ *  @brief   Initialization and configuration functions
  *
 @verbatim
  ===============================================================================
-          ##### Initialization and de-initialization functions #####
+          ##### Initialization and configuration functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the RNG according to the specified parameters 
+      (+) Initialize the RNG according to the specified parameters
           in the RNG_InitTypeDef and create the associated handle
       (+) DeInitialize the RNG peripheral
       (+) Initialize the RNG MSP
-      (+) DeInitialize RNG MSP 
+      (+) DeInitialize RNG MSP
 
 @endverbatim
   * @{
@@ -110,83 +148,121 @@
 
 /**
   * @brief  Initializes the RNG peripheral and creates the associated handle.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
-{ 
+{
   /* Check the RNG handle allocation */
-  if(hrng == NULL)
+  if (hrng == NULL)
   {
     return HAL_ERROR;
   }
-  
-  __HAL_LOCK(hrng);
-  
-  if(hrng->State == HAL_RNG_STATE_RESET)
-  {  
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hrng->Lock = HAL_UNLOCKED;
+
+    hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
+    hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
+
+    if (hrng->MspInitCallback == NULL)
+    {
+      hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hrng->MspInitCallback(hrng);
+  }
+#else
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
     /* Init the low level hardware */
     HAL_RNG_MspInit(hrng);
   }
-  
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
   /* Change RNG peripheral state */
   hrng->State = HAL_RNG_STATE_BUSY;
 
+
   /* Enable the RNG Peripheral */
   __HAL_RNG_ENABLE(hrng);
 
   /* Initialize the RNG state */
   hrng->State = HAL_RNG_STATE_READY;
-  
-  __HAL_UNLOCK(hrng);
-  
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the RNG peripheral. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @brief  DeInitializes the RNG peripheral.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
-{ 
+{
   /* Check the RNG handle allocation */
-  if(hrng == NULL)
+  if (hrng == NULL)
   {
     return HAL_ERROR;
   }
+
   /* Disable the RNG Peripheral */
   CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
-  
+
   /* Clear RNG interrupt status flags */
   CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
-  
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->MspDeInitCallback == NULL)
+  {
+    hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hrng->MspDeInitCallback(hrng);
+#else
   /* DeInit the low level hardware */
   HAL_RNG_MspDeInit(hrng);
-  
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
   /* Update the RNG state */
-  hrng->State = HAL_RNG_STATE_RESET; 
+  hrng->State = HAL_RNG_STATE_RESET;
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
 
   /* Release Lock */
   __HAL_UNLOCK(hrng);
-  
+
   /* Return the function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval None
   */
 __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_MspInit must be implemented in the user file.
    */
@@ -194,32 +270,261 @@ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
 
 /**
   * @brief  DeInitializes the RNG MSP.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval None
   */
 __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_MspDeInit must be implemented in the user file.
    */
 }
 
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User RNG Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_RNG_ERROR_CB_ID :
+      hrng->ErrorCallback = pCallback;
+      break;
+
+    case HAL_RNG_MSPINIT_CB_ID :
+      hrng->MspInitCallback = pCallback;
+      break;
+
+    case HAL_RNG_MSPDEINIT_CB_ID :
+      hrng->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_RNG_MSPINIT_CB_ID :
+      hrng->MspInitCallback = pCallback;
+      break;
+
+    case HAL_RNG_MSPDEINIT_CB_ID :
+      hrng->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  Unregister an RNG Callback
+  *         RNG callabck is redirected to the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_RNG_ERROR_CB_ID :
+      hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
+      break;
+
+    case HAL_RNG_MSPINIT_CB_ID :
+      hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+      break;
+
+    case HAL_RNG_MSPDEINIT_CB_ID :
+      hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
+      break;
+
+    default :
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+    case HAL_RNG_MSPINIT_CB_ID :
+      hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+      break;
+
+    case HAL_RNG_MSPDEINIT_CB_ID :
+      hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
+      break;
+
+    default :
+      /* Update the error code */
+      hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  Register Data Ready RNG Callback
+  *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @param  pCallback pointer to the Data Ready Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Data Ready RNG Callback
+  *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
 /** @addtogroup RNG_Exported_Functions_Group2
- *  @brief   Peripheral Control functions 
+ *  @brief   Peripheral Control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Get the 32 bit Random number
       (+) Get the 32 bit Random number with interrupt enabled
-      (+) Handle RNG interrupt request 
+      (+) Handle RNG interrupt request
 
 @endverbatim
   * @{
@@ -227,158 +532,100 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
 
 /**
   * @brief  Generates a 32-bit random number.
-  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
+  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag
   *         is automatically cleared.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
-  * @param  random32bit: pointer to generated random number variable if successful.
+  * @param  random32bit pointer to generated random number variable if successful.
   * @retval HAL status
   */
 
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
 {
-  uint32_t tickstart = 0;    
+  uint32_t tickstart;
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Process Locked */
-  __HAL_LOCK(hrng); 
-  
+  __HAL_LOCK(hrng);
+
   /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
+  if (hrng->State == HAL_RNG_STATE_READY)
   {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
 
     /* Get tick */
     tickstart = HAL_GetTick();
-  
+
     /* Check if data register contains valid random data */
-    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
-      {    
-        hrng->State = HAL_RNG_STATE_ERROR;
-
+      if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
         /* Process Unlocked */
         __HAL_UNLOCK(hrng);
-      
-        return HAL_TIMEOUT;
-      } 
+        return HAL_ERROR;
+      }
     }
-  
+
     /* Get a 32bit Random number */
     hrng->RandomNumber = hrng->Instance->DR;
     *random32bit = hrng->RandomNumber;
-  
+
     hrng->State = HAL_RNG_STATE_READY;
   }
   else
   {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
     status = HAL_ERROR;
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(hrng);
-  
+
   return status;
 }
 
 /**
   * @brief  Generates a 32-bit random number in interrupt mode.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Process Locked */
   __HAL_LOCK(hrng);
-  
+
   /* Check RNG peripheral state */
-  if(hrng->State == HAL_RNG_STATE_READY)
+  if (hrng->State == HAL_RNG_STATE_READY)
   {
-    /* Change RNG peripheral state */  
-    hrng->State = HAL_RNG_STATE_BUSY;  
-  
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrng);
-    
-    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
     __HAL_RNG_ENABLE_IT(hrng);
   }
   else
   {
     /* Process Unlocked */
     __HAL_UNLOCK(hrng);
-    
+
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
     status = HAL_ERROR;
   }
-  
+
   return status;
 }
 
-/**
-  * @brief  Handles RNG interrupt request.
-  * @note   In the case of a clock error, the RNG is no more able to generate 
-  *         random numbers because the PLL48CLK clock is not correct. User has 
-  *         to check that the clock controller is correctly configured to provide
-  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
-  *         The clock error has no impact on the previously generated 
-  *         random numbers, and the RNG_DR register contents can be used.
-  * @note   In the case of a seed error, the generation of random numbers is 
-  *         interrupted as long as the SECS bit is '1'. If a number is 
-  *         available in the RNG_DR register, it must not be used because it may 
-  *         not have enough entropy. In this case, it is recommended to clear the 
-  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
-  *         the RNG peripheral to reinitialize and restart the RNG.
-  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
-  *         or CEIS are set.  
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
-  *                the configuration information for RNG.
-  * @retval None
-
-  */
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
-{
-  /* RNG clock error interrupt occurred */
-  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
-  { 
-    /* Change RNG peripheral state */
-    hrng->State = HAL_RNG_STATE_ERROR;
-  
-    HAL_RNG_ErrorCallback(hrng);
-    
-    /* Clear the clock error flag */
-    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
-    
-  }
-  
-  /* Check RNG data ready interrupt occurred */    
-  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
-  {
-    /* Generate random number once, so disable the IT */
-    __HAL_RNG_DISABLE_IT(hrng);
-    
-    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
-    hrng->RandomNumber = hrng->Instance->DR;
-    
-    if(hrng->State != HAL_RNG_STATE_ERROR)
-    {
-      /* Change RNG peripheral state */
-      hrng->State = HAL_RNG_STATE_READY; 
-      
-      /* Data Ready callback */ 
-      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
-    } 
-  }
-} 
-
 /**
   * @brief  Returns generated random number in polling mode (Obsolete)
   *         Use HAL_RNG_GenerateRandomNumber() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval Random value
   */
@@ -386,61 +633,151 @@ uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
 {
   if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
   {
-    return hrng->RandomNumber; 
+    return hrng->RandomNumber;
   }
   else
   {
-    return 0;
+    return 0U;
   }
 }
 
 /**
   * @brief  Returns a 32-bit random number with interrupt enabled (Obsolete),
   *         Use HAL_RNG_GenerateRandomNumber_IT() API instead.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval 32-bit random number
   */
 uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
 {
-  uint32_t random32bit = 0;
-  
+  uint32_t random32bit = 0U;
+
   /* Process locked */
   __HAL_LOCK(hrng);
-  
-  /* Change RNG peripheral state */  
-  hrng->State = HAL_RNG_STATE_BUSY;  
-  
-  /* Get a 32bit Random number */ 
+
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Get a 32bit Random number */
   random32bit = hrng->Instance->DR;
-  
-  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
-  __HAL_RNG_ENABLE_IT(hrng); 
-  
-  /* Return the 32 bit random number */   
+
+  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+  __HAL_RNG_ENABLE_IT(hrng);
+
+  /* Return the 32 bit random number */
   return random32bit;
 }
 
 /**
-  * @brief  Read latest generated random number. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @brief  Handles RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate
+  *         random numbers because the PLL48CLK clock is not correct. User has
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+  *         The clock error has no impact on the previously generated
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is
+  *         interrupted as long as the SECS bit is '1'. If a number is
+  *         available in the RNG_DR register, it must not be used because it may
+  *         not have enough entropy. In this case, it is recommended to clear the
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  uint32_t rngclockerror = 0U;
+
+  /* RNG clock error interrupt occurred */
+  if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+    rngclockerror = 1U;
+  }
+  else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+    rngclockerror = 1U;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (rngclockerror == 1U)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback */
+    hrng->ErrorCallback(hrng);
+#else
+    /* Call legacy weak Error callback */
+    HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+  }
+
+  /* Check RNG data ready interrupt occurred */
+  if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */
+    hrng->RandomNumber = hrng->Instance->DR;
+
+    if (hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+      /* Call registered Data Ready callback */
+      hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+      /* Call legacy weak Data Ready callback */
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Read latest generated random number.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval random value
   */
 uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
 {
-  return(hrng->RandomNumber);
+  return (hrng->RandomNumber);
 }
 
 /**
-  * @brief  Data Ready callback in non-blocking mode. 
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @brief  Data Ready callback in non-blocking mode.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
-  * @param  random32bit: generated random number.
+  * @param  random32bit generated random number.
   * @retval None
   */
 __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  UNUSED(random32bit);
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_ReadyDataCallback must be implemented in the user file.
    */
@@ -448,12 +785,14 @@ __weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32
 
 /**
   * @brief  RNG error callbacks.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval None
   */
 __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_RNG_ErrorCallback must be implemented in the user file.
    */
@@ -462,16 +801,16 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
   * @}
   */
 
-  
+
 /** @addtogroup RNG_Exported_Functions_Group3
- *  @brief   Peripheral State functions 
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral State functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection permits to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -480,7 +819,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
 
 /**
   * @brief  Returns the RNG state.
-  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *                the configuration information for RNG.
   * @retval HAL state
   */
@@ -489,6 +828,16 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
   return hrng->State;
 }
 
+/**
+  * @brief  Return the RNG handle error code.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval RNG Error Code
+*/
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+{
+  /* Return RNG Error Code */
+  return hrng->ErrorCode;
+}
 /**
   * @}
   */
@@ -497,11 +846,14 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
   * @}
   */
 
+
 #endif /* HAL_RNG_MODULE_ENABLED */
 /**
   * @}
   */
 
+#endif /* RNG */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc.c
index be4fbee3..a89c2868 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc.c
@@ -2,26 +2,24 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Real Time Clock (RTC) peripheral:
   *           + Initialization and de-initialization functions
   *           + RTC Time and Date functions
   *           + RTC Alarm functions
-  *           + Peripheral Control functions   
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
               ##### Backup Domain Operating Condition #####
   ==============================================================================
-  [..] The real-time clock (RTC), the RTC backup registers, and the backup 
-       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
+  [..] The real-time clock (RTC), the RTC backup registers, and the backup
+       SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
        VDD supply is powered off.
-       To retain the content of the RTC backup registers, backup SRAM, and supply 
-       the RTC when VDD is turned off, VBAT pin can be connected to an optional 
+       To retain the content of the RTC backup registers, backup SRAM, and supply
+       the RTC when VDD is turned off, VBAT pin can be connected to an optional
        standby voltage supplied by a battery or by another source.
 
   [..] To allow the RTC operating even when the main digital supply (VDD) is turned
@@ -30,110 +28,146 @@
     (#) The LSE oscillator
     (#) The backup SRAM when the low power backup regulator is enabled
     (#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
-  
+
   [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
        the following pins are available:
     (#) PC14 and PC15 can be used as either GPIO or LSE pins
     (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
     (#) PI8 can be used as a GPIO or as the RTC_AF2 pin
-  
-  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT 
+
+  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
        because VDD is not present), the following pins are available:
     (#) PC14 and PC15 can be used as LSE pins only
-    (#) PC13 can be used as the RTC_AF1 pin 
+    (#) PC13 can be used as the RTC_AF1 pin
     (#) PI8 can be used as the RTC_AF2 pin
-             
+
                    ##### Backup Domain Reset #####
   ==================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register 
+  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
        to their reset values. The BKPSRAM is not affected by this reset. The only
-       way to reset the BKPSRAM is through the Flash interface by requesting 
+       way to reset the BKPSRAM is through the Flash interface by requesting
        a protection level change from 1 to 0.
   [..] A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the 
-        RCC Backup domain control register (RCC_BDCR). 
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.  
+    (#) Software reset, triggered by setting the BDRST bit in the
+        RCC Backup domain control register (RCC_BDCR).
+    (#) VDD or VBAT power on, if both supplies have previously been powered off.
 
                    ##### Backup Domain Access #####
   ==================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data 
-       registers and backup SRAM) is protected against possible unwanted write 
-       accesses. 
+  [..] After reset, the backup domain (RTC registers, RTC backup data
+       registers and backup SRAM) is protected against possible unwanted write
+       accesses.
   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
     (+) Enable the Power Controller (PWR) APB1 interface clock using the
         __HAL_RCC_PWR_CLK_ENABLE() function.
     (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
     (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
     (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-  
-  
+
+
                   ##### How to use this driver #####
   ==================================================================
-  [..] 
+  [..]
     (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
         format using the HAL_RTC_Init() function.
-  
+
   *** Time and Date configuration ***
   ===================================
-  [..] 
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() 
+  [..]
+    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
         and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. 
-  
+    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
   *** Alarm configuration ***
   ===========================
   [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. 
+    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
         You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-  
+
                   ##### RTC and low power modes #####
   ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate 
+  [..] The MCU can be woken up from a low power mode by an RTC alternate
        function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
        RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and 
+       These RTC alternate functions can wake up the system from the Stop and
        Standby low power modes.
-  [..] The system can also wake up from low power modes without depending 
-       on an external interrupt (Auto-wake-up mode), by using the RTC alarm 
+  [..] The system can also wake up from low power modes without depending
+       on an external interrupt (Auto-wake-up mode), by using the RTC alarm
        or the RTC wake-up events.
-  [..] The RTC provides a programmable time base for waking up from the 
+  [..] The RTC provides a programmable time base for waking up from the
        Stop or Standby mode at regular intervals.
        Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
        is LSE or LSI.
-     
+
+  *** Callback registration ***
+  =============================================
+  [..]
+  The compilation define  USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+  [..]
+  Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
+    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
+    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
+    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
+    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
+    (+) MspInitCallback              : RTC MspInit callback.
+    (+) MspDeInitCallback            : RTC MspDeInit callback.
+  [..]	
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+  [..]
+  Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) AlarmAEventCallback          : RTC Alarm A Event callback.
+    (+) AlarmBEventCallback          : RTC Alarm B Event callback.
+    (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
+    (+) WakeUpTimerEventCallback     : RTC WakeUpTimer Event callback.
+    (+) Tamper1EventCallback         : RTC Tamper 1 Event callback.
+    (+) MspInitCallback              : RTC MspInit callback.
+    (+) MspDeInitCallback            : RTC MspDeInit callback.
+  [..]
+  By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+  all callbacks are set to the corresponding weak functions :
+  examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+  Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+  in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+  (not registered beforehand).
+  If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+  [..]
+  Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+  or @ref HAL_RTC_Init() function.
+  [..]
+  When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
    @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -160,200 +194,247 @@
   * @{
   */
 
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-@verbatim    
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the 
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
-         RTC registers Write protection, enter and exit the RTC initialization mode, 
+   [..] This section provides functions allowing to initialize and configure the
+         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+         RTC registers Write protection, enter and exit the RTC initialization mode,
          RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. 
+         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
              It is split into 2 programmable prescalers to minimize power consumption.
              (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the 
+             (++) When both prescalers are used, it is recommended to configure the
                  asynchronous prescaler to a high value to minimize power consumption.
          (#) All RTC registers are Write protected. Writing to the RTC registers
              is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter 
-             initialization mode. In this mode, the calendar counter is stopped 
-             and its value can be updated. When the initialization sequence is 
+         (#) To configure the RTC Calendar, user application should enter
+             initialization mode. In this mode, the calendar counter is stopped
+             and its value can be updated. When the initialization sequence is
              complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar 
-             initialization, calendar update or after wake-up from low power modes 
-             the software must first clear the RSF flag. The software must then 
-             wait until it is set again before reading the calendar, which means 
-             that the calendar registers have been correctly copied into the 
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function 
+         (#) To read the calendar through the shadow registers after Calendar
+             initialization, calendar update or after wake-up from low power modes
+             the software must first clear the RSF flag. The software must then
+             wait until it is set again before reading the calendar, which means
+             that the calendar registers have been correctly copied into the
+             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
              implements the above software sequence (RSF clear and RSF check).
- 
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Initializes the RTC peripheral
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
 {
   /* Check the RTC peripheral state */
-  if(hrtc == NULL)
+  if (hrtc == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
   assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
+  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
+  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
   assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-    
-  if(hrtc->State == HAL_RTC_STATE_RESET)
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+  if (hrtc->State == HAL_RTC_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hrtc->Lock = HAL_UNLOCKED;
+
+    hrtc->AlarmAEventCallback          =  HAL_RTC_AlarmAEventCallback;        /* Legacy weak AlarmAEventCallback      */
+    hrtc->AlarmBEventCallback          =  HAL_RTCEx_AlarmBEventCallback;      /* Legacy weak AlarmBEventCallback      */
+    hrtc->TimeStampEventCallback       =  HAL_RTCEx_TimeStampEventCallback;   /* Legacy weak TimeStampEventCallback   */
+    hrtc->WakeUpTimerEventCallback     =  HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+    hrtc->Tamper1EventCallback         =  HAL_RTCEx_Tamper1EventCallback;     /* Legacy weak Tamper1EventCallback     */
+
+    if (hrtc->MspInitCallback == NULL)
+    {
+      hrtc->MspInitCallback = HAL_RTC_MspInit;
+    }
+    /* Init the low level hardware */
+    hrtc->MspInitCallback(hrtc);
+
+    if (hrtc->MspDeInitCallback == NULL)
+    {
+      hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+    }
+  }
+#else
+  if (hrtc->State == HAL_RTC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrtc->Lock = HAL_UNLOCKED;
+
     /* Initialize RTC MSP */
     HAL_RTC_MspInit(hrtc);
   }
-  
-  /* Set RTC state */  
-  hrtc->State = HAL_RTC_STATE_BUSY;  
-       
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+  /* Set RTC state */
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state */
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
-  { 
+  {
     /* Clear RTC_CR FMT, OSEL and POL Bits */
     hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
     /* Set RTC_CR register */
     hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-    
+
     /* Configure the RTC PRER */
     hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
-    
+    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-    
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
     hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
-    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 
-    
+    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state */
     hrtc->State = HAL_RTC_STATE_READY;
-    
+
     return HAL_OK;
   }
 }
 
 /**
-  * @brief  DeInitializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  DeInitializes the RTC peripheral
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @note   This function doesn't reset the RTC Backup Data registers.   
+  * @note   This function doesn't reset the RTC Backup Data registers.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state */
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
+
     return HAL_ERROR;
-  }  
+  }
   else
   {
     /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000;
-    hrtc->Instance->DR = (uint32_t)0x00002101;
+    hrtc->Instance->TR = 0x00000000U;
+    hrtc->Instance->DR = 0x00002101U;
     /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= (uint32_t)0x00000007;
+    hrtc->Instance->CR &= 0x00000007U;
 
     /* Get tick */
     tickstart = HAL_GetTick();
 
     /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+    while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      { 
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
         /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-        
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
         /* Set RTC state */
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        
+
         return HAL_TIMEOUT;
-      }      
+      }
     }
-    
+
     /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000;
-    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
-    hrtc->Instance->PRER = (uint32_t)0x007F00FF;
-    hrtc->Instance->CALIBR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
-    
+    hrtc->Instance->CR &= 0x00000000U;
+    hrtc->Instance->WUTR = 0x0000FFFFU;
+    hrtc->Instance->PRER = 0x007F00FFU;
+    hrtc->Instance->CALIBR = 0x00000000U;
+    hrtc->Instance->ALRMAR = 0x00000000U;
+    hrtc->Instance->ALRMBR = 0x00000000U;
+
     /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000;
-    
+    hrtc->Instance->ISR = 0x00000000U;
+
     /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAFCR = 0x00000000;
+    hrtc->Instance->TAFCR = 0x00000000U;
 
-    if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
     {
       /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
       hrtc->State = HAL_RTC_STATE_ERROR;
 
       return HAL_ERROR;
-    }    
+    }
   }
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+  if (hrtc->MspDeInitCallback == NULL)
+  {
+    hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC.*/
+  hrtc->MspDeInitCallback(hrtc);
+
+#else
   /* De-Initialize RTC MSP */
   HAL_RTC_MspDeInit(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_RESET; 
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+  hrtc->State = HAL_RTC_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(hrtc);
@@ -361,30 +442,222 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
   return HAL_OK;
 }
 
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User RTC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hrtc RTC handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
+  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
+  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
+  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      Wake-Up Timer Event Callback ID
+  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_MSPINIT_CB_ID                Msp Init callback ID
+  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID              Msp DeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hrtc);
+
+  if (HAL_RTC_STATE_READY == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_ALARM_A_EVENT_CB_ID :
+        hrtc->AlarmAEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_ALARM_B_EVENT_CB_ID :
+        hrtc->AlarmBEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+        hrtc->TimeStampEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+        hrtc->WakeUpTimerEventCallback = pCallback;
+        break;
+
+      case HAL_RTC_TAMPER1_EVENT_CB_ID :
+        hrtc->Tamper1EventCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RTC_STATE_RESET == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an RTC Callback
+  *         RTC callabck is redirected to the weak predefined callback
+  * @param  hrtc RTC handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID          Alarm A Event Callback ID
+  *          @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID          Alarm B Event Callback ID
+  *          @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID        TimeStamp Event Callback ID
+  *          @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID      Wake-Up Timer Event Callback ID
+  *          @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID          Tamper 1 Callback ID
+  *          @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+  *          @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrtc);
+
+  if (HAL_RTC_STATE_READY == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_ALARM_A_EVENT_CB_ID :
+        hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback;         /* Legacy weak AlarmAEventCallback    */
+        break;
+
+      case HAL_RTC_ALARM_B_EVENT_CB_ID :
+        hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback;          /* Legacy weak AlarmBEventCallback */
+        break;
+
+      case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+        hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback;    /* Legacy weak TimeStampEventCallback    */
+        break;
+
+      case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+        hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+        break;
+
+      case HAL_RTC_TAMPER1_EVENT_CB_ID :
+        hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback;         /* Legacy weak Tamper1EventCallback   */
+        break;
+
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = HAL_RTC_MspInit;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RTC_STATE_RESET == hrtc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RTC_MSPINIT_CB_ID :
+        hrtc->MspInitCallback = HAL_RTC_MspInit;
+        break;
+
+      case HAL_RTC_MSPDEINIT_CB_ID :
+        hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrtc);
+
+  return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
 /**
   * @brief  Initializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval None
   */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DeInitializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval None
   */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -394,11 +667,11 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
 /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
  *  @brief   RTC Time and Date functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                  ##### RTC Time and Date functions #####
- ===============================================================================  
- 
+ ===============================================================================
+
  [..] This section provides functions allowing to configure Time and Date features
 
 @endverbatim
@@ -407,309 +680,306 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
 
 /**
   * @brief  Sets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  sTime Pointer to Time structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BIN: Binary data format
   *            @arg RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
 {
-  uint32_t tmpreg = 0;
-  
- /* Check the parameters */
+  uint32_t tmpreg = 0U;
+
+  /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
   assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
   assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-  
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
+
+  if (Format == RTC_FORMAT_BIN)
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
       assert_param(IS_RTC_HOUR12(sTime->Hours));
       assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    } 
+    }
     else
     {
-      sTime->TimeFormat = 0x00;
+      sTime->TimeFormat = 0x00U;
       assert_param(IS_RTC_HOUR24(sTime->Hours));
     }
     assert_param(IS_RTC_MINUTES(sTime->Minutes));
     assert_param(IS_RTC_SECONDS(sTime->Seconds));
-    
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
+                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
                         ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16));  
+                        (((uint32_t)sTime->TimeFormat) << 16U));
   }
   else
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
-      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); 
-    } 
+      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
+      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+    }
     else
     {
-      sTime->TimeFormat = 0x00;
+      sTime->TimeFormat = 0x00U;
       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
     }
     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
-              ((uint32_t)(sTime->Minutes) << 8) | \
+    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
+              ((uint32_t)(sTime->Minutes) << 8U) | \
               ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16));   
+              ((uint32_t)(sTime->TimeFormat) << 16U));
   }
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state */
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
   {
     /* Set the RTC_TR register */
     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-     
+
     /* Clear the bits to be configured */
     hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
-    
+
     /* Configure the RTC_CR register */
     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-    
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
     if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
     {
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
+
       hrtc->State = HAL_RTC_STATE_ERROR;
-        
-      /* Process Unlocked */ 
+
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
-        
+
       return HAL_ERROR;
     }
-    
+
     /* Enable the write protection for RTC registers */
     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-    
-   hrtc->State = HAL_RTC_STATE_READY;
-  
-   __HAL_UNLOCK(hrtc); 
-     
-   return HAL_OK;
+
+    hrtc->State = HAL_RTC_STATE_READY;
+
+    __HAL_UNLOCK(hrtc);
+
+    return HAL_OK;
   }
 }
 
 /**
   * @brief  Gets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  sTime Pointer to Time structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BIN: Binary data format
   *            @arg RTC_FORMAT_BCD: BCD data format
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
+  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
   * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
   * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
 {
-  uint32_t tmpreg = 0;
+  uint32_t tmpreg = 0U;
 
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
-  
+
   /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); 
-  
+  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
   /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
   sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); 
-  
+  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+
   /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
+  if (Format == RTC_FORMAT_BIN)
   {
     /* Convert the time structure parameters to Binary format */
     sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
     sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  
+    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
   }
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Sets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
+  * @param  sDate Pointer to date structure
+  * @param  Format specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN: Binary data format 
+  *            @arg RTC_FORMAT_BIN: Binary data format
   *            @arg RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
 {
-  uint32_t datetmpreg = 0;
-  
- /* Check the parameters */
+  uint32_t datetmpreg = 0U;
+
+  /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
-  
- /* Process Locked */ 
- __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
-  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+
+  /* Process Locked */
+  __HAL_LOCK(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_BUSY;
+
+  if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
   {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~0x10) + (uint8_t)0x0A);
   }
-  
+
   assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-  
-  if(Format == RTC_FORMAT_BIN)
-  {   
+
+  if (Format == RTC_FORMAT_BIN)
+  {
     assert_param(IS_RTC_YEAR(sDate->Year));
     assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date)); 
-    
-   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                 ((uint32_t)sDate->WeekDay << 13));   
+    assert_param(IS_RTC_DATE(sDate->Date));
+
+    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
+                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
+                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+                  ((uint32_t)sDate->WeekDay << 13U));
   }
   else
-  {   
+  {
     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
-    assert_param(IS_RTC_MONTH(datetmpreg));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
-    assert_param(IS_RTC_DATE(datetmpreg));
-    
-    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
-                  (((uint32_t)sDate->Month) << 8) | \
+    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
+    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
+                  (((uint32_t)sDate->Month) << 8U) | \
                   ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13));  
+                  (((uint32_t)sDate->WeekDay) << 13U));
   }
 
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state*/
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
   {
     /* Set the RTC_DR register */
     hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-    
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
-    if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {   
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+
+    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+    {
       /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-        
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
       hrtc->State = HAL_RTC_STATE_ERROR;
-        
-      /* Process Unlocked */ 
+
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
-        
+
       return HAL_ERROR;
     }
-    
+
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     hrtc->State = HAL_RTC_STATE_READY ;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
-    return HAL_OK;    
+
+    return HAL_OK;
   }
 }
 
 /**
   * @brief  Gets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  sDate Pointer to Date structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *            @arg RTC_FORMAT_BIN:  Binary data format 
+  *            @arg RTC_FORMAT_BIN:  Binary data format
   *            @arg RTC_FORMAT_BCD:  BCD data format
-  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
+  * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
   * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
   * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
 {
-  uint32_t datetmpreg = 0;
+  uint32_t datetmpreg = 0U;
 
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
-          
+
   /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); 
+  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
 
   /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
+  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
   sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); 
+  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
 
   /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
-  {    
+  if (Format == RTC_FORMAT_BIN)
+  {
     /* Convert the date structure parameters to Binary format */
     sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
     sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  
+    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
   }
   return HAL_OK;
 }
@@ -721,11 +991,11 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
 /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
  *  @brief   RTC Alarm functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                  ##### RTC Alarm functions #####
- ===============================================================================  
- 
+ ===============================================================================
+
  [..] This section provides functions allowing to configure Alarm feature
 
 @endverbatim
@@ -733,38 +1003,38 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
   */
 /**
   * @brief  Sets the specified RTC Alarm.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  sAlarm Pointer to Alarm structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BIN: Binary data format
   *             @arg RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
 {
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0;
-  
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
 
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
+
+  if (Format == RTC_FORMAT_BIN)
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
+    }
     else
     {
       sAlarm->AlarmTime.TimeFormat = 0x00;
@@ -772,8 +1042,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
     }
     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
     {
       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
     }
@@ -781,84 +1051,81 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
     {
       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
     }
-    
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
+              ((uint32_t)sAlarm->AlarmMask));
   }
   else
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
+    }
     else
     {
       sAlarm->AlarmTime.TimeFormat = 0x00;
       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
     }
-    
+
     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
     }
     else
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }  
-    
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+    }
+
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));   
+              ((uint32_t)sAlarm->AlarmMask));
   }
 
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
+  if (sAlarm->Alarm == RTC_ALARM_A)
   {
     /* Disable the Alarm A interrupt */
     __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
 
     /* Get tick */
     tickstart = HAL_GetTick();
 
     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }   
+      }
     }
-    
+
     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
     /* Configure the Alarm state: Enable Alarm */
     __HAL_RTC_ALARMA_ENABLE(hrtc);
@@ -867,81 +1134,81 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
   {
     /* Disable the Alarm B interrupt */
     __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
 
     /* Get tick */
     tickstart = HAL_GetTick();
 
     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }  
-    }    
-    
+      }
+    }
+
     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
     /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc); 
+    __HAL_RTC_ALARMB_ENABLE(hrtc);
   }
-  
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   
-  
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Sets the specified RTC Alarm with Interrupt 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Sets the specified RTC Alarm with Interrupt
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
+  * @param  sAlarm Pointer to Alarm structure
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BIN: Binary data format
   *             @arg RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
 {
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+  __IO uint32_t count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
+
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
   assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
   assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-      
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == RTC_FORMAT_BIN)
+
+  if (Format == RTC_FORMAT_BIN)
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
       assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
+    }
     else
     {
       sAlarm->AlarmTime.TimeFormat = 0x00;
@@ -949,8 +1216,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     }
     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
     {
       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
     }
@@ -958,55 +1225,52 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     {
       assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
     }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
               ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
+              ((uint32_t)sAlarm->AlarmMask));
   }
   else
   {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
       assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
+    }
     else
     {
       sAlarm->AlarmTime.TimeFormat = 0x00;
       assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
     }
-    
+
     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+    if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
     }
     else
     {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
     }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
               ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
               ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));     
+              ((uint32_t)sAlarm->AlarmMask));
   }
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
+  if (sAlarm->Alarm == RTC_ALARM_A)
   {
     /* Disable the Alarm A interrupt */
     __HAL_RTC_ALARMA_DISABLE(hrtc);
@@ -1014,31 +1278,29 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     /* Clear flag alarm A */
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
     /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if (count-- == 0U)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }  
+      }
     }
-    
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
+
     hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
     /* Configure the Alarm state: Enable Alarm */
     __HAL_RTC_ALARMA_ENABLE(hrtc);
     /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
   }
   else
   {
@@ -1048,25 +1310,23 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     /* Clear flag alarm B */
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
     /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if (count-- == 0)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }  
+      }
     }
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
 
     hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
     /* Configure the Alarm state: Enable Alarm */
@@ -1077,25 +1337,25 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
 
   /* RTC Alarm Interrupt Configuration: EXTI configuration */
   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-  
+
   EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
-  
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Deactivate the specified RTC Alarm 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Deactivate the specified RTC Alarm
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Alarm: Specifies the Alarm.
+  * @param  Alarm Specifies the Alarm.
   *          This parameter can be one of the following values:
   *            @arg RTC_ALARM_A:  AlarmA
   *            @arg RTC_ALARM_B:  AlarmB
@@ -1103,192 +1363,204 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
   */
 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
 {
-  uint32_t tickstart = 0;
-  
+  uint32_t tickstart = 0U;
+
   /* Check the parameters */
   assert_param(IS_RTC_ALARM(Alarm));
-  
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  if(Alarm == RTC_ALARM_A)
+
+  if (Alarm == RTC_ALARM_A)
   {
     /* AlarmA */
     __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
 
     /* Get tick */
     tickstart = HAL_GetTick();
 
     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      { 
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }      
+      }
     }
   }
   else
   {
     /* AlarmB */
     __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
+
+    /* In case of interrupt mode is used, the interrupt source must disabled */
+    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
 
     /* Get tick */
     tickstart = HAL_GetTick();
 
     /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
+
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-        
+
         return HAL_TIMEOUT;
-      }    
+      }
     }
   }
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
-  return HAL_OK; 
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrtc);
+
+  return HAL_OK;
 }
-           
+
 /**
   * @brief  Gets the RTC Alarm value and masks.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
+  * @param  sAlarm Pointer to Date structure
+  * @param  Alarm Specifies the Alarm.
   *          This parameter can be one of the following values:
   *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB  
-  * @param  Format: Specifies the format of the entered parameters.
+  *             @arg RTC_ALARM_B: AlarmB
+  * @param  Format Specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *             @arg RTC_FORMAT_BIN: Binary data format 
+  *             @arg RTC_FORMAT_BIN: Binary data format
   *             @arg RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
 {
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
   assert_param(IS_RTC_ALARM(Alarm));
-  
-  if(Alarm == RTC_ALARM_A)
+
+  if (Alarm == RTC_ALARM_A)
   {
     /* AlarmA */
     sAlarm->Alarm = RTC_ALARM_A;
-    
+
     tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
   }
   else
   {
     sAlarm->Alarm = RTC_ALARM_B;
-    
+
     tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
   }
-    
+
   /* Fill the structure with the read parameters */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
+  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
   sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
+  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
   sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
   sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-    
-  if(Format == RTC_FORMAT_BIN)
+
+  if (Format == RTC_FORMAT_BIN)
   {
     sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
     sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
     sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
     sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }  
-    
+  }
+
   return HAL_OK;
 }
 
 /**
   * @brief  This function handles Alarm interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+  /* Get the AlarmA interrupt source enable status */
+  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
   {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
+    /* Get the pending status of the AlarmA Interrupt */
+    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
     {
-      /* AlarmA callback */ 
+      /* AlarmA callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      hrtc->AlarmAEventCallback(hrtc);
+#else
       HAL_RTC_AlarmAEventCallback(hrtc);
-      
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
       /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
     }
   }
-  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
+
+  /* Get the AlarmB interrupt source enable status */
+  if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
   {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
+    /* Get the pending status of the AlarmB Interrupt */
+    if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
     {
-      /* AlarmB callback */ 
+      /* AlarmB callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      hrtc->AlarmBEventCallback(hrtc);
+#else
       HAL_RTCEx_AlarmBEventCallback(hrtc);
-      
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
       /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
+      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
     }
   }
-  
+
   /* Clear the EXTI's line Flag for RTC Alarm */
   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
+  hrtc->State = HAL_RTC_STATE_READY;
 }
 
 /**
   * @brief  Alarm A callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
    */
@@ -1296,50 +1568,50 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
 
 /**
   * @brief  This function handles AlarmA Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
 {
-  uint32_t tickstart = 0; 
+  uint32_t tickstart = 0U;
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
   {
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
   /* Clear the Alarm interrupt pending bit */
   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK;  
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ *  @brief   Peripheral Control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                      ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Wait for RTC Time and Date Synchronization
@@ -1349,37 +1621,37 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
   */
 
 /**
-  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
   *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the 
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. 
-  * @note   To read the calendar through the shadow registers after Calendar 
-  *         initialization, calendar update or after wake-up from low power modes 
-  *         the software must first clear the RSF flag. 
-  *         The software must then wait until it is set again before reading 
-  *         the calendar, which means that the calendar registers have been 
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wake-up from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   /* Clear RSF flag */
   hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
   /* Wait the registers to be synchronised */
-  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+  while ((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
   {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-    {       
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+    {
       return HAL_TIMEOUT;
-    } 
+    }
   }
 
   return HAL_OK;
@@ -1389,13 +1661,13 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
   * @}
   */
 
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions 
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                      ##### Peripheral State functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Get RTC state
@@ -1405,11 +1677,11 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
   */
 /**
   * @brief  Returns the RTC state.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval HAL state
   */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
 {
   return hrtc->State;
 }
@@ -1422,16 +1694,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
   * @brief  Enters the RTC Initialization mode.
   * @note   The RTC Initialization mode is write protected, use the
   *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
 {
-  uint32_t tickstart = 0; 
-  
+  uint32_t tickstart = 0U;
+
   /* Check if the Initialization mode is set */
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
   {
     /* Set the Initialization mode */
     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
@@ -1440,45 +1712,45 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
     tickstart = HAL_GetTick();
 
     /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
-      {       
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
         return HAL_TIMEOUT;
-      } 
+      }
     }
   }
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
 
 
 /**
   * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
+  * @param  Value Byte to be converted
   * @retval Converted byte
   */
 uint8_t RTC_ByteToBcd2(uint8_t Value)
 {
-  uint32_t bcdhigh = 0;
-  
-  while(Value >= 10)
+  uint32_t bcdhigh = 0U;
+
+  while (Value >= 10)
   {
     bcdhigh++;
     Value -= 10;
   }
-  
-  return  ((uint8_t)(bcdhigh << 4) | Value);
+
+  return ((uint8_t)(bcdhigh << 4U) | Value);
 }
 
 /**
   * @brief  Converts from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
+  * @param  Value BCD value to be converted
   * @retval Converted word
   */
 uint8_t RTC_Bcd2ToByte(uint8_t Value)
 {
-  uint32_t tmp = 0;
+  uint32_t tmp = 0U;
   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
   return (tmp + (Value & (uint8_t)0x0F));
 }
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc_ex.c
index cf3a30cb..784b1944 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc_ex.c
@@ -2,99 +2,78 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
   *           + RTC Time Stamp functions
-  *           + RTC Tamper functions 
+  *           + RTC Tamper functions
   *           + RTC Wake-up functions
   *           + Extension Control functions
-  *           + Extension RTC features functions    
-  *         
+  *           + Extension RTC features functions
+  *
   @verbatim
   ==============================================================================
                   ##### How to use this driver #####
   ==============================================================================
-  [..] 
+  [..]
     (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
+    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
         format using the HAL_RTC_Init() function.
-  
+
   *** RTC Wake-up configuration ***
   ================================
-  [..] 
-    (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
-        function. You can also configure the RTC Wake-up timer in interrupt mode 
-        using the HAL_RTC_SetWakeUpTimer_IT() function.
-    (+) To read the RTC Wake-up Counter register, use the HAL_RTC_GetWakeUpTimer() 
+  [..]
+    (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+        function. You can also configure the RTC Wake-up timer in interrupt mode
+        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+    (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer()
         function.
-  
+
   *** TimeStamp configuration ***
   ===============================
   [..]
-    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the 
-        HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with 
-        interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
+    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
+        HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+        interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
+    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
         function.
     (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13)
-        or RTC_AF2 (PI8) depending on the value of TSINSEL bit in 
-        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTimeStamp()
-        or HAL_RTC_SetTimeStamp_IT() function.
-  
+        or RTC_AF2 (PI8) depending on the value of TSINSEL bit in
+        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp()
+        or HAL_RTCEx_SetTimeStamp_IT() function.
+
   *** Tamper configuration ***
   ============================
   [..]
-    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
-        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
-        value, sampling frequency, precharge or discharge and Pull-UP using the 
-        HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt 
-        mode using HAL_RTC_SetTamper_IT() function.
+    (+) Enable the RTC Tamper and configure the trigger using the HAL_RTCEx_SetTamper() function.
+        You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT() function.
     (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
-        or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in 
-        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTC_SetTamper()
-        or HAL_RTC_SetTamper_IT() function.
-  
+        or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
+        RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTamper()
+        or HAL_RTCEx_SetTamper_IT() function.
+
   *** Backup Data Registers configuration ***
   ===========================================
   [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
-        function.  
-    (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
+    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
         function.
-     
+    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
+        function.
+
    @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -117,18 +96,18 @@
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+/** @defgroup RTCEx_Exported_Functions RTC Exported Functions
   * @{
-  */  
+  */
 
 /** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
   *  @brief   RTC TimeStamp and Tamper functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                  ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================  
- 
+ ===============================================================================
+
  [..] This section provides functions allowing to configure TimeStamp feature
 
 @endverbatim
@@ -137,17 +116,17 @@
 
 /**
   * @brief  Sets TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @note   This API must be called before enabling the TimeStamp feature.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
   *         activated.
   *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
   *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
   *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+  * @param  RTC_TimeStampPin specifies the RTC TimeStamp Pin.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
   *             @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC TimeStamp Pin.
@@ -155,58 +134,58 @@
   */
 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
 {
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-  
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Get the RTC_CR register and clear the bits to be configured */
   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-    
-  tmpreg|= TimeStampEdge;
-  
+
+  tmpreg |= TimeStampEdge;
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
-  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
-  
+  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
+
   /* Configure the Time Stamp TSEDGE and Enable bits */
   hrtc->Instance->CR = (uint32_t)tmpreg;
-  
+
   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-  
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);    
-  
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Sets TimeStamp with Interrupt. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Sets TimeStamp with Interrupt.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  * @param  TimeStampEdge Specifies the pin edge on which the TimeStamp is
   *         activated.
   *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
+  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
   *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
+  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
   *                                         falling edge of the related pin.
-  * @param  RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+  * @param  RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
   *          This parameter can be one of the following values:
   *             @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
   *             @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC TimeStamp Pin.
@@ -214,105 +193,108 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
   */
 HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
 {
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
   assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
   assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
-  
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Get the RTC_CR register and clear the bits to be configured */
   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-  
+
   tmpreg |= TimeStampEdge;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Configure the Time Stamp TSEDGE and Enable bits */
   hrtc->Instance->CR = (uint32_t)tmpreg;
-  
+
   hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL;
-  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); 
-  
+  hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin);
+
+  /* Clear RTC Timestamp flag */
+  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
   __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-  
-  /* Enable IT timestamp */ 
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-  
+
+  /* Enable IT timestamp */
+  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
+
   /* RTC timestamp Interrupt Configuration: EXTI configuration */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-  
+
   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-  
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-  
-  hrtc->State = HAL_RTC_STATE_READY;  
-  
-  /* Process Unlocked */ 
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Deactivates TimeStamp. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Deactivates TimeStamp.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
 {
-  uint32_t tmpreg = 0;
-  
-  /* Process Locked */ 
+  uint32_t tmpreg = 0U;
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* In case of interrupt mode is used, the interrupt source must disabled */ 
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
   __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-  
+
   /* Get the RTC_CR register and clear the bits to be configured */
   tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-  
+
   /* Configure the Time Stamp TSEDGE and Enable bits */
   hrtc->Instance->CR = (uint32_t)tmpreg;
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- 
-  hrtc->State = HAL_RTC_STATE_READY;  
-  
-  /* Process Unlocked */ 
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Gets the RTC TimeStamp value.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure  
-  * @param  Format: specifies the format of the entered parameters.
+  * @param  sTimeStamp Pointer to Time structure
+  * @param  sTimeStampDate Pointer to Date structure
+  * @param  Format specifies the format of the entered parameters.
   *          This parameter can be one of the following values:
-  *             RTC_FORMAT_BIN: Binary data format 
+  *             RTC_FORMAT_BIN: Binary data format
   *             RTC_FORMAT_BCD: BCD data format
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
 {
-  uint32_t tmptime = 0, tmpdate = 0;
+  uint32_t tmptime = 0U, tmpdate = 0U;
 
   /* Check the parameters */
   assert_param(IS_RTC_FORMAT(Format));
@@ -322,57 +304,57 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
   tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
 
   /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
   sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
-  
+  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
+
   /* Fill the Date structure fields with the read parameters */
   sTimeStampDate->Year = 0;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
   sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
 
   /* Check the input parameters format */
-  if(Format == RTC_FORMAT_BIN)
+  if (Format == RTC_FORMAT_BIN)
   {
     /* Convert the TimeStamp structure parameters to Binary format */
     sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
     sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
     sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-    
+
     /* Convert the DateTimeStamp structure parameters to Binary format */
     sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
     sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
     sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
   }
-  
+
   /* Clear the TIMESTAMP Flag */
   __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-    
+
   return HAL_OK;
 }
 
 /**
   * @brief  Sets Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @note   By calling this API we disable the tamper interrupt for all tampers.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTamper: Pointer to Tamper Structure.
+  * @param  sTamper Pointer to Tamper Structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
 {
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
-  assert_param(IS_TAMPER(sTamper->Tamper)); 
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
   assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
-  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
 
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-    
+
   hrtc->State = HAL_RTC_STATE_BUSY;
 
   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)(sTamper->Trigger));
@@ -380,35 +362,35 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPINSEL);
 
   hrtc->Instance->TAFCR |= tmpreg;
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
 
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-    
+
   return HAL_OK;
 }
 
 /**
   * @brief  Sets Tamper with interrupt.
   * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  sTamper: Pointer to RTC Tamper.
+  * @param  sTamper Pointer to RTC Tamper.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
 {
-  uint32_t tmpreg = 0;
-  
+  uint32_t tmpreg = 0U;
+
   /* Check the parameters */
-  assert_param(IS_TAMPER(sTamper->Tamper)); 
+  assert_param(IS_RTC_TAMPER(sTamper->Tamper));
   assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection));
-  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
+  assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
 
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-      
+
   hrtc->State = HAL_RTC_STATE_BUSY;
 
   tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger);
@@ -416,114 +398,130 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
   hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE);
 
   hrtc->Instance->TAFCR |= tmpreg;
-  
+
   /* Configure the Tamper Interrupt in the RTC_TAFCR */
   hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-  
+
+  /* Clear RTC Tamper 1 flag */
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+
   /* RTC Tamper Interrupt Configuration: EXTI configuration */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-  
+
   EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Deactivates Tamper.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Tamper: Selected tamper pin.
-  *          This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
+  * @param  Tamper Selected tamper pin.
+  *          This parameter can be RTC_Tamper_1.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
 {
-  assert_param(IS_RTC_TAMPER(Tamper)); 
-  
-  /* Process Locked */ 
+  assert_param(IS_RTC_TAMPER(Tamper));
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-      
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the selected Tamper pin */
-  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;  
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */  
+  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief  This function handles TimeStamp interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{  
-  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
+{
+  /* Get the TimeStamp interrupt source enable status */
+  if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
   {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
+    /* Get the pending status of the TIMESTAMP Interrupt */
+    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
     {
-      /* TIMESTAMP callback */ 
+      /* TIMESTAMP callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      hrtc->TimeStampEventCallback(hrtc);
+#else
       HAL_RTCEx_TimeStampEventCallback(hrtc);
-  
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
       /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
     }
   }
-  
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
+
+  /* Get the Tamper interrupts source enable status */
+  if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
   {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET) 
+    /* Get the pending status of the Tamper Interrupt */
+    if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
     {
-      /* Tamper callback */ 
+      /* Tamper callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      hrtc->Tamper1EventCallback(hrtc);
+#else
       HAL_RTCEx_Tamper1EventCallback(hrtc);
-  
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
       /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
     }
   }
-  
+
   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
+  hrtc->State = HAL_RTC_STATE_READY;
 }
 
 /**
-  * @brief  TimeStamp callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  TimeStamp callback.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_TimeStampEventCallback could be implemented in the user file
   */
 }
 
 /**
-  * @brief  Tamper 1 callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Tamper 1 callback.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_Tamper1EventCallback could be implemented in the user file
    */
@@ -531,95 +529,95 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
 
 /**
   * @brief  This function handles TimeStamp polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{ 
-  uint32_t tickstart = 0; 
+{
+  uint32_t tickstart = 0U;
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+  while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
   {
-    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+    if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
     {
       /* Clear the TIMESTAMP Overrun Flag */
       __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-      
+
       /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR; 
-      
-      return HAL_ERROR; 
+      hrtc->State = HAL_RTC_STATE_ERROR;
+
+      return HAL_ERROR;
     }
-    
-    if(Timeout != HAL_MAX_DELAY)
+
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK; 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
 }
-  
+
 /**
   * @brief  This function handles Tamper1 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0; 
+{
+  uint32_t tickstart = 0U;
 
   /* Get tick */
   tickstart = HAL_GetTick();
-  
+
   /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET)
+  while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET)
   {
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
   /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-  
+  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
-  
+
 /** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
   *  @brief   RTC Wake-up functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                         ##### RTC Wake-up functions #####
- ===============================================================================  
- 
+ ===============================================================================
+
  [..] This section provides functions allowing to configure Wake-up feature
 
 @endverbatim
@@ -627,45 +625,45 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
   */
 
 /**
-  * @brief  Sets wake up timer. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @brief  Sets wake up timer.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
 {
-  uint32_t tickstart = 0;
+  uint32_t tickstart = 0U;
 
   /* Check the parameters */
   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
- 
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-    
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+  if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
   {
     tickstart = HAL_GetTick();
 
     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
+
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-        /* Process Unlocked */ 
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
 
         return HAL_TIMEOUT;
@@ -679,114 +677,113 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
   tickstart = HAL_GetTick();
 
   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
   {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
     {
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-      /* Process Unlocked */ 
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
-      
+
       return HAL_TIMEOUT;
-    }  
+    }
   }
-  
+
   /* Clear the Wake-up Timer clock source bits in CR register */
   hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-  
+
   /* Configure the clock source */
   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
+
   /* Configure the Wake-up Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-  
-   /* Enable the Wake-up Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);   
-  
+
+  /* Enable the Wake-up Timer */
+  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Sets wake up timer with interrupt
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
+  * @param  WakeUpCounter Wake up counter
+  * @param  WakeUpClock Wake up clock
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
 {
-  uint32_t tickstart = 0;
-  
+  __IO uint32_t count;
+
   /* Check the parameters */
   assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
   assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
-  
-  /* Process Locked */ 
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
-  if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+  if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
   {
-    tickstart = HAL_GetTick();
- 
     /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+    count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
+    do
     {
-      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+      if (count-- == 0U)
       {
-       /* Enable the write protection for RTC registers */
-       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-       hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-       /* Process Unlocked */ 
-       __HAL_UNLOCK(hrtc);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
 
-       return HAL_TIMEOUT;
+        return HAL_TIMEOUT;
       }
     }
+    while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET);
   }
 
   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
 
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U);
+  do
   {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    if (count-- == 0U)
     {
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-      /* Process Unlocked */ 
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
-      
+
       return HAL_TIMEOUT;
-    }  
+    }
   }
-  
+  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET);
+
   /* Configure the Wake-up Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
 
@@ -795,132 +792,142 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
 
   /* Configure the clock source */
   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
+
   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-  
+
   EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-  
+
+  /* Clear RTC Wake Up timer Flag */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
   /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-  
+  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
+
   /* Enable the Wake-up Timer */
   __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-    
+
   /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
+  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
- 
+
   return HAL_OK;
 }
 
 /**
   * @brief  Deactivates wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval HAL status
   */
 uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
 {
-  uint32_t tickstart = 0;
-  
-  /* Process Locked */ 
+  uint32_t tickstart = 0U;
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Disable the Wake-up Timer */
   __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-  
-  /* In case of interrupt mode is used, the interrupt source must disabled */ 
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+
+  /* In case of interrupt mode is used, the interrupt source must disabled */
+  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
   /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
   {
-    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
     {
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-      
-      hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-      /* Process Unlocked */ 
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
       __HAL_UNLOCK(hrtc);
-      
+
       return HAL_TIMEOUT;
-    }   
+    }
   }
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_READY;   
-  
-  /* Process Unlocked */ 
+
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Gets wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval Counter value
   */
 uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
 {
   /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); 
+  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
 }
 
 /**
   * @brief  This function handles Wake Up Timer interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{  
-  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
+{
+  /* Get the WAKEUPTIMER interrupt source enable status */
+  if (__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(hrtc, RTC_IT_WUT) != RESET)
   {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
+    /* Get the pending status of the WAKEUPTIMER Interrupt */
+    if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
     {
-      /* WAKEUPTIMER callback */ 
+      /* WAKEUPTIMER callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+      hrtc->WakeUpTimerEventCallback(hrtc);
+#else
       HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-      
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
       /* Clear the WAKEUPTIMER interrupt pending bit */
       __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
     }
   }
-  
+
   /* Clear the EXTI's line Flag for RTC WakeUpTimer */
   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
 
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
+  hrtc->State = HAL_RTC_STATE_READY;
 }
 
 /**
   * @brief  Wake Up Timer callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file
    */
@@ -928,65 +935,62 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
 
 /**
   * @brief  This function handles Wake Up Timer Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0; 
+{
+  uint32_t tickstart = 0U;
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+  while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
   {
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
-      
+
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
   /* Clear the WAKEUPTIMER Flag */
   __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
+
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions 
-  *  @brief   Extension Peripheral Control functions 
+/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
+  *  @brief   Extension Peripheral Control functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
               ##### Extension Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Write a data in a specified RTC Backup data register
       (+) Read a data in a specified RTC Backup data register
       (+) Set the Coarse calibration parameters.
       (+) Deactivate the Coarse calibration parameters
-      (+) Set the Smooth calibration parameters.
       (+) Configure the Synchronization Shift Control Settings.
-      (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+      (+) Configure the Calibration Pinout (RTC_CALIB).
+      (+) Deactivate the Calibration Pinout (RTC_CALIB).
       (+) Enable the RTC reference clock detection.
       (+) Disable the RTC reference clock detection.
-      (+) Enable the Bypass Shadow feature.
-      (+) Disable the Bypass Shadow feature.
 
 @endverbatim
   * @{
@@ -994,327 +998,327 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
 
 /**
   * @brief  Writes a data in a specified RTC Backup data register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  BackupRegister RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
   *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.
+  * @param  Data Data to be written in the specified RTC Backup data register.
   * @retval None
   */
 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
 {
-  uint32_t tmp = 0;
-  
+  uint32_t tmp = 0U;
+
   /* Check the parameters */
   assert_param(IS_RTC_BKP(BackupRegister));
-  
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-  
+
+  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4U);
+
   /* Write the specified register */
   *(__IO uint32_t *)tmp = (uint32_t)Data;
 }
 
 /**
   * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  BackupRegister RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
   *                                 specify the register.
   * @retval Read value
   */
 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
 {
-  uint32_t tmp = 0;
-  
+  uint32_t tmp = 0U;
+
   /* Check the parameters */
   assert_param(IS_RTC_BKP(BackupRegister));
 
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-  
+  tmp = (uint32_t) & (hrtc->Instance->BKP0R);
+  tmp += (BackupRegister * 4U);
+
   /* Read the specified register */
   return (*(__IO uint32_t *)tmp);
 }
-      
+
 /**
   * @brief  Sets the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @param  CalibSign: Specifies the sign of the coarse calibration value.
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
+  * @param  CalibSign Specifies the sign of the coarse calibration value.
   *          This parameter can be  one of the following values :
-  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive 
+  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
   *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
-  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
-  *    
+  * @param  Value value of coarse calibration expressed in ppm (coded on 5 bits).
+  *
   * @note   This Calibration value should be between 0 and 63 when using negative
   *         sign with a 2-ppm step.
-  *           
+  *
   * @note   This Calibration value should be between 0 and 126 when using positive
   *         sign with a 4-ppm step.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
+HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value)
 {
   /* Check the parameters */
   assert_param(IS_RTC_CALIB_SIGN(CalibSign));
-  assert_param(IS_RTC_CALIB_VALUE(Value)); 
-  
-  /* Process Locked */ 
+  assert_param(IS_RTC_CALIB_VALUE(Value));
+
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
 
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state*/
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
-  { 
+  {
     /* Enable the Coarse Calibration */
     __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
-    
+
     /* Set the coarse calibration value */
-    hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
-    
+    hrtc->Instance->CALIBR = (uint32_t)(CalibSign | Value);
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+  }
 
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
   /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Deactivates the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
-{ 
-  /* Process Locked */ 
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state*/
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
-  { 
+  {
     /* Enable the Coarse Calibration */
     __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
-    
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+  }
 
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
   /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Configure the Calibration Pinout (RTC_CALIB).
-  * @param  hrtc : RTC handle    
+  * @param  hrtc RTC handle
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc)
 {
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
 
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
+  * @brief  Deactivates the Calibration Pinout (RTC_CALIB).
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
 {
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-    
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Enables the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
 {
-  /* Process Locked */ 
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state*/
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
   {
     __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
 
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
   }
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+
+  /* Change RTC state */
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
+  *                the configuration information for RTC.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{ 
-  /* Process Locked */ 
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
+{
+  /* Process Locked */
   __HAL_LOCK(hrtc);
-  
+
   hrtc->State = HAL_RTC_STATE_BUSY;
-  
+
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
+
   /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
+  if (RTC_EnterInitMode(hrtc) != HAL_OK)
   {
     /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
+    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
     /* Set RTC state*/
     hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
+
+    /* Process Unlocked */
     __HAL_UNLOCK(hrtc);
-    
+
     return HAL_ERROR;
-  } 
+  }
   else
   {
     __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-    
+
     /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
+    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
   }
-  
+
   /* Enable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  /* Process Unlocked */
   __HAL_UNLOCK(hrtc);
-  
+
   return HAL_OK;
 }
 
@@ -1322,29 +1326,31 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
   * @}
   */
 
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions 
-  *  @brief    Extended features functions  
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
+  *  @brief    Extended features functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                  ##### Extended features functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) RTC Alarm B callback
       (+) RTC Poll for Alarm B request
-               
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Alarm B callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
   * @retval None
   */
 __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrtc);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_RTC_AlarmBEventCallback could be implemented in the user file
    */
@@ -1352,37 +1358,37 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
 
 /**
   * @brief  This function handles AlarmB Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
+  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
   *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = 0; 
+{
+  uint32_t tickstart = 0U;
 
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+  while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
   {
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
       {
         hrtc->State = HAL_RTC_STATE_TIMEOUT;
         return HAL_TIMEOUT;
       }
     }
   }
-  
+
   /* Clear the Alarm Flag */
   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-  
+
   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK; 
+  hrtc->State = HAL_RTC_STATE_READY;
+
+  return HAL_OK;
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
index 4df41a0a..569c8b1c 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
@@ -2,429 +2,522 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sd.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Secure Digital (SD) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
   [..]
-    This driver implements a high level communication layer for read and write from/to 
-    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by 
-    the user in HAL_SD_MspInit() function (MSP layer).                             
-    Basically, the MSP layer configuration should be the same as we provide in the 
+    This driver implements a high level communication layer for read and write from/to
+    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
+    the user in HAL_SD_MspInit() function (MSP layer).
+    Basically, the MSP layer configuration should be the same as we provide in the
     examples.
     You can easily tailor this configuration according to hardware resources.
 
   [..]
-    This driver is a generic layered driver for SDIO memories which uses the HAL 
-    SDIO driver functions to interface with SD and uSD cards devices. 
+    This driver is a generic layered driver for SDIO memories which uses the HAL
+    SDIO driver functions to interface with SD and uSD cards devices.
     It is used as follows:
- 
-    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
-        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE(); 
+
+    (#)Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:
+        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
         (##) SDIO pins configuration for SD card
-            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();   
+            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
             (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
                   and according to your pin assignment;
-        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
+        (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
              and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); 
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
+            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
             (+++) Configure the SDIO and DMA interrupt priorities using functions
                   HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
             (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() 
-                  and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
-            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
-                  and __HAL_SD_SDIO_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
+            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+             and HAL_SD_WriteBlocks_IT() APIs).
+            (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();
+            (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
+            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+                  and __HAL_SD_DISABLE_IT() inside the communication process.
+            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+                  and __HAL_SD_CLEAR_IT()
+    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
+
 
-         
   *** SD Card Initialization and configuration ***
-  ================================================    
+  ================================================
   [..]
-    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
-    the SD Card and put it into Standby State (Ready for data transfer). 
+    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+    SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
     This function provide the following operations:
-  
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card 
-        type (Standard Capacity or High Capacity). You can change or adapt this 
-        frequency by adjusting the "ClockDiv" field. 
+
+    (#) Apply the SD Card initialization process at 400KHz and check the SD Card
+        type (Standard Capacity or High Capacity). You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
         The SD Card frequency (SDIO_CK) is computed as follows:
-  
+
            SDIO_CK = SDIOCLK / (ClockDiv + 2)
-  
-        In initialization mode and according to the SD Card standard, 
+
+        In initialization mode and according to the SD Card standard,
         make sure that the SDIO_CK frequency doesn't exceed 400KHz.
-  
-    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo 
-        structure. This structure provide also ready computed SD Card capacity 
-        and Block size.
-        
-        -@- These information are stored in SD handle structure in case of future use.  
-  
-    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
-        frequency is set to 24MHz. You can change or adapt this frequency by adjusting 
-        the "ClockDiv" field.
-        In transfer mode and according to the SD Card standard, make sure that the 
+
+        This phase of initialization is done through SDIO_Init() and
+        SDIO_PowerState_ON() SDIO low level APIs.
+
+    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+        This phase allows the card initialization and identification
+        and check the SD Card type (Standard Capacity or High Capacity)
+        The initialization flow is compatible with SD standard.
+
+        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+        of plug-off plug-in.
+
+    (#) Configure the SD Card Data transfer frequency. You can change or adapt this
+        frequency by adjusting the "ClockDiv" field.
+        In transfer mode and according to the SD Card standard, make sure that the
         SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDIO 
-        peripheral in bypass mode. Refer to the corresponding reference manual 
+        To be able to use a frequency higher than 24MHz, you should use the SDIO
+        peripheral in bypass mode. Refer to the corresponding reference manual
         for more details.
-  
+
     (#) Select the corresponding SD Card according to the address read with the step 2.
-    
+
     (#) Configure the SD Card in wide bus mode: 4-bits data.
-  
+
   *** SD Card Read operation ***
   ==============================
-  [..] 
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
+  [..]
+    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
+        This function support only 512-bytes block length (the block size should be
         chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
+        You can choose either one block read operation or multiple block read operation
         by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
 
     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
+        This function support only 512-bytes block length (the block size should be
         chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
+        You can choose either one block read operation or multiple block read operation
         by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
-        that the read transfer is done correctly in both DMA and SD sides.
-  
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Rx interrupt event.
+
+    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Rx interrupt event.
+
   *** SD Card Write operation ***
-  =============================== 
-  [..] 
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
-        This function support only 512-bytes block length (the block size should be 
+  ===============================
+  [..]
+    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
+        This function support only 512-bytes block length (the block size should be
         chosen as 512 bytes).
-        You can choose either one block read operation or multiple block read operation 
+        You can choose either one block read operation or multiple block read operation
         by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
 
     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-bytes block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
         by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
-        that the write transfer is done correctly in both DMA and SD sides.  
-  
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the DMA transfer process through the SD Tx interrupt event.
+
+    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+        This function support only 512-bytes block length (the block size should be
+        chosen as 512 bytes).
+        You can choose either one block read operation or multiple block read operation
+        by adjusting the "NumberOfBlocks" parameter.
+        After this, you have to ensure that the transfer is done correctly. The check is done
+        through HAL_SD_GetCardState() function for SD card state.
+        You could also check the IT transfer process through the SD Tx interrupt event.
+
   *** SD card status ***
-  ====================== 
+  ======================
+  [..]
+    (+) The SD Status contains status bits that are related to the SD Memory
+        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+  *** SD card information ***
+  ===========================
   [..]
-    (+) At any time, you can check the SD Card status and get the SD card state 
-        by using the HAL_SD_GetStatus() function. This function checks first if the 
-        SD card is still connected and then get the internal SD Card transfer state.     
-    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() 
-        function.    
+    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+        It returns useful information about the SD card such as block size, card type,
+        block number ...
+
+  *** SD card CSD register ***
+  ============================
+    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+        Some of the CSD parameters are useful for card initialization and identification.
+
+  *** SD card CID register ***
+  ============================
+    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+        Some of the CSD parameters are useful for card initialization and identification.
 
   *** SD HAL driver macros list ***
   ==================================
   [..]
     Below the list of most used macros in SD HAL driver.
 
-    (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
-    (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
-    (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
-      
-    (@) You can refer to the SD HAL driver header file for more useful macros 
-      
+    (+) __HAL_SD_ENABLE : Enable the SD device
+    (+) __HAL_SD_DISABLE : Disable the SD device
+    (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
+    (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
+    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+
+    (@) You can refer to the SD HAL driver header file for more useful macros
+
+  *** Callback registration ***
+  =============================================
+  [..]
+    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+    it allows to register following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function. It allows to reset following callbacks:
+      (+) TxCpltCallback : callback when a transmission transfer is completed.
+      (+) RxCpltCallback : callback when a reception transfer is completed.
+      (+) ErrorCallback : callback when error occurs.
+      (+) AbortCpltCallback : callback when abort is completed.
+      (+) MspInitCallback    : SD MspInit.
+      (+) MspDeInitCallback  : SD MspDeInit.
+    This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+    By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+    Exception done for MspInit and MspDeInit callbacks that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
+    and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+    Callbacks can be registered/unregistered in READY state only.
+    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+    during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
+    or @ref HAL_SD_Init function.
+
+    When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
-#ifdef HAL_SD_MODULE_ENABLED
+#if defined(SDIO)
 
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
-/** @addtogroup SD 
+/** @addtogroup SD
   * @{
   */
 
+#ifdef HAL_SD_MODULE_ENABLED
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @addtogroup SD_Private_Defines
   * @{
   */
-/** 
-  * @brief  SDIO Data block size 
-  */ 
-#define DATA_BLOCK_SIZE                  ((uint32_t)(9 << 4))
-/** 
-  * @brief  SDIO Static flags, Timeout, FIFO Address  
-  */
-#define SDIO_STATIC_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
-                                                    SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
-                                                    SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
-                                                    SDIO_FLAG_DBCKEND))  
-
-#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
-
-/** 
-  * @brief  Mask for errors Card Status R1 (OCR Register) 
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRITE       ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO                      ((uint32_t)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Command Class Supported 
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_SDIO_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
 
 /**
   * @}
   */
-  
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SD_Private_Functions_Prototypes
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
   * @{
   */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); 
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static void SD_PowerOFF(SD_HandleTypeDef *hsd);
+static void SD_Write_IT(SD_HandleTypeDef *hsd);
+static void SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAError(DMA_HandleTypeDef *hdma);
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SD_Exported_Functions
   * @{
   */
 
 /** @addtogroup SD_Exported_Functions_Group1
- *  @brief   Initialization and de-initialization functions 
+ *  @brief   Initialization and de-initialization functions
  *
-@verbatim  
+@verbatim
   ==============================================================================
           ##### Initialization and de-initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to initialize/de-initialize the SD
     card device to be ready for use.
-      
- 
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the SD card according to the specified parameters in the 
+  * @brief  Initializes the SD according to the specified parameters in the
             SD_HandleTypeDef and create the associated handle.
-  * @param  hsd: SD handle
-  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   
-  * @retval HAL SD error state
+  * @param  hsd: Pointer to the SD handle
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{ 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SD_InitTypeDef tmpinit;
-  
-  /* Allocate lock resource and initialize it */
-  hsd->Lock = HAL_UNLOCKED;
-  /* Initialize the low level hardware (MSP) */
-  HAL_SD_MspInit(hsd);
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+  assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+  assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
+
+  if(hsd->State == HAL_SD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsd->Lock = HAL_UNLOCKED;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+    /* Reset Callback pointers in HAL_SD_STATE_RESET only */
+    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;
+    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;
+    hsd->ErrorCallback     = HAL_SD_ErrorCallback;
+    hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+
+    if(hsd->MspInitCallback == NULL)
+    {
+      hsd->MspInitCallback = HAL_SD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsd->MspInitCallback(hsd);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_SD_MspInit(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+  }
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Initialize the Card parameters */
+  if (HAL_SD_InitCard(hsd) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Initialize the error code */
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  /* Initialize the SD state */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the SD Card.
+  * @param  hsd: Pointer to SD handle
+  * @note   This function initializes the SD card. It could be used when a card
+            re-initialization is needed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  uint32_t errorstate;
+  HAL_StatusTypeDef status;
+  SD_InitTypeDef Init;
   
   /* Default SDIO peripheral configuration for SD card initialization */
-  tmpinit.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
-  tmpinit.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
-  tmpinit.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  tmpinit.BusWide             = SDIO_BUS_WIDE_1B;
-  tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
-  tmpinit.ClockDiv            = SDIO_INIT_CLK_DIV;
-  
+  Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
+  Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
+  Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  Init.BusWide             = SDIO_BUS_WIDE_1B;
+  Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  Init.ClockDiv            = SDIO_INIT_CLK_DIV;
+
   /* Initialize SDIO peripheral interface with default configuration */
-  SDIO_Init(hsd->Instance, tmpinit);
-  
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd); 
-  
-  if(errorstate != SD_OK)     
+  status = SDIO_Init(hsd->Instance, Init);
+  if(status != HAL_OK)
   {
-    return errorstate;
+    return HAL_ERROR;
   }
-  
-  /* Initialize the present SDIO card(s) and put them in idle state */
-  errorstate = SD_Initialize_Cards(hsd);
-  
-  if (errorstate != SD_OK)
+
+  /* Disable SDIO Clock */
+  __HAL_SD_DISABLE(hsd);
+
+  /* Set Power State to ON */
+  (void)SDIO_PowerState_ON(hsd->Instance);
+
+  /* Enable SDIO Clock */
+  __HAL_SD_ENABLE(hsd);
+
+  /* Identify card operating voltage */
+  errorstate = SD_PowerON(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
   }
-  
-  /* Read CSD/CID MSD registers */
-  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-  
-  if (errorstate == SD_OK)
+
+  /* Card initialization */
+  errorstate = SD_InitCard(hsd);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    /* Select the Card */
-    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->ErrorCode |= errorstate;
+    return HAL_ERROR;
   }
-  
-  /* Configure SDIO peripheral interface */
-  SDIO_Init(hsd->Instance, hsd->Init);   
-  
-  return errorstate;
+
+  return HAL_OK;
 }
 
 /**
   * @brief  De-Initializes the SD card.
-  * @param  hsd: SD handle
+  * @param  hsd: Pointer to SD handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
 {
-  
-  /* Set SD power state to off */ 
+  /* Check the SD handle allocation */
+  if(hsd == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  /* Set SD power state to off */
   SD_PowerOFF(hsd);
-  
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+  if(hsd->MspDeInitCallback == NULL)
+  {
+    hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsd->MspDeInitCallback(hsd);
+#else
   /* De-Initialize the MSP layer */
   HAL_SD_MspDeInit(hsd);
-  
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+  hsd->ErrorCode = HAL_SD_ERROR_NONE;
+  hsd->State = HAL_SD_STATE_RESET;
+
   return HAL_OK;
 }
 
 
 /**
   * @brief  Initializes the SD MSP.
-  * @param  hsd: SD handle
+  * @param  hsd: Pointer to SD handle
   * @retval None
   */
 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SD_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  De-Initialize SD MSP.
-  * @param  hsd: SD handle
+  * @param  hsd: Pointer to SD handle
   * @retval None
   */
 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SD_MspDeInit could be implemented in the user file
    */
 }
@@ -434,14 +527,14 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
   */
 
 /** @addtogroup SD_Exported_Functions_Group2
- *  @brief   Data transfer functions 
+ *  @brief   Data transfer functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                         ##### IO operation functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection provides a set of functions allowing to manage the data 
+    This subsection provides a set of functions allowing to manage the data
     transfer from/to SD card.
 
 @endverbatim
@@ -449,2969 +542,2687 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
   */
 
 /**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: pointer to the buffer that will contain the received data
-  * @param  ReadAddr: Address from where data is to be read  
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to read   
-  * @retval SD Card error state
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of SD blocks to read
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
 {
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t) BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
   {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Read block(s) in polling mode */
-  if(NumberOfBlocks > 1)
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-    
-    if (errorstate != SD_OK)
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
     {
-      return errorstate;
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
     }
-    
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Read block(s) in polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
     /* Poll on SDIO flags */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+    dataremaining = config.DataLength;
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
     {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))
       {
         /* Read data from SDIO Rx FIFO */
-        for (count = 0; count < 8; count++)
+        for(count = 0U; count < 8U; count++)
         {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+          data = SDIO_ReadFIFO(hsd->Instance);
+          *tempbuff = (uint8_t)(data & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
+          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+          tempbuff++;
+          dataremaining--;
         }
-        
-        tempbuff += 8;
       }
-    }      
-  }
-  else
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); 
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }    
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
     
-    /* In case of single block transfer, no need of stop transfer at all */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+    /* Send stop transmission command in case of multiblock read */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
     {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      if(hsd->SdCard.CardType != CARD_SECURED)
       {
-        /* Read data from SDIO Rx FIFO */
-        for (count = 0; count < 8; count++)
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
         {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
         }
-        
-        tempbuff += 8;
       }
     }
-  }
-  
-  /* Send stop transmission command in case of multiblock read */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
-      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
     {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
     }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Empty FIFO if there is still any data */
+    while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))
+    {
+      data = SDIO_ReadFIFO(hsd->Instance);
+      *tempbuff = (uint8_t)(data & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+      *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
+      tempbuff++;
+      dataremaining--;
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+        hsd->State= HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
   }
   else
   {
-    /* No error flag set */
-  }
-  
-  count = SD_DATATIMEOUT;
-  
-  /* Empty FIFO if there is still any data */
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
-  {
-    *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-    tempbuff++;
-    count--;
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
   }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
 }
 
 /**
   * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  WriteAddr: Address from where data is to be written 
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
-  * @param  NumberOfBlocks: Number of SD blocks to write 
-  * @retval SD Card error state
+  *         transfer is managed by polling mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of SD blocks to write
+  * @param  Timeout: Specify timeout value
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
-  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
-  uint8_t cardstate  = 0;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count, data, dataremaining;
+  uint32_t add = BlockAdd;
+  uint8_t *tempbuff = pData;
+
+  if(NULL == pData)
   {
-    return errorstate;
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
-  
-  if(NumberOfBlocks > 1)
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }  
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Set total number of bytes to write */
-  totalnumberofbytes = NumberOfBlocks * BlockSize;
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Write block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = NumberOfBlocks * BLOCKSIZE;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
     {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Write block(s) in polling mode */
+    dataremaining = config.DataLength;
+    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+    {
+      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))
       {
-        if ((totalnumberofbytes - bytestransferred) < 32)
+        /* Write data to SDIO Tx FIFO */
+        for(count = 0U; count < 8U; count++)
         {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
+          data = (uint32_t)(*tempbuff);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 8U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 16U);
+          tempbuff++;
+          dataremaining--;
+          data |= ((uint32_t)(*tempbuff) << 24U);
+          tempbuff++;
+          dataremaining--;
+          (void)SDIO_WriteFIFO(hsd->Instance, &data);
         }
       }
-    }   
-  }
-  else
-  {
-    /* In case of single data block transfer no need of stop command at all */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+
+      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Send stop transmission command in case of multiblock write */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
     {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+      if(hsd->SdCard.CardType != CARD_SECURED)
       {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++; 
-            bytestransferred += 4;
-          }
-        }
-        else
+        /* Send stop transmission command */
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
         {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
+          /* Clear all the static flags */
+          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+          hsd->ErrorCode |= errorstate;
+          hsd->State = HAL_SD_STATE_READY;
+          hsd->Context = SD_CONTEXT_NONE;
+          return HAL_ERROR;
         }
       }
-    }  
-  }
-  
-  /* Send stop transmission command in case of multiblock write */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+    }
+
+    /* Get error state */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
     {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
     }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    errorstate = SD_TX_UNDERRUN;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
   }
   else
   {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Wait till the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
+    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+    return HAL_ERROR;
   }
-  
-  return errorstate;
 }
 
 /**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
-  *         to check the completion of the read process   
-  * @param  hsd: SD handle                 
-  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
-  * @param  ReadAddr: Address from where data is to be read  
-  * @param  BlockSize: SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
   * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval SD Card error state
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK; 
-  
-  /* Initialize SD Read operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
-  }
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_RXOVERR  |\
-                                SDIO_IT_STBITERR));
-  
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
-  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
   {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
-  
-  sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    hsd->pRxBuffPtr = pData;
+    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    /* Read Blocks in IT mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Multi Block command */
+      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Read Single Block command */
+      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    return HAL_OK;
   }
   else
   {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
+    return HAL_BUSY;
   }
-  
-  /* Update the SD transfer error in SD handle */
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
 }
 
-
 /**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
-  *         to check the completion of the write process (by SD current status polling).  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  WriteAddr: Address from where data is to be read   
-  * @param  BlockSize: the SD card Data block size 
-  * @note   BlockSize must be 512 bytes.
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed in interrupt mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the IT transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
   * @param  NumberOfBlocks: Number of blocks to write
-  * @retval SD Card error state
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK;
-  
-  /* Initialize SD Write operation */
-  if(NumberOfBlocks > 1)
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
+
+  if(NULL == pData)
   {
-    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
-  else
-  {
-    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
-  }  
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXUNDERR |\
-                                SDIO_IT_STBITERR));
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
-  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
 
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
 
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
 
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
+    hsd->State = HAL_SD_STATE_BUSY;
 
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks <= 1)
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  else
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
 
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
+    hsd->pTxBuffPtr = pData;
+    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+    /* Enable transfer interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
+
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Configure the SD DPSM (Data Path State Machine) */
+    config.DataTimeOut   = SDMMC_DATATIMEOUT;
+    config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+    config.DPSM          = SDIO_DPSM_ENABLE;
+    (void)SDIO_ConfigData(hsd->Instance, &config);
+
+    return HAL_OK;
   }
   else
   {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
+    return HAL_BUSY;
   }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
 }
 
 /**
-  * @brief  This function waits until the SD DMA data read transfer is finished. 
-  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
+  * @brief  Reads block(s) from a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Rx
+  *         interrupt event.
+  * @param  hsd: Pointer SD handle
+  * @param  pData: Pointer to the buffer that will contain the received data
+  * @param  BlockAdd: Block Address from where data is to be read
+  * @param  NumberOfBlocks: Number of blocks to read.
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-  
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Rx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0))
-  {
-    timeout--;  
-  }
-  
-  /* Send stop command in multiblock read */
-  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  return errorstate;
-}
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
 
-/**
-  * @brief  This function waits until the SD DMA data write transfer is finished. 
-  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
+  if(NULL == pData)
   {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Tx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT))  && (timeout > 0))
-  {
-    timeout--;  
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
 
-  /* Send stop command in multiblock write */
-  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  /* Wait until write is complete */
-  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
-  {    
-  }
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
 
-  return errorstate; 
-}
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
 
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @param  hsd: SD handle 
-  * @param  startaddr: Start byte address
-  * @param  endaddr: End byte address
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  
-  uint32_t delay         = 0;
-  __IO uint32_t maxdelay = 0;
-  uint8_t cardstate      = 0;
-  
-  /* Check if the card command class supports erase command */
-  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  /* Get max delay value */
-  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get start and end block for high capacity cards */
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512;
-    endaddr   /= 512;
-  }
-  
-  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    sdio_cmdinitstructure.Argument         =(uint32_t)startaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-    
-    if (errorstate != SD_OK)
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
+
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+
+    /* Set the DMA transfer complete callback */
+    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+
+    /* Set the DMA error callback */
+    hsd->hdmarx->XferErrorCallback = SD_DMAError;
+
+    /* Set the DMA Abort callback */
+    hsd->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
     {
-      return errorstate;
+      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
     }
-    
-    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    sdio_cmdinitstructure.Argument         = (uint32_t)endaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-    
-    if (errorstate != SD_OK)
+    else
     {
-      return errorstate;
+      /* Enable SD DMA transfer */
+      __HAL_SD_DMA_ENABLE(hsd);
+
+      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+      {
+        add *= 512U;
+      }
+
+      /* Set Block Size for Card */
+      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDIO_DPSM_ENABLE;
+      (void)SDIO_ConfigData(hsd->Instance, &config);
+
+      /* Read Blocks in DMA mode */
+      if(NumberOfBlocks > 1U)
+      {
+        hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Multi Block command */
+        errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
+      }
+      else
+      {
+        hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+        /* Read Single Block command */
+        errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
+      }
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+        return HAL_ERROR;
+      }
+
+      return HAL_OK;
     }
   }
-  
-  /* Send CMD38 ERASE */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  for (; delay < maxdelay; delay++)
-  {
-  }
-  
-  /* Wait until the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  delay = SD_DATATIMEOUT;
-  
-  while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+  else
   {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-    delay--;
+    return HAL_BUSY;
   }
-  
-  return errorstate;
 }
 
 /**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: SD handle
-  * @retval None
+  * @brief  Writes block(s) to a specified address in a card. The Data transfer
+  *         is managed by DMA mode.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @note   You could also check the DMA transfer process through the SD Tx
+  *         interrupt event.
+  * @param  hsd: Pointer to SD handle
+  * @param  pData: Pointer to the buffer that will contain the data to transmit
+  * @param  BlockAdd: Block Address where data will be written
+  * @param  NumberOfBlocks: Number of blocks to write
+  * @retval HAL status
   */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{  
-  /* Check for SDIO interrupt flags */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);  
-      
-    /* SD transfer is complete */
-    hsd->SdTransferCplt = 1;
-
-    /* No transfer error */ 
-    hsd->SdTransferErr  = SD_OK;
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t add = BlockAdd;
 
-    HAL_SD_XferCpltCallback(hsd);  
-  }  
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
-    
-    HAL_SD_XferErrorCallback(hsd);
-    
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    hsd->SdTransferErr = SD_DATA_TIMEOUT;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    hsd->SdTransferErr = SD_RX_OVERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    hsd->SdTransferErr = SD_TX_UNDERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
+  if(NULL == pData)
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    hsd->SdTransferErr = SD_START_BIT_ERR;
-    
-    HAL_SD_XferErrorCallback(hsd);
+    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    return HAL_ERROR;
   }
-  else
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    /* No error flag set */
-  }
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
 
-  /* Disable all SDIO peripheral interrupt sources */
-  __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
-                                SDIO_IT_RXOVERR  | SDIO_IT_STBITERR);                               
-}
+    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
+    }
 
+    hsd->State = HAL_SD_STATE_BUSY;
 
-/**
-  * @brief  SD end of transfer callback.
-  * @param  hsd: SD handle 
-  * @retval None
-  */
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferCpltCallback could be implemented in the user file
-   */ 
-}
+    /* Initialize data control register */
+    hsd->Instance->DCTRL = 0U;
 
-/**
-  * @brief  SD Transfer Error callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferErrorCallback could be implemented in the user file
-   */ 
-}
+    /* Enable SD Error interrupts */
+    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
 
-/**
-  * @brief  SD Transfer complete Rx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
-   */ 
-}  
+    /* Set the DMA transfer complete callback */
+    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
 
-/**
-  * @brief  SD DMA transfer complete Rx error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
-   */ 
-}
+    /* Set the DMA error callback */
+    hsd->hdmatx->XferErrorCallback = SD_DMAError;
 
-/**
-  * @brief  SD Transfer complete Tx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
-   */ 
-}  
+    /* Set the DMA Abort callback */
+    hsd->hdmatx->XferAbortCallback = NULL;
 
-/**
-  * @brief  SD DMA transfer complete error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
-   */ 
-}
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      add *= 512U;
+    }
 
-/**
-  * @}
-  */
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
 
-/** @addtogroup SD_Exported_Functions_Group3
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the SD card 
-    operations.
+    /* Write Blocks in Polling mode */
+    if(NumberOfBlocks > 1U)
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
 
-@endverbatim
-  * @{
-  */
+      /* Write Multi Block command */
+      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
+    }
+    else
+    {
+      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
 
-/**
-  * @brief  Returns information about specific card.
-  * @param  hsd: SD handle
-  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  
-  *         contains all SD cardinformation  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  
-  pCardInfo->CardType = (uint8_t)(hsd->CardType);
-  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
-  
-  /* Byte 0 */
-  tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
-  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
-  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
-  
-  /* Byte 1 */
-  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
-  
-  /* Byte 3 */
-  tmp = hsd->CSD[0] & 0x000000FF;
-  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
-  
-  /* Byte 5 */
-  tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
-  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
-  
-  /* Byte 6 */
-  tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
-  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
-  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
-  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
-  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
-  
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
-  {
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
-    
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
-    
-    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
-    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
-    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
-    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
-    
-    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
-    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
-    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
-    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
-  }
-  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp);
-    
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    
-    pCardInfo->CardCapacity = (uint64_t)((((uint64_t)pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024);
-    pCardInfo->CardBlockSize = 512;    
+      /* Write Single Block command */
+      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
+    }
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+
+    /* Enable SDIO DMA transfer */
+    __HAL_SD_DMA_ENABLE(hsd);
+
+    /* Enable the DMA Channel */
+    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
+    {
+      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));   
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      return HAL_ERROR;
+    }
+    else
+    {
+      /* Configure the SD DPSM (Data Path State Machine) */
+      config.DataTimeOut   = SDMMC_DATATIMEOUT;
+      config.DataLength    = BLOCKSIZE * NumberOfBlocks;
+      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+      config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
+      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+      config.DPSM          = SDIO_DPSM_ENABLE;
+      (void)SDIO_ConfigData(hsd->Instance, &config);
+
+      return HAL_OK;
+    }
   }
   else
   {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
+    return HAL_BUSY;
   }
-    
-  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
-  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
-  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
-  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
-  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.Reserved3           = 0;
-  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
-  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
-  pCardInfo->SD_csd.ECC              = (tmp & 0x03);
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
-  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_csd.Reserved4 = 1;
-  
-  /* Byte 0 */
-  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ManufacturerID = tmp;
-  
-  /* Byte 1 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
-  
-  /* Byte 2 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
-  pCardInfo->SD_cid.OEM_AppliID |= tmp;
-  
-  /* Byte 3 */
-  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName1 = tmp << 24;
-  
-  /* Byte 4 */
-  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 16;
-  
-  /* Byte 5 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 8;
-  
-  /* Byte 6 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdName1 |= tmp;
-  
-  /* Byte 7 */
-  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName2 = tmp;
-  
-  /* Byte 8 */
-  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdRev = tmp;
-  
-  /* Byte 9 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdSN = tmp << 24;
-  
-  /* Byte 10 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdSN |= tmp << 16;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
-  pCardInfo->SD_cid.ProdSN |= tmp << 8;
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdSN |= tmp;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
-  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ManufactDate |= tmp;
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
-  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_cid.Reserved2 = 1;
-  
-  return errorstate;
 }
 
 /**
-  * @brief  Enables wide bus operation for the requested card if supported by 
-  *         card.
-  * @param  hsd: SD handle       
-  * @param  WideMode: Specifies the SD card wide bus mode 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
-  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
-  * @retval SD Card error state
+  * @brief  Erases the specified memory area of the given SD card.
+  * @note   This API should be followed by a check on the card state through
+  *         HAL_SD_GetCardState().
+  * @param  hsd: Pointer to SD handle
+  * @param  BlockStartAdd: Start Block address
+  * @param  BlockEndAdd: End Block address
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_InitTypeDef tmpinit;
-  
-  /* MMC Card does not support this feature */
-  if (hsd->CardType == MULTIMEDIA_CARD)
-  {
-    errorstate = SD_UNSUPPORTED_FEATURE;
-    
-    return errorstate;
-  }
-  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+  uint32_t errorstate;
+  uint32_t start_add = BlockStartAdd;
+  uint32_t end_add = BlockEndAdd;
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    if (WideMode == SDIO_BUS_WIDE_8B)
+    hsd->ErrorCode = HAL_SD_ERROR_NONE;
+
+    if(end_add < start_add)
     {
-      errorstate = SD_UNSUPPORTED_FEATURE;
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+      return HAL_ERROR;
     }
-    else if (WideMode == SDIO_BUS_WIDE_4B)
+
+    if(end_add > (hsd->SdCard.LogBlockNbr))
     {
-      errorstate = SD_WideBus_Enable(hsd);
+      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+      return HAL_ERROR;
     }
-    else if (WideMode == SDIO_BUS_WIDE_1B)
+
+    hsd->State = HAL_SD_STATE_BUSY;
+
+    /* Check if the card command class supports erase command */
+    if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
     {
-      errorstate = SD_WideBus_Disable(hsd);
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
     }
-    else
+
+    if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
     {
-      /* WideMode is not a valid argument*/
-      errorstate = SD_INVALID_PARAMETER;
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
+    }
+
+    /* Get start and end block for high capacity cards */
+    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+    {
+      start_add *= 512U;
+      end_add   *= 512U;
+    }
+
+    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+    if(hsd->SdCard.CardType != CARD_SECURED)
+    {
+      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
+
+      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
+      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
+      }
     }
-      
-    if (errorstate == SD_OK)
+
+    /* Send CMD38 ERASE */
+    errorstate = SDMMC_CmdErase(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
     {
-      /* Configure the SDIO peripheral */
-      tmpinit.ClockEdge           = hsd->Init.ClockEdge;
-      tmpinit.ClockBypass         = hsd->Init.ClockBypass;
-      tmpinit.ClockPowerSave      = hsd->Init.ClockPowerSave;
-      tmpinit.BusWide             = WideMode;
-      tmpinit.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-      tmpinit.ClockDiv            = hsd->Init.ClockDiv;
-      SDIO_Init(hsd->Instance, tmpinit);
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
     }
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
   }
-  
-  return errorstate;
 }
 
 /**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  This function handles SD card interrupt request.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
   */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-  
-  return errorstate;
-}
+  uint32_t errorstate;
+  uint32_t context = hsd->Context;
 
-/**
-  * @brief  Switches the SD card to High Speed mode.
-  *         This API must be used after "Transfer State"
-  * @note   This operation should be followed by the configuration 
-  *         of PLL to have SDIOCK clock between 67 and 75 MHz
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  
-  uint8_t SD_hs[64]  = {0};
-  uint32_t SD_scr[2] = {0, 0};
-  uint32_t SD_SPEC   = 0 ;
-  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
-  
-  /* Initialize the Data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, SD_scr);
-  
-  if (errorstate != SD_OK)
+  /* Check for SDIO interrupt flags */
+  if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
   {
-    return errorstate;
+    SD_Read_IT(hsd);
   }
-  
-  /* Test the Version supported by the card*/ 
-  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
-  
-  if (SD_SPEC != SD_ALLZERO)
+
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)
   {
-    /* Set Block Size for Card */
-    sdio_cmdinitstructure.Argument         = (uint32_t)64;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Configure the SD DPSM (Data Path State Machine) */
-    sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-    sdio_datainitstructure.DataLength    = 64;
-    sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
-    sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-    sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-    SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-    
-    /* Send CMD6 switch mode */
-    sdio_cmdinitstructure.Argument         = 0x80FFFF01;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); 
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
+
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\
+                             SDIO_IT_RXFIFOHF);
+
+    hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);
     
-    if (errorstate != SD_OK)
+    if((context & SD_CONTEXT_IT) != 0U)
     {
-      return errorstate;
-    }
+      if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
 
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->RxCpltCallback(hsd);
+#else
+        HAL_SD_RxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+      else
+      {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else if((context & SD_CONTEXT_DMA) != 0U)
     {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+      if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
       {
-        for (count = 0; count < 8; count++)
+        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+        if(errorstate != HAL_SD_ERROR_NONE)
         {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
+          hsd->ErrorCode |= errorstate;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+          hsd->ErrorCallback(hsd);
+#else
+          HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
         }
-        
-        tempbuff += 8;
+      }
+      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))
+      {
+        /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+        in the SD DCTRL register */
+        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+        hsd->State = HAL_SD_STATE_READY;
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->TxCpltCallback(hsd);
+#else
+        HAL_SD_TxCpltCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
       }
     }
-    
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+    else
     {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-      
-      errorstate = SD_DATA_TIMEOUT;
-      
-      return errorstate;
+      /* Nothing to do */
     }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  }
+
+  else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))
+  {
+    SD_Write_IT(hsd);
+  }
+
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)
+  {
+    /* Set Error code */
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)
     {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-      
-      errorstate = SD_DATA_CRC_FAIL;
-      
-      return errorstate;
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
     }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)
     {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-      
-      errorstate = SD_RX_OVERRUN;
-      
-      return errorstate;
+      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
     }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)
     {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-      
-      errorstate = SD_START_BIT_ERR;
-      
-      return errorstate;
+      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
     }
-    else
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)
     {
-      /* No error flag set */
+      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
     }
-    
-    count = SD_DATATIMEOUT;
-    
-    while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
+
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);
+
+    /* Disable all interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+    if((context & SD_CONTEXT_IT) != 0U)
     {
-      *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-      tempbuff++;
-      count--;
+      /* Set the SD state to ready to be able to start again the process */
+      hsd->State = HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
     }
-    
-    /* Clear all the static flags */
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    
-    /* Test if the switch mode HS is ok */
-    if ((SD_hs[13]& 2) != 2)
+    else if((context & SD_CONTEXT_DMA) != 0U)
+    {
+      /* Abort the SD DMA channel */
+      if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Tx abort callback */
+        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+        {
+          SD_DMATxAbort(hsd->hdmatx);
+        }
+      }
+      else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+      {
+        /* Set the DMA Rx abort callback */
+        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+        /* Abort DMA in IT mode */
+        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+        {
+          SD_DMARxAbort(hsd->hdmarx);
+        }
+      }
+      else
+      {
+        hsd->ErrorCode = HAL_SD_ERROR_NONE;
+        hsd->State = HAL_SD_STATE_READY;
+        hsd->Context = SD_CONTEXT_NONE;
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+        hsd->AbortCpltCallback(hsd);
+#else
+        HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+      }
+    }
+    else
     {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    } 
+      /* Nothing to do */
+    }
+  }
+  else
+  {
+    /* Nothing to do */
   }
-  
-  return errorstate;
 }
 
 /**
-  * @}
+  * @brief return the SD state
+  * @param hsd: Pointer to sd handle
+  * @retval HAL state
   */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+  return hsd->State;
+}
 
-/** @addtogroup SD_Exported_Functions_Group4
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in runtime the status of the peripheral 
-    and the data flow.
+/**
+* @brief  Return the SD error code
+* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+  return hsd->ErrorCode;
+}
 
-@endverbatim
-  * @{
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param hsd: Pointer to SD handle
+  * @retval None
   */
+__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_TxCpltCallback can be implemented in the user file
+   */
+}
 
 /**
-  * @brief  Returns the current SD card's status.
-  * @param  hsd: SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
-  *         SD Status register)
-  * @retval SD Card error state
+  * @brief Rx Transfer completed callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
   */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0;
-  
-  /* Check SD response */
-  if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Set block size for card if it is not equal to current block size for card */
-  sdio_cmdinitstructure.Argument         = 64;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 64;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Send ACMD13 (SD_APP_STATUS)  with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STATUS;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
-  
-  if (errorstate != SD_OK)
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD error callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_ErrorCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief SD Abort callbacks
+  * @param hsd: Pointer SD handle
+  * @retval None
+  */
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsd);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SD_AbortCallback can be implemented in the user file
+   */
+}
+
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SD Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
   {
-    return errorstate;
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
   }
-  
-  /* Get status data */
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+    switch (CallbackID)
     {
-      for (count = 0; count < 8; count++)
-      {
-        *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
-      }
-      
-      pSDstatus += 8;
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = pCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = pCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = pCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = pCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
     }
   }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+  else if (hsd->State == HAL_SD_STATE_RESET)
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = pCallback;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
   }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+  else
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
   }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+
+/**
+  * @brief  Unregister a User SD Callback
+  *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsd : SD handle
+  * @param CallbackID : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID
+  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID
+  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID
+  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID
+  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID
+  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsd);
+
+  if(hsd->State == HAL_SD_STATE_READY)
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
+    switch (CallbackID)
+    {
+    case HAL_SD_TX_CPLT_CB_ID :
+      hsd->TxCpltCallback = HAL_SD_TxCpltCallback;
+      break;
+    case HAL_SD_RX_CPLT_CB_ID :
+      hsd->RxCpltCallback = HAL_SD_RxCpltCallback;
+      break;
+    case HAL_SD_ERROR_CB_ID :
+      hsd->ErrorCallback = HAL_SD_ErrorCallback;
+      break;
+    case HAL_SD_ABORT_CB_ID :
+      hsd->AbortCpltCallback = HAL_SD_AbortCallback;
+      break;
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
   }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  else if (hsd->State == HAL_SD_STATE_RESET)
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
+    switch (CallbackID)
+    {
+    case HAL_SD_MSP_INIT_CB_ID :
+      hsd->MspInitCallback = HAL_SD_MspInit;
+      break;
+    case HAL_SD_MSP_DEINIT_CB_ID :
+      hsd->MspDeInitCallback = HAL_SD_MspDeInit;
+      break;
+    default :
+      /* Update the error code */
+      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
   }
   else
   {
-    /* No error flag set */
-  }  
-  
-  count = SD_DATATIMEOUT;
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
-  {
-    *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
-    pSDstatus++;
-    count--;
+    /* Update the error code */
+    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
   }
-  
-  /* Clear all the static status flags*/
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsd);
+  return status;
+}
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup SD_Exported_Functions_Group3
+ *  @brief   management functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the SD card
+    operations and get the related information
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CID register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that  
+  *         contains all CID register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
+{
+  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);
+
+  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);
+
+  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));
+
+  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);
+
+  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);
+
+  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));
+
+  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);
+
+  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);
+
+  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);
+
+  pCID->Reserved2 = 1U;
+
+  return HAL_OK;
 }
 
-/**
-  * @brief  Gets the current sd card data status.
-  * @param  hsd: SD handle
-  * @retval Data Transfer state
-  */
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
+/**
+  * @brief  Returns information the information of the card which are stored on
+  *         the CSD register.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that  
+  *         contains all CSD register parameters
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
+
+  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
+
+  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
+
+  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
+
+  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
+
+  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
+
+  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
+
+  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
+
+  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
+
+  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
+
+  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
 
-  /* Get SD card state */
-  cardstate = SD_GetState(hsd);
-  
-  /* Find SD status according to card state*/
-  if (cardstate == SD_CARD_TRANSFER)
+  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
+
+  pCSD->Reserved2 = 0U; /*!< Reserved */
+
+  if(hsd->SdCard.CardType == CARD_SDSC)
   {
-    return SD_TRANSFER_OK;
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
+
+    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
+
+    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
+
+    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
+
+    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
+
+    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
+
+    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
+    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
+    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
+
+    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+    hsd->SdCard.LogBlockSize = 512U;
   }
-  else if(cardstate == SD_CARD_ERROR)
+  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
   {
-    return SD_TRANSFER_ERROR;
+    /* Byte 7 */
+    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
+
+    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
+    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
+    hsd->SdCard.BlockSize = 512U;
+    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
   }
   else
   {
-    return SD_TRANSFER_BUSY;
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
   }
+
+  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
+
+  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
+
+  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
+
+  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
+
+  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
+
+  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
+
+  pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
+
+  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
+
+  pCSD->Reserved3 = 0;
+
+  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
+
+  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
+
+  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
+
+  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
+
+  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
+
+  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
+
+  pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
+
+  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
+
+  pCSD->Reserved4 = 1;
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Gets the SD card status.
-  * @param  hsd: SD handle      
-  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
-  *         will contain the SD card status information 
-  * @retval SD Card error state
+  * @brief  Gets the SD status info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that 
+  *         will contain the SD card status information
+  * @retval HAL status
   */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
   uint32_t sd_status[16];
-  
-  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-  
-  if (errorstate  != SD_OK)
+  uint32_t errorstate;
+
+  errorstate = SD_SendSDStatus(hsd, sd_status);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return errorstate;
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->ErrorCode |= errorstate;
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
   }
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0xC0) >> 6;
-  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0x20) >> 5;
-  pCardStatus->SECURED_MODE = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (sd_status[2] & 0xFF);
-  pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
-  
-  /* Byte 3 */
-  tmp = (sd_status[3] & 0xFF);
-  pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (sd_status[4] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
-  
-  /* Byte 5 */
-  tmp = (sd_status[5] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
-  
-  /* Byte 6 */
-  tmp = (sd_status[6] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
-  
-  /* Byte 7 */
-  tmp = (sd_status[7] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
-  
-  /* Byte 8 */
-  tmp = (sd_status[8] & 0xFF);
-  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-  
-  /* Byte 9 */
-  tmp = (sd_status[9] & 0xFF);
-  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-  
-  /* Byte 10 */
-  tmp = (sd_status[10] & 0xF0) >> 4;
-  pCardStatus->AU_SIZE = (uint8_t)tmp;
-  
-  /* Byte 11 */
-  tmp = (sd_status[11] & 0xFF);
-  pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
-  
-  /* Byte 12 */
-  tmp = (sd_status[12] & 0xFF);
-  pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0xFC) >> 2;
-  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0x3);
-  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-  
-  return errorstate;
-}
-         
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Private function ----------------------------------------------------------*/  
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-  
-/**
-  * @brief  SD DMA transfer complete Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
+  else
   {
+    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);
+
+    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);
+
+    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));
+
+    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |
+                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));
+
+    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);
+
+    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);
+
+    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);
+
+    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));
+
+    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);
+
+    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);
   }
-  
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
 
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   
+  return HAL_OK;
 }
 
 /**
-  * @brief  SD DMA transfer Error Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
+  * @brief  Gets the SD card info.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+  *         will contain the SD card status information
+  * @retval HAL status
   */
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
 {
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
+  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
+  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
+  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
+  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
+  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
+  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
+  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
+  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  SD DMA transfer complete Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
+  * @brief  Enables wide bus operation for the requested card if supported by
+  *         card.
+  * @param  hsd: Pointer to SD handle
+  * @param  WideMode: Specifies the SD card wide bus mode
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
+  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+  * @retval HAL status
   */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
 {
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
+  SDIO_InitTypeDef Init;
+  uint32_t errorstate;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+  /* Change State */
+  hsd->State = HAL_SD_STATE_BUSY;
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
+  {
+    if(WideMode == SDIO_BUS_WIDE_8B)
+    {
+      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+    else if(WideMode == SDIO_BUS_WIDE_4B)
+    {
+      errorstate = SD_WideBus_Enable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else if(WideMode == SDIO_BUS_WIDE_1B)
+    {
+      errorstate = SD_WideBus_Disable(hsd);
+
+      hsd->ErrorCode |= errorstate;
+    }
+    else
+    {
+      /* WideMode is not a valid argument*/
+      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+    }
+  }
+  else
   {
+    /* MMC Card does not support this feature */
+    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
   }
- 
-  /* Disable the DMA channel */
-  HAL_DMA_Abort(hdma);
 
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  
-}
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+    hsd->State = HAL_SD_STATE_READY;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Configure the SDIO peripheral */
+    Init.ClockEdge           = hsd->Init.ClockEdge;
+    Init.ClockBypass         = hsd->Init.ClockBypass;
+    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
+    Init.BusWide             = WideMode;
+    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+    Init.ClockDiv            = hsd->Init.ClockDiv;
+    (void)SDIO_Init(hsd->Instance, Init);
+  }
 
-/**
-  * @brief  SD DMA transfer Error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
+  /* Change State */
+  hsd->State = HAL_SD_STATE_READY;
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Returns the SD current state.
-  * @param  hsd: SD handle
-  * @retval SD card current state
+  * @brief  Gets the current sd card data state.
+  * @param  hsd: pointer to SD handle
+  * @retval Card state
   */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
 {
+  uint32_t cardstate;
+  uint32_t errorstate;
   uint32_t resp1 = 0;
-  
-  if (SD_SendStatus(hsd, &resp1) != SD_OK)
-  {
-    return SD_CARD_ERROR;
-  }
-  else
+
+  errorstate = SD_SendStatus(hsd, &resp1);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
+    hsd->ErrorCode |= errorstate;
   }
+
+  cardstate = ((resp1 >> 9U) & 0x0FU);
+
+  return (HAL_SD_CardStateTypeDef)cardstate;
 }
 
 /**
-  * @brief  Initializes all cards or single card as the case may be Card(s) come 
-  *         into standby state.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  Abort the current transfer and disable the SD.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
   */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint16_t sd_rca = 1;
-  
-  if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* DIsable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
   {
-    /* Send CMD2 ALL_SEND_CID */
-    sdio_cmdinitstructure.Argument         = 0;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
     {
-      return errorstate;
+      if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
     }
-    
-    /* Get Card identification number data */
-    hsd->CID[0] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CID[1] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CID[2] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CID[3] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  
-  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-    
-    if(errorstate != SD_OK)
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
     {
-      return errorstate;
+      if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      }
     }
-  }
-  
-  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Get the SD card RCA */
-    hsd->RCA = sd_rca;
-    
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
+    else
     {
-      return errorstate;
+      /* Nothing to do */
     }
-    
-    /* Get Card Specific Data */
-    hsd->CSD[0] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CSD[1] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CSD[2] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CSD[3] = SDIO_GetResponse(SDIO_RESP4);
   }
-  
-  /* All cards are initialized */
-  return errorstate;
-}
 
-/**
-  * @brief  Selects of Deselects the corresponding card.
-  * @param  hsd: SD handle
-  * @param  addr: Address of the card to be selected  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD7 SDIO_SEL_DESEL_CARD */
-  sdio_cmdinitstructure.Argument         = (uint32_t)addr;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-  
-  return errorstate;
+  hsd->State = HAL_SD_STATE_READY;
+
+  /* Initialize the SD operation */
+  hsd->Context = SD_CONTEXT_NONE;
+
+  CardState = HAL_SD_GetCardState(hsd);
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  {
+    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+  }
+  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+  {
+    return HAL_ERROR;
+  }
+  return HAL_OK;
 }
 
 /**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  Abort the current transfer and disable the SD (IT mode).
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *                the configuration information for SD module.
+  * @retval HAL status
   */
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK; 
-  uint32_t response = 0, count = 0, validvoltage = 0;
-  uint32_t sdtype = SD_STD_CAPACITY;
-  
-  /* Power ON Sequence -------------------------------------------------------*/
-  /* Disable SDIO Clock */
-  __HAL_SD_SDIO_DISABLE(); 
-  
-  /* Set Power State to ON */
-  SDIO_PowerState_ON(hsd->Instance);
-  
-  /* 1ms: required power up waiting time before starting the SD initialization 
-     sequence */
-  HAL_Delay(1);
-  
-  /* Enable SDIO Clock */
-  __HAL_SD_SDIO_ENABLE();
-  
-  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
-  /* No CMD response required */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_NO;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdError(hsd);
-  
-  if(errorstate != SD_OK)
-  {
-    /* CMD Response Timeout (wait for CMDSENT flag) */
-    return errorstate;
-  }
-  
-  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdio_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
-  sdio_cmdinitstructure.CmdIndex         = SD_SDIO_SEND_IF_COND;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */ 
-  errorstate = SD_CmdResp7Error(hsd);
-  
-  if (errorstate == SD_OK)
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t context = hsd->Context;
+
+  /* Disable All interrupts */
+  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);
+
+  if ((context & SD_CONTEXT_DMA) != 0U)
   {
-    /* SD Card 2.0 */
-    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; 
-    sdtype        = SD_HIGH_CAPACITY;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  /* If errorstate is Command Timeout, it is a MMC card */
-  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if(errorstate == SD_OK)
-  {
-    /* SD CARD */
-    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-      
-      /* SEND CMD55 APP_CMD with RCA as 0 */
-      sdio_cmdinitstructure.Argument         = 0;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-      
-      if(errorstate != SD_OK)
+    /* Disable the SD DMA request */
+    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+    /* Abort the SD DMA Tx channel */
+    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
       {
-        return errorstate;
+        hsd->hdmatx = NULL;
       }
-      
-      /* Send CMD41 */
-      sdio_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp3Error(hsd);
-      
-      if(errorstate != SD_OK)
+    }
+    /* Abort the SD DMA Rx channel */
+    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
+    {
+      hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
       {
-        return errorstate;
+        hsd->hdmarx = NULL;
       }
-      
-      /* Get command response */
-      response = SDIO_GetResponse(SDIO_RESP1);
-      
-      /* Get operating voltage*/
-      validvoltage = (((response >> 31) == 1) ? 1 : 0);
-      
-      count++;
     }
-    
-    if(count >= SD_MAX_VOLT_TRIAL)
+    else
     {
-      errorstate = SD_INVALID_VOLTRANGE;
-      
-      return errorstate;
+      /* Nothing to do */
     }
-    
-    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+  }
+  /* No transfer ongoing on both DMA channels*/
+  else
+  {
+    /* Clear All flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    CardState = HAL_SD_GetCardState(hsd);
+    hsd->State = HAL_SD_STATE_READY;
+    hsd->Context = SD_CONTEXT_NONE;
+    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
     {
-      hsd->CardType = HIGH_CAPACITY_SD_CARD;
+      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
     }
-    
-  } /* else MMC Card */
-  
-  return errorstate;
+    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
+      hsd->AbortCpltCallback(hsd);
+#else
+      HAL_SD_AbortCallback(hsd);
+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
+    }
+  }
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Turns the SDIO output signals off.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+  * @{
   */
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
+
+/**
+  * @brief  DMA SD transmit process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
+  */
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Set Power State to OFF */
-  SDIO_PowerState_OFF(hsd->Instance);
-  
-  return errorstate;
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+
+  /* Enable DATAEND Interrupt */
+  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
 }
 
 /**
-  * @brief  Returns the current card's status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
-  *         status (Card Status register)  
-  * @retval SD Card error state
+  * @brief  DMA SD receive process complete callback
+  * @param  hdma: DMA handle
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  if(pCardStatus == NULL)
-  {
-    errorstate = SD_INVALID_PARAMETER;
-    
-    return errorstate;
-  }
-  
-  /* Send Status command */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-  
-  if(errorstate != SD_OK)
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  uint32_t errorstate;
+
+  /* Send stop command in multiblock write */
+  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
   {
-    return errorstate;
+    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      hsd->ErrorCode |= errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+      hsd->ErrorCallback(hsd);
+#else
+      HAL_SD_ErrorCallback(hsd);
+#endif
+    }
   }
-  
-  /* Get SD card status */
-  *pCardStatus = SDIO_GetResponse(SDIO_RESP1);
-  
-  return errorstate;
+
+  /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+  in the SD DCTRL register */
+  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+  /* Clear all the static flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+  hsd->RxCpltCallback(hsd);
+#else
+  HAL_SD_RxCpltCallback(hsd);
+#endif
 }
 
 /**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  DMA SD communication error callback
+  * @param  hdma: DMA handle
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout, tmp;
-  
-  timeout = SDIO_CMD0TIMEOUT;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    
-  while((timeout > 0) && (!tmp))
-  {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    timeout--;
-  }
-  
-  if(timeout == 0)
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+  uint32_t RxErrorCode, TxErrorCode;
+
+  /* if DMA error is FIFO error ignore it */
+  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
   {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    return errorstate;
+    RxErrorCode = hsd->hdmarx->ErrorCode;
+    TxErrorCode = hsd->hdmatx->ErrorCode;  
+    if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
+    {
+      /* Clear All flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+      /* Disable All interrupts */
+      __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+        SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+      hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+      CardState = HAL_SD_GetCardState(hsd);
+      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+      {
+        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+      }
+
+      hsd->State= HAL_SD_STATE_READY;
+      hsd->Context = SD_CONTEXT_NONE;
+    }
+
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
   }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
 }
 
 /**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  DMA SD Tx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_ERROR;
-  uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); 
-  
-  while((!tmp) && (timeout > 0))
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
   {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
-    timeout--;
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
   }
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); 
-  
-  if((timeout == 0) || tmp)
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
   {
-    /* Card is not V2.0 compliant or card does not support the set voltage range */
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
   }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
+  else
   {
-    /* Card is SD V2.0 compliant */
-    errorstate = SD_OK;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
-    
-    return errorstate;
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
   }
-  
-  return errorstate;
 }
 
 /**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index  
-  * @retval SD Card error state
+  * @brief  DMA SD Rx Abort callback
+  * @param  hdma: DMA handle
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
+  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+  HAL_SD_CardStateTypeDef CardState;
+
+  /* Clear All flags */
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  CardState = HAL_SD_GetCardState(hsd);
+  hsd->State = HAL_SD_STATE_READY;
+  hsd->Context = SD_CONTEXT_NONE;
+  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
   {
-    return(SD_BLOCK_LEN_ERR);
+    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
   }
-  
-  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
+
+  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)
   {
-    return(SD_ERASE_SEQ_ERR);
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->AbortCpltCallback(hsd);
+#else
+    HAL_SD_AbortCallback(hsd);
+#endif
   }
-  
-  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
+  else
   {
-    return(SD_BAD_ERASE_PARAM);
+#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
+    hsd->ErrorCallback(hsd);
+#else
+    HAL_SD_ErrorCallback(hsd);
+#endif
   }
-  
-  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
+}
+
+/**
+  * @brief  Initializes the sd card.
+  * @param  hsd: Pointer to SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
+{
+  HAL_SD_CardCSDTypeDef CSD;
+  uint32_t errorstate;
+  uint16_t sd_rca = 1U;
+
+  /* Check the power State */
+  if(SDIO_GetPowerState(hsd->Instance) == 0U)
   {
-    return(SD_WRITE_PROT_VIOLATION);
+    /* Power off */
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
   }
-  
-  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
   {
-    return(SD_LOCK_UNLOCK_FAILED);
+    /* Send CMD2 ALL_SEND_CID */
+    errorstate = SDMMC_CmdSendCID(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card identification number data */
+      hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+      hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+      hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+      hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+    }
   }
-  
-  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
+
+  if(hsd->SdCard.CardType != CARD_SECURED)
   {
-    return(SD_COM_CRC_FAILED);
+    /* Send CMD3 SET_REL_ADDR with argument 0 */
+    /* SD Card publishes its RCA. */
+    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
   }
-  
-  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
+  if(hsd->SdCard.CardType != CARD_SECURED)
   {
-    return(SD_ILLEGAL_CMD);
+    /* Get the SD card RCA */
+    hsd->SdCard.RelCardAdd = sd_rca;
+
+    /* Send CMD9 SEND_CSD with argument as card's RCA */
+    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+    else
+    {
+      /* Get Card Specific Data */
+      hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+      hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+      hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+      hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+    }
   }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
+
+  /* Get the Card Class */
+  hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
+
+  /* Get CSD parameters */
+  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
   {
-    return(SD_CARD_ECC_FAILED);
+    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
   }
-  
-  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
+
+  /* Select the Card */
+  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return(SD_CC_ERROR);
+    return errorstate;
   }
-  
-  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
+
+  /* Configure SDIO peripheral interface */
+  (void)SDIO_Init(hsd->Instance, hsd->Init);
+
+  /* All cards are initialized */
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Enquires cards about their operating voltage and configures clock
+  *         controls and stores SD information that will be needed in future
+  *         in the SD handle.
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
+  */
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
+{
+  __IO uint32_t count = 0U;
+  uint32_t response = 0U, validvoltage = 0U;
+  uint32_t errorstate;
+
+  /* CMD0: GO_IDLE_STATE */
+  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return(SD_GENERAL_UNKNOWN_ERROR);
+    return errorstate;
   }
-  
-  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
+
+  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+  errorstate = SDMMC_CmdOperCond(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return(SD_STREAM_READ_UNDERRUN);
+    hsd->SdCard.CardVersion = CARD_V1_X;
+    /* CMD0: GO_IDLE_STATE */
+    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
   }
-  
-  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
+  else
   {
-    return(SD_STREAM_WRITE_OVERRUN);
+    hsd->SdCard.CardVersion = CARD_V2_X;
   }
-  
-  if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
+
+  if( hsd->SdCard.CardVersion == CARD_V2_X)
   {
-    return(SD_CID_CSD_OVERWRITE);
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
   }
-  
-  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
+  /* SD CARD */
+  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+  while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
   {
-    return(SD_WP_ERASE_SKIP);
+    /* SEND CMD55 APP_CMD with RCA as 0 */
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return errorstate;
+    }
+
+    /* Send CMD41 */
+    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+    }
+
+    /* Get command response */
+    response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+    /* Get operating voltage*/
+    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+
+    count++;
   }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
+
+  if(count >= SDMMC_MAX_VOLT_TRIAL)
   {
-    return(SD_CARD_ECC_DISABLED);
+    return HAL_SD_ERROR_INVALID_VOLTRANGE;
   }
-  
-  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+
+  if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
   {
-    return(SD_ERASE_RESET);
+    hsd->SdCard.CardType = CARD_SDHC_SDXC;
   }
-  
-  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+  else
   {
-    return(SD_AKE_SEQ_ERROR);
+    hsd->SdCard.CardType = CARD_SDSC;
   }
-  
-  return errorstate;
+
+
+  return HAL_SD_ERROR_NONE;
 }
 
 /**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  Turns the SDIO output signals off.
+  * @param  hsd: Pointer to SD handle
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
+static void SD_PowerOFF(SD_HandleTypeDef *hsd)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
+  /* Set Power State to OFF */
+  (void)SDIO_PowerState_OFF(hsd->Instance);
 }
 
 /**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @brief  Send Status info command.
+  * @param  hsd: pointer to SD handle
+  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
+  *         SD Status register)
+  * @retval error state
   */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
 {
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t count;
+  uint32_t *pData = pSDstatus;
+
+  /* Check SD response */
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
   {
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
   }
-    
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+
+  /* Set block size for card if it is not equal to current block size for card */
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
     return errorstate;
   }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+
+  /* Send CMD55 */
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
     return errorstate;
   }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
 
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
-  *         address RCA   
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+  /* Configure the SD DPSM (Data Path State Machine) */
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 64U;
+  config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDIO_DPSM_ENABLE;
+  (void)SDIO_ConfigData(hsd->Instance, &config);
+
+  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
+  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
+    hsd->ErrorCode |= HAL_SD_ERROR_NONE;
     return errorstate;
   }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
+
+  /* Get status data */
+  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
   {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+    {
+      for(count = 0U; count < 8U; count++)
+      {
+        *pData = SDIO_ReadFIFO(hsd->Instance);
+        pData++;
+      }
+    }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
   }
-  else
+
+  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
   {
-    /* No error flag set */
+    return HAL_SD_ERROR_DATA_TIMEOUT;
   }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
   {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
   }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it.  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
   {
-    *pRCA = (uint16_t) (response_r1 >> 16);
-    
-    return errorstate;
+    return HAL_SD_ERROR_RX_OVERRUN;
   }
-  
-  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
+  else
   {
-    return(SD_GENERAL_UNKNOWN_ERROR);
+    /* Nothing to do */
   }
-  
-  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
+
+  while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+  {
+    *pData = SDIO_ReadFIFO(hsd->Instance);
+    pData++;
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
+  }
+
+  /* Clear all the static status flags*/
+  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+  return HAL_SD_ERROR_NONE;
+}
+
+/**
+  * @brief  Returns the current card's status.
+  * @param  hsd: Pointer to SD handle
+  * @param  pCardStatus: pointer to the buffer that will contain the SD card
+  *         status (Card Status register)
+  * @retval error state
+  */
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+{
+  uint32_t errorstate;
+
+  if(pCardStatus == NULL)
   {
-    return(SD_ILLEGAL_CMD);
+    return HAL_SD_ERROR_PARAM;
   }
-  
-  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
+
+  /* Send Status command */
+  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
-    return(SD_COM_CRC_FAILED);
+    return errorstate;
   }
-  
-  return errorstate;
+
+  /* Get SD card status */
+  *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+  return HAL_SD_ERROR_NONE;
 }
 
 /**
   * @brief  Enables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @param  hsd: pointer to SD handle
+  * @retval error state
   */
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
   {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
   }
-  
+
   /* Get SCR Register */
   errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
     return errorstate;
   }
-  
+
   /* If requested card supports wide bus operation */
-  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+  if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
   {
     /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
     }
-    
+
     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    sdio_cmdinitstructure.Argument         = 2;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+    if(errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
     }
-    
-    return errorstate;
+
+    return HAL_SD_ERROR_NONE;
   }
   else
   {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
   }
-}   
+}
 
 /**
   * @brief  Disables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
+  * @param  hsd: Pointer to SD handle
+  * @retval error state
   */
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+  uint32_t scr[2U] = {0U, 0U};
+  uint32_t errorstate;
+
+  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
   {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
+    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
   }
-  
+
   /* Get SCR Register */
   errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
     return errorstate;
   }
-  
+
   /* If requested card supports 1 bit mode operation */
-  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+  if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
   {
     /* Send CMD55 APP_CMD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
+    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+    if(errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
     }
-    
+
     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    sdio_cmdinitstructure.Argument         = 0;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
+    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+    if(errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
     }
-    
-    return errorstate;
+
+    return HAL_SD_ERROR_NONE;
   }
   else
   {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
+    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
   }
 }
-  
-  
+
+
 /**
   * @brief  Finds the SD card SCR register value.
-  * @param  hsd: SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value  
-  * @retval SD Card error state
+  * @param  hsd: Pointer to SD handle
+  * @param  pSCR: pointer to the buffer that will contain the SCR value
+  * @retval error state
   */
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
 {
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t index = 0;
-  uint32_t tempscr[2] = {0, 0};
-  
+  SDIO_DataInitTypeDef config;
+  uint32_t errorstate;
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t index = 0U;
+  uint32_t tempscr[2U] = {0U, 0U};
+  uint32_t *scr = pSCR;
+
   /* Set Block Size To 8 Bytes */
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)8;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if(errorstate != SD_OK)
+  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
     return errorstate;
   }
-  
+
   /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if(errorstate != SD_OK)
+  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
     return errorstate;
   }
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 8;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
+
+  config.DataTimeOut   = SDMMC_DATATIMEOUT;
+  config.DataLength    = 8U;
+  config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
+  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
+  config.DPSM          = SDIO_DPSM_ENABLE;
+  (void)SDIO_ConfigData(hsd->Instance, &config);
+
   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-  
-  if(errorstate != SD_OK)
+  errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+  if(errorstate != HAL_SD_ERROR_NONE)
   {
     return errorstate;
   }
 
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
   {
-    if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
     {
       *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
       index++;
     }
+
+    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+    {
+      return HAL_SD_ERROR_TIMEOUT;
+    }
   }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+
+  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+
+    return HAL_SD_ERROR_DATA_TIMEOUT;
   }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+
+    return HAL_SD_ERROR_DATA_CRC_FAIL;
   }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
+  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
   {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+
+    return HAL_SD_ERROR_RX_OVERRUN;
   }
   else
   {
     /* No error flag set */
+    /* Clear all the static flags */
+    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
+
+    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
+    scr++;
+    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
+            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
+
   }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
-    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-  
-  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
-    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-  
-  return errorstate;
+
+  return HAL_SD_ERROR_NONE;
 }
 
 /**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  hsd: SD handle
-  * @param  pStatus: pointer to the variable that will contain the SD card state  
-  * @retval SD Card error state
+  * @brief  Wrap up reading in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
   */
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
+static void SD_Read_IT(SD_HandleTypeDef *hsd)
 {
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  __IO uint32_t responseR1 = 0;
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  
-  /* We have received response, retrieve it for analysis */
-  responseR1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  /* Find out card status */
-  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
-  
-  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pRxBuffPtr;
+  dataremaining = hsd->RxXferSize;
+
+  if (dataremaining > 0U)
   {
-    return(SD_ERASE_RESET);
+    /* Read data from SDIO Rx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = SDIO_ReadFIFO(hsd->Instance);
+      *tmp = (uint8_t)(data & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 8U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 16U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+      *tmp = (uint8_t)((data >> 24U) & 0xFFU);
+      tmp++;
+      dataremaining--;
+    }
+
+    hsd->pRxBuffPtr = tmp;
+    hsd->RxXferSize = dataremaining;
   }
-  
-  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
+}
+
+/**
+  * @brief  Wrap up writing in non-blocking mode.
+  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
+  *              the configuration information.
+  * @retval None
+  */
+static void SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+  uint32_t count, data, dataremaining;
+  uint8_t* tmp;
+
+  tmp = hsd->pTxBuffPtr;
+  dataremaining = hsd->TxXferSize;
+
+  if (dataremaining > 0U)
   {
-    return(SD_AKE_SEQ_ERROR);
+    /* Write data to SDIO Tx FIFO */
+    for(count = 0U; count < 8U; count++)
+    {
+      data = (uint32_t)(*tmp);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 8U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 16U);
+      tmp++;
+      dataremaining--;
+      data |= ((uint32_t)(*tmp) << 24U);
+      tmp++;
+      dataremaining--;
+      (void)SDIO_WriteFIFO(hsd->Instance, &data);
+    }
+
+    hsd->pTxBuffPtr = tmp;
+    hsd->TxXferSize = dataremaining;
   }
-  
-  return errorstate;
-}   
+}
 
 /**
   * @}
@@ -3427,4 +3238,6 @@ static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *
   * @}
   */
 
+#endif /* SDIO */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c
index 0d424cae..3e0e015e 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_smartcard.c
@@ -2,28 +2,27 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   SMARTCARD HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the SMARTCARD peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral State and Errors functions 
-  *           
-  @verbatim       
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
   ==============================================================================
                      ##### How to use this driver #####
   ==============================================================================
     [..]
       The SMARTCARD HAL driver can be used as follows:
-    
+
     (#) Declare a SMARTCARD_HandleTypeDef handle structure.
     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
-        (##) Enable the USARTx interface clock.
+        (##) Enable the interface clock of the USARTx associated to the SMARTCARD.
         (##) SMARTCARD pins configuration:
             (+++) Enable the clock for the SMARTCARD GPIOs.
-            (+++) Configure these SMARTCARD pins as alternate function pull-up.
+            (+++) Configure SMARTCARD pins as alternate function pull-up.
         (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
              and HAL_SMARTCARD_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
@@ -32,100 +31,146 @@
              and HAL_SMARTCARD_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx stream.
             (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx stream.
             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+                  (used for last byte sending completion detection in DMA non circular mode)
 
-    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
         flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
 
     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
         (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SMARTCARD_MspInit() API.
-    [..]  
-    (@) The specific SMARTCARD interrupts (Transmission complete interrupt, 
+    [..]
+    (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
         RXNE interrupt and Error Interrupts) will be managed using the macros
         __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-                   
-    [..]   
-    Three operation modes are available within this driver :     
-  
+
+    [..]
+    Three operation modes are available within this driver :
+
     *** Polling mode IO operation ***
     =================================
-    [..]    
-      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() 
+    [..]
+      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-       
-    *** Interrupt mode IO operation ***    
+
+    *** Interrupt mode IO operation ***
     ===================================
-    [..]    
-      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() 
-      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
+    [..]
+      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
+      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() 
-      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
+      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
+      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
-      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
+      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
 
-    *** DMA mode IO operation ***    
+    *** DMA mode IO operation ***
     ==============================
-    [..] 
-      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() 
-      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
+    [..]
+      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() 
-      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
+      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
-      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
-          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback    
+      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
 
     *** SMARTCARD HAL driver macros list ***
-    ============================================= 
+    ========================================
     [..]
       Below the list of most used macros in SMARTCARD HAL driver.
-       
-      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral 
-      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral     
+
+      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
       (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-    
-    [..]  
+
+    [..]
       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-          
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
+    Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : SMARTCARD MspInit.
+    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : SMARTCARD MspInit.
+    (+) MspDeInitCallback         : SMARTCARD MspDeInit.
+
+    [..]
+    By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
+    and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
+    or @ref HAL_SMARTCARD_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -135,7 +180,7 @@
   */
 
 /** @defgroup SMARTCARD SMARTCARD
-  * @brief HAL USART SMARTCARD module driver
+  * @brief HAL SMARTCARD module driver
   * @{
   */
 #ifdef HAL_SMARTCARD_MODULE_ENABLED
@@ -144,48 +189,59 @@
 /** @addtogroup SMARTCARD_Private_Constants
   * @{
   */
-#define SMARTCARD_TIMEOUT_VALUE  22000
 /**
   * @}
   */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /** @addtogroup SMARTCARD_Private_Functions
   * @{
   */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
 static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
 /**
   * @}
   */
+
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
   * @{
   */
 
-/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-@verbatim 
+@verbatim
   ==============================================================================
               ##### Initialization and Configuration functions #####
   ==============================================================================
   [..]
-  This subsection provides a set of functions allowing to initialize the USART 
+  This subsection provides a set of functions allowing to initialize the USART
   in Smartcard mode.
   [..]
   The Smartcard interface is designed to support asynchronous protocol Smartcards as
   defined in the ISO 7816-3 standard.
   [..]
   The USART can provide a clock to the smartcard through the SCLK output.
-  In smartcard mode, SCLK is not associated to the communication but is simply derived 
+  In smartcard mode, SCLK is not associated to the communication but is simply derived
   from the internal peripheral input clock through a 5-bit prescaler.
   [..]
   (+) For the Smartcard mode only these parameters can be configured:
@@ -193,13 +249,6 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
       (++) Word Length => Should be 9 bits (8 bits + parity)
       (++) Stop Bit
       (++) Parity: => Should be enabled
-
-      (+++) +-------------------------------------------------------------+
-      (+++) |   M bit |  PCE bit  |        SMARTCARD frame                |
-      (+++) |---------------------|---------------------------------------|
-      (+++) |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-      (+++) +-------------------------------------------------------------+
-
       (++) USART polarity
       (++) USART phase
       (++) USART LastBit
@@ -217,21 +266,29 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
   [..]
   Please refer to the ISO 7816-3 specification for more details.
 
-    -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended 
-        to use 1.5 stop bits for both transmitting and receiving to avoid switching 
-        between the two configurations.
   [..]
-    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration 
-    procedure (details for the procedure are available in reference manual (RM0329)).
+   (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
+       to use 1.5 stop bits for both transmitting and receiving to avoid switching
+       between the two configurations.
+  [..]
+    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
+    procedures (details for the procedures are available in reference manual (RM0033)).
 
 @endverbatim
+
+  The SMARTCARD frame format is given in the following table:
+       +-------------------------------------------------------------+
+       |   M bit |  PCE bit  |        SMARTCARD frame                |
+       |---------------------|---------------------------------------|
+       |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+       +-------------------------------------------------------------+
   * @{
   */
 
 /**
-  * @brief Initializes the SmartCard mode according to the specified
-  *         parameters in the SMARTCARD_InitTypeDef and create the associated handle .
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief  Initializes the SmartCard mode according to the specified
+  *         parameters in the SMARTCARD_InitTypeDef and create the associated handle.
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval HAL status
   */
@@ -247,36 +304,49 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
   assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
 
-  if(hsc->State == HAL_SMARTCARD_STATE_RESET)
-  {  
+  if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hsc->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+    SMARTCARD_InitCallbacksToDefault(hsc);
+
+    if (hsc->MspInitCallback == NULL)
+    {
+      hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
+    }
+
+    /* Init the low level hardware */
+    hsc->MspInitCallback(hsc);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_SMARTCARD_MspInit(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
   }
-  
-  hsc->State = HAL_SMARTCARD_STATE_BUSY;
+
+  hsc->gState = HAL_SMARTCARD_STATE_BUSY;
 
   /* Set the Prescaler */
   MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
 
   /* Set the Guard Time */
-  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
+  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
 
   /* Set the Smartcard Communication parameters */
   SMARTCARD_SetConfig(hsc);
 
-  /* In SmartCard mode, the following bits must be kept cleared: 
+  /* In SmartCard mode, the following bits must be kept cleared:
   - LINEN bit in the USART_CR2 register
   - HDSEL and IREN bits in the USART_CR3 register.*/
-  hsc->Instance->CR2 &= ~USART_CR2_LINEN;
-  hsc->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_HDSEL);
+  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
 
   /* Enable the SMARTCARD Parity Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+  SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
 
   /* Enable the SMARTCARD Framing Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+  SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
   /* Enable the Peripheral */
   __HAL_SMARTCARD_ENABLE(hsc);
@@ -289,14 +359,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
 
   /* Initialize the SMARTCARD state*/
   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->State= HAL_SMARTCARD_STATE_READY;
+  hsc->gState= HAL_SMARTCARD_STATE_READY;
+  hsc->RxState= HAL_SMARTCARD_STATE_READY;
 
   return HAL_OK;
 }
 
 /**
-  * @brief DeInitializes the USART SmartCard peripheral 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief DeInitializes the USART SmartCard peripheral
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval HAL status
   */
@@ -311,16 +382,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
   /* Check the parameters */
   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
 
-  hsc->State = HAL_SMARTCARD_STATE_BUSY;
+  hsc->gState = HAL_SMARTCARD_STATE_BUSY;
 
   /* Disable the Peripheral */
   __HAL_SMARTCARD_DISABLE(hsc);
 
   /* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+  if (hsc->MspDeInitCallback == NULL)
+  {
+    hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hsc->MspDeInitCallback(hsc);
+#else
   HAL_SMARTCARD_MspDeInit(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 
   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->State = HAL_SMARTCARD_STATE_RESET;
+  hsc->gState = HAL_SMARTCARD_STATE_RESET;
+  hsc->RxState = HAL_SMARTCARD_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(hsc);
@@ -329,66 +410,296 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
 }
 
 /**
-  * @brief SMARTCARD MSP Init
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief  SMARTCARD MSP Init
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval None
   */
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit can be implemented in the user file
    */
 }
 
 /**
   * @brief SMARTCARD MSP DeInit
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval None
   */
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_MspDeInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
    */
 }
 
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SMARTCARD Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hsc smartcard handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hsc);
+
+  if (hsc->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+
+      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+        hsc->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+        hsc->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ERROR_CB_ID :
+        hsc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+        hsc->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hsc->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hsc->AbortReceiveCpltCallback = pCallback;
+        break;
+
+
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hsc->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsc);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an SMARTCARD callback
+  *         SMARTCARD callback is redirected to the weak predefined callback
+  * @param  hsc smartcard handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hsc);
+
+  if (HAL_SMARTCARD_STATE_READY == hsc->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+        hsc->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+        hsc->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_SMARTCARD_ERROR_CB_ID :
+        hsc->ErrorCallback = HAL_SMARTCARD_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+        hsc->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+        hsc->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsc->MspInitCallback = HAL_SMARTCARD_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SMARTCARD_STATE_RESET == hsc->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SMARTCARD_MSPINIT_CB_ID :
+        hsc->MspInitCallback = HAL_SMARTCARD_MspInit;
+        break;
+
+      case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+        hsc->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsc);
+
+  return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
 
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions 
-  *  @brief   SMARTCARD Transmit and Receive functions 
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+  * @brief    SMARTCARD Transmit and Receive functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### IO operation functions #####
  ===============================================================================
-    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-    [..]
-    Smartcard is a single wire half duplex communication protocol. 
+ [..]
+   This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+ [..]
+    (#) Smartcard is a single wire half duplex communication protocol.
     The Smartcard interface is designed to support asynchronous protocol Smartcards as
-    defined in the ISO 7816-3 standard. The USART should be configured as:
-    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
-    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+    defined in the ISO 7816-3 standard.
+    (#) The USART should be configured as:
+       (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+       (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
 
     (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) Non Blocking mode: The communication is performed using Interrupts 
+       (++) Blocking mode: The communication is performed in polling mode.
+            The HAL status of all data processing is returned by the same function
+            after finishing transfer.
+       (++) Non Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the 
-           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when 
+           The end of the data processing will be indicated through the
+           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
-           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks 
+           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
            will be executed respectively at the end of the Transmit or Receive process
            The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
 
     (#) Blocking mode APIs are :
         (++) HAL_SMARTCARD_Transmit()
-        (++) HAL_SMARTCARD_Receive() 
+        (++) HAL_SMARTCARD_Receive()
 
     (#) Non Blocking mode APIs with Interrupt are :
         (++) HAL_SMARTCARD_Transmit_IT()
@@ -404,28 +715,51 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
         (++) HAL_SMARTCARD_RxCpltCallback()
         (++) HAL_SMARTCARD_ErrorCallback()
 
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_SMARTCARD_Abort()
+        (+) HAL_SMARTCARD_AbortTransmit()
+        (+) HAL_SMARTCARD_AbortReceive()
+        (+) HAL_SMARTCARD_Abort_IT()
+        (+) HAL_SMARTCARD_AbortTransmit_IT()
+        (+) HAL_SMARTCARD_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_SMARTCARD_AbortCpltCallback()
+        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief Send an amount of data in blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Send an amount of data in blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be sent
-  * @param Timeout: Timeout duration 
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+  uint32_t tickstart = 0U;
+
+  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
@@ -434,44 +768,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
     __HAL_LOCK(hsc);
 
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-    
+    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
+
     hsc->TxXferSize = Size;
     hsc->TxXferCount = Size;
-    while(hsc->TxXferCount > 0)
+    while(hsc->TxXferCount > 0U)
     {
-      hsc->TxXferCount--;      
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+      hsc->TxXferCount--;
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
       tmp = (uint16_t*) pData;
       hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
-      pData +=1;
+      pData +=1U;
     }
-    
-    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
 
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_READY;
-    }
+	/* At end of Tx process, restore hsc->gState to Ready */
+    hsc->gState = HAL_SMARTCARD_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
 
@@ -484,67 +807,53 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
 }
 
 /**
-  * @brief Receive an amount of data in blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Receive an amount of data in blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be received
-  * @param Timeout: Timeout duration   
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be received
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+  uint32_t tickstart = 0U;
+
+  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
 
     /* Process Locked */
     __HAL_LOCK(hsc);
-    
+
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
 
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
 
     hsc->RxXferSize = Size;
     hsc->RxXferCount = Size;
 
     /* Check the remain data to be received */
-    while(hsc->RxXferCount > 0)
+    while(hsc->RxXferCount > 0U)
     {
       hsc->RxXferCount--;
-      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
       tmp = (uint16_t*) pData;
-      *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
-      pData +=1;
+      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+      pData +=1U;
     }
 
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_READY;
-    }
+    /* At end of Rx process, restore hsc->RxState to Ready */
+    hsc->RxState = HAL_SMARTCARD_STATE_READY;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
@@ -558,21 +867,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
 }
 
 /**
-  * @brief Send an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Send an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be sent
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+  /* Check that a Tx process is not already ongoing */
+  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -585,27 +892,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
     hsc->TxXferCount = Size;
 
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
+    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
-    
+
     /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
 
     /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the SMARTCARD Transmit data register empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
+    SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
@@ -616,21 +915,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_
 }
 
 /**
-  * @brief Receive an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Receive an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be received
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+  /* Check that a Rx process is not already ongoing */
+  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -643,26 +940,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
     hsc->RxXferCount = Size;
 
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
+    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
-    
-    /* Enable the SMARTCARD Data Register not empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); 
 
-    /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+    /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
 
     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
     return HAL_OK;
   }
@@ -673,22 +960,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t
 }
 
 /**
-  * @brief Send an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Send an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be sent
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
+
+  /* Check that a Tx process is not already ongoing */
+  if(hsc->gState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -701,15 +987,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
     hsc->TxXferCount = Size;
 
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
+    hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
 
     /* Set the SMARTCARD DMA transfer complete callback */
     hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@@ -717,20 +995,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
     /* Set the DMA error callback */
     hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
 
-    /* Enable the SMARTCARD transmit DMA Stream */
+    /* Set the DMA abort callback */
+    hsc->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the SMARTCARD transmit DMA stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
 
      /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the SMARTCARD CR3 register */
-    hsc->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
 
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the SMARTCARD CR3 register */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -740,23 +1021,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8
 }
 
 /**
-  * @brief Receive an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Receive an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
-  * @param pData: pointer to data buffer
-  * @param Size: amount of data to be received
+  * @param  pData  Pointer to data buffer
+  * @param  Size   Amount of data to be received
   * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
+
+  /* Check that a Rx process is not already ongoing */
+  if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
   {
-    if((pData == NULL) || (Size == 0)) 
+    if((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -768,15 +1048,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
     hsc->RxXferSize = Size;
 
     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
+    hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
 
     /* Set the SMARTCARD DMA transfer complete callback */
     hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
@@ -784,17 +1056,29 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
     /* Set the DMA error callback */
     hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
 
-    /* Enable the DMA Stream */
+    /* Set the DMA abort callback */
+    hsc->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the DMA stream */
     tmp = (uint32_t*)&pData;
     HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
 
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-    in the SMARTCARD CR3 register */
-    hsc->Instance->CR3 |= USART_CR3_DMAR;
+    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+    __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hsc);
 
+    /* Enable the SMARTCARD Parity Error Interrupt */
+    SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+    in the SMARTCARD CR3 register */
+    SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
     return HAL_OK;
   }
   else
@@ -804,151 +1088,708 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_
 }
 
 /**
-  * @brief This function handles SMARTCARD interrupt request.
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
 {
-  uint32_t tmp1 = 0, tmp2 = 0; 
-  
-  tmp1 = hsc->Instance->SR;  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
-
-  /* SMARTCARD parity error interrupt occurred --------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD frame error interrupt occurred ---------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD noise error interrupt occurred ---------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
-  }
-
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD Over-Run interrupt occurred ------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
-  }
-  
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
-  /* SMARTCARD in mode Receiver ----------------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
-  { 
-    SMARTCARD_Receive_IT(hsc);
-  }
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
 
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
-  /* SMARTCARD in mode Transmitter -------------------------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_TXE) != RESET) && (tmp2 != RESET))
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
   {
-    SMARTCARD_Transmit_IT(hsc);
-  }
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
 
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
-  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
-  if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
-  {
-    SMARTCARD_EndTransmit_IT(hsc);
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsc->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsc->hdmatx);
+    }
   }
-  
-  /* Call the Error call Back in case of Errors */
-  if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
   {
-    /* Set the SMARTCARD state ready to be able to start again the process */
-    hsc->State= HAL_SMARTCARD_STATE_READY;
-    HAL_SMARTCARD_ErrorCallback(hsc);
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsc->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsc->hdmarx);
+    }
   }
-}
 
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
-   */ 
+  /* Reset Tx and Rx transfer counters */
+  hsc->TxXferCount = 0x00U;
+  hsc->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Restore hsc->RxState and hsc->gState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
 }
 
 /**
-  * @brief Rx Transfer completed callbacks
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
-   */
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsc->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsc->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hsc->TxXferCount = 0x00U;
+
+  /* Restore hsc->gState to Ready */
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
 }
 
 /**
-  * @brief SMARTCARD error callbacks
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
-   */ 
-}
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      hsc->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsc->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hsc->RxXferCount = 0x00U;
+
+  /* Restore hsc->RxState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hsc->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+    }
+    else
+    {
+      hsc->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hsc->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+    }
+    else
+    {
+      hsc->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at SMARTCARD level */
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsc->hdmatx != NULL)
+    {
+      /* SMARTCARD Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+      {
+        hsc->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsc->hdmarx != NULL)
+    {
+      /* SMARTCARD Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+      {
+        hsc->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if(AbortCplt == 0x01U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hsc->TxXferCount = 0x00U;
+    hsc->RxXferCount = 0x00U;
+
+    /* Reset ErrorCode */
+    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Restore hsc->gState and hsc->RxState to Ready */
+    hsc->gState  = HAL_SMARTCARD_STATE_READY;
+    hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    hsc->AbortCpltCallback(hsc);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
+        hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hsc->TxXferCount = 0x00U;
+
+      /* Restore hsc->gState to Ready */
+      hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      hsc->AbortTransmitCpltCallback(hsc);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hsc->TxXferCount = 0x00U;
+
+    /* Restore hsc->gState to Ready */
+    hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    hsc->AbortTransmitCpltCallback(hsc);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hsc SMARTCARD handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsc->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback :
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
+        hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hsc->RxXferCount = 0x00U;
+
+      /* Restore hsc->RxState to Ready */
+      hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      hsc->AbortReceiveCpltCallback(hsc);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hsc->RxXferCount = 0x00U;
+
+    /* Restore hsc->RxState to Ready */
+    hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    hsc->AbortReceiveCpltCallback(hsc);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief This function handles SMARTCARD interrupt request.
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+{
+  uint32_t isrflags   = READ_REG(hsc->Instance->SR);
+  uint32_t cr1its     = READ_REG(hsc->Instance->CR1);
+  uint32_t cr3its     = READ_REG(hsc->Instance->CR3);
+  uint32_t dmarequest = 0x00U;
+  uint32_t errorflags = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if(errorflags == RESET)
+  {
+    /* SMARTCARD in mode Receiver -------------------------------------------------*/
+    if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      SMARTCARD_Receive_IT(hsc);
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* SMARTCARD parity error interrupt occurred ---------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
+
+    /* SMARTCARD frame error interrupt occurred ----------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred ----------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
+    if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+    /* Call the Error call Back in case of Errors --------------------------*/
+    if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver ----------------------------------------*/
+      if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        SMARTCARD_Receive_IT(hsc);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+      if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+          Set the SMARTCARD state ready to be able to start again the process,
+          Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsc);
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if(hsc->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback :
+              will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+           if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+            }
+          }
+          else
+          {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+            /* Call registered user error callback */
+            hsc->ErrorCallback(hsc);
+#else
+            /* Call legacy weak user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+          }
+        }
+        else
+        {
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+          /* Call registered user error callback */
+          hsc->ErrorCallback(hsc);
+#else
+          /* Call legacy weak user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+        /* Call registered user error callback */
+        hsc->ErrorCallback(hsc);
+#else
+        /* Call legacy weak user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+        hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
+  /* SMARTCARD in mode Transmitter ------------------------------------------*/
+  if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    SMARTCARD_Transmit_IT(hsc);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter (transmission end) -----------------------*/
+  if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    SMARTCARD_EndTransmit_IT(hsc);
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callbacks
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief SMARTCARD error callback
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsc SMARTCARD handle.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Transmit Complete callback.
+  * @param  hsc SMARTCARD handle.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+    /* Prevent unused argument(s) compilation warning */
+    UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Receive Complete callback.
+  * @param  hsc SMARTCARD handle.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+    /* Prevent unused argument(s) compilation warning */
+    UNUSED(hsc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
 
 /**
   * @}
   */
 
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   SMARTCARD State and Errors functions 
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   SMARTCARD State and Errors functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                 ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides a set of functions allowing to control the SmartCard.
      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
-     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication. 
+     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
 @endverbatim
   * @{
   */
 
 /**
-  * @brief return the SMARTCARD state
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Return the SMARTCARD handle state
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval HAL state
   */
 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
 {
-  return hsc->State;
+  uint32_t temp1= 0x00U, temp2 = 0x00U;
+  temp1 = hsc->gState;
+  temp2 = hsc->RxState;
+
+  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
 }
 
 /**
   * @brief  Return the SMARTCARD error code
-  * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param  hsc  Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *              the configuration information for the specified SMARTCARD.
   * @retval SMARTCARD Error Code
   */
@@ -962,131 +1803,152 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
   */
 
 /**
-  * @brief DMA SMARTCARD transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+  * @{
+  */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  hsc SMARTCARD handle.
+  * @retval none
+  */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* Init the SMARTCARD Callback settings */
+  hsc->TxCpltCallback            = HAL_SMARTCARD_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  hsc->RxCpltCallback            = HAL_SMARTCARD_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  hsc->ErrorCallback             = HAL_SMARTCARD_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  hsc->AbortCpltCallback         = HAL_SMARTCARD_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  hsc->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  hsc->AbortReceiveCpltCallback  = HAL_SMARTCARD_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+  * @brief DMA SMARTCARD transmit process complete callback
+  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  hsc->TxXferCount = 0;
-  
+
+  hsc->TxXferCount = 0U;
+
   /* Disable the DMA transfer for transmit request by setting the DMAT bit
-  in the USART CR3 register */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+     in the USART CR3 register */
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
 
-  /* Enable the SMARTCARD Transmit Complete Interrupt */    
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+  /* Enable the SMARTCARD Transmit Complete Interrupt */
+  SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
 }
 
 /**
-  * @brief DMA SMARTCARD receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief DMA SMARTCARD receive process complete callback
+  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
-  hsc->RxXferCount = 0;
-  
-  /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-  in the USART CR3 register */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
-  
-  /* Check if a non-blocking transmit process is ongoing or not */
-  if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-  {
-    hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-  }
-  else
-  {
-    hsc->State = HAL_SMARTCARD_STATE_READY;
-  }
-  
+  hsc->RxXferCount = 0U;
+
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+     in the USART CR3 register */
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+  /* At end of Rx process, restore hsc->RxState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx complete callback */
+  hsc->RxCpltCallback(hsc);
+#else
+  /* Call legacy weak Rx complete callback */
   HAL_SMARTCARD_RxCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
 }
 
 /**
-  * @brief DMA SMARTCARD communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @brief DMA SMARTCARD communication error callback
+  * @param  hdma   Pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)   
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
 {
+  uint32_t dmarequest = 0x00U;
   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->RxXferCount = 0;
-  hsc->TxXferCount = 0;
+  hsc->RxXferCount = 0U;
+  hsc->TxXferCount = 0U;
   hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-  hsc->State= HAL_SMARTCARD_STATE_READY;
 
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
+  if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
+  {
+    SMARTCARD_EndTxTransfer(hsc);
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+  if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
+  {
+    SMARTCARD_EndRxTransfer(hsc);
+  }
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hsc->ErrorCallback(hsc);
+#else
+  /* Call legacy weak user error callback */
   HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
 }
 
 /**
   * @brief  This function handles SMARTCARD Communication Timeout.
-  * @param  hsc: SMARTCARD handle
-  * @param  Flag: specifies the SMARTCARD flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @param  Flag   Specifies the SMARTCARD flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
-  {    
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-          
-          hsc->State= HAL_SMARTCARD_STATE_READY;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
+  while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-          
-          hsc->State= HAL_SMARTCARD_STATE_READY;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-          
-          return HAL_TIMEOUT;
-        }
+        /* Disable TXE and RXNE interrupts for the interrupt process */
+        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+        CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+
+        hsc->gState= HAL_SMARTCARD_STATE_READY;
+        hsc->RxState= HAL_SMARTCARD_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsc);
+
+        return HAL_TIMEOUT;
       }
     }
   }
@@ -1094,32 +1956,63 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe
 }
 
 /**
-  * @brief Send an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* At end of Tx process, restore hsc->gState to Ready */
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+  /* At end of Rx process, restore hsc->RxState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief Send an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
 {
   uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+
+  /* Check that a Tx process is ongoing */
+  if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
   {
     tmp = (uint16_t*) hsc->pTxBuffPtr;
     hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-    hsc->pTxBuffPtr += 1;    
-    
-    if(--hsc->TxXferCount == 0)
+    hsc->pTxBuffPtr += 1U;
+
+    if(--hsc->TxXferCount == 0U)
     {
       /* Disable the SMARTCARD Transmit data register empty Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-      
-      /* Enable the SMARTCARD Transmit Complete Interrupt */    
-      __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the SMARTCARD Transmit Complete Interrupt */
+      SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
     }
-    
+
     return HAL_OK;
   }
   else
@@ -1130,99 +2023,256 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
 
 /**
   * @brief  Wraps up transmission in non blocking mode.
-  * @param  hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for the specified SMARTCARD module.
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
 {
-  /* Disable the SMARTCARD Transmit Complete Interrupt */    
-  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-  {
-    hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-    
-    hsmartcard->State = HAL_SMARTCARD_STATE_READY;
-  }
-  
-  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-  
+  /* Disable the SMARTCARD Transmit Complete Interrupt */
+  CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
+
+  /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+  /* Tx process is ended, restore hsc->gState to Ready */
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx complete callback */
+  hsc->TxCpltCallback(hsc);
+#else
+  /* Call legacy weak Tx complete callback */
+  HAL_SMARTCARD_TxCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+
   return HAL_OK;
 }
 
 /**
-  * @brief Receive an amount of data in non blocking mode 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief Receive an amount of data in non blocking mode
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
 {
   uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+
+  /* Check that a Rx process is ongoing */
+  if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
   {
     tmp = (uint16_t*) hsc->pRxBuffPtr;
-    *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
-    hsc->pRxBuffPtr += 1;
-    
-    if(--hsc->RxXferCount == 0)
+    *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+    hsc->pRxBuffPtr += 1U;
+
+    if(--hsc->RxXferCount == 0U)
     {
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-      
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+
       /* Disable the SMARTCARD Parity Error Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
-      
+      CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
       /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
-      
-      /* Check if a non-blocking transmit process is ongoing or not */
-      if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-      {
-        hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-      }
-      else
-      {
-        hsc->State = HAL_SMARTCARD_STATE_READY;
-      }
-      
+      CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore hsc->RxState to Ready */
+      hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx complete callback */
+      hsc->RxCpltCallback(hsc);
+#else
+      /* Call legacy weak Rx complete callback */
       HAL_SMARTCARD_RxCpltCallback(hsc);
-      
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+
       return HAL_OK;
     }
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  hsc->RxXferCount = 0x00U;
+  hsc->TxXferCount = 0x00U;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered user error callback */
+  hsc->ErrorCallback(hsc);
+#else
+  /* Call legacy weak user error callback */
+  HAL_SMARTCARD_ErrorCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsc->hdmarx != NULL)
+  {
+    if(hsc->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsc->TxXferCount = 0x00U;
+  hsc->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Restore hsc->gState and hsc->RxState to Ready */
+  hsc->gState  = HAL_SMARTCARD_STATE_READY;
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hsc->AbortCpltCallback(hsc);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsc->hdmatx != NULL)
+  {
+    if(hsc->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
   }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsc->TxXferCount = 0x00U;
+  hsc->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Restore hsc->gState and hsc->RxState to Ready */
+  hsc->gState  = HAL_SMARTCARD_STATE_READY;
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  hsc->AbortCpltCallback(hsc);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->TxXferCount = 0x00U;
+
+  /* Restore hsc->gState to Ready */
+  hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  hsc->AbortTransmitCpltCallback(hsc);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
 }
 
 /**
-  * @brief Configure the SMARTCARD peripheral 
-  * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  hsc->RxXferCount = 0x00U;
+
+  /* Restore hsc->RxState to Ready */
+  hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  hsc->AbortReceiveCpltCallback(hsc);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
+}
+
+/**
+  * @brief Configure the SMARTCARD peripheral
+  * @param  hsc    Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                the configuration information for SMARTCARD module.
   * @retval None
   */
 static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
 {
-  uint32_t tmpreg = 0x00;
-  
+  uint32_t tmpreg = 0x00U;
+  uint32_t pclk;
+
   /* Check the parameters */
   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
   assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
   assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
   assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
-  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));  
+  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
   assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
   assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
   assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
@@ -1231,8 +2281,8 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
 
   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  hsc->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
+  CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
   /*---------------------------- USART CR2 Configuration ---------------------*/
   tmpreg = hsc->Instance->CR2;
   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
@@ -1242,11 +2292,11 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
   /* Set CPHA bit according to hsc->Init.CLKPhase value */
   /* Set LBCL bit according to hsc->Init.CLKLastBit value */
   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
-  tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | 
+  tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
                       hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
   /* Write to USART CR2 */
-  hsc->Instance->CR2 = (uint32_t)tmpreg;
-  
+  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
+
   tmpreg = hsc->Instance->CR2;
 
   /* Clear STOP[13:12] bits */
@@ -1254,9 +2304,9 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
 
   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
   tmpreg |= (uint32_t)(hsc->Init.StopBits);
-  
+
   /* Write to USART CR2 */
-  hsc->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = hsc->Instance->CR1;
@@ -1265,27 +2315,29 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
                                    USART_CR1_RE));
 
-  /* Configure the SMARTCARD Word Length, Parity and mode: 
-     Set the M bits according to hsc->Init.WordLength value 
+  /* Configure the SMARTCARD Word Length, Parity and mode:
+     Set the M bits according to hsc->Init.WordLength value
      Set PCE and PS bits according to hsc->Init.Parity value
      Set TE and RE bits according to hsc->Init.Mode value */
   tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
 
   /* Write to USART CR1 */
-  hsc->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
 
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Clear CTSE and RTSE bits */
-  hsc->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
 
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((hsc->Instance == USART1) || (hsc->Instance == USART6))
   {
-    hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK2Freq();
+    hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
   }
   else
   {
-    hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK1Freq();
+    hsc->Instance->BRR = SMARTCARD_BRR(pclk, hsc->Init.BaudRate);
   }
 }
 
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_spi.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_spi.c
index e3093013..62effefd 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_spi.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_spi.c
@@ -2,16 +2,14 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   SPI HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
+  *
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -20,25 +18,25 @@
       The SPI HAL driver can be used as follows:
 
       (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi; 
+          SPI_HandleTypeDef  hspi;
 
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
-          (##) Enable the SPIx interface clock 
+      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+          (##) Enable the SPIx interface clock
           (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs 
+              (+++) Enable the clock for the SPI GPIOs
               (+++) Configure these SPI pins as alternate function push-pull
           (##) NVIC configuration if you need to use interrupt process
               (+++) Configure the SPIx interrupt priority
               (+++) Enable the NVIC SPI IRQ handle
           (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
-              (+++) Enable the DMAx interface clock using 
-              (+++) Configure the DMA handle parameters 
-              (+++) Configure the DMA Tx or Rx Stream
-              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
-
-      (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS 
+              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+              (+++) Enable the DMAx clock
+              (+++) Configure the DMA handle parameters
+              (+++) Configure the DMA Tx or Rx Stream/Channel
+              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+
+      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
 
       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
@@ -50,38 +48,152 @@
           (##) Master 2Lines RxOnly
           (##) Master 1Line Rx
       (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs 
+      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+     [..]
+       Master Receive mode restriction:
+      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
+          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+          does not initiate a new transfer the following procedure has to be respected:
+          (##) HAL_SPI_DeInit()
+          (##) HAL_SPI_Init()
+     [..]
+       Callback registration:
+
+      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+          allows the user to configure dynamically the driver callbacks.
+          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+            (++) TxCpltCallback        : SPI Tx Completed callback
+            (++) RxCpltCallback        : SPI Rx Completed callback
+            (++) TxRxCpltCallback      : SPI TxRx Completed callback
+            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
+            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
+            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
+            (++) ErrorCallback         : SPI Error callback
+            (++) AbortCpltCallback     : SPI Abort callback
+            (++) MspInitCallback       : SPI Msp Init callback
+            (++) MspDeInitCallback     : SPI Msp DeInit callback
+          This function takes as parameters the HAL peripheral handle, the Callback ID
+          and a pointer to the user callback function.
+
+
+      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+          weak function.
+          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+          and the Callback ID.
+          This function allows to reset following callbacks:
+            (++) TxCpltCallback        : SPI Tx Completed callback
+            (++) RxCpltCallback        : SPI Rx Completed callback
+            (++) TxRxCpltCallback      : SPI TxRx Completed callback
+            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
+            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
+            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
+            (++) ErrorCallback         : SPI Error callback
+            (++) AbortCpltCallback     : SPI Abort callback
+            (++) MspInitCallback       : SPI Msp Init callback
+            (++) MspDeInitCallback     : SPI Msp DeInit callback
+
+       [..]
+       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+       all callbacks are set to the corresponding weak functions:
+       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+       Exception done for MspInit and MspDeInit functions that are
+       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+       these callbacks are null (not registered beforehand).
+       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+       [..]
+       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+       Exception done MspInit/MspDeInit functions that can be registered/unregistered
+       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+       Then, the user first registers the MspInit/MspDeInit user callbacks
+       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+       or HAL_SPI_Init() function.
+
+       [..]
+       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+       not defined, the callback registering feature is not available
+       and weak (surcharged) callbacks are used.
 
+     [..]
+       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
+       the following table resume the max SPI frequency reached with data size 8bits/16bits,
+         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
 
-            
   @endverbatim
+
+  Additional table :
+
+       DataSize = SPI_DATASIZE_8BIT:
+       +----------------------------------------------------------------------------------------------+
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
+       |==============================================================================================|
+       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
+       +----------------------------------------------------------------------------------------------+
+
+       DataSize = SPI_DATASIZE_16BIT:
+       +----------------------------------------------------------------------------------------------+
+       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
+       | Process | Tranfert mode  |---------------------|----------------------|----------------------|
+       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
+       |==============================================================================================|
+       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
+       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
+       |=========|================|==========|==========|===========|==========|===========|==========|
+       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
+       |         |----------------|----------|----------|-----------|----------|-----------|----------|
+       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
+       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
+       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
+       +----------------------------------------------------------------------------------------------+
+       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
+             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+       @note
+            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -93,28 +205,28 @@
   * @{
   */
 
-/** @defgroup SPI SPI 
+/** @defgroup SPI SPI
   * @brief SPI HAL module driver
   * @{
   */
-
 #ifdef HAL_SPI_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define SPI_TIMEOUT_VALUE  10
-/* Private macro -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+  * @{
+  */
+#define SPI_DEFAULT_TIMEOUT 100U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
+/** @defgroup SPI_Private_Functions SPI Private Functions
   * @{
   */
-static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
-static void SPI_TxISR(SPI_HandleTypeDef *hspi);
-static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
-static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
-static void SPI_RxISR(SPI_HandleTypeDef *hspi);
-static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi); 
 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -122,33 +234,58 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+                                                       uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 /**
   * @}
   */
-  
+
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup SPI_Exported_Functions SPI Exported Functions
   * @{
   */
 
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
 @verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
+    [..]  This subsection provides a set of functions allowing to initialize and
           de-initialize the SPIx peripheral:
 
-      (+) User must implement HAL_SPI_MspInit() function in which he configures 
+      (+) User must implement HAL_SPI_MspInit() function in which he configures
           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 
-      (+) Call the function HAL_SPI_Init() to configure the selected device with 
+      (+) Call the function HAL_SPI_Init() to configure the selected device with
           the selected configuration:
         (++) Mode
-        (++) Direction 
+        (++) Direction
         (++) Data Size
         (++) Clock Polarity and Phase
         (++) NSS Management
@@ -158,49 +295,81 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
         (++) CRC Calculation
         (++) CRC Polynomial if CRC enabled
 
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration 
-          of the selected SPIx peripheral.       
+      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+          of the selected SPIx peripheral.
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the SPI according to the specified parameters 
-  *         in the SPI_InitTypeDef and create the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Initialize the SPI according to the specified parameters
+  *         in the SPI_InitTypeDef and initialize the associated handle.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
 {
   /* Check the SPI handle allocation */
-  if(hspi == NULL)
+  if (hspi == NULL)
   {
     return HAL_ERROR;
   }
 
   /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
   assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
   assert_param(IS_SPI_NSS(hspi->Init.NSS));
   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
   assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+  {
+    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+  }
+#if (USE_SPI_CRC != 0U)
   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+  }
+#else
+  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
 
-  if(hspi->State == HAL_SPI_STATE_RESET)
+  if (hspi->State == HAL_SPI_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    /* Init the SPI Callback settings */
+    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
+    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
+    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
+    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
+    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
+    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
+    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+
+    if (hspi->MspInitCallback == NULL)
+    {
+      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+    hspi->MspInitCallback(hspi);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
     HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
   }
-  
+
   hspi->State = HAL_SPI_STATE_BUSY;
 
   /* Disable the selected SPI peripheral */
@@ -209,45 +378,67 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
   /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
   Communication speed, First bit and CRC calculation state */
-  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
-                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
-                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
+  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
+                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation));
 
-  /* Configure : NSS management */
-  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
+  /* Configure : NSS management, TI Mode */
+  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
 
+#if (USE_SPI_CRC != 0U)
   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
   /* Configure : CRC Polynomial */
-  hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+  }
+#endif /* USE_SPI_CRC */
 
+#if defined(SPI_I2SCFGR_I2SMOD)
   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
+  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
 
   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_READY;
-  
+  hspi->State     = HAL_SPI_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the SPI peripheral 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  De-Initialize the SPI peripheral.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
 {
   /* Check the SPI handle allocation */
-  if(hspi == NULL)
+  if (hspi == NULL)
   {
     return HAL_ERROR;
   }
 
+  /* Check SPI Instance parameter */
+  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+  hspi->State = HAL_SPI_STATE_BUSY;
+
   /* Disable the SPI Peripheral Clock */
   __HAL_SPI_DISABLE(hspi);
 
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  if (hspi->MspDeInitCallback == NULL)
+  {
+    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+  hspi->MspDeInitCallback(hspi);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
   HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 
   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   hspi->State = HAL_SPI_STATE_RESET;
@@ -259,42 +450,265 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
 }
 
 /**
-  * @brief SPI MSP Init
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Initialize the SPI MSP.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
- __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
- {
-   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit could be implemented in the user file
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspInit should be implemented in the user file
    */
 }
 
 /**
-  * @brief SPI MSP DeInit
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  De-Initialize the SPI MSP.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
- __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_MspDeInit should be implemented in the user file
    */
 }
 
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+  * @brief  Register a User SPI Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for the specified SPI.
+  * @param  CallbackID ID of the callback to be registered
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+                                           pSPI_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  if (HAL_SPI_STATE_READY == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_TX_COMPLETE_CB_ID :
+        hspi->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_RX_COMPLETE_CB_ID :
+        hspi->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+        hspi->TxRxCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+        hspi->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+        hspi->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+        hspi->TxRxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_ERROR_CB_ID :
+        hspi->ErrorCallback = pCallback;
+        break;
+
+      case HAL_SPI_ABORT_CB_ID :
+        hspi->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPI_STATE_RESET == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = pCallback;
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspi);
+  return status;
+}
+
+/**
+  * @brief  Unregister an SPI Callback
+  *         SPI callback is redirected to the weak predefined callback
+  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
+  *                the configuration information for the specified SPI.
+  * @param  CallbackID ID of the callback to be unregistered
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  if (HAL_SPI_STATE_READY == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_TX_COMPLETE_CB_ID :
+        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
+        break;
+
+      case HAL_SPI_RX_COMPLETE_CB_ID :
+        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
+        break;
+
+      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
+        break;
+
+      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
+        break;
+
+      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
+        break;
+
+      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+        break;
+
+      case HAL_SPI_ERROR_CB_ID :
+        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        break;
+
+      case HAL_SPI_ABORT_CB_ID :
+        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        break;
+
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_SPI_STATE_RESET == hspi->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_SPI_MSPINIT_CB_ID :
+        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_SPI_MSPDEINIT_CB_ID :
+        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hspi);
+  return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
+  *  @brief   Data transfers functions
+  *
 @verbatim
   ==============================================================================
                       ##### IO operation functions #####
  ===============================================================================
+ [..]
     This subsection provides a set of functions allowing to manage the SPI
     data transfers.
 
@@ -305,13 +719,13 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
-           or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the 
-           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when 
-           using DMA mode.
-           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks 
-           will be executed respectively at the end of the transmit or Receive process
-           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+            or DMA, These APIs return the HAL status.
+            The end of the data processing will be indicated through the
+            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+            using DMA mode.
+            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+            will be executed respectively at the end of the transmit or Receive process
+            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
 
     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
         exist for 1Line (simplex) and 2Lines (full duplex) modes.
@@ -321,1328 +735,1829 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
   */
 
 /**
-  * @brief  Transmit an amount of data in blocking mode
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @brief  Transmit an amount of data in blocking mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
+  uint32_t tickstart;
+  HAL_StatusTypeDef errorcode = HAL_OK;
+  uint16_t initial_TxXferCount;
 
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+  initial_TxXferCount = Size;
 
-    /* Configure communication */
-    hspi->State = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    hspi->pTxBuffPtr = pData;
-    hspi->TxXferSize = Size;
-    hspi->TxXferCount = Size;
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->RxISR = 0;
-    hspi->RxXferSize   = 0;
-    hspi->RxXferCount  = 0;
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      /* Configure communication direction : 1Line */
-      SPI_1LINE_TX(hspi);
-    }
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  /* Transmit data in 16 Bit mode */
+  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
     {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
+      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint16_t);
+      hspi->TxXferCount--;
     }
-
-    /* Transmit data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+    /* Transmit data in 16 Bit mode */
+    while (hspi->TxXferCount > 0U)
     {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+      /* Wait until TXE flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
       {
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint16_t);
         hspi->TxXferCount--;
       }
-      while(hspi->TxXferCount > 0)
+      else
       {
-        /* Wait until TXE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
         }
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-        hspi->TxXferCount--;
-      }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 
-      {
-        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
       }
     }
-    /* Transmit data in 16 Bit mode */
-    else
+  }
+  /* Transmit data in 8 Bit mode */
+  else
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+    {
+      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint8_t);
+      hspi->TxXferCount--;
+    }
+    while (hspi->TxXferCount > 0U)
     {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+      /* Wait until TXE flag is set to send data */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
       {
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
+        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint8_t);
         hspi->TxXferCount--;
       }
-      while(hspi->TxXferCount > 0)
+      else
       {
-        /* Wait until TXE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
         }
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
-        hspi->TxXferCount--;
       }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 
-      {
-        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-      }
-    }
-
-    /* Wait until TXE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-      return HAL_TIMEOUT;
-    }
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
-    { 
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-      return HAL_TIMEOUT;
     }
- 
-    /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->State = HAL_SPI_STATE_READY; 
+  }
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
 
-    return HAL_OK;
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
   }
-  else
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
-    return HAL_BUSY;
+    errorcode = HAL_ERROR;
   }
+
+error:
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Receive an amount of data in blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be received
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  __IO uint16_t tmpreg;
-  uint32_t tmp = 0;
+  uint32_t tickstart;
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-  if(hspi->State == HAL_SPI_STATE_READY)
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
   {
-    if((pData == NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+  }
 
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-    hspi->pRxBuffPtr  = pData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-    hspi->TxXferSize   = 0;
-    hspi->TxXferCount  = 0;
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_RX(hspi);
-    }
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-    
-    if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+    /* this is done to handle the CRCNEXT before the latest data */
+    hspi->RxXferCount--;
+  }
+#endif /* USE_SPI_CRC */
 
-      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-      return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-    }
+  /* Configure communication direction: 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
 
-    /* Receive data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  /* Receive data in 8 Bit mode */
+  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0U)
     {
-      while(hspi->RxXferCount > 1)
+      /* Check the RXNE flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
       {
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+        /* read the received data */
+        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+        hspi->pRxBuffPtr += sizeof(uint8_t);
         hspi->RxXferCount--;
       }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 
+      else
       {
-        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
       }
     }
-    /* Receive data in 16 Bit mode */
-    else
+  }
+  else
+  {
+    /* Transfer loop */
+    while (hspi->RxXferCount > 0U)
     {
-      while(hspi->RxXferCount > 1)
+      /* Check the RXNE flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
       {
-        /* Wait until RXNE flag is set to read data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr+=2;
+        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+        hspi->pRxBuffPtr += sizeof(uint16_t);
         hspi->RxXferCount--;
       }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 
+      else
       {
-        hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+        /* Timeout management */
+        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+        {
+          errorcode = HAL_TIMEOUT;
+          goto error;
+        }
       }
     }
+  }
 
-    /* Wait until RXNE flag is set */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
+#if (USE_SPI_CRC != 0U)
+  /* Handle the CRC Transmission */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* freeze the CRC before the latest data */
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 
-    /* Receive last data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+    /* Read the latest data */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
     {
-      (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+      /* the latest data has not been received */
+      errorcode = HAL_TIMEOUT;
+      goto error;
     }
+
     /* Receive last data in 16 Bit mode */
-    else
+    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
     {
-      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-      hspi->pRxBuffPtr+=2;
+      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
     }
-    hspi->RxXferCount--;
-
-    /* Wait until RXNE flag is set: CRC Received */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    /* Receive last data in 8 Bit mode */
+    else
     {
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-        return HAL_TIMEOUT;
-      }
-
-      /* Read CRC to Flush RXNE flag */
-      tmpreg = hspi->Instance->DR;
-      UNUSED(tmpreg);
+      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
     }
-    
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+
+    /* Wait the CRC data */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
     {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      errorcode = HAL_TIMEOUT;
+      goto error;
     }
 
-    hspi->State = HAL_SPI_STATE_READY;
-
-    tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
-    /* Check if CRC error occurred */
-    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
-    {  
-      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
+    /* Read CRC to Flush DR and RXNE flag */
+    READ_REG(hspi->Instance->DR);
+  }
+#endif /* USE_SPI_CRC */
 
-      /* Reset CRC Calculation */
-      SPI_RESET_CRC(hspi);
+  /* Check the end of the transaction */
+  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+  }
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
-
-      return HAL_ERROR; 
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    return HAL_OK;
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
   }
-  else
+#endif /* USE_SPI_CRC */
+
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
-    return HAL_BUSY;
+    errorcode = HAL_ERROR;
   }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Transmit and Receive an amount of data in blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer to be
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
+  * @brief  Transmit and Receive an amount of data in blocking mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
+  * @param  Size amount of data to be sent and received
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+                                          uint32_t Timeout)
 {
-  __IO uint16_t tmpreg;
-  uint32_t tmpstate = 0, tmp = 0;
-  
-  tmpstate = hspi->State; 
-  if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
+  uint16_t             initial_TxXferCount;
+  uint32_t             tmp_mode;
+  HAL_SPI_StateTypeDef tmp_state;
+  uint32_t             tickstart;
+
+  /* Variable used to alternate Rx and Tx during transfer */
+  uint32_t             txallowed = 1U;
+  HAL_StatusTypeDef    errorcode = HAL_OK;
+
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process Locked */
+  __HAL_LOCK(hspi);
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* Init temporary variables */
+  tmp_state           = hspi->State;
+  tmp_mode            = hspi->Init.Mode;
+  initial_TxXferCount = Size;
+
+  if (!((tmp_state == HAL_SPI_STATE_READY) || \
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
   {
-    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Process Locked */
-    __HAL_LOCK(hspi);
- 
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State == HAL_SPI_STATE_READY)
-    {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-    }
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
 
-     /* Configure communication */   
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferCount = Size;
+  hspi->RxXferSize  = Size;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferCount = Size;
+  hspi->TxXferSize  = Size;
 
-    hspi->pRxBuffPtr  = pRxData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;  
-    
-    hspi->pTxBuffPtr  = pTxData;
-    hspi->TxXferSize  = Size; 
-    hspi->TxXferCount = Size;
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
 
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+  /* Transmit and Receive data in 16 Bit mode */
+  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
     {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
+      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint16_t);
+      hspi->TxXferCount--;
     }
-
-    /* Transmit and Receive data in 16 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
     {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+      /* Check TXE flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
       {
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
+        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint16_t);
         hspi->TxXferCount--;
-      }
-      if(hspi->TxXferCount == 0)
-      {
+        /* Next Data is a reception (Rx). Tx not allowed */
+        txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
         /* Enable CRC Transmission */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
         {
-          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-        }
-
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
         }
+#endif /* USE_SPI_CRC */
+      }
 
-        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr+=2;
+      /* Check RXNE flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
+      {
+        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+        hspi->pRxBuffPtr += sizeof(uint16_t);
         hspi->RxXferCount--;
+        /* Next Data is a Transmission (Tx). Tx is allowed */
+        txallowed = 1U;
       }
-      else
+      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
       {
-        while(hspi->TxXferCount > 0)
-        {
-          /* Wait until TXE flag is set to send data */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-          { 
-            return HAL_TIMEOUT;
-          }
-
-          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr+=2;
-          hspi->TxXferCount--;
-
-          /* Enable CRC Transmission */
-          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-          {
-            hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-          }
-
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          { 
-            return HAL_TIMEOUT;
-          }
-          
-          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-          hspi->pRxBuffPtr+=2;
-          hspi->RxXferCount--;
-        }
-        /* Receive the last byte */
-        if(hspi->Init.Mode == SPI_MODE_SLAVE)
-        {
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-          
-          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-          hspi->pRxBuffPtr+=2;
-          hspi->RxXferCount--;
-        }
+        errorcode = HAL_TIMEOUT;
+        goto error;
       }
     }
-    /* Transmit and Receive data in 8 Bit mode */
-    else
+  }
+  /* Transmit and Receive data in 8 Bit mode */
+  else
+  {
+    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
+    {
+      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint8_t);
+      hspi->TxXferCount--;
+    }
+    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
     {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+      /* Check TXE flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
       {
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr++;
         hspi->TxXferCount--;
-      }
-      if(hspi->TxXferCount == 0)
-      {
-        /* Enable CRC Transmission */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-        {
-          hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-        }
+        /* Next Data is a reception (Rx). Tx not allowed */
+        txallowed = 0U;
 
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+#if (USE_SPI_CRC != 0U)
+        /* Enable CRC Transmission */
+        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
         {
-          return HAL_TIMEOUT;
+          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
         }
-
-        (*hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->RxXferCount--;
+#endif /* USE_SPI_CRC */
       }
-      else
-      {
-        while(hspi->TxXferCount > 0)
-        {
-          /* Wait until TXE flag is set to send data */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-          hspi->TxXferCount--;
-
-          /* Enable CRC Transmission */
-          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
-          {
-            hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
-          }
 
-            /* Wait until RXNE flag is set */
-            if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-            {
-              return HAL_TIMEOUT;
-            }
-            
-            (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-            hspi->RxXferCount--;
-        }
-        if(hspi->Init.Mode == SPI_MODE_SLAVE)
-        {
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-          
-          (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-          hspi->RxXferCount--;
-        }
+      /* Wait until RXNE flag is reset */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
+      {
+        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+        hspi->pRxBuffPtr++;
+        hspi->RxXferCount--;
+        /* Next Data is a Transmission (Tx). Tx is allowed */
+        txallowed = 1U;
       }
-    }
-
-    /* Read CRC from DR to close CRC calculation process */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      /* Wait until RXNE flag is set */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
       {
-        hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-        return HAL_TIMEOUT;
+        errorcode = HAL_TIMEOUT;
+        goto error;
       }
-      /* Read CRC */
-      tmpreg = hspi->Instance->DR;
-      UNUSED(tmpreg);
     }
+  }
 
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
+#if (USE_SPI_CRC != 0U)
+  /* Read CRC from DR to close CRC calculation process */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    /* Wait until TXE flag */
+    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-      return HAL_TIMEOUT;
+      /* Error on the CRC reception */
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      errorcode = HAL_TIMEOUT;
+      goto error;
     }
-    
-    hspi->State = HAL_SPI_STATE_READY;
-
-    tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
-    /* Check if CRC error occurred */
-    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
-    {
-      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-
-      /* Reset CRC Calculation */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-      {
-        SPI_RESET_CRC(hspi);
-      }
+    /* Read CRC */
+    READ_REG(hspi->Instance->DR);
+  }
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
-      
-      return HAL_ERROR; 
-    }
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    /* Clear CRC Flag */
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+    errorcode = HAL_ERROR;
+  }
+#endif /* USE_SPI_CRC */
 
-    return HAL_OK;
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
+  {
+    errorcode = HAL_ERROR;
+    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+    goto error;
   }
-  else
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
   {
-    return HAL_BUSY;
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
   }
+
+error :
+  hspi->State = HAL_SPI_STATE_READY;
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Transmit an amount of data in no-blocking mode with Interrupt
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-    /* Configure communication */
-    hspi->State        = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    hspi->TxISR = &SPI_TxISR;
-    hspi->pTxBuffPtr   = pData;
-    hspi->TxXferSize   = Size;
-    hspi->TxXferCount  = Size;
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->RxXferSize   = 0;
-    hspi->RxXferCount  = 0;
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+  hspi->RxISR       = NULL;
+
+  /* Set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->TxISR = SPI_TxISR_16BIT;
+  }
+  else
+  {
+    hspi->TxISR = SPI_TxISR_8BIT;
+  }
 
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_TX(hspi);
-    }
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
-    }else
-    {
-      /* Enable TXE and ERR interrupt */
-      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
 
-    return HAL_OK;
-  }
-  else
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
-    return HAL_BUSY;
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
   }
+
+error :
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Receive an amount of data in no-blocking mode with Interrupt
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-    /* Configure communication */
-    hspi->State        = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
-
-    hspi->RxISR = &SPI_RxISR;
-    hspi->pRxBuffPtr   = pData;
-    hspi->RxXferSize   = Size;
-    hspi->RxXferCount  = Size ; 
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+  }
 
-   /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->TxXferSize   = 0;
-    hspi->TxXferCount  = 0;
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-       SPI_1LINE_RX(hspi);
-    }
-    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-       /* Process Unlocked */
-       __HAL_UNLOCK(hspi);
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-       return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-    }
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pTxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+  hspi->TxISR       = NULL;
+
+  /* Set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->RxISR = SPI_RxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR = SPI_RxISR_8BIT;
+  }
 
-    /* Enable TXE and ERR interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Note : The SPI must be enabled after unlocking current process 
-              to avoid the risk of SPI interrupt handle execution before current
-              process unlock */
+  /* Enable TXE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 
-        /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
+  /* Note : The SPI must be enabled after unlocking current process
+            to avoid the risk of SPI interrupt handle execution before current
+            process unlock */
 
-    return HAL_OK;
-  }
-  else
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
-    return HAL_BUSY; 
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
   }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Transmit and Receive an amount of data in no-blocking mode with Interrupt 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer to be
-  * @param  Size: amount of data to be sent
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
+  * @param  Size amount of data to be sent and received
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 {
- uint32_t tmpstate = 0;
-
- tmpstate = hspi->State;
-  if((tmpstate == HAL_SPI_STATE_READY) || \
-     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
-  {
-    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
+  uint32_t             tmp_mode;
+  HAL_SPI_StateTypeDef tmp_state;
+  HAL_StatusTypeDef    errorcode = HAL_OK;
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
-    /* Process locked */
-    __HAL_LOCK(hspi);
-
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State != HAL_SPI_STATE_BUSY_RX)
-    {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-    }
+  /* Process locked */
+  __HAL_LOCK(hspi);
 
-    /* Configure communication */
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
+  /* Init temporary variables */
+  tmp_state           = hspi->State;
+  tmp_mode            = hspi->Init.Mode;
 
-    hspi->TxISR = &SPI_TxISR;
-    hspi->pTxBuffPtr   = pTxData;
-    hspi->TxXferSize   = Size;
-    hspi->TxXferCount  = Size;
+  if (!((tmp_state == HAL_SPI_STATE_READY) || \
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    hspi->RxISR = &SPI_2LinesRxISR;
-    hspi->pRxBuffPtr   = pRxData;
-    hspi->RxXferSize   = Size;
-    hspi->RxXferCount  = Size;
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
 
-    /* Enable TXE, RXNE and ERR interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Set the function for IT treatment */
+  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+  {
+    hspi->RxISR     = SPI_2linesRxISR_16BIT;
+    hspi->TxISR     = SPI_2linesTxISR_16BIT;
+  }
+  else
+  {
+    hspi->RxISR     = SPI_2linesRxISR_8BIT;
+    hspi->TxISR     = SPI_2linesTxISR_8BIT;
+  }
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
+  /* Enable TXE, RXNE and ERR interrupt */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 
-    return HAL_OK;
-  }
-  else
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
-    return HAL_BUSY; 
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
   }
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Transmit an amount of data in no-blocking mode with DMA
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
+  * @brief  Transmit an amount of data in non-blocking mode with DMA.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+  /* Check tx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pTxBuffPtr  = pData;
-    hspi->TxXferSize  = Size;
-    hspi->TxXferCount = Size;
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-    /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->RxISR = 0;
-    hspi->RxXferSize   = 0;
-    hspi->RxXferCount  = 0;
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_TX(hspi);
-    }
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->pRxBuffPtr  = (uint8_t *)NULL;
+  hspi->TxISR       = NULL;
+  hspi->RxISR       = NULL;
+  hspi->RxXferSize  = 0U;
+  hspi->RxXferCount = 0U;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_TX(hspi);
+  }
 
-    /* Set the SPI TxDMA Half transfer complete callback */
-    hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-    
-    /* Set the SPI TxDMA transfer complete callback */
-    hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Set the DMA error callback */
-    hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+  /* Set the SPI TxDMA Half transfer complete callback */
+  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
 
-    /* Enable the Tx DMA Stream */
-    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+  /* Set the SPI TxDMA transfer complete callback */
+  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmatx->XferAbortCallback = NULL;
 
-    /* Enable Tx DMA Request */
-    hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+  /* Enable the Tx DMA Stream/Channel */
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+                                 hspi->TxXferCount))
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    errorcode = HAL_ERROR;
 
-    return HAL_OK;
+    hspi->State = HAL_SPI_STATE_READY;
+    goto error;
   }
-  else
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
-    return HAL_BUSY;
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
   }
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Receive an amount of data in no-blocking mode with DMA 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *         the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @note  When the CRC feature is enabled the pData Length must be Size + 1. 
-  * @param  Size: amount of data to be sent
+  * @brief  Receive an amount of data in non-blocking mode with DMA.
+  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pData pointer to data buffer
+  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
+  * @param  Size amount of data to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-    /* Process Locked */
-    __HAL_LOCK(hspi);
+  /* Check rx dma handle */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
 
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_RX;
 
-    hspi->pRxBuffPtr  = pData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
+    /* Check tx dma handle */
+    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-    hspi->TxXferSize   = 0;
-    hspi->TxXferCount  = 0;
+    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+  }
 
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-       SPI_1LINE_RX(hspi);
-    }
-    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-       /* Process Unlocked */
-       __HAL_UNLOCK(hspi);
+  /* Process Locked */
+  __HAL_LOCK(hspi);
 
-       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-       return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-    }
+  if (hspi->State != HAL_SPI_STATE_READY)
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-    {
-      SPI_RESET_CRC(hspi);
-    }
+  if ((pData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
 
-    /* Set the SPI RxDMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    
-    /* Set the SPI Rx DMA transfer complete callback */
-    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+  /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_RX;
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pRxBuffPtr  = (uint8_t *)pData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /*Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+  hspi->TxXferSize  = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Configure communication direction : 1Line */
+  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+  {
+    SPI_1LINE_RX(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
 
-    /* Set the DMA error callback */
-    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+  /* Set the SPI RxDMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
 
-    /* Enable the Rx DMA Stream */
-    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+  /* Set the SPI Rx DMA transfer complete callback */
+  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the Rx DMA Stream/Channel  */
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+                                 hspi->RxXferCount))
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    errorcode = HAL_ERROR;
+
+    hspi->State = HAL_SPI_STATE_READY;
+    goto error;
+  }
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
+  }
+
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
+}
+
+/**
+  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  pTxData pointer to transmission data buffer
+  * @param  pRxData pointer to reception data buffer
+  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
+  * @param  Size amount of data to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size)
+{
+  uint32_t             tmp_mode;
+  HAL_SPI_StateTypeDef tmp_state;
+  HAL_StatusTypeDef errorcode = HAL_OK;
 
-    /* Enable Rx DMA Request */  
-    hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
+  /* Check rx & tx dma handles */
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 
-    return HAL_OK;
+  /* Check Direction parameter */
+  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+  /* Process locked */
+  __HAL_LOCK(hspi);
+
+  /* Init temporary variables */
+  tmp_state           = hspi->State;
+  tmp_mode            = hspi->Init.Mode;
+
+  if (!((tmp_state == HAL_SPI_STATE_READY) ||
+        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+  {
+    errorcode = HAL_BUSY;
+    goto error;
+  }
+
+  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+  {
+    errorcode = HAL_ERROR;
+    goto error;
+  }
+
+  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+  {
+    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+  }
+
+  /* Set the transaction information */
+  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->TxXferSize  = Size;
+  hspi->TxXferCount = Size;
+  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
+  hspi->RxXferSize  = Size;
+  hspi->RxXferCount = Size;
+
+  /* Init field not used in handle to zero */
+  hspi->RxISR       = NULL;
+  hspi->TxISR       = NULL;
+
+#if (USE_SPI_CRC != 0U)
+  /* Reset CRC Calculation */
+  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  {
+    SPI_RESET_CRC(hspi);
+  }
+#endif /* USE_SPI_CRC */
+
+  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+  {
+    /* Set the SPI Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
   }
   else
   {
-    return HAL_BUSY;
+    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
+  }
+
+  /* Set the DMA error callback */
+  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+  /* Set the DMA AbortCpltCallback */
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the Rx DMA Stream/Channel  */
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+                                 hspi->RxXferCount))
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    errorcode = HAL_ERROR;
+
+    hspi->State = HAL_SPI_STATE_READY;
+    goto error;
+  }
+
+  /* Enable Rx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+  is performed in DMA reception complete callback  */
+  hspi->hdmatx->XferHalfCpltCallback = NULL;
+  hspi->hdmatx->XferCpltCallback     = NULL;
+  hspi->hdmatx->XferErrorCallback    = NULL;
+  hspi->hdmatx->XferAbortCallback    = NULL;
+
+  /* Enable the Tx DMA Stream/Channel  */
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+                                 hspi->TxXferCount))
+  {
+    /* Update SPI error code */
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+    errorcode = HAL_ERROR;
+
+    hspi->State = HAL_SPI_STATE_READY;
+    goto error;
+  }
+
+  /* Check if the SPI is already enabled */
+  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+  {
+    /* Enable SPI peripheral */
+    __HAL_SPI_ENABLE(hspi);
   }
+  /* Enable the SPI Error Interrupt Bit */
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+  /* Enable Tx DMA Request */
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+  /* Process Unlocked */
+  __HAL_UNLOCK(hspi);
+  return errorcode;
 }
 
 /**
-  * @brief  Transmit and Receive an amount of data in no-blocking mode with DMA 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1 
-  * @param  Size: amount of data to be sent
+  * @brief  Abort ongoing transfer (blocking mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SPI Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
 {
-  uint32_t tmpstate = 0;
-  tmpstate = hspi->State;
-  if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \
-     (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
+  HAL_StatusTypeDef errorcode;
+  __IO uint32_t count;
+  __IO uint32_t resetcount;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
+
+  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
   {
-    if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+    hspi->TxISR = SPI_AbortTx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
-      return  HAL_ERROR;
-    }
+      if (count == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+      count--;
+    } while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+  {
+    hspi->RxISR = SPI_AbortRx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+      count--;
+    } while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
+
+  /* Disable the SPI DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+  {
+    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+    if (hspi->hdmatx != NULL)
+    {
+      /* Set the SPI DMA Abort callback :
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+      hspi->hdmatx->XferAbortCallback = NULL;
+
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable Tx DMA Request */
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
 
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-    
-    /* Process locked */
-    __HAL_LOCK(hspi);
+      /* Wait until TXE flag is set */
+      do
+      {
+        if (count == 0U)
+        {
+          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+          break;
+        }
+        count--;
+      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+    }
+  }
 
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+  /* Disable the SPI DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+  {
+    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+    if (hspi->hdmarx != NULL)
     {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+      /* Set the SPI DMA Abort callback :
+      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+      hspi->hdmarx->XferAbortCallback = NULL;
+
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+      {
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+
+      /* Disable peripheral */
+      __HAL_SPI_DISABLE(hspi);
+
+      /* Disable Rx DMA Request */
+      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
     }
+  }
+  /* Reset Tx and Rx transfer counters */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check error during Abort procedure */
+  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+  {
+    /* return HAL_Error in case of error during Abort procedure */
+    errorcode = HAL_ERROR;
+  }
+  else
+  {
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+  }
 
-    /* Configure communication */
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
 
-    hspi->pTxBuffPtr  = (uint8_t*)pTxData;
-    hspi->TxXferSize  = Size;
-    hspi->TxXferCount = Size;
+  /* Restore hspi->state to ready */
+  hspi->State = HAL_SPI_STATE_READY;
 
-    hspi->pRxBuffPtr  = (uint8_t*)pRxData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
+  return errorcode;
+}
 
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
+/**
+  * @brief  Abort ongoing transfer (Interrupt mode).
+  * @param  hspi SPI handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+  *         started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable SPI Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+  HAL_StatusTypeDef errorcode;
+  uint32_t abortcplt ;
+  __IO uint32_t count;
+  __IO uint32_t resetcount;
+
+  /* Initialized local variable  */
+  errorcode = HAL_OK;
+  abortcplt = 1U;
+  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+  count = resetcount;
+
+  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+  {
+    hspi->TxISR = SPI_AbortTx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
+    {
+      if (count == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+      count--;
+    } while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
 
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+  {
+    hspi->RxISR = SPI_AbortRx_ISR;
+    /* Wait HAL_SPI_STATE_ABORT state */
+    do
     {
-      SPI_RESET_CRC(hspi);
-    }
+      if (count == 0U)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+      count--;
+    } while (hspi->State != HAL_SPI_STATE_ABORT);
+    /* Reset Timeout Counter */
+    count = resetcount;
+  }
 
-    /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-    if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (hspi->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
     {
-      /* Set the SPI Rx DMA Half transfer complete callback */
-      hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-      
-      hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
     }
     else
     {
-      /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-      hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-  
-      hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+      hspi->hdmatx->XferAbortCallback = NULL;
     }
-
-    /* Set the DMA error callback */
-    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-    /* Enable the Rx DMA Stream */
-    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-    /* Enable Rx DMA Request */  
-    hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-
-    /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
-    is performed in DMA reception complete callback  */
-    hspi->hdmatx->XferCpltCallback = NULL;
-    
-    if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+  }
+  /* DMA Rx Handle is valid */
+  if (hspi->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
     {
-      /* Set the DMA error callback */
-      hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
     }
     else
     {
-      hspi->hdmatx->XferErrorCallback = NULL;
-    }    
-    
-    /* Enable the Tx DMA Stream */
-    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+      hspi->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the SPI DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+  {
+    /* Abort the SPI DMA Tx Stream/Channel */
+    if (hspi->hdmatx != NULL)
+    {
+      /* Abort DMA Tx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+      {
+        hspi->hdmatx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+  /* Disable the SPI DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+  {
+    /* Abort the SPI DMA Rx Stream/Channel */
+    if (hspi->hdmarx != NULL)
+    {
+      /* Abort DMA Rx Handle linked to SPI Peripheral */
+      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
+      {
+        hspi->hdmarx->XferAbortCallback = NULL;
+        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hspi->RxXferCount = 0U;
+    hspi->TxXferCount = 0U;
 
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+    /* Check error during Abort procedure */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+    {
+      /* return HAL_Error in case of error during Abort procedure */
+      errorcode = HAL_ERROR;
+    }
+    else
     {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
+      /* Reset errorCode */
+      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
     }
 
-    /* Enable Tx DMA Request */  
-    hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
+    /* Clear the Error flags in the SR register */
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+    __HAL_SPI_CLEAR_FREFLAG(hspi);
 
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
+    /* Restore hspi->State to Ready */
+    hspi->State = HAL_SPI_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    hspi->AbortCpltCallback(hspi);
+#else
+    HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
   }
+
+  return errorcode;
 }
 
 /**
-  * @brief Pauses the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI module.
+  * @brief  Pause the DMA Transfer.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
 {
   /* Process Locked */
   __HAL_LOCK(hspi);
-  
+
   /* Disable the SPI DMA Tx & Rx requests */
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
   /* Process Unlocked */
   __HAL_UNLOCK(hspi);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
-  * @brief Resumes the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI module.
+  * @brief  Resume the DMA Transfer.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
 {
   /* Process Locked */
   __HAL_LOCK(hspi);
-  
+
   /* Enable the SPI DMA Tx & Rx requests */
-  hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
-  hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
-  
+  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
   /* Process Unlocked */
   __HAL_UNLOCK(hspi);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief Stops the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI module.
+  * @brief  Stop the DMA Transfer.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
 {
+  HAL_StatusTypeDef errorcode = HAL_OK;
   /* The Lock is not implemented on this API to allow the user application
      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
      */
-  
-  /* Abort the SPI DMA tx Stream */
-  if(hspi->hdmatx != NULL)
+
+  /* Abort the SPI DMA tx Stream/Channel  */
+  if (hspi->hdmatx != NULL)
   {
-    HAL_DMA_Abort(hspi->hdmatx);
+    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
   }
-  /* Abort the SPI DMA rx Stream */
-  if(hspi->hdmarx != NULL)
+  /* Abort the SPI DMA rx Stream/Channel  */
+  if (hspi->hdmarx != NULL)
   {
-    HAL_DMA_Abort(hspi->hdmarx);
+    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+      errorcode = HAL_ERROR;
+    }
   }
-  
+
   /* Disable the SPI DMA Tx & Rx requests */
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
   hspi->State = HAL_SPI_STATE_READY;
-  
-  return HAL_OK;
+  return errorcode;
 }
 
 /**
-  * @brief  This function handles SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL status
+  * @brief  Handle SPI interrupt request.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval None
   */
 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
 {
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+  uint32_t itsource = hspi->Instance->CR2;
+  uint32_t itflag   = hspi->Instance->SR;
 
-  tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
-  tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
-  tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
-  /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
+  /* SPI in mode Receiver ----------------------------------------------------*/
+  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
   {
     hspi->RxISR(hspi);
     return;
-  } 
+  }
 
-  tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
-  tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
-  /* SPI in mode Transmitter ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* SPI in mode Transmitter -------------------------------------------------*/
+  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
   {
     hspi->TxISR(hspi);
     return;
   }
 
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
+  /* SPI in Error Treatment --------------------------------------------------*/
+  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
+       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
   {
-    /* SPI CRC error interrupt occurred ---------------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    /* SPI Overrun error interrupt occurred ----------------------------------*/
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
+      }
+      else
+      {
+        __HAL_SPI_CLEAR_OVRFLAG(hspi);
+        return;
+      }
     }
-    /* SPI Mode Fault error interrupt occurred --------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
+
+    /* SPI Mode Fault error interrupt occurred -------------------------------*/
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
       __HAL_SPI_CLEAR_MODFFLAG(hspi);
     }
-    
-    /* SPI Overrun error interrupt occurred -----------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
-    {
-      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);      
-      }
-    }
 
-    /* SPI Frame error interrupt occurred -------------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
+    /* SPI Frame error interrupt occurred ------------------------------------*/
+    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
       __HAL_SPI_CLEAR_FREFLAG(hspi);
     }
 
-    /* Call the Error call Back in case of Errors */
-    if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
     {
+      /* Disable all interrupts */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
       hspi->State = HAL_SPI_STATE_READY;
-      HAL_SPI_ErrorCallback(hspi);
+      /* Disable the SPI DMA requests if enabled */
+      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+      {
+        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+        /* Abort the SPI DMA Rx channel */
+        if (hspi->hdmarx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+          {
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+          }
+        }
+        /* Abort the SPI DMA Tx channel */
+        if (hspi->hdmatx != NULL)
+        {
+          /* Set the SPI DMA Abort callback :
+          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+          {
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+          }
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+        hspi->ErrorCallback(hspi);
+#else
+        HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      }
     }
+    return;
   }
 }
 
 /**
-  * @brief Tx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Tx Transfer completed callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxCpltCallback should be implemented in the user file
    */
 }
 
 /**
-  * @brief Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Rx Transfer completed callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback() could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxCpltCallback should be implemented in the user file
    */
 }
 
 /**
-  * @brief Tx and Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Tx and Rx Transfer completed callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
    */
 }
 
 /**
-  * @brief Tx Half Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Tx Half Transfer completed callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
    */
 }
 
 /**
-  * @brief Rx Half Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Rx Half Transfer completed callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
    */
 }
 
 /**
-  * @brief Tx and Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Tx and Rx Half Transfer callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+   */
+}
+
+/**
+  * @brief  SPI error callback.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_ErrorCallback should be implemented in the user file
+   */
+  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+            and user can use HAL_SPI_GetError() API to check the latest error occurred
    */
 }
 
 /**
-  * @brief SPI error callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  SPI Abort Complete callback.
+  * @param  hspi SPI handle.
   * @retval None
   */
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
 {
-  /* NOTE : - This function Should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback() could be implemented in the user file.
-            - The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred.
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
    */
 }
 
@@ -1650,13 +2565,13 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   * @}
   */
 
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   SPI control functions 
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+  * @brief   SPI control functions
   *
 @verbatim
  ===============================================================================
                       ##### Peripheral State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides a set of functions allowing to control the SPI.
      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
@@ -1666,24 +2581,26 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   */
 
 /**
-  * @brief  Return the SPI state
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL state
+  * @brief  Return the SPI handle state.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI state
   */
 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
 {
+  /* Return SPI handle state */
   return hspi->State;
 }
 
 /**
-  * @brief  Return the SPI error code
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval SPI Error Code
+  * @brief  Return the SPI error code.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval SPI error code in bitmap format
   */
 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
 {
+  /* Return SPI ErrorCode */
   return hspi->ErrorCode;
 }
 
@@ -1691,602 +2608,1149 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
   * @}
   */
 
-  /**
-  * @brief  Interrupt Handler to close Tx transfer 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
+/**
+  * @}
+  */
+
+/** @addtogroup SPI_Private_Functions
+  * @brief   Private functions
+  * @{
+  */
+
+/**
+  * @brief  DMA SPI transmit process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
   */
-static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  /* Wait until TXE flag is set to send data */
-  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-  }
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tickstart;
 
-  /* Disable TXE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
-  /* Disable ERR interrupt if Receive process is finished */
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
   {
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    /* Check the end of the transaction */
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
     }
 
-    /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
+    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
     {
       __HAL_SPI_CLEAR_OVRFLAG(hspi);
     }
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
+
+    hspi->TxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
     {
-      /* Check if we are in Tx or in Rx/Tx Mode */
-      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-      else
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      /* Set state to READY before run the Callback Complete */
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call Error call back in case of Error */
+      /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->ErrorCallback(hspi);
+#else
       HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      return;
     }
   }
+  /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->TxCpltCallback(hspi);
+#else
+  HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  Interrupt Handler to transmit amount of data in no-blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
+  * @brief  DMA SPI receive process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
   */
-static void SPI_TxISR(SPI_HandleTypeDef *hspi)
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  /* Transmit data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  }
-  /* Transmit data in 16 Bit mode */
-  else
-  {
-    hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-    hspi->pTxBuffPtr+=2;
-  }
-  hspi->TxXferCount--;
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tickstart;
 
-  if(hspi->TxXferCount == 0)
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
+
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
   {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    /* Disable ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
+    /* CRC handling */
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      /* calculate and transfer CRC on Tx line */
-      hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+      /* Wait until RXNE flag */
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+      {
+        /* Error on the CRC reception */
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      }
+      /* Read CRC */
+      READ_REG(hspi->Instance->DR);
     }
-    SPI_TxCloseIRQHandler(hspi);
-  }
-}
+#endif /* USE_SPI_CRC */
 
-/**
-  * @brief  Interrupt Handler to close Rx transfer 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
-{
-  __IO uint16_t tmpreg;
+    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-  {
-    /* Wait until RXNE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    /* Check the end of the transaction */
+    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
     }
 
-    /* Read CRC to reset RXNE flag */
-    tmpreg = hspi->Instance->DR;
-    UNUSED(tmpreg);
+    hspi->RxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
 
-    /* Wait until RXNE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+#if (USE_SPI_CRC != 0U)
+    /* Check if CRC error occurred */
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
     }
+#endif /* USE_SPI_CRC */
 
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-
-      /* Reset CRC Calculation */
-      SPI_RESET_CRC(hspi);
+      /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->ErrorCallback(hspi);
+#else
+      HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      return;
     }
   }
+  /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->RxCpltCallback(hspi);
+#else
+  HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
 
-  /* Disable RXNE and ERR interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
+/**
+  * @brief  DMA SPI transmit receive process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  uint32_t tickstart;
+
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
-  /* if Transmit process is finished */
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
+  /* DMA Normal Mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
   {
     /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
+#if (USE_SPI_CRC != 0U)
+    /* CRC handling */
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      /* Check if we are in Rx or in Rx/Tx Mode */
-      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+      /* Wait the CRC data */
+      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
       {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-      else
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_RxCpltCallback(hspi);
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
       }
+      /* Read CRC to Flush DR and RXNE flag */
+      READ_REG(hspi->Instance->DR);
     }
-    else
+#endif /* USE_SPI_CRC */
+
+    /* Check the end of the transaction */
+    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
     {
-      /* Set state to READY before run the Callback Complete */
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call Error call back in case of Error */
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    }
+
+    /* Disable Rx/Tx DMA Request */
+    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+    hspi->TxXferCount = 0U;
+    hspi->RxXferCount = 0U;
+    hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+    /* Check if CRC error occurred */
+    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    }
+#endif /* USE_SPI_CRC */
+
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+      /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->ErrorCallback(hspi);
+#else
       HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      return;
     }
   }
+  /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->TxRxCpltCallback(hspi);
+#else
+  HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  Interrupt Handler to receive amount of data in 2Lines mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
+  * @brief  DMA SPI half transmit process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
   */
-static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  /* Receive data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->TxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI half receive process complete callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->RxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI half transmit receive process complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->TxRxHalfCpltCallback(hspi);
+#else
+  HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI communication error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Stop the disable DMA transfer on SPI side */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+  hspi->State = HAL_SPI_STATE_READY;
+  /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->ErrorCallback(hspi);
+#else
+  HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->ErrorCallback(hspi);
+#else
+  HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA SPI Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  __IO uint32_t count;
+
+  hspi->hdmatx->XferAbortCallback = NULL;
+  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+  /* Disable Tx DMA Request */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+  /* Wait until TXE flag is set */
+  do
   {
-    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-  }
-  /* Receive data in 16 Bit mode */
-  else
+    if (count == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
+    count--;
+  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmarx != NULL)
   {
-    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr+=2;
+    if (hspi->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
   }
-  hspi->RxXferCount--;
 
-  if(hspi->RxXferCount==0)
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check no error during Abort procedure */
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
   {
-    SPI_RxCloseIRQHandler(hspi);
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   }
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State  = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->AbortCpltCallback(hspi);
+#else
+  HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  Interrupt Handler to receive amount of data in no-blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
+  * @brief  DMA SPI Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
   */
-static void SPI_RxISR(SPI_HandleTypeDef *hspi)
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
 {
-  /* Receive data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-  }
-  /* Receive data in 16 Bit mode */
-  else
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  hspi->hdmarx->XferAbortCallback = NULL;
+
+  /* Disable Rx DMA Request */
+  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+  /* Check Busy flag */
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
   {
-    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr+=2;
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
   }
-    hspi->RxXferCount--;
 
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  /* Check if an Abort process is still ongoing */
+  if (hspi->hdmatx != NULL)
   {
-    /* Set CRC Next to calculate CRC on Rx side */
-    hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;  
+    if (hspi->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
   }
 
-  if(hspi->RxXferCount == 0)
+  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+  hspi->RxXferCount = 0U;
+  hspi->TxXferCount = 0U;
+
+  /* Check no error during Abort procedure */
+  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
   {
-    SPI_RxCloseIRQHandler(hspi);
+    /* Reset errorCode */
+    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   }
+
+  /* Clear the Error flags in the SR register */
+  __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+  /* Restore hspi->State to Ready */
+  hspi->State  = HAL_SPI_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+  hspi->AbortCpltCallback(hspi);
+#else
+  HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA SPI transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  /* Receive data in 8bit mode */
+  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+  hspi->pRxBuffPtr++;
+  hspi->RxXferCount--;
 
-  /* DMA Normal Mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  /* Check end of the reception */
+  if (hspi->RxXferCount == 0U)
   {
-    /* Wait until TXE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
+      return;
     }
-    /* Disable Tx DMA Request */
-    hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
+#endif /* USE_SPI_CRC */
 
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+    /* Disable RXNE  and ERR interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+    if (hspi->TxXferCount == 0U)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+      SPI_CloseRxTx_ISR(hspi);
     }
-
-    hspi->TxXferCount = 0;
-
-    hspi->State = HAL_SPI_STATE_READY;
   }
+}
 
-  /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-   __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Read 8bit CRC to flush Data Regsiter */
+  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
 
-  /* Check if Errors has been detected during transfer */
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  if (hspi->TxXferCount == 0U)
   {
-    HAL_SPI_TxCpltCallback(hspi);
+    SPI_CloseRxTx_ISR(hspi);
   }
 }
+#endif /* USE_SPI_CRC */
 
 /**
-  * @brief DMA SPI receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  __IO uint16_t tmpreg;
-  
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr++;
+  hspi->TxXferCount--;
+
+  /* Check the end of the transmission */
+  if (hspi->TxXferCount == 0U)
   {
-    if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-       SPI_DMAEndTransmitReceive(hspi);  
-    }
-    /* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
-    else
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-      {
-        /* Disable SPI peripheral */
-        __HAL_SPI_DISABLE(hspi);
-      }
-      
-      /* Disable Rx DMA Request */
-      hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-      
-      hspi->RxXferCount = 0;
-      
-      /* Reset CRC Calculation */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-      {
-        /* Wait until RXNE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-        {
-          hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-        }
-        
-        /* Read CRC */
-        tmpreg = hspi->Instance->DR;
-        UNUSED(tmpreg);
-        
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-        {
-          hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-        }
-        
-        /* Check if CRC error occurred */
-        if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-        {
-          hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-          __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-        }
-      }
+      /* Set CRC Next Bit to send CRC */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      /* Disable TXE interrupt */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
     }
-    
-    hspi->State = HAL_SPI_STATE_READY;
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if (hspi->RxXferCount == 0U)
     {
-      HAL_SPI_ErrorCallback(hspi);
+      SPI_CloseRxTx_ISR(hspi);
     }
-    else
-    {
-      HAL_SPI_RxCpltCallback(hspi);
-    } 
-  }
-  else
-  {
-    HAL_SPI_RxCpltCallback(hspi);
   }
 }
 
 /**
-  * @brief End DMA SPI transmit receive process 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)   
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  __IO uint16_t tmpreg;
-  
-  /* Reset CRC Calculation */
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+  /* Receive data in 16 Bit mode */
+  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
+
+  if (hspi->RxXferCount == 0U)
   {
-    /* Check if CRC is done on going (RXNE flag set) */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      /* Wait until RXNE flag is set to send data */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-      {
-        hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-      }
+      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
+      return;
     }
-    /* Read CRC */
-    tmpreg = hspi->Instance->DR;
-    UNUSED(tmpreg);
-    
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+#endif /* USE_SPI_CRC */
+
+    /* Disable RXNE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+    if (hspi->TxXferCount == 0U)
     {
-      hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+      SPI_CloseRxTx_ISR(hspi);
     }
   }
-  
-  /* Wait until TXE flag is set to send data */
-  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-  }
-  /* Disable Tx DMA Request */
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-  
-  /* Wait until Busy flag is reset before disabling SPI */
-  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-  {
-    hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
-  }
-  
-  /* Disable Rx DMA Request */
-  hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-  
-  hspi->TxXferCount = 0;
-  hspi->RxXferCount = 0;
 }
 
+#if (USE_SPI_CRC != 0U)
 /**
-  * @brief DMA SPI transmit receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
-  { /**/
-    SPI_DMAEndTransmitReceive(hspi);
-    
-    hspi->State = HAL_SPI_STATE_READY;
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  /* Read 16bit CRC to flush Data Regsiter */
+  READ_REG(hspi->Instance->DR);
+
+  /* Disable RXNE interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+  SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  /* Enable CRC Transmission */
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
     {
-      HAL_SPI_ErrorCallback(hspi);
+      /* Set CRC Next Bit to send CRC */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+      /* Disable TXE interrupt */
+      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+      return;
     }
-    else
+#endif /* USE_SPI_CRC */
+
+    /* Disable TXE interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+    if (hspi->RxXferCount == 0U)
     {
-      HAL_SPI_TxRxCpltCallback(hspi);
+      SPI_CloseRxTx_ISR(hspi);
     }
   }
-  else
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+  * @brief  Manage the CRC 8-bit receive in Interrupt context.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+  /* Read 8bit CRC to flush Data Register */
+  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
+
+  SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+  * @brief  Manage the receive 8-bit in Interrupt context.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+  hspi->pRxBuffPtr++;
+  hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->RxXferCount == 0U)
   {
-    HAL_SPI_TxRxCpltCallback(hspi);
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR =  SPI_RxISR_8BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseRx_ISR(hspi);
   }
 }
 
+#if (USE_SPI_CRC != 0U)
 /**
-  * @brief DMA SPI half transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Manage the CRC 16-bit receive in Interrupt context.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  /* Read 16bit CRC to flush Data Register */
+  READ_REG(hspi->Instance->DR);
 
-  HAL_SPI_TxHalfCpltCallback(hspi);
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+  SPI_CloseRx_ISR(hspi);
 }
+#endif /* USE_SPI_CRC */
 
 /**
-  * @brief DMA SPI half receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Manage the 16-bit receive in Interrupt context.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
+  hspi->pRxBuffPtr += sizeof(uint16_t);
+  hspi->RxXferCount--;
 
-  HAL_SPI_RxHalfCpltCallback(hspi);
+#if (USE_SPI_CRC != 0U)
+  /* Enable CRC Transmission */
+  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+  {
+    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+  }
+#endif /* USE_SPI_CRC */
+
+  if (hspi->RxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      hspi->RxISR = SPI_RxISR_16BITCRC;
+      return;
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseRx_ISR(hspi);
+  }
 }
 
 /**
-  * @brief DMA SPI Half transmit receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Handle the data 8-bit transmit in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)   
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr++;
+  hspi->TxXferCount--;
 
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseTx_ISR(hspi);
+  }
 }
 
 /**
-  * @brief DMA SPI communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  Handle the data 16-bit transmit in Interrupt mode.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
   * @retval None
   */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 {
-  SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hspi->TxXferCount = 0;
-  hspi->RxXferCount = 0;
-  hspi->State= HAL_SPI_STATE_READY;
-  hspi->ErrorCode |= HAL_SPI_ERROR_DMA;
-  HAL_SPI_ErrorCallback(hspi);
+  /* Transmit data in 16 Bit mode */
+  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+  hspi->pTxBuffPtr += sizeof(uint16_t);
+  hspi->TxXferCount--;
+
+  if (hspi->TxXferCount == 0U)
+  {
+#if (USE_SPI_CRC != 0U)
+    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+    {
+      /* Enable CRC Transmission */
+      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+    }
+#endif /* USE_SPI_CRC */
+    SPI_CloseTx_ISR(hspi);
+  }
 }
 
 /**
-  * @brief This function handles SPI Communication Timeout.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  Flag: SPI flag to check
-  * @param  Status: Flag status to check: RESET or set
-  * @param  Timeout: Timeout duration
+  * @brief  Handle SPI Communication Timeout.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *              the configuration information for SPI module.
+  * @param  Flag SPI flag to check
+  * @param  State flag state to check
+  * @param  Timeout Timeout duration
+  * @param  Tickstart tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
+                                                       uint32_t Timeout, uint32_t Tickstart)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
+  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
   {
-    while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if(Timeout != HAL_MAX_DELAY)
+      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable the SPI and reset the CRC: the CRC value should be cleared
-             on both master and slave sides in order to resynchronize the master
-             and slave for their respective CRC calculation */
+        /* Disable the SPI and reset the CRC: the CRC value should be cleared
+        on both master and slave sides in order to resynchronize the master
+        and slave for their respective CRC calculation */
 
-          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 
+        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+        {
           /* Disable SPI peripheral */
           __HAL_SPI_DISABLE(hspi);
+        }
 
-          /* Reset CRC Calculation */
-          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-          {
-            SPI_RESET_CRC(hspi);
-          }
+        /* Reset CRC Calculation */
+        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+        {
+          SPI_RESET_CRC(hspi);
+        }
 
-          hspi->State= HAL_SPI_STATE_READY;
+        hspi->State = HAL_SPI_STATE_READY;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hspi);
 
-          return HAL_TIMEOUT;
-        }
+        return HAL_TIMEOUT;
       }
     }
   }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the check of the RX transaction complete.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
+{
+  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+  {
+    /* Disable SPI peripheral */
+    __HAL_SPI_DISABLE(hspi);
+  }
+
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the check of the RXTX or TX transaction complete.
+  * @param  hspi SPI handle
+  * @param  Timeout Timeout duration
+  * @param  Tickstart tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+  /* Control the BSY flag */
+  if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+    return HAL_TIMEOUT;
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle the end of the RXTX transaction.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  uint32_t tickstart;
+  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Disable ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+  /* Wait until TXE flag is set */
+  do
+  {
+    if (count == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      break;
+    }
+    count--;
+  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    hspi->State = HAL_SPI_STATE_READY;
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    hspi->ErrorCallback(hspi);
+#else
+    HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
   else
   {
-    while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
+#endif /* USE_SPI_CRC */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
     {
-      if(Timeout != HAL_MAX_DELAY)
+      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable the SPI and reset the CRC: the CRC value should be cleared
-             on both master and slave sides in order to resynchronize the master
-             and slave for their respective CRC calculation */
+        hspi->State = HAL_SPI_STATE_READY;
+        /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+        hspi->RxCpltCallback(hspi);
+#else
+        HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        hspi->State = HAL_SPI_STATE_READY;
+        /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+        hspi->TxRxCpltCallback(hspi);
+#else
+        HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      }
+    }
+    else
+    {
+      hspi->State = HAL_SPI_STATE_READY;
+      /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->ErrorCallback(hspi);
+#else
+      HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+#if (USE_SPI_CRC != 0U)
+  }
+#endif /* USE_SPI_CRC */
+}
 
-          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+/**
+  * @brief  Handle the end of the RX transaction.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+  /* Disable RXNE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
+  /* Check the end of the transaction */
+  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+  }
 
-          /* Reset CRC Calculation */
-          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
-          {
-            SPI_RESET_CRC(hspi);
-          }
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+  hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+  /* Check if CRC error occurred */
+  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+    /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    hspi->ErrorCallback(hspi);
+#else
+    HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+#endif /* USE_SPI_CRC */
+    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+    {
+      /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->RxCpltCallback(hspi);
+#else
+      HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+      hspi->ErrorCallback(hspi);
+#else
+      HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    }
+#if (USE_SPI_CRC != 0U)
+  }
+#endif /* USE_SPI_CRC */
+}
 
-          hspi->State= HAL_SPI_STATE_READY;
+/**
+  * @brief  Handle the end of the TX transaction.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  uint32_t tickstart;
+  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
-          return HAL_TIMEOUT;
-        }
-      }
+  /* Wait until TXE flag is set */
+  do
+  {
+    if (count == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+      break;
     }
+    count--;
+  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+  /* Disable TXE and ERR interrupt */
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
+  /* Check the end of the transaction */
+  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+  {
+    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
   }
-  return HAL_OK;
+
+  /* Clear overrun flag in 2 Lines communication mode because received is not read */
+  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+  {
+    __HAL_SPI_CLEAR_OVRFLAG(hspi);
+  }
+
+  hspi->State = HAL_SPI_STATE_READY;
+  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+  {
+    /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    hspi->ErrorCallback(hspi);
+#else
+    HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+    hspi->TxCpltCallback(hspi);
+#else
+    HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  Handle abort a Rx transaction.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+  /* Wait until TXE flag is set */
+  do
+  {
+    if (count == 0U)
+    {
+      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+      break;
+    }
+    count--;
+  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+  /* Read CRC to flush Data Register */
+  READ_REG(hspi->Instance->DR);
+
+  hspi->State = HAL_SPI_STATE_ABORT;
 }
 
+/**
+  * @brief  Handle abort a Tx or Rx/Tx transaction.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for SPI module.
+  * @retval None
+  */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+  /* Disable TXEIE interrupt */
+  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
+
+  /* Disable SPI Peripheral */
+  __HAL_SPI_DISABLE(hspi);
+
+  hspi->State = HAL_SPI_STATE_ABORT;
+}
 
 /**
   * @}
   */
 
 #endif /* HAL_SPI_MODULE_ENABLED */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c
index 833c541c..25864179 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c
@@ -2,187 +2,248 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_sram.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   SRAM HAL module driver.
-  *          This file provides a generic firmware to drive SRAM memories  
+  *          This file provides a generic firmware to drive SRAM memories
   *          mounted as external device.
-  *         
+  *
   @verbatim
   ==============================================================================
                           ##### How to use this driver #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This driver is a generic layered driver which contains a set of APIs used to 
-    control SRAM memories. It uses the FSMC layer functions to interface 
-    with SRAM devices.  
+    This driver is a generic layered driver which contains a set of APIs used to
+    control SRAM memories. It uses the FSMC layer functions to interface
+    with SRAM devices.
     The following sequence should be followed to configure the FSMC to interface
-    with SRAM/PSRAM memories: 
-      
+    with SRAM/PSRAM memories:
+
    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
-          SRAM_HandleTypeDef  hsram; and: 
-          
-       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 
+          SRAM_HandleTypeDef  hsram; and:
+
+       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
             values of the structure member.
-            
-       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 
-            base register instance for NOR or SRAM device 
-                         
+
+       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
+            base register instance for NOR or SRAM device
+
        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
-            base register instance for NOR or SRAM extended mode 
-             
-   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended 
+            base register instance for NOR or SRAM extended mode
+
+   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
        mode timings; for example:
           FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
       and fill its fields with the allowed values of the structure member.
-      
+
    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
        performs the following sequence:
-          
+
        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
-       (##) Control register configuration using the FSMC NORSRAM interface function 
+       (##) Control register configuration using the FSMC NORSRAM interface function
             FSMC_NORSRAM_Init()
-       (##) Timing register configuration using the FSMC NORSRAM interface function 
+       (##) Timing register configuration using the FSMC NORSRAM interface function
             FSMC_NORSRAM_Timing_Init()
-       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function 
+       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
             FSMC_NORSRAM_Extended_Timing_Init()
-       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()    
+       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
 
-   (#) At this stage you can perform read/write accesses from/to the memory connected 
+   (#) At this stage you can perform read/write accesses from/to the memory connected
        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
        following APIs:
        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-       
+
    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
-       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  
-       
+       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
+
    (#) You can continuously monitor the SRAM device HAL state by calling the function
-       HAL_SRAM_GetState()              
-                             
+       HAL_SRAM_GetState()
+
+       *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+      Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+      Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : SRAM MspInit.
+        (+) MspDeInitCallback  : SRAM MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
+      and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
+      or @ref HAL_SRAM_Init function.
+
+      When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
+#ifdef HAL_SRAM_MODULE_ENABLED
+
 /** @defgroup SRAM SRAM
   * @brief SRAM driver modules
   * @{
   */
-#ifdef HAL_SRAM_MODULE_ENABLED
 
+/**
+  @cond 0
+  */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/    
+/* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SRAM_DMACplt    (DMA_HandleTypeDef *hdma);
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
+static void SRAM_DMAError   (DMA_HandleTypeDef *hdma);
+/**
+  @endcond
+  */
 
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
   * @{
   */
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
+
+/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions.
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
            ##### SRAM Initialization and de_initialization functions #####
   ==============================================================================
     [..]  This section provides functions allowing to initialize/de-initialize
           the SRAM memory
-  
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Performs the SRAM device initialization sequence
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  Timing: Pointer to SRAM control timing structure 
-  * @param  ExtTiming: Pointer to SRAM extended mode timing structure  
+  * @param  Timing Pointer to SRAM control timing structure
+  * @param  ExtTiming Pointer to SRAM extended mode timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{ 
+{
   /* Check the SRAM handle parameter */
-  if(hsram == NULL)
+  if (hsram == NULL)
   {
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
-  
-  if(hsram->State == HAL_SRAM_STATE_RESET)
-  {  
+
+  if (hsram->State == HAL_SRAM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hsram->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+    if(hsram->MspInitCallback == NULL)
+    {
+      hsram->MspInitCallback = HAL_SRAM_MspInit;
+    }
+    hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+    hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+
+    /* Init the low level hardware */
+    hsram->MspInitCallback(hsram);
+#else
     /* Initialize the low level hardware (MSP) */
     HAL_SRAM_MspInit(hsram);
+#endif
   }
-  
+
   /* Initialize SRAM control Interface */
-  FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
+  (void)FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
 
   /* Initialize SRAM timing Interface */
-  FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 
+  (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
 
   /* Initialize SRAM extended mode timing Interface */
-  FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  
-  
+  (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
+
   /* Enable the NORSRAM device */
-  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 
-  
+  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
+
+  /* Initialize the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Performs the SRAM device De-initialization sequence.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval HAL status
   */
-HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{ 
+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
+{
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  if(hsram->MspDeInitCallback == NULL)
+  {
+    hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+  }
+
+  /* DeInit the low level hardware */
+  hsram->MspDeInitCallback(hsram);
+#else
   /* De-Initialize the low level hardware (MSP) */
   HAL_SRAM_MspDeInit(hsram);
-   
+#endif
+
   /* Configure the SRAM registers with their reset values */
-  FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
+  (void)FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
 
+  /* Reset the SRAM controller state */
   hsram->State = HAL_SRAM_STATE_RESET;
-  
+
   /* Release Lock */
   __HAL_UNLOCK(hsram);
 
@@ -191,387 +252,664 @@ HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
 
 /**
   * @brief  SRAM MSP Init.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval None
   */
 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  SRAM MSP DeInit.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval None
   */
 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsram);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DMA transfer complete callback.
-  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval None
   */
 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DMA transfer complete error callback.
-  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hdma pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval None
   */
 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdma);
+
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
+/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
+  * @brief    Input Output and memory control functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
                   ##### SRAM Input and Output functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to use and control the SRAM memory
-  
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Reads 8-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Reads 8-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
 {
-  __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t * pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *pDstBuffer = *(__IO uint8_t *)pSramAddress;
-    pDstBuffer++;
-    pSramAddress++;
+    return HAL_ERROR;
   }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;   
+  return HAL_OK;
 }
 
 /**
-  * @brief  Writes 8-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Writes 8-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
 {
-  __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
-  
+  uint32_t size;
+  __IO uint8_t *psramaddress = (uint8_t *)pAddress;
+  uint8_t * psrcbuff = pSrcBuffer;
+
   /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  if (hsram->State == HAL_SRAM_STATE_READY)
   {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
+    /* Process Locked */
+    __HAL_LOCK(hsram);
 
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *(__IO uint8_t *)pSramAddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    pSramAddress++;    
-  }    
+    return HAL_ERROR;
+  }
 
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;   
+  return HAL_OK;
 }
 
 /**
-  * @brief  Reads 16-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Reads 16-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
 {
-  __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t *pdestbuff = pDstBuffer;
+  uint8_t limit;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits mulitple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Read data from memory */
+    for (size = BufferSize; size != limit; size-=2U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+      pdestbuff++;
+      *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Read last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *pDstBuffer = *(__IO uint16_t *)pSramAddress;
-    pDstBuffer++;
-    pSramAddress++;
+    return HAL_ERROR;
   }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
-  * @brief  Writes 16-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Writes 16-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
 {
-  __IO uint16_t * pSramAddress = (uint16_t *)pAddress; 
-  
+  uint32_t size;
+  __IO uint32_t *psramaddress = pAddress;
+  uint16_t * psrcbuff = pSrcBuffer;
+  uint8_t limit;
+
   /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  if (hsram->State == HAL_SRAM_STATE_READY)
   {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
+    /* Process Locked */
+    __HAL_LOCK(hsram);
 
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Check if the size is a 32-bits mulitple */
+    limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
+
+    /* Write data to memory */
+    for (size = BufferSize; size != limit; size-=2U)
+    {
+      *psramaddress = (uint32_t)(*psrcbuff);
+      psrcbuff++;
+      *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Write last 16-bits if size is not 32-bits multiple */
+    if (limit != 0U)
+    {
+      *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *(__IO uint16_t *)pSramAddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    pSramAddress++;    
-  }    
+    return HAL_ERROR;
+  }
 
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
-  * @brief  Reads 32-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Reads 32-bit buffer from SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 {
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
+  uint32_t size;
+  __IO uint32_t * psramaddress = pAddress;
+  uint32_t * pdestbuff = pDstBuffer;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Read data from memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *pdestbuff = *psramaddress;
+      pdestbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = state;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *pDstBuffer = *(__IO uint32_t *)pAddress;
-    pDstBuffer++;
-    pAddress++;
+    return HAL_ERROR;
   }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
 
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
-  * @brief  Writes 32-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @brief  Writes 32-bit buffer to SRAM memory.
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 {
+  uint32_t size;
+  __IO uint32_t * psramaddress = pAddress;
+  uint32_t * psrcbuff = pSrcBuffer;
+
   /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  if (hsram->State == HAL_SRAM_STATE_READY)
   {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
+    /* Process Locked */
+    __HAL_LOCK(hsram);
 
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Write data to memory */
+    for (size = BufferSize; size != 0U; size--)
+    {
+      *psramaddress = *psrcbuff;
+      psrcbuff++;
+      psramaddress++;
+    }
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
   {
-    *(__IO uint32_t *)pAddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    pAddress++;    
-  }    
+    return HAL_ERROR;
+  }
 
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;   
+  return HAL_OK;
 }
 
 /**
   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
+  * @param  pAddress Pointer to read start address
+  * @param  pDstBuffer Pointer to destination buffer
+  * @param  BufferSize Size of the buffer to read from memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 {
-  /* Process Locked */
-  __HAL_LOCK(hsram);  
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;   
-  
-  /* Configure DMA user callbacks */
-  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
-  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);  
-  
-  return HAL_OK; 
+  HAL_StatusTypeDef status;
+  HAL_SRAM_StateTypeDef state = hsram->State;
+
+  /* Check the SRAM controller state */
+  if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    if (state == HAL_SRAM_STATE_READY)
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    }
+    else
+    {
+      hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
+    }
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
 }
 
 /**
   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
+  * @param  pAddress Pointer to write start address
+  * @param  pSrcBuffer Pointer to source buffer to write
+  * @param  BufferSize Size of the buffer to write to memory
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 {
+  HAL_StatusTypeDef status;
+
   /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  if (hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Configure DMA user callbacks */
+    hsram->hdma->XferCpltCallback = SRAM_DMACplt;
+    hsram->hdma->XferErrorCallback = SRAM_DMAError;
+
+    /* Enable the DMA Stream */
+    status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return status;
+}
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User SRAM Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if(pCallback == NULL)
   {
-    return  HAL_ERROR; 
+    return HAL_ERROR;
   }
-  
-  /* Process Locked */
+
+  /* Process locked */
   __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
-  
-  /* Configure DMA user callbacks */
-  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
-  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;  
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);  
-  
-  return HAL_OK;
+
+  state = hsram->State;
+  if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+    case HAL_SRAM_MSP_INIT_CB_ID :
+      hsram->MspInitCallback = pCallback;
+      break;
+    case HAL_SRAM_MSP_DEINIT_CB_ID :
+      hsram->MspDeInitCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
 }
 
+/**
+  * @brief  Unregister a User SRAM Callback
+  *         SRAM Callback is redirected to the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_MSP_INIT_CB_ID       SRAM MspInit callback ID
+  *          @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID     SRAM MspDeInit callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+    case HAL_SRAM_MSP_INIT_CB_ID :
+      hsram->MspInitCallback = HAL_SRAM_MspInit;
+      break;
+    case HAL_SRAM_MSP_DEINIT_CB_ID :
+      hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+      break;
+    case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+      hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+      break;
+    case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+      hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(state == HAL_SRAM_STATE_RESET)
+  {
+    switch (CallbackId)
+    {
+    case HAL_SRAM_MSP_INIT_CB_ID :
+      hsram->MspInitCallback = HAL_SRAM_MspInit;
+      break;
+    case HAL_SRAM_MSP_DEINIT_CB_ID :
+      hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+
+/**
+  * @brief  Register a User SRAM Callback for DMA transfers
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hsram : SRAM handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID  SRAM DMA Xfer Complete callback ID
+  *          @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID   SRAM DMA Xfer Error callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_SRAM_StateTypeDef state;
+
+  if(pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hsram);
+
+  state = hsram->State;
+  if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+    case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+      hsram->DmaXferCpltCallback = pCallback;
+      break;
+    case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+      hsram->DmaXferErrorCallback = pCallback;
+      break;
+    default :
+      /* update return status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hsram);
+  return status;
+}
+#endif
+
 /**
   * @}
   */
-  
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions 
- *  @brief   management functions 
+
+/** @defgroup SRAM_Exported_Functions_Group3 Control functions
+ *  @brief   Control functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                         ##### SRAM Control functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control dynamically
     the SRAM interface.
@@ -579,78 +917,97 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Enables dynamically SRAM write operation.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
 {
-  /* Process Locked */
-  __HAL_LOCK(hsram);
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
 
-  /* Enable write operation */
-  FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-  
-  return HAL_OK;  
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Enable write operation */
+    (void)FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically SRAM write operation.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
 {
-  /* Process Locked */
-  __HAL_LOCK(hsram);
+  /* Check the SRAM controller state */
+  if(hsram->State == HAL_SRAM_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsram);
 
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;
-    
-  /* Disable write operation */
-  FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_PROTECTED;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-  
-  return HAL_OK;  
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_BUSY;
+
+    /* Disable write operation */
+    (void)FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
+
+    /* Update the SRAM controller state */
+    hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hsram);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup SRAM_Exported_Functions_Group4 State functions 
- *  @brief   Peripheral State functions 
+/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
+ *  @brief   Peripheral State functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
                       ##### SRAM State functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection permits to get in run-time the status of the SRAM controller 
+    This subsection permits to get in run-time the status of the SRAM controller
     and the data flow.
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Returns the SRAM controller state
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
+  * @param  hsram pointer to a SRAM_HandleTypeDef structure that contains
   *                the configuration information for SRAM module.
   * @retval HAL state
   */
@@ -666,13 +1023,88 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
 /**
   * @}
   */
-#endif /* HAL_SRAM_MODULE_ENABLED */
+
+/**
+  @cond 0
+  */
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_READY;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif
+}
+
+/**
+  * @brief  DMA SRAM process complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_PROTECTED;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferCpltCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferCpltCallback(hdma);
+#endif
+}
+
+/**
+  * @brief  DMA SRAM error callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+
+  /* Disable the DMA channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Update the SRAM controller state */
+  hsram->State = HAL_SRAM_STATE_ERROR;
+
+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
+  hsram->DmaXferErrorCallback(hdma);
+#else
+  HAL_SRAM_DMA_XferErrorCallback(hdma);
+#endif
+}
+/**
+  @endcond
+  */
+
 /**
   * @}
   */
 
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
 /**
   * @}
   */
 
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c
index b429c9ec..12dd98c3 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c
@@ -2,87 +2,88 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Timer (TIM) peripheral:
-  *           + Time Base Initialization
-  *           + Time Base Start
-  *           + Time Base Start Interruption
-  *           + Time Base Start DMA
-  *           + Time Output Compare/PWM Initialization
-  *           + Time Output Compare/PWM Channel Configuration
-  *           + Time Output Compare/PWM  Start
-  *           + Time Output Compare/PWM  Start Interruption
-  *           + Time Output Compare/PWM Start DMA
-  *           + Time Input Capture Initialization
-  *           + Time Input Capture Channel Configuration
-  *           + Time Input Capture Start
-  *           + Time Input Capture Start Interruption 
-  *           + Time Input Capture Start DMA
-  *           + Time One Pulse Initialization
-  *           + Time One Pulse Channel Configuration
-  *           + Time One Pulse Start 
-  *           + Time Encoder Interface Initialization
-  *           + Time Encoder Interface Start
-  *           + Time Encoder Interface Start Interruption
-  *           + Time Encoder Interface Start DMA
+  *           + TIM Time Base Initialization
+  *           + TIM Time Base Start
+  *           + TIM Time Base Start Interruption
+  *           + TIM Time Base Start DMA
+  *           + TIM Output Compare/PWM Initialization
+  *           + TIM Output Compare/PWM Channel Configuration
+  *           + TIM Output Compare/PWM  Start
+  *           + TIM Output Compare/PWM  Start Interruption
+  *           + TIM Output Compare/PWM Start DMA
+  *           + TIM Input Capture Initialization
+  *           + TIM Input Capture Channel Configuration
+  *           + TIM Input Capture Start
+  *           + TIM Input Capture Start Interruption
+  *           + TIM Input Capture Start DMA
+  *           + TIM One Pulse Initialization
+  *           + TIM One Pulse Channel Configuration
+  *           + TIM One Pulse Start
+  *           + TIM Encoder Interface Initialization
+  *           + TIM Encoder Interface Start
+  *           + TIM Encoder Interface Start Interruption
+  *           + TIM Encoder Interface Start DMA
   *           + Commutation Event configuration with Interruption and DMA
-  *           + Time OCRef clear configuration
-  *           + Time External Clock configuration
-  @verbatim 
+  *           + TIM OCRef clear configuration
+  *           + TIM External Clock configuration
+  @verbatim
   ==============================================================================
                       ##### TIMER Generic features #####
   ==============================================================================
-  [..] The Timer features include: 
+  [..] The Timer features include:
        (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 
+       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
            counter clock frequency either by any factor between 1 and 65536.
        (#) Up to 4 independent channels for:
            (++) Input Capture
            (++) Output Compare
            (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output               
-   
-                        ##### How to use this driver #####
+           (++) One-pulse mode output
+       (#) Synchronization circuit to control the timer with external signals and to interconnect
+            several timers together.
+       (#) Supports incremental encoder for positioning purposes
+
+            ##### How to use this driver #####
   ==============================================================================
     [..]
-     (#) Initialize the TIM low level resources by implementing the following functions 
-         depending from feature used :
-           (++) Time Base : HAL_TIM_Base_MspInit() 
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Time Base : HAL_TIM_Base_MspInit()
            (++) Input Capture : HAL_TIM_IC_MspInit()
            (++) Output Compare : HAL_TIM_OC_MspInit()
            (++) PWM generation : HAL_TIM_PWM_MspInit()
            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-           
+
      (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
         (##) TIM pins configuration
             (+++) Enable the clock for the TIM GPIOs using the following function:
-                 __GPIOx_CLK_ENABLE();   
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
+             __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
 
-     (#) The external Clock can be configured, if needed (the default clock is the 
+     (#) The external Clock can be configured, if needed (the default clock is the
          internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
          any start function.
-  
-     (#) Configure the TIM in the desired functioning mode using one of the 
-         initialization function of this driver:
-         (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-         (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 
-              Output Compare signal.
-         (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 
-              PWM signal.
-         (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 
-              external signal.
-         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 
-              in One Pulse Mode.
-         (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-         
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+       Initialization function of this driver:
+       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+            Output Compare signal.
+       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+            PWM signal.
+       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+            external signal.
+       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+            in One Pulse Mode.
+       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
@@ -93,37 +94,93 @@
      (#) The DMA Burst is managed with the two following functions:
          HAL_TIM_DMABurst_WriteStart()
          HAL_TIM_DMABurst_ReadStart()
-  
+
+    *** Callback registration ***
+  =============================================
+
+  [..]
+  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+
+  [..]
+  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  the Callback ID and a pointer to the user callback function.
+
+  [..]
+  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+
+  [..]
+  These functions allow to register/unregister following callbacks:
+    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.
+    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.
+    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.
+    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.
+    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.
+    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.
+    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.
+    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.
+    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.
+    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.
+    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.
+    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.
+    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.
+    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.
+    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.
+    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.
+    (+) TriggerCallback                   : TIM Trigger Callback.
+    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.
+    (+) IC_CaptureCallback                : TIM Input Capture Callback.
+    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.
+    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.
+    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.
+    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+    (+) ErrorCallback                     : TIM Error Callback.
+    (+) CommutationCallback               : TIM Commutation Callback.
+    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.
+    (+) BreakCallback                     : TIM Break Callback.
+
+  [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+  [..]
+  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+  functionalities in the Init / DeInit only when these callbacks are null
+  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+  [..]
+    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+    Exception done MspInit / MspDeInit that can be registered / unregistered
+    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+  [..]
+      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registration feature is not available and all callbacks
+      are set to the corresponding weak functions.
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -143,50 +200,47 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
 /** @addtogroup TIM_Private_Functions
   * @{
   */
-/* Private function prototypes -----------------------------------------------*/
 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-
 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
+                              uint32_t TIM_ICFilter);
 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
+                              uint32_t TIM_ICFilter);
 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
+                              uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                     TIM_SlaveConfigTypeDef * sSlaveConfig);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
 /**
   * @}
   */
-  
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup TIM_Exported_Functions TIM Exported Functions
   * @{
   */
 
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions 
- *  @brief    Time Base functions 
- *
-@verbatim    
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+  *  @brief    Time Base functions
+  *
+@verbatim
   ==============================================================================
               ##### Time Base functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Initialize and configure the TIM base. 
+    (+) Initialize and configure the TIM base.
     (+) De-initialize the TIM base.
     (+) Start the Time Base.
     (+) Stop the Time Base.
@@ -194,72 +248,97 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
     (+) Stop the Time Base and disable interrupt.
     (+) Start the Time Base and enable DMA transfer.
     (+) Stop the Time Base and disable DMA transfer.
- 
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{ 
+{
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance)); 
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {  
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Base_MspInitCallback == NULL)
+    {
+      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC */
     HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
   /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-  
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the TIM Base peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM Base peripheral
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{  
+{
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
 
   htim->State = HAL_TIM_STATE_BUSY;
-   
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-    
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Base_MspDeInitCallback == NULL)
+  {
+    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Base_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_TIM_Base_MspDeInit(htim);
-  
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
-  
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
+
   /* Release Lock */
   __HAL_UNLOCK(htim);
 
@@ -268,103 +347,116 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval None
   */
 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_Base_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM Base MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval None
   */
 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_Base_MspDeInit could be implemented in the user file
    */
 }
 
+
 /**
   * @brief  Starts the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Base generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   /* Enable the TIM Update interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-      
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-      
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -373,120 +465,139 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   /* Disable the TIM Update interrupt */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-      
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-    
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to peripheral.
+  * @param  htim TIM Base handle
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to peripheral.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if((pData == 0 ) && (Length > 0)) 
+    if ((pData == NULL) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }  
-  /* Set the DMA Period elapsed callback */
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+  /* Set the DMA Period elapsed callbacks */
   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
+  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
   /* Set the DMA error callback */
   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-  
+
+  /* Enable the DMA stream */
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+
   /* Enable the TIM Update DMA request */
   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
-  
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Base handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-  
+
   /* Disable the TIM Update DMA request */
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-      
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-    
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-      
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 
- *  @brief    Time Output Compare functions 
- *
-@verbatim    
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+  *  @brief    TIM Output Compare functions
+  *
+@verbatim
   ==============================================================================
-                  ##### Time Output Compare functions #####
+                  ##### TIM Output Compare functions #####
   ==============================================================================
   [..]
     This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare. 
+    (+) Initialize and configure the TIM Output Compare.
     (+) De-initialize the TIM Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
- 
+    (+) Start the TIM Output Compare.
+    (+) Stop the TIM Output Compare.
+    (+) Start the TIM Output Compare and enable interrupt.
+    (+) Stop the TIM Output Compare and disable interrupt.
+    (+) Start the TIM Output Compare and enable DMA transfer.
+    (+) Stop the TIM Output Compare and disable DMA transfer.
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+  * @param  htim TIM Output Compare handle
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
 {
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
@@ -495,48 +606,70 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
- 
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OC_MspInitCallback == NULL)
+    {
+      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OC_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Init the base time for the Output Compare */  
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init); 
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the Output Compare */
+  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Output Compare handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
-   htim->State = HAL_TIM_STATE_BUSY;
-   
+
+  htim->State = HAL_TIM_STATE_BUSY;
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-  
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OC_MspDeInitCallback == NULL)
+  {
+    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OC_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
   HAL_TIM_OC_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(htim);
@@ -546,68 +679,76 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Output Compare handle
   * @retval None
   */
 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_OC_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Output Compare handle
   * @retval None
   */
 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_OC_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.  
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected   
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   /* Enable the Output compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -619,28 +760,27 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   /* Disable the Output compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
-  }  
-  
+  }
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);  
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
-}  
+}
 
 /**
   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -650,64 +790,69 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Enable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Enable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Enable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Enable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  } 
+      break;
+  }
 
   /* Enable the Output compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -719,182 +864,205 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break; 
-  } 
-  
+      break;
+  }
+
   /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-  
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);  
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    if ((pData == NULL) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }    
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
       /* Enable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
       /* Enable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 3 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
-     /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 4 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Enable the Output compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
-  }  
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+  }
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -906,95 +1074,103 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Disable the Output compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
 
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 
- *  @brief    Time PWM functions 
- *
-@verbatim    
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+  *  @brief    TIM PWM functions
+  *
+@verbatim
   ==============================================================================
-                          ##### Time PWM functions #####
+                          ##### TIM PWM functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Initialize and configure the TIM OPWM. 
+    (+) Initialize and configure the TIM PWM.
     (+) De-initialize the TIM PWM.
-    (+) Start the Time PWM.
-    (+) Stop the Time PWM.
-    (+) Start the Time PWM and enable interrupt.
-    (+) Stop the Time PWM and disable interrupt.
-    (+) Start the Time PWM and enable DMA transfer.
-    (+) Stop the Time PWM and disable DMA transfer.
- 
+    (+) Start the TIM PWM.
+    (+) Stop the TIM PWM.
+    (+) Start the TIM PWM and enable interrupt.
+    (+) Stop the TIM PWM and disable interrupt.
+    (+) Start the TIM PWM and enable DMA transfer.
+    (+) Stop the TIM PWM and disable DMA transfer.
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+  * @param  htim TIM PWM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
 {
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
@@ -1003,48 +1179,70 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
-  if(htim->State == HAL_TIM_STATE_RESET)
+  if (htim->State == HAL_TIM_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->PWM_MspInitCallback == NULL)
+    {
+      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->PWM_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
 
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;  
-  
-  /* Init the base time for the PWM */  
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-   
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the PWM */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
-}  
+}
 
 /**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM PWM handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-    
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->PWM_MspDeInitCallback == NULL)
+  {
+    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->PWM_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
   HAL_TIM_PWM_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(htim);
@@ -1054,35 +1252,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM PWM handle
   * @retval None
   */
 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_PWM_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM PWM handle
   * @retval None
   */
 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1092,30 +1293,35 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
 
   /* Enable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Stops the PWM signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1124,34 +1330,33 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
+{
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-    
+
   /* Disable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1161,64 +1366,68 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Enable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Enable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Enable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Enable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Enable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1226,186 +1435,208 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break; 
+      break;
   }
-  
+
   /* Disable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    if ((pData == NULL) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }    
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
       /* Enable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Output Capture/Compare 3 request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
-     /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 4 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Enable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM PWM handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1417,95 +1648,103 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Disable the Capture compare channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
 
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 
- *  @brief    Time Input Capture functions 
- *
-@verbatim    
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+  *  @brief    TIM Input Capture functions
+  *
+@verbatim
   ==============================================================================
-              ##### Time Input Capture functions #####
+              ##### TIM Input Capture functions #####
   ==============================================================================
- [..]  
+ [..]
    This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture. 
+   (+) Initialize and configure the TIM Input Capture.
    (+) De-initialize the TIM Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
- 
+   (+) Start the TIM Input Capture.
+   (+) Stop the TIM Input Capture.
+   (+) Start the TIM Input Capture and enable interrupt.
+   (+) Stop the TIM Input Capture and disable interrupt.
+   (+) Start the TIM Input Capture and enable DMA transfer.
+   (+) Stop the TIM Input Capture and disable DMA transfer.
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+  * @param  htim TIM Input Capture handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
 {
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
@@ -1513,32 +1752,45 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->IC_MspInitCallback == NULL)
+    {
+      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->IC_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;   
-  
-  /* Init the base time for the input capture */  
-  TIM_Base_SetConfig(htim->Instance, &htim->Init); 
-   
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Init the base time for the input capture */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the TIM peripheral 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM peripheral
+  * @param  htim TIM Input Capture handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1547,14 +1799,23 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
 
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-    
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->IC_MspDeInitCallback == NULL)
+  {
+    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->IC_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
   HAL_TIM_IC_MspDeInit(htim);
-    
-  /* Change TIM state */  
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
   htim->State = HAL_TIM_STATE_RESET;
 
   /* Release Lock */
@@ -1564,36 +1825,39 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Initializes the TIM INput Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Initializes the TIM Input Capture MSP.
+  * @param  htim TIM Input Capture handle
   * @retval None
   */
 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_IC_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_IC_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1601,26 +1865,31 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   /* Enable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
 
   /* Return function status */
-  return HAL_OK;  
-} 
+  return HAL_OK;
+}
 
 /**
   * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1629,25 +1898,24 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
+{
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   /* Disable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1655,59 +1923,64 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Enable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Enable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Enable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Enable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  }  
+      break;
+  }
   /* Enable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-    
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
 
   /* Return function status */
-  return HAL_OK;  
-} 
+  return HAL_OK;
+}
 
 /**
   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1719,172 +1992,192 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break; 
-  } 
-  
+      break;
+  }
+
   /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 
-  
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @brief  Starts the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if((pData == 0 ) && (Length > 0)) 
+    if ((pData == NULL) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }  
-   
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); 
-      
-      /* Enable the TIM Capture/Compare 1 DMA request */      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 2  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 3  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 4  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+      break;
     }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Enable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-   
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @brief  Stops the TIM Input Capture measurement in DMA mode.
+  * @param  htim TIM Input Capture handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1897,84 +2190,91 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
   /* Check the parameters */
   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3  DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
       /* Disable the TIM Capture/Compare 4  DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
     }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Disable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-  
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
-}  
+}
 /**
   * @}
   */
-  
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 
- *  @brief    Time One Pulse functions 
- *
-@verbatim    
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+  *  @brief    TIM One Pulse functions
+  *
+@verbatim
   ==============================================================================
-                        ##### Time One Pulse functions #####
+                        ##### TIM One Pulse functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse. 
+    (+) Initialize and configure the TIM One Pulse.
     (+) De-initialize the TIM One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
- 
+    (+) Start the TIM One Pulse.
+    (+) Stop the TIM One Pulse.
+    (+) Start the TIM One Pulse and enable interrupt.
+    (+) Stop the TIM One Pulse and disable interrupt.
+    (+) Start the TIM One Pulse and enable DMA transfer.
+    (+) Stop the TIM One Pulse and disable DMA transfer.
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OnePulseMode: Select the One pulse mode.
+  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+  * @param  htim TIM One Pulse handle
+  * @param  OnePulseMode Select the One pulse mode.
   *         This parameter can be one of the following values:
   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
@@ -1983,7 +2283,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
 {
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
@@ -1993,53 +2293,75 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-  
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->OnePulse_MspInitCallback == NULL)
+    {
+      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->OnePulse_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;  
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
   /* Configure the Time base in the One Pulse Mode */
   TIM_Base_SetConfig(htim->Instance, &htim->Init);
-  
+
   /* Reset the OPM Bit */
   htim->Instance->CR1 &= ~TIM_CR1_OPM;
 
   /* Configure the OPM Mode */
   htim->Instance->CR1 |= OnePulseMode;
-   
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the TIM One Pulse  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM One Pulse
+  * @param  htim TIM One Pulse handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-  
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->OnePulse_MspDeInitCallback == NULL)
+  {
+    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->OnePulse_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_TIM_OnePulse_MspDeInit(htim);
-    
-  /* Change TIM state */  
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
   htim->State = HAL_TIM_STATE_RESET;
 
   /* Release Lock */
@@ -2050,35 +2372,38 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM One Pulse handle
   * @retval None
   */
 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM One Pulse handle
   * @retval None
   */
 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2086,33 +2411,35 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
-  /* Enable the Capture compare and the Input Capture channels 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
-    
-    No need to enable the counter, it's enabled automatically by hardware 
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
     (the counter starts in response to a stimulus and generate a pulse */
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be disable.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be disable
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2120,33 +2447,35 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
-  /* Disable the Capture compare and the Input Capture channels 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Disable the Capture compare and the Input Capture channels
   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-    
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2154,39 +2483,41 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
-  /* Enable the Capture compare and the Input Capture channels 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
+  /* Enable the Capture compare and the Input Capture channels
     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 
-    
-    No need to enable the counter, it's enabled automatically by hardware 
+    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+    No need to enable the counter, it's enabled automatically by hardware
     (the counter starts in response to a stimulus and generate a pulse */
- 
+
   /* Enable the TIM Capture/Compare 1 interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
+
   /* Enable the TIM Capture/Compare 2 interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
-  
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Enable the main output */
     __HAL_TIM_MOE_ENABLE(htim);
   }
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel : TIM Channels to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2194,77 +2525,90 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
   */
 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(OutputChannel);
+
   /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);  
-  
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
   /* Disable the TIM Capture/Compare 2 interrupt */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  
-  /* Disable the Capture compare and the Input Capture channels 
+
+  /* Disable the Capture compare and the Input Capture channels
   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
-  if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)  
+  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
   {
     /* Disable the Main Output */
     __HAL_TIM_MOE_DISABLE(htim);
   }
-    
+
   /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);  
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
 
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 
- *  @brief    Time Encoder functions 
- *
-@verbatim    
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+  *  @brief    TIM Encoder functions
+  *
+@verbatim
   ==============================================================================
-                          ##### Time Encoder functions #####
+                          ##### TIM Encoder functions #####
   ==============================================================================
   [..]
     This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder. 
+    (+) Initialize and configure the TIM Encoder.
     (+) De-initialize the TIM Encoder.
-    (+) Start the Time Encoder.
-    (+) Stop the Time Encoder.
-    (+) Start the Time Encoder and enable interrupt.
-    (+) Stop the Time Encoder and disable interrupt.
-    (+) Start the Time Encoder and enable DMA transfer.
-    (+) Stop the Time Encoder and disable DMA transfer.
- 
+    (+) Start the TIM Encoder.
+    (+) Stop the TIM Encoder.
+    (+) Start the TIM Encoder and enable interrupt.
+    (+) Stop the TIM Encoder and disable interrupt.
+    (+) Start the TIM Encoder and enable DMA transfer.
+    (+) Stop the TIM Encoder and disable DMA transfer.
+
 @endverbatim
   * @{
   */
 /**
-  * @brief  Initializes the TIM Encoder Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Encoder Interface configuration structure
+  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.
+  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *         requires a timer reset to avoid unexpected direction
+  *         due to DIR bit readonly in center aligned mode.
+  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together
+  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+  * @param  htim TIM Encoder Interface handle
+  * @param  sConfig TIM Encoder Interface configuration structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
 {
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-  
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
-   
+
   /* Check the parameters */
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
@@ -2276,23 +2620,36 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
 
-  if(htim->State == HAL_TIM_STATE_RESET)
-  { 
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy weak callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->Encoder_MspInitCallback == NULL)
+    {
+      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Encoder_MspInitCallback(htim);
+#else
     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
     HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
   }
-  
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;   
-    
-  /* Reset the SMS bits */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
+  /* Reset the SMS and ECE bits */
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
   /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);  
-  
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
   /* Get the TIMx SMCR register value */
   tmpsmcr = htim->Instance->SMCR;
 
@@ -2307,19 +2664,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
 
   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-  
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
   /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
-  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
 
   /* Set the TI1 and the TI2 Polarities */
   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-  
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
   /* Write to TIMx SMCR */
   htim->Instance->SMCR = tmpsmcr;
 
@@ -2328,35 +2685,44 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
 
   /* Write to TIMx CCER */
   htim->Instance->CCER = tmpccer;
-  
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-  
+  htim->State = HAL_TIM_STATE_READY;
+
   return HAL_OK;
 }
 
+
 /**
-  * @brief  DeInitializes the TIM Encoder interface  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM Encoder interface
+  * @param  htim TIM Encoder Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-  
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->Encoder_MspDeInitCallback == NULL)
+  {
+    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->Encoder_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_TIM_Encoder_MspDeInit(htim);
-    
-  /* Change TIM state */  
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
   htim->State = HAL_TIM_STATE_RESET;
- 
+
   /* Release Lock */
   __HAL_UNLOCK(htim);
 
@@ -2365,35 +2731,38 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Encoder Interface handle
   * @retval None
   */
 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_Encoder_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Encoder Interface handle
   * @retval None
   */
 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2404,39 +2773,40 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  
+
   /* Enable the encoder interface channels */
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break; 
+      break;
     }
+
     case TIM_CHANNEL_2:
-    { 
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
       break;
-    }  
+    }
+
     default :
     {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     break; 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
     }
-  }  
+  }
   /* Enable the Peripheral */
   __HAL_TIM_ENABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Encoder Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2446,41 +2816,43 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
-   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
+  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channels 1 and 2
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break; 
+      break;
     }
+
     case TIM_CHANNEL_2:
-    { 
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
+    {
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
       break;
-    }  
+    }
+
     default :
     {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-     break; 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+      break;
     }
-  }  
+  }
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2491,7 +2863,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  
+
   /* Enable the encoder interface channels */
   /* Enable the capture compare Interrupts 1 and/or 2 */
   switch (Channel)
@@ -2500,36 +2872,37 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
     {
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break; 
+      break;
     }
+
     case TIM_CHANNEL_2:
-    { 
+    {
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
       break;
-    }  
+    }
+
     default :
     {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-     break; 
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
   }
-  
+
   /* Enable the Peripheral */
   __HAL_TIM_ENABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be disabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2540,169 +2913,185 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
+
   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
-  if(Channel == TIM_CHANNEL_1)
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
   {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
     /* Disable the capture compare Interrupts 1 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }  
-  else if(Channel == TIM_CHANNEL_2)
-  {  
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
     /* Disable the capture compare Interrupts 2 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }  
+    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+  }
   else
   {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
     /* Disable the capture compare Interrupts 1 and 2 */
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
   }
-    
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @param  pData1: The destination Buffer address for IC1.
-  * @param  pData2: The destination Buffer address for IC2.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @param  pData1 The destination Buffer address for IC1.
+  * @param  pData2 The destination Buffer address for IC2.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+                                            uint32_t *pData2, uint16_t Length)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) 
+    if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }  
-   
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); 
-      
-      /* Enable the TIM Input Capture DMA request */      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the TIM Input Capture DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-            
+
       /* Enable the Peripheral */
       __HAL_TIM_ENABLE(htim);
-      
+
       /* Enable the Capture compare channel */
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-      
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-     
+
       /* Enable the Peripheral */
       __HAL_TIM_ENABLE(htim);
-      
+
       /* Enable the Capture compare channel */
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_ALL:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-      
-      /* Set the DMA Period elapsed callback */
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-          
-     /* Enable the Peripheral */
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      /* Enable the Peripheral */
       __HAL_TIM_ENABLE(htim);
-      
+
       /* Enable the Capture compare channel */
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      
+
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     default:
-    break;
-  }  
+      break;
+  }
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Encoder Interface handle
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2713,299 +3102,364 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-  
+
   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 
-  if(Channel == TIM_CHANNEL_1)
+    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+  if (Channel == TIM_CHANNEL_1)
   {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
     /* Disable the capture compare DMA Request 1 */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-  }  
-  else if(Channel == TIM_CHANNEL_2)
-  {  
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+  }
+  else if (Channel == TIM_CHANNEL_2)
+  {
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
     /* Disable the capture compare DMA Request 2 */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }  
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+  }
   else
   {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 
-    
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
     /* Disable the capture compare DMA Request 1 and 2 */
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
   }
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 
- *  @brief    IRQ handler management 
- *
-@verbatim   
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+  *  @brief    TIM IRQ handler management
+  *
+@verbatim
   ==============================================================================
                         ##### IRQ handler management #####
-  ==============================================================================  
-  [..]  
+  ==============================================================================
+  [..]
     This section provides Timer IRQ handler function.
-               
+
 @endverbatim
   * @{
   */
 /**
   * @brief  This function handles TIM interrupts requests.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM  handle
   * @retval None
   */
 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
 {
   /* Capture compare 1 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
     {
       {
         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-        
+
         /* Input capture event */
-        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
         {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
           HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
         }
         /* Output compare event */
         else
         {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
           HAL_TIM_OC_DelayElapsedCallback(htim);
           HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
         }
         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
       }
     }
   }
   /* Capture compare 2 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
       /* Input capture event */
-      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
-      {          
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
         HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       /* Output compare event */
       else
       {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
         HAL_TIM_OC_DelayElapsedCallback(htim);
         HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
     }
   }
   /* Capture compare 3 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
       /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
-      {          
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
         HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       /* Output compare event */
       else
       {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
         HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim); 
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
     }
   }
   /* Capture compare 4 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
       /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
-      {          
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
         HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       /* Output compare event */
       else
       {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
         HAL_TIM_OC_DelayElapsedCallback(htim);
         HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
       }
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
     }
   }
   /* TIM Update event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
       HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
     }
   }
   /* TIM Break input event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
       HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
     }
   }
   /* TIM Trigger detection event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
       HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
     }
   }
   /* TIM commutation event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
   {
-    if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
     {
       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
-      HAL_TIMEx_CommutationCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
     }
   }
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+  *  @brief    TIM Peripheral Control functions
+  *
+@verbatim
   ==============================================================================
                    ##### Peripheral Control functions #####
-  ==============================================================================  
- [..] 
+  ==============================================================================
+ [..]
    This section provides functions allowing to:
-   (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
-   (+) Configure External Clock source.
-   (+) Configure Complementary channels, break features and dead time.
-   (+) Configure Master and the Slave synchronization.
-   (+) Configure the DMA Burst Mode.
-      
+      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+      (+) Configure External Clock source.
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master and the Slave synchronization.
+      (+) Configure the DMA Burst Mode.
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the TIM Output Compare Channels according to the specified
   *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  sConfig TIM Output Compare configuration structure
+  * @param  Channel TIM Channels to configure
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+                                           TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel)
 {
-  /* Check the parameters */ 
-  assert_param(IS_TIM_CHANNELS(Channel)); 
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  
-  /* Check input state */
-  __HAL_LOCK(htim); 
-  
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
       /* Configure the TIM Channel 1 in Output Compare */
       TIM_OC1_SetConfig(htim->Instance, sConfig);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
       /* Configure the TIM Channel 2 in Output Compare */
       TIM_OC2_SetConfig(htim->Instance, sConfig);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
-       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+      /* Check the parameters */
+      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
       /* Configure the TIM Channel 3 in Output Compare */
       TIM_OC3_SetConfig(htim->Instance, sConfig);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
       /* Configure the TIM Channel 4 in Output Compare */
       TIM_OC4_SetConfig(htim->Instance, sConfig);
+      break;
     }
-    break;
-    
+
     default:
-    break;    
+      break;
   }
+
   htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim); 
-  
+
+  __HAL_UNLOCK(htim);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the TIM Input Capture Channels according to the specified
   *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Input Capture configuration structure
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM IC handle
+  * @param  sConfig TIM Input Capture configuration structure
+  * @param  Channel TIM Channel to configure
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected 
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -3013,19 +3467,20 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-  
+
+  /* Process Locked */
   __HAL_LOCK(htim);
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   if (Channel == TIM_CHANNEL_1)
   {
     /* TI1 Configuration */
     TIM_TI1_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
     /* Reset the IC1PSC Bits */
     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
 
@@ -3036,28 +3491,28 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   {
     /* TI2 Configuration */
     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    
-    TIM_TI2_SetConfig(htim->Instance, 
+
+    TIM_TI2_SetConfig(htim->Instance,
                       sConfig->ICPolarity,
                       sConfig->ICSelection,
                       sConfig->ICFilter);
-               
+
     /* Reset the IC2PSC Bits */
     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
 
     /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
   }
   else if (Channel == TIM_CHANNEL_3)
   {
     /* TI3 Configuration */
     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-    
-    TIM_TI3_SetConfig(htim->Instance,  
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
+
+    TIM_TI3_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
     /* Reset the IC3PSC Bits */
     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
 
@@ -3068,33 +3523,32 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   {
     /* TI4 Configuration */
     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-    
-    TIM_TI4_SetConfig(htim->Instance, 
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-               
+
+    TIM_TI4_SetConfig(htim->Instance,
+                      sConfig->ICPolarity,
+                      sConfig->ICSelection,
+                      sConfig->ICFilter);
+
     /* Reset the IC4PSC Bits */
     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
 
     /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
   }
-  
+
   htim->State = HAL_TIM_STATE_READY;
-    
+
   __HAL_UNLOCK(htim);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Initializes the TIM PWM  channels according to the specified
   *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM PWM handle
+  * @param  sConfig TIM PWM configuration structure
+  * @param  Channel TIM Channels to be configured
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3102,212 +3556,228 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+                                            TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel)
 {
-  __HAL_LOCK(htim);
-  
-  /* Check the parameters */ 
-  assert_param(IS_TIM_CHANNELS(Channel)); 
+  /* Check the parameters */
+  assert_param(IS_TIM_CHANNELS(Channel));
   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
 
+  /* Process Locked */
+  __HAL_LOCK(htim);
+
   htim->State = HAL_TIM_STATE_BUSY;
-    
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
       /* Configure the Channel 1 in PWM mode */
       TIM_OC1_SetConfig(htim->Instance, sConfig);
-      
+
       /* Set the Preload enable bit for channel1 */
       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-      
+
       /* Configure the Output Fast mode */
       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
       htim->Instance->CCMR1 |= sConfig->OCFastMode;
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
       /* Configure the Channel 2 in PWM mode */
       TIM_OC2_SetConfig(htim->Instance, sConfig);
-      
+
       /* Set the Preload enable bit for channel2 */
       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-      
+
       /* Configure the Output Fast mode */
       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
       /* Configure the Channel 3 in PWM mode */
       TIM_OC3_SetConfig(htim->Instance, sConfig);
-      
+
       /* Set the Preload enable bit for channel3 */
       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-      
-     /* Configure the Output Fast mode */
+
+      /* Configure the Output Fast mode */
       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;  
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_4:
     {
+      /* Check the parameters */
       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
       /* Configure the Channel 4 in PWM mode */
       TIM_OC4_SetConfig(htim->Instance, sConfig);
-      
+
       /* Set the Preload enable bit for channel4 */
       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-      
-     /* Configure the Output Fast mode */
+
+      /* Configure the Output Fast mode */
       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;  
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+      break;
     }
-    break;
-    
+
     default:
-    break;    
+      break;
   }
-  
+
   htim->State = HAL_TIM_STATE_READY;
-    
+
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the TIM One Pulse Channels according to the specified
   *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM One Pulse configuration structure
-  * @param  OutputChannel: TIM Channels to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  sConfig TIM One Pulse configuration structure
+  * @param  OutputChannel TIM output channel to configure
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel: TIM Channels to be enabled.
+  * @param  InputChannel TIM input Channel to configure
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  * @note  To output a waveform with a minimum delay user can enable the fast
+  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+  *        output is forced in response to the edge detection on TIx input,
+  *        without taking in account the comparison.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
+                                                 uint32_t OutputChannel,  uint32_t InputChannel)
 {
   TIM_OC_InitTypeDef temp1;
-  
+
   /* Check the parameters */
   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
 
-  if(OutputChannel != InputChannel)  
+  if (OutputChannel != InputChannel)
   {
+    /* Process Locked */
     __HAL_LOCK(htim);
-  
+
     htim->State = HAL_TIM_STATE_BUSY;
 
-    /* Extract the Output compare configuration from sConfig structure */  
+    /* Extract the Output compare configuration from sConfig structure */
     temp1.OCMode = sConfig->OCMode;
     temp1.Pulse = sConfig->Pulse;
     temp1.OCPolarity = sConfig->OCPolarity;
     temp1.OCNPolarity = sConfig->OCNPolarity;
     temp1.OCIdleState = sConfig->OCIdleState;
-    temp1.OCNIdleState = sConfig->OCNIdleState; 
-    
+    temp1.OCNIdleState = sConfig->OCNIdleState;
+
     switch (OutputChannel)
     {
       case TIM_CHANNEL_1:
       {
         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
-        TIM_OC1_SetConfig(htim->Instance, &temp1); 
+
+        TIM_OC1_SetConfig(htim->Instance, &temp1);
+        break;
       }
-      break;
       case TIM_CHANNEL_2:
       {
         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
+
         TIM_OC2_SetConfig(htim->Instance, &temp1);
+        break;
       }
-      break;
       default:
-      break;  
-    } 
+        break;
+    }
+
     switch (InputChannel)
     {
       case TIM_CHANNEL_1:
       {
         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
+
         TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                        sConfig->ICSelection, sConfig->ICFilter);
-               
+                          sConfig->ICSelection, sConfig->ICFilter);
+
         /* Reset the IC1PSC Bits */
         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
 
         /* Select the Trigger source */
         htim->Instance->SMCR &= ~TIM_SMCR_TS;
         htim->Instance->SMCR |= TIM_TS_TI1FP1;
-      
-        /* Select the Slave Mode */      
+
+        /* Select the Slave Mode */
         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
       }
-      break;
       case TIM_CHANNEL_2:
       {
         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
+
         TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                 sConfig->ICSelection, sConfig->ICFilter);
-               
+                          sConfig->ICSelection, sConfig->ICFilter);
+
         /* Reset the IC2PSC Bits */
         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
 
         /* Select the Trigger source */
         htim->Instance->SMCR &= ~TIM_SMCR_TS;
         htim->Instance->SMCR |= TIM_TS_TI2FP2;
-      
-        /* Select the Slave Mode */      
+
+        /* Select the Slave Mode */
         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
         htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+        break;
       }
-      break;
-    
+
       default:
-      break;  
+        break;
     }
-  
+
     htim->State = HAL_TIM_STATE_READY;
-    
+
     __HAL_UNLOCK(htim);
-  
+
     return HAL_OK;
   }
   else
   {
     return HAL_ERROR;
   }
-} 
+}
 
 /**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1  
+  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
   *            @arg TIM_DMABASE_CR2
   *            @arg TIM_DMABASE_SMCR
   *            @arg TIM_DMABASE_DIER
@@ -3316,18 +3786,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
   *            @arg TIM_DMABASE_CCMR1
   *            @arg TIM_DMABASE_CCMR2
   *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT   
-  *            @arg TIM_DMABASE_PSC   
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
   *            @arg TIM_DMABASE_ARR
   *            @arg TIM_DMABASE_RCR
   *            @arg TIM_DMABASE_CCR1
   *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3  
+  *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3335,204 +3804,245 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
   *            @arg TIM_DMA_COM: TIM Commutation DMA source
   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
+                                              uint32_t *BurstBuffer, uint32_t  BurstLength)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if((BurstBuffer == 0 ) && (BurstLength > 0)) 
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
   }
-  switch(BurstRequestSrc)
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
   {
     case TIM_DMA_UPDATE:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA Period elapsed callbacks */
       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC1:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC2:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC3:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC4:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_COM:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-     
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_TRIGGER:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA trigger callbacks */
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-     
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+                           (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     default:
-    break;  
-  }
-   /* configure the DMA Burst Mode */
-   htim->Instance->DCR = BurstBaseAddress | BurstLength;  
-   
-   /* Enable the TIM DMA Request */
-   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);  
-   
-   htim->State = HAL_TIM_STATE_READY;
-  
+      break;
+  }
+  /* configure the DMA Burst Mode */
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+  /* Enable the TIM DMA Request */
+  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+  htim->State = HAL_TIM_STATE_READY;
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stops the TIM DMA Burst mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable
+  * @brief  Stops the TIM DMA Burst mode
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the parameters */
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
   {
     case TIM_DMA_UPDATE:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
     }
-    break;
     case TIM_DMA_CC1:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
     case TIM_DMA_CC2:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
     case TIM_DMA_CC3:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+    {
+      status =  HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
     case TIM_DMA_CC4:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
     }
-    break;
     case TIM_DMA_COM:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
     }
-    break;
     case TIM_DMA_TRIGGER:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
     }
-    break;
     default:
-    break;
+      break;
+  }
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
   }
 
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-      
   /* Return function status */
-  return HAL_OK;  
+  return status;
 }
 
 /**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABASE_CR1  
+  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+  * @param  htim TIM handle
+  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read
+  *         This parameter can be one of the following values:
+  *            @arg TIM_DMABASE_CR1
   *            @arg TIM_DMABASE_CR2
   *            @arg TIM_DMABASE_SMCR
   *            @arg TIM_DMABASE_DIER
@@ -3541,18 +4051,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
   *            @arg TIM_DMABASE_CCMR1
   *            @arg TIM_DMABASE_CCMR2
   *            @arg TIM_DMABASE_CCER
-  *            @arg TIM_DMABASE_CNT   
-  *            @arg TIM_DMABASE_PSC   
+  *            @arg TIM_DMABASE_CNT
+  *            @arg TIM_DMABASE_PSC
   *            @arg TIM_DMABASE_ARR
   *            @arg TIM_DMABASE_RCR
   *            @arg TIM_DMABASE_CCR1
   *            @arg TIM_DMABASE_CCR2
-  *            @arg TIM_DMABASE_CCR3  
+  *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources.
-  *         This parameters can be on of the following values:
+  * @param  BurstRequestSrc TIM DMA Request sources
+  *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
@@ -3560,491 +4069,562 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
   *            @arg TIM_DMA_COM: TIM Commutation DMA source
   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @param  BurstBuffer The Buffer address.
+  * @param  BurstLength DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if((BurstBuffer == 0 ) && (BurstLength > 0)) 
+    if ((BurstBuffer == NULL) && (BurstLength > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }  
-  switch(BurstRequestSrc)
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  switch (BurstRequestSrc)
   {
     case TIM_DMA_UPDATE:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA Period elapsed callbacks */
       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-     
+      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC1:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC2:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA capture/compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);     
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC3:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_CC4:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_COM:
-    {  
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
-     
+    {
+      /* Set the DMA commutation callbacks */
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
+      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     case TIM_DMA_TRIGGER:
-    {  
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA trigger callbacks */
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-     
+      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-  
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
+      break;
     }
-    break;
     default:
-    break;  
+      break;
   }
 
   /* configure the DMA Burst Mode */
-  htim->Instance->DCR = BurstBaseAddress | BurstLength;  
-  
+  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
   /* Enable the TIM DMA Request */
   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-  
+
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stop the DMA burst reading 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
+  * @brief  Stop the DMA burst reading
+  * @param  htim TIM handle
+  * @param  BurstRequestSrc TIM DMA Request sources to disable.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the parameters */
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
+
+  /* Abort the DMA transfer (at least disable the DMA stream) */
+  switch (BurstRequestSrc)
   {
     case TIM_DMA_UPDATE:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+      break;
     }
-    break;
     case TIM_DMA_CC1:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
     case TIM_DMA_CC2:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
     case TIM_DMA_CC3:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
     case TIM_DMA_CC4:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+      break;
     }
-    break;
     case TIM_DMA_COM:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+      break;
     }
-    break;
     case TIM_DMA_TRIGGER:
-    {  
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+    {
+      status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+      break;
     }
-    break;
     default:
-    break;  
+      break;
   }
-  
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-      
+
+  if (HAL_OK == status)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  }
+
   /* Return function status */
-  return HAL_OK;  
+  return status;
 }
 
 /**
   * @brief  Generate a software event
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  EventSource: specifies the event source.
+  * @param  htim TIM handle
+  * @param  EventSource specifies the event source.
   *          This parameter can be one of the following values:
   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source  
+  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
-  * @note   TIM6 and TIM7 can only generate an update event. 
-  * @note   TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
+  * @note   Basic timers can only generate an update event.
+  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+  * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances
+  *         supporting a break input.
   * @retval HAL status
-  */ 
+  */
 
 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
 {
   /* Check the parameters */
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-  
+
   /* Process Locked */
   __HAL_LOCK(htim);
-  
+
   /* Change the TIM state */
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Set the event sources */
   htim->Instance->EGR = EventSource;
-  
+
   /* Change the TIM state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   __HAL_UNLOCK(htim);
-  
+
   /* Return function status */
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Configures the OCRef clear feature
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral. 
-  * @param  Channel: specifies the TIM Channel.
+  * @param  htim TIM handle
+  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+  *         contains the OCREF clear feature and parameters for the TIM peripheral.
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
   * @retval HAL status
-  */ 
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{ 
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           uint32_t Channel)
+{
   /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CHANNELS(Channel));
+  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-  assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-  assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-  assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-   
+
   /* Process Locked */
   __HAL_LOCK(htim);
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
-  if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
+
+  switch (sClearInputConfig->ClearInputSource)
   {
-    TIM_ETR_SetConfig(htim->Instance, 
-                      sClearInputConfig->ClearInputPrescaler,
-                      sClearInputConfig->ClearInputPolarity,
-                      sClearInputConfig->ClearInputFilter);
+    case TIM_CLEARINPUTSOURCE_NONE:
+    {
+      /* Clear the OCREF clear selection bit and the the ETR Bits */
+      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+      break;
+    }
+
+    case TIM_CLEARINPUTSOURCE_ETR:
+    {
+      /* Check the parameters */
+      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+      {
+        htim->State = HAL_TIM_STATE_READY;
+        __HAL_UNLOCK(htim);
+        return HAL_ERROR;
+      }
+
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClearInputConfig->ClearInputPrescaler,
+                        sClearInputConfig->ClearInputPolarity,
+                        sClearInputConfig->ClearInputFilter);
+      break;
+    }
+
+    default:
+      break;
   }
-  
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {        
-      if(sClearInputConfig->ClearInputState != RESET)  
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
       {
-        /* Enable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
+        /* Enable the OCREF clear feature for Channel 1 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
       }
       else
       {
-        /* Disable the Ocref clear feature for Channel 1 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;      
+        /* Disable the OCREF clear feature for Channel 1 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
       }
-    }    
-    break;
-    case TIM_CHANNEL_2:    
-    { 
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 
-      if(sClearInputConfig->ClearInputState != RESET)  
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
       {
-        /* Enable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
+        /* Enable the OCREF clear feature for Channel 2 */
+        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
       }
       else
       {
-        /* Disable the Ocref clear feature for Channel 2 */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;      
+        /* Disable the OCREF clear feature for Channel 2 */
+        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
       }
-    } 
-    break;
-    case TIM_CHANNEL_3:   
-    {  
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)  
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
       {
-        /* Enable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
+        /* Enable the OCREF clear feature for Channel 3 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
       }
       else
       {
-        /* Disable the Ocref clear feature for Channel 3 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;      
+        /* Disable the OCREF clear feature for Channel 3 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
       }
-    } 
-    break;
-    case TIM_CHANNEL_4:    
-    {  
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      if(sClearInputConfig->ClearInputState != RESET)  
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
       {
-        /* Enable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
+        /* Enable the OCREF clear feature for Channel 4 */
+        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
       }
       else
       {
-        /* Disable the Ocref clear feature for Channel 4 */
-        htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;      
+        /* Disable the OCREF clear feature for Channel 4 */
+        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
       }
-    } 
-    break;
-    default:  
-    break;
-  } 
+      break;
+    }
+    default:
+      break;
+  }
 
   htim->State = HAL_TIM_STATE_READY;
-  
+
   __HAL_UNLOCK(htim);
-  
-  return HAL_OK;  
-}  
+
+  return HAL_OK;
+}
 
 /**
   * @brief   Configures the clock source to be used
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral. 
+  * @param  htim TIM handle
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
   * @retval HAL status
-  */ 
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)    
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
 {
-  uint32_t tmpsmcr = 0;
-    
+  uint32_t tmpsmcr;
+
   /* Process Locked */
   __HAL_LOCK(htim);
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Check the parameters */
   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-  assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-  assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-  assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-  
+
   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
   tmpsmcr = htim->Instance->SMCR;
   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
   htim->Instance->SMCR = tmpsmcr;
-  
+
   switch (sClockSourceConfig->ClockSource)
   {
     case TIM_CLOCKSOURCE_INTERNAL:
-    { 
-      assert_param(IS_TIM_INSTANCE(htim->Instance));      
-      /* Disable slave mode to clock the prescaler directly with the internal clock */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+    {
+      assert_param(IS_TIM_INSTANCE(htim->Instance));
+      break;
     }
-    break;
-    
+
     case TIM_CLOCKSOURCE_ETRMODE1:
     {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
       /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sClockSourceConfig->ClockPrescaler, 
-                        sClockSourceConfig->ClockPolarity, 
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
                         sClockSourceConfig->ClockFilter);
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      /* Reset the SMS and TS Bits */
-      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+
       /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
       /* Write to TIMx SMCR */
       htim->Instance->SMCR = tmpsmcr;
+      break;
     }
-    break;
-    
+
     case TIM_CLOCKSOURCE_ETRMODE2:
     {
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+      /* Check ETR input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
       /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sClockSourceConfig->ClockPrescaler, 
+      TIM_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
                         sClockSourceConfig->ClockPolarity,
                         sClockSourceConfig->ClockFilter);
       /* Enable the External clock mode2 */
       htim->Instance->SMCR |= TIM_SMCR_ECE;
+      break;
     }
-    break;
-    
+
     case TIM_CLOCKSOURCE_TI1:
     {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      TIM_TI1_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity, 
-                        sClockSourceConfig->ClockFilter);
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+      break;
     }
-    break;
+
     case TIM_CLOCKSOURCE_TI2:
     {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_TI2_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity, 
-                        sClockSourceConfig->ClockFilter);
+      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+      break;
     }
-    break;
+
     case TIM_CLOCKSOURCE_TI1ED:
     {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      TIM_TI1_ConfigInputStage(htim->Instance, 
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
+      /* Check whether or not the timer instance supports external clock mode 1 */
+      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter);
       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+      break;
     }
-    break;
+
     case TIM_CLOCKSOURCE_ITR0:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
-    }
-    break;
     case TIM_CLOCKSOURCE_ITR1:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
-    }
-    break;
     case TIM_CLOCKSOURCE_ITR2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
-    }
-    break;
     case TIM_CLOCKSOURCE_ITR3:
     {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
     }
-    break;
-    
+
     default:
-    break;    
+      break;
   }
   htim->State = HAL_TIM_STATE_READY;
-  
+
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
   *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
+  * @param  htim TIM handle.
+  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the
   *         output of a XOR gate.
-  *         This parameter can be one of the following values:
+  *          This parameter can be one of the following values:
   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
   *            pins are connected to the TI1 input (XOR combination)
@@ -4052,10 +4632,10 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
   */
 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
 {
-  uint32_t tmpcr2 = 0;
-  
+  uint32_t tmpcr2;
+
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 
+  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
 
   /* Get the TIMx CR2 register value */
@@ -4066,7 +4646,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
 
   /* Set the TI1 selection */
   tmpcr2 |= TI1_Selection;
-  
+
   /* Write to TIMxCR2 */
   htim->Instance->CR2 = tmpcr2;
 
@@ -4075,81 +4655,89 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
 
 /**
   * @brief  Configures the TIM in Slave mode
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
   *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave 
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
   /* Check the parameters */
   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-   
+
   __HAL_LOCK(htim);
-  
+
   htim->State = HAL_TIM_STATE_BUSY;
 
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-  
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
   /* Disable Trigger Interrupt */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-  
+
   /* Disable Trigger DMA request */
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-  
+
   htim->State = HAL_TIM_STATE_READY;
-     
-  __HAL_UNLOCK(htim);  
-  
+
+  __HAL_UNLOCK(htim);
+
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Configures the TIM in Slave mode in interrupt mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+  * @param  htim TIM handle.
+  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
   *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave 
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1). 
+  *         timer input or external trigger input) and the Slave mode
+  *         (Disable, Reset, Gated, Trigger, External clock mode 1).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 
-                                                        TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
   /* Check the parameters */
   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-  
+
   __HAL_LOCK(htim);
 
   htim->State = HAL_TIM_STATE_BUSY;
-  
-  TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-  
+
+  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+  {
+    htim->State = HAL_TIM_STATE_READY;
+    __HAL_UNLOCK(htim);
+    return HAL_ERROR;
+  }
+
   /* Enable Trigger Interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-  
+
   /* Disable Trigger DMA request */
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-  
+
   htim->State = HAL_TIM_STATE_READY;
-     
-  __HAL_UNLOCK(htim);  
-  
+
+  __HAL_UNLOCK(htim);
+
   return HAL_OK;
 }
 
 /**
   * @brief  Read the captured value from Capture Compare unit
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channels to be enabled.
+  * @param  htim TIM handle.
+  * @param  Channel TIM Channels to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4159,207 +4747,759 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
   */
 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
-  uint32_t tmpreg = 0;
-  
-  __HAL_LOCK(htim);
-  
+  uint32_t tmpreg = 0U;
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      
+
       /* Return the capture 1 value */
-      tmpreg = htim->Instance->CCR1;
-      
+      tmpreg =  htim->Instance->CCR1;
+
       break;
     }
     case TIM_CHANNEL_2:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      
+
       /* Return the capture 2 value */
-      tmpreg = htim->Instance->CCR2;
-      
+      tmpreg =   htim->Instance->CCR2;
+
       break;
     }
-    
+
     case TIM_CHANNEL_3:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      
+
       /* Return the capture 3 value */
-      tmpreg = htim->Instance->CCR3;
-      
+      tmpreg =   htim->Instance->CCR3;
+
       break;
     }
-    
+
     case TIM_CHANNEL_4:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      
+
       /* Return the capture 4 value */
-      tmpreg = htim->Instance->CCR4;
-      
+      tmpreg =   htim->Instance->CCR4;
+
       break;
     }
-    
+
     default:
-    break;  
+      break;
   }
-     
-  __HAL_UNLOCK(htim);  
+
   return tmpreg;
 }
+
 /**
   * @}
   */
-  
+
 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions 
- *
-@verbatim   
+  *  @brief    TIM Callbacks functions
+  *
+@verbatim
   ==============================================================================
                         ##### TIM Callbacks functions #####
-  ==============================================================================  
- [..]  
+  ==============================================================================
+ [..]
    This section provides TIM callback functions:
-   (+) Timer Period elapsed callback
-   (+) Timer Output Compare callback
-   (+) Timer Input capture callback
-   (+) Timer Trigger callback
-   (+) Timer Error callback
+   (+) TIM Period elapsed callback
+   (+) TIM Output Compare callback
+   (+) TIM Input capture callback
+   (+) TIM Trigger callback
+   (+) TIM Error callback
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Period elapsed callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Period elapsed callback in non-blocking mode
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
    */
-  
 }
+
 /**
-  * @brief  Output Compare callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Period elapsed half complete callback in non-blocking mode
+  * @param  htim TIM handle
   * @retval None
   */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
    */
 }
+
 /**
-  * @brief  Input Capture callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
   * @retval None
   */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  PWM Pulse finished callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
   * @retval None
   */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Hall Trigger detection callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Input Capture half complete callback in non-blocking mode
+  * @param  htim TIM IC handle
   * @retval None
   */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Timer error callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
   * @retval None
   */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
    */
 }
+
 /**
-  * @}
+  * @brief  PWM Pulse finished half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
   */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
 
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+   */
+}
 
 /**
-  * @brief  Return the TIM Base state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
   */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
 {
-  return htim->State;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
 }
 
 /**
-  * @brief  Return the TIM OC state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
+  * @brief  Hall Trigger detection half complete callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
   */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
 {
-  return htim->State;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+   */
 }
 
 /**
-  * @brief  Return the TIM PWM state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @retval HAL state
+  * @brief  Timer error callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User TIM callback to be used instead of the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @param pCallback pointer to the callback function
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+                                           pTIM_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback               = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback                 = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback                = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback             = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback              = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback            = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback                = pCallback;
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback        = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                      = pCallback;
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback              = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                   = pCallback;
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback              = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback            = pCallback;
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                        = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback                  = pCallback;
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback          = pCallback;
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                        = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = pCallback;
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = pCallback;
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = pCallback;
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = pCallback;
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = pCallback;
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a TIM callback
+  *         TIM callback is redirected to the weak predefined callback
+  * @param htim tim handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+  *          @retval status
+  */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(htim);
+
+  if (htim->State == HAL_TIM_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        break;
+
+      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_CB_ID :
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        break;
+
+      case HAL_TIM_TRIGGER_HALF_CB_ID :
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_CB_ID :
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        break;
+
+      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        break;
+
+      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        break;
+
+      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        break;
+
+      case HAL_TIM_ERROR_CB_ID :
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_CB_ID :
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        break;
+
+      case HAL_TIM_COMMUTATION_HALF_CB_ID :
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        break;
+
+      case HAL_TIM_BREAK_CB_ID :
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_TIM_BASE_MSPINIT_CB_ID :
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        break;
+
+      case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_IC_MSPINIT_CB_ID :
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        break;
+
+      case HAL_TIM_IC_MSPDEINIT_CB_ID :
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_OC_MSPINIT_CB_ID :
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        break;
+
+      case HAL_TIM_OC_MSPDEINIT_CB_ID :
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPINIT_CB_ID :
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        break;
+
+      case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        break;
+
+      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        break;
+
+      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        break;
+
+      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        break;
+
+      default :
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(htim);
+
+  return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+  *  @brief   TIM Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                        ##### Peripheral State functions #####
+  ==============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the TIM Base handle state.
+  * @param  htim TIM Base handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM OC handle state.
+  * @param  htim TIM Output Compare handle
+  * @retval HAL state
+  */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+  return htim->State;
+}
+
+/**
+  * @brief  Return the TIM PWM handle state.
+  * @param  htim TIM handle
+  * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
 {
@@ -4367,9 +5507,8 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Return the TIM Input Capture state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Return the TIM Input Capture handle state.
+  * @param  htim TIM IC handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -4378,9 +5517,8 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Return the TIM One Pulse Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Return the TIM One Pulse Mode handle state.
+  * @param  htim TIM OPM handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -4389,371 +5527,382 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Return the TIM Encoder Mode state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Return the TIM Encoder Mode handle state.
+  * @param  htim TIM Encoder Interface handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
+
 /**
   * @}
   */
 
 /**
-  * @brief  Time Base configuration
-  * @param  TIMx: TIM peripheral
-  * @param  Structure: pointer on TIM Time Base required parameters  
+  * @}
+  */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA error callback
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tmpcr1 = 0;
-  tmpcr1 = TIMx->CR1;
-  
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)   
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
- 
-  if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)  
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
-  /* Set the Auto-reload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
- 
-  /* Set the Prescaler value */
-  TIMx->PSC = (uint32_t)Structure->Prescaler;
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)  
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = Structure->RepetitionCounter;
-  }
+  htim->State = HAL_TIM_STATE_READY;
 
-  /* Generate an update event to reload the Prescaler 
-     and the repetition counter(only for TIM1 and TIM8) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->ErrorCallback(htim);
+#else
+  HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge  
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
+  * @brief  TIM DMA Delay Pulse complete callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-  
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
-  /* Select the Input */
-  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
   {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  } 
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
   else
   {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+    /* nothing to do */
   }
 
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 }
 
 /**
-  * @brief  Time Output Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
+  * @brief  TIM DMA Delay Pulse half complete callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-   
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  
-  /* Get the TIMx CCER register value */  
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
   {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC2NP;
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 4);
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC2NE;
-    
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS2;
-    tmpcr2 &= ~TIM_CR2_OIS2N;
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 2);
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
   }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-  
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+  }
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+  {
+    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 }
 
 /**
-  * @brief  TIM DMA Delay Pulse complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
+  * @brief  TIM DMA Capture complete callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
 {
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY; 
-  
-  if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
   }
+  else
+  {
+    /* nothing to do */
+  }
 
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureCallback(htim);
+#else
+  HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;  
+  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 }
 
 /**
-  * @brief  TIM DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  TIM DMA Capture half complete callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_DMAError(DMA_HandleTypeDef *hdma)
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-   
-  HAL_TIM_ErrorCallback(htim);
-}
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
-/**
-  * @brief  TIM DMA Capture complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-  
-  if(hdma == htim->hdma[TIM_DMA_ID_CC1])
+  htim->State = HAL_TIM_STATE_READY;
+
+  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
   }
-  else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
+  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
   {
     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
   }
-  
-  HAL_TIM_IC_CaptureCallback(htim); 
-  
+  else
+  {
+    /* nothing to do */
+  }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->IC_CaptureHalfCpltCallback(htim);
+#else
+  HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 }
 
 /**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  *            @arg TIM_Channel_4: TIM Channel 4
-  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 
+  * @brief  TIM DMA Period Elapse complete callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
 {
-  uint32_t tmp = 0;
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 
-  assert_param(IS_TIM_CHANNELS(Channel));
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Period Elapse half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerCallback(htim);
+#else
+  HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  TIM DMA Trigger half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->TriggerHalfCpltCallback(htim);
+#else
+  HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Time Base configuration
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+    tmpcr1 |= Structure->CounterMode;
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 
-  tmp = TIM_CCER_CC1E << Channel;
+  TIMx->CR1 = tmpcr1;
 
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
 
-  /* Set or reset the CCxE Bit */ 
-  TIMx->CCER |= (uint32_t)(ChannelState << Channel);
-}
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
 
-/**
-  * @brief  TIM DMA Period Elapse complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-  
-  HAL_TIM_PeriodElapsedCallback(htim);
-}
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+  }
 
-/**
-  * @brief  TIM DMA Trigger callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;  
-  
-  htim->State= HAL_TIM_STATE_READY; 
-  
-  HAL_TIM_TriggerCallback(htim);
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
 }
 
 /**
-  * @brief  Time Output Compare 1 configuration
+  * @brief  Timer Output Compare 1 configuration
   * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 {
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;  
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
 
   /* Disable the Channel 1: Reset the CC1E Bit */
   TIMx->CCER &= ~TIM_CCER_CC1E;
-  
+
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
+  tmpcr2 =  TIMx->CR2;
+
   /* Get the TIMx CCMR1 register value */
   tmpccmrx = TIMx->CCMR1;
-    
+
   /* Reset the Output Compare Mode Bits */
   tmpccmrx &= ~TIM_CCMR1_OC1M;
   tmpccmrx &= ~TIM_CCMR1_CC1S;
   /* Select the Output Compare Mode */
   tmpccmrx |= OC_Config->OCMode;
-  
+
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC1P;
   /* Set the Output Compare Polarity */
   tmpccer |= OC_Config->OCPolarity;
 
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
-  {   
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC1NP;
     /* Set the Output N Polarity */
     tmpccer |= OC_Config->OCNPolarity;
     /* Reset the Output N State */
     tmpccer &= ~TIM_CCER_CC1NE;
-    
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
     /* Reset the Output Compare and Output Compare N IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS1;
     tmpcr2 &= ~TIM_CR2_OIS1N;
@@ -4762,159 +5911,244 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
     /* Set the Output N Idle state */
     tmpcr2 |= OC_Config->OCNIdleState;
   }
+
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
-  
+
   /* Write to TIMx CCMR1 */
   TIMx->CCMR1 = tmpccmrx;
-  
+
   /* Set the Capture Compare Register value */
   TIMx->CCR1 = OC_Config->Pulse;
-  
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Timer Output Compare 2 configuration
+  * @param  TIMx to select the TIM peripheral
+  * @param  OC_Config The ouput configuration structure
+  * @retval None
+  */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= ~TIM_CCMR1_OC2M;
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
+  /* Reset the Output Polarity level */
+  tmpccer &= ~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+  {
+    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+    /* Reset the Output N Polarity level */
+    tmpccer &= ~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+    /* Reset the Output N State */
+    tmpccer &= ~TIM_CCER_CC2NE;
+
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= ~TIM_CR2_OIS2;
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (OC_Config->OCIdleState << 2U);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+  }
+
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = OC_Config->Pulse;
+
   /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;  
-} 
+  TIMx->CCER = tmpccer;
+}
 
 /**
-  * @brief  Time Output Compare 3 configuration
+  * @brief  Timer Output Compare 3 configuration
   * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 {
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;   
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
 
   /* Disable the Channel 3: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC3E;
-  
+
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
+  tmpcr2 =  TIMx->CR2;
+
   /* Get the TIMx CCMR2 register value */
   tmpccmrx = TIMx->CCMR2;
-    
+
   /* Reset the Output Compare mode and Capture/Compare selection Bits */
   tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;  
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
   /* Select the Output Compare Mode */
   tmpccmrx |= OC_Config->OCMode;
-  
+
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC3P;
   /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8);
-    
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  tmpccer |= (OC_Config->OCPolarity << 8U);
+
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
   {
     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-    
+
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC3NP;
     /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 8);
+    tmpccer |= (OC_Config->OCNPolarity << 8U);
     /* Reset the Output N State */
     tmpccer &= ~TIM_CCER_CC3NE;
-    
+  }
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+  {
+    /* Check parameters */
+    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
     /* Reset the Output Compare and Output Compare N IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS3;
     tmpcr2 &= ~TIM_CR2_OIS3N;
     /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 4);
+    tmpcr2 |= (OC_Config->OCIdleState << 4U);
     /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 4);
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
   }
+
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
-  
+
   /* Write to TIMx CCMR2 */
   TIMx->CCMR2 = tmpccmrx;
-  
+
   /* Set the Capture Compare Register value */
   TIMx->CCR3 = OC_Config->Pulse;
-  
+
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
 }
 
 /**
-  * @brief  Time Output Compare 4 configuration
+  * @brief  Timer Output Compare 4 configuration
   * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The output configuration structure
+  * @param  OC_Config The ouput configuration structure
   * @retval None
   */
 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
 {
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
+  uint32_t tmpccmrx;
+  uint32_t tmpccer;
+  uint32_t tmpcr2;
 
   /* Disable the Channel 4: Reset the CC4E Bit */
   TIMx->CCER &= ~TIM_CCER_CC4E;
-  
+
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
-  tmpcr2 = TIMx->CR2;
-  
+  tmpcr2 =  TIMx->CR2;
+
   /* Get the TIMx CCMR2 register value */
   tmpccmrx = TIMx->CCMR2;
-    
+
   /* Reset the Output Compare mode and Capture/Compare selection Bits */
   tmpccmrx &= ~TIM_CCMR2_OC4M;
   tmpccmrx &= ~TIM_CCMR2_CC4S;
-  
+
   /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-  
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC4P;
   /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12);
-   
-  /*if((TIMx == TIM1) || (TIMx == TIM8))*/
-  if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
+  tmpccer |= (OC_Config->OCPolarity << 12U);
+
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
   {
+    /* Check parameters */
     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
     /* Reset the Output Compare IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS4;
+
     /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 6);
+    tmpcr2 |= (OC_Config->OCIdleState << 6U);
   }
+
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */  
+
+  /* Write to TIMx CCMR2 */
   TIMx->CCMR2 = tmpccmrx;
-    
+
   /* Set the Capture Compare Register value */
   TIMx->CCR4 = OC_Config->Pulse;
-  
+
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
 }
 
 /**
-  * @brief  Time Output Compare 4 configuration
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sSlaveConfig: The slave configuration structure
+  * @brief  Slave Timer configuration function
+  * @param  htim TIM handle
+  * @param  sSlaveConfig Slave timer configuration
   * @retval None
   */
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                              TIM_SlaveConfigTypeDef * sSlaveConfig)
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
+  uint32_t tmpsmcr;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
 
- /* Get the TIMx SMCR register value */
+  /* Get the TIMx SMCR register value */
   tmpsmcr = htim->Instance->SMCR;
 
   /* Reset the Trigger Selection Bits */
@@ -4929,48 +6163,52 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
 
   /* Write to TIMx SMCR */
   htim->Instance->SMCR = tmpsmcr;
-  
+
   /* Configure the trigger prescaler, filter, and polarity */
   switch (sSlaveConfig->InputTrigger)
   {
-  case TIM_TS_ETRF:
+    case TIM_TS_ETRF:
     {
       /* Check the parameters */
-      assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
+      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
       /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance, 
-                        sSlaveConfig->TriggerPrescaler, 
-                        sSlaveConfig->TriggerPolarity, 
+      TIM_ETR_SetConfig(htim->Instance,
+                        sSlaveConfig->TriggerPrescaler,
+                        sSlaveConfig->TriggerPolarity,
                         sSlaveConfig->TriggerFilter);
+      break;
     }
-    break;
-    
-  case TIM_TS_TI1F_ED:
+
+    case TIM_TS_TI1F_ED:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      
+
+      if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+      {
+        return HAL_ERROR;
+      }
+
       /* Disable the Channel 1: Reset the CC1E Bit */
       tmpccer = htim->Instance->CCER;
       htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;    
-      
+      tmpccmr1 = htim->Instance->CCMR1;
+
       /* Set the filter */
       tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-      
+      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
       /* Write to TIMx CCMR1 and CCER registers */
       htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;                               
-                               
+      htim->Instance->CCER = tmpccer;
+      break;
     }
-    break;
-    
-  case TIM_TS_TI1FP1:
+
+    case TIM_TS_TI1FP1:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -4981,87 +6219,124 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
       TIM_TI1_ConfigInputStage(htim->Instance,
                                sSlaveConfig->TriggerPolarity,
                                sSlaveConfig->TriggerFilter);
+      break;
     }
-    break;
-    
-  case TIM_TS_TI2FP2:
+
+    case TIM_TS_TI2FP2:
     {
       /* Check the parameters */
       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      
+
       /* Configure TI2 Filter and Polarity */
       TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-    
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-    
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+                               sSlaveConfig->TriggerPolarity,
+                               sSlaveConfig->TriggerFilter);
+      break;
     }
-    break;
-    
-  case TIM_TS_ITR3:
+
+    case TIM_TS_ITR0:
+    case TIM_TS_ITR1:
+    case TIM_TS_ITR2:
+    case TIM_TS_ITR3:
     {
       /* Check the parameter */
       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
     }
-    break;
-       
-  default:
-    break;
+
+    default:
+      break;
   }
+  return HAL_OK;
 }
 
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx to select the TIM peripheral.
+  * @param  TIM_ICPolarity The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
+  */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+                       uint32_t TIM_ICFilter)
+{
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input */
+  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+  {
+    tmpccmr1 &= ~TIM_CCMR1_CC1S;
+    tmpccmr1 |= TIM_ICSelection;
+  }
+  else
+  {
+    tmpccmr1 |= TIM_CCMR1_CC1S_0;
+  }
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
 
 /**
   * @brief  Configure the Polarity and Filter for TI1.
   * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   */
 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
 {
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-  
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
   /* Disable the Channel 1: Reset the CC1E Bit */
   tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;    
-  
+  tmpccmr1 = TIMx->CCMR1;
+
   /* Set the filter */
   tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4);
-  
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+
   /* Select the Polarity and set the CC1E Bit */
   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
   tmpccer |= TIM_ICPolarity;
-  
+
   /* Write to TIMx CCMR1 and CCER registers */
   TIMx->CCMR1 = tmpccmr1;
   TIMx->CCER = tmpccer;
@@ -5070,42 +6345,45 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
 /**
   * @brief  Configure the TI2 as Input.
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge   
-  * @param  TIM_ICSelection: specifies the input to be used.
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+  *        protected against un-initialized filter and polarity values.
   */
 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
+                              uint32_t TIM_ICFilter)
 {
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
 
   /* Disable the Channel 2: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC2E;
   tmpccmr1 = TIMx->CCMR1;
   tmpccer = TIMx->CCER;
-  
+
   /* Select the Input */
   tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8);
-  
+  tmpccmr1 |= (TIM_ICSelection << 8U);
+
   /* Set the filter */
   tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
 
   /* Select the Polarity and set the CC2E Bit */
   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
 
   /* Write to TIMx CCMR1 and CCER registers */
   TIMx->CCMR1 = tmpccmr1 ;
@@ -5115,32 +6393,32 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 /**
   * @brief  Configure the Polarity and Filter for TI2.
   * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
   */
 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
 {
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-  
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
   /* Disable the Channel 2: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC2E;
   tmpccmr1 = TIMx->CCMR1;
   tmpccer = TIMx->CCER;
-  
+
   /* Set the filter */
   tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12);
+  tmpccmr1 |= (TIM_ICFilter << 12U);
 
   /* Select the Polarity and set the CC2E Bit */
   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4);
+  tmpccer |= (TIM_ICPolarity << 4U);
 
   /* Write to TIMx CCMR1 and CCER registers */
   TIMx->CCMR1 = tmpccmr1 ;
@@ -5150,25 +6428,28 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
 /**
   * @brief  Configure the TI3 as Input.
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge         
-  * @param  TIM_ICSelection: specifies the input to be used.
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
   * @retval None
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
   */
 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
+                              uint32_t TIM_ICFilter)
 {
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
 
   /* Disable the Channel 3: Reset the CC3E Bit */
   TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5181,11 +6462,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 
   /* Set the filter */
   tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
 
   /* Select the Polarity and set the CC3E Bit */
   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
 
   /* Write to TIMx CCMR2 and CCER registers */
   TIMx->CCMR2 = tmpccmr2;
@@ -5195,25 +6476,28 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 /**
   * @brief  Configure the TI4 as Input.
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
+  * @param  TIM_ICPolarity The Input Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICPolarity_Rising
-  *            @arg TIM_ICPolarity_Falling
-  *            @arg TIM_ICPolarity_BothEdge     
-  * @param  TIM_ICSelection: specifies the input to be used.
+  *            @arg TIM_ICPOLARITY_RISING
+  *            @arg TIM_ICPOLARITY_FALLING
+  *            @arg TIM_ICPOLARITY_BOTHEDGE
+  * @param  TIM_ICSelection specifies the input to be used.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
   *          This parameter must be a value between 0x00 and 0x0F.
+  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+  *        protected against un-initialized filter and polarity values.
   * @retval None
   */
 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
+                              uint32_t TIM_ICFilter)
 {
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
+  uint32_t tmpccmr2;
+  uint32_t tmpccer;
 
   /* Disable the Channel 4: Reset the CC4E Bit */
   TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5222,15 +6506,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 
   /* Select the Input */
   tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8);
+  tmpccmr2 |= (TIM_ICSelection << 8U);
 
   /* Set the filter */
   tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
 
   /* Select the Polarity and set the CC4E Bit */
   tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
 
   /* Write to TIMx CCMR2 and CCER registers */
   TIMx->CCMR2 = tmpccmr2;
@@ -5240,7 +6524,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
 /**
   * @brief  Selects the Input Trigger source
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ITRx: The Input Trigger source.
+  * @param  InputTriggerSource The Input Trigger source.
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal Trigger 0
   *            @arg TIM_TS_ITR1: Internal Trigger 1
@@ -5252,41 +6536,40 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   *            @arg TIM_TS_ETRF: External Trigger input
   * @retval None
   */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
 {
-  uint32_t tmpsmcr = 0;
-  
-   /* Get the TIMx SMCR register value */
-   tmpsmcr = TIMx->SMCR;
-   /* Reset the TS Bits */
-   tmpsmcr &= ~TIM_SMCR_TS;
-   /* Set the Input Trigger source and the slave mode*/
-   tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
-   /* Write to TIMx SMCR */
-   TIMx->SMCR = tmpsmcr;
-}
+  uint32_t tmpsmcr;
 
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
 /**
   * @brief  Configures the TIMx External Trigger (ETR).
   * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
-  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.
   *          This parameter can be one of the following values:
-  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
+  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+  * @param  ExtTRGFilter External Trigger Filter.
   *          This parameter must be a value between 0x00 and 0x0F
   * @retval None
   */
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
 {
-  uint32_t tmpsmcr = 0;
+  uint32_t tmpsmcr;
 
   tmpsmcr = TIMx->SMCR;
 
@@ -5294,11 +6577,67 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 
   /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 
   /* Write to TIMx SMCR */
   TIMx->SMCR = tmpsmcr;
-} 
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx to select the TIM peripheral
+  * @param  Channel specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  *            @arg TIM_CHANNEL_4: TIM Channel 4
+  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+  * @retval None
+  */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+  assert_param(IS_TIM_CHANNELS(Channel));
+
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= ~tmp;
+
+  /* Set or reset the CCxE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
+  * @param  htim pointer to a TIM_HandleTypeDef structure that contains
+  *                the configuration information for TIM module.
+  * @retval None
+  */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+  /* Reset the TIM callback to the legacy weak callbacks */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -5307,9 +6646,9 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
 #endif /* HAL_TIM_MODULE_ENABLED */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c
index 133c7f87..9e5e0c05 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c
@@ -2,99 +2,77 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Timer extension peripheral:
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Timer Extended peripheral:
   *           + Time Hall Sensor Interface Initialization
   *           + Time Hall Sensor Interface Start
-  *           + Time Complementary signal bread and dead time configuration  
+  *           + Time Complementary signal break and dead time configuration
   *           + Time Master and Slave synchronization configuration
-  @verbatim 
+  *           + Timer remapping capabilities configuration
+  @verbatim
   ==============================================================================
                       ##### TIMER Extended features #####
   ==============================================================================
-  [..] 
-    The Timer Extension features include: 
+  [..]
+    The Timer Extended features include:
     (#) Complementary outputs with programmable dead-time for :
-        (++) Input Capture
         (++) Output Compare
         (++) PWM generation (Edge and Center-aligned Mode)
         (++) One-pulse mode output
-    (#) Synchronization circuit to control the timer with external signals and to 
+    (#) Synchronization circuit to control the timer with external signals and to
         interconnect several timers together.
     (#) Break input to put the timer output signals in reset state or in a known state.
-    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for 
-        positioning purposes                
-   
-                        ##### How to use this driver #####
+    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+        positioning purposes
+
+            ##### How to use this driver #####
   ==============================================================================
-  [..]
-     (#) Initialize the TIM low level resources by implementing the following functions 
-         depending from feature used :
-           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
-           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
-           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
-           
+    [..]
+     (#) Initialize the TIM low level resources by implementing the following functions
+         depending on the selected feature:
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
      (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); 
+        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
         (##) TIM pins configuration
             (+++) Enable the clock for the TIM GPIOs using the following function:
-                 __GPIOx_CLK_ENABLE();   
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();  
+              __HAL_RCC_GPIOx_CLK_ENABLE();
+            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
 
-     (#) The external Clock can be configured, if needed (the default clock is the 
+     (#) The external Clock can be configured, if needed (the default clock is the
          internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before 
+         HAL_TIM_ConfigClockSource, the clock configuration should be done before
          any start function.
-  
-    (#) Configure the TIM in the desired functioning mode using one of the 
-        initialization function of this driver:
-        (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the 
-             Timer Hall Sensor Interface and the commutation event with the corresponding 
-             Interrupt and DMA request if needed (Note that One Timer is used to interface 
-             with the Hall sensor Interface and another Timer should be used to use 
-             the commutation event).
-
-    (#) Activate the TIM peripheral using one of the start functions: 
+
+     (#) Configure the TIM in the desired functioning mode using one of the
+         initialization function of this driver:
+          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+               Timer Hall Sensor Interface and the commutation event with the corresponding
+               Interrupt and DMA request if needed (Note that One Timer is used to interface
+               with the Hall sensor Interface and another Timer should be used to use
+               the commutation event).
+
+     (#) Activate the TIM peripheral using one of the start functions:
            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
 
-  
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -103,8 +81,8 @@
   * @{
   */
 
-/** @defgroup TIMEx  TIMEx
-  * @brief TIM HAL module driver
+/** @defgroup TIMEx TIMEx
+  * @brief TIM Extended HAL module driver
   * @{
   */
 
@@ -114,30 +92,24 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions
-  * @{
-  */
 /* Private function prototypes -----------------------------------------------*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/**
-  * @}
-  */
-      
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Functions TIM Exported Functions
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
   * @{
   */
 
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions 
- *  @brief    Timer Hall Sensor functions 
- *
-@verbatim    
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+  * @brief    Timer Hall Sensor functions
+  *
+@verbatim
   ==============================================================================
                       ##### Timer Hall Sensor functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Initialize and configure TIM HAL Sensor. 
+    (+) Initialize and configure TIM HAL Sensor.
     (+) De-initialize TIM HAL Sensor.
     (+) Start the Hall Sensor Interface.
     (+) Stop the Hall Sensor Interface.
@@ -145,62 +117,81 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
     (+) Stop the Hall Sensor Interface and disable interrupts.
     (+) Start the Hall Sensor Interface and enable DMA transfers.
     (+) Stop the Hall Sensor Interface and disable DMA transfers.
- 
+
 @endverbatim
   * @{
   */
 /**
-  * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sConfig: TIM Hall Sensor configuration structure
+  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  sConfig TIM Hall Sensor configuration structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
 {
   TIM_OC_InitTypeDef OC_Config;
-    
+
   /* Check the TIM handle allocation */
-  if(htim == NULL)
+  if (htim == NULL)
   {
     return HAL_ERROR;
   }
-  
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+
+  /* Check the parameters */
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
 
+  if (htim->State == HAL_TIM_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+    /* Reset interrupt callbacks to legacy week callbacks */
+    TIM_ResetCallback(htim);
+
+    if (htim->HallSensor_MspInitCallback == NULL)
+    {
+      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->HallSensor_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+    HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
   /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-  HAL_TIMEx_HallSensor_MspInit(htim);
-  
+  htim->State = HAL_TIM_STATE_BUSY;
+
   /* Configure the Time base in the Encoder Mode */
   TIM_Base_SetConfig(htim->Instance, &htim->Init);
-  
+
   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-  
+
   /* Reset the IC1PSC Bits */
   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
   /* Set the IC1PSC value */
   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-  
+
   /* Enable the Hall sensor interface (XOR function of the three inputs) */
   htim->Instance->CR2 |= TIM_CR2_TI1S;
-  
+
   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
   htim->Instance->SMCR &= ~TIM_SMCR_TS;
   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-  
-  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */  
+
+  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-  
+
   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
@@ -208,25 +199,24 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
-  OC_Config.Pulse = sConfig->Commutation_Delay; 
-    
+  OC_Config.Pulse = sConfig->Commutation_Delay;
+
   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-  
+
   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
     register to 101 */
   htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  htim->Instance->CR2 |= TIM_TRGO_OC2REF; 
-  
+  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
   /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
+  htim->State = HAL_TIM_STATE_READY;
 
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the TIM Hall Sensor interface  
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  DeInitializes the TIM Hall Sensor interface
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -235,15 +225,24 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
 
   htim->State = HAL_TIM_STATE_BUSY;
-  
+
   /* Disable the TIM Peripheral Clock */
   __HAL_TIM_DISABLE(htim);
-    
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  if (htim->HallSensor_MspDeInitCallback == NULL)
+  {
+    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  htim->HallSensor_MspDeInitCallback(htim);
+#else
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   HAL_TIMEx_HallSensor_MspDeInit(htim);
-    
-  /* Change TIM state */  
-  htim->State = HAL_TIM_STATE_RESET; 
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+  /* Change TIM state */
+  htim->State = HAL_TIM_STATE_RESET;
 
   /* Release Lock */
   __HAL_UNLOCK(htim);
@@ -253,211 +252,236 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
 
 /**
   * @brief  Initializes the TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval None
   */
 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  DeInitializes TIM Hall Sensor MSP.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval None
   */
 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
    */
 }
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Hall sensor Interface.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
   /* Disable the Input Capture channels 1, 2 and 3
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
 
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{ 
+{
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
   /* Enable the capture compare Interrupts 1 event */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);  
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
-  
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
   /* Disable the capture compare Interrupts event */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
+  * @param  htim TIM Hall Sensor Interface handle
+  * @param  pData The destination Buffer address.
+  * @param  Length The length of data to be transferred from TIM peripheral to memory.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-   if((htim->State == HAL_TIM_STATE_BUSY))
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    if (((uint32_t)pData == 0U) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
   }
-  /* Enable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 
-  
-  /* Set the DMA Input Capture 1 Callback */
-  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;     
+  else
+  {
+    /* nothing to do */
+  }
+  /* Enable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+  /* Set the DMA Input Capture 1 Callbacks */
+  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
   /* Set the DMA error callback */
   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-  
-  /* Enable the DMA Stream for Capture 1*/
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);    
-  
+
+  /* Enable the DMA stream for Capture 1*/
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
   /* Enable the capture compare 1 Interrupt */
   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @param  htim TIM Hall Sensor Interface handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  
-  /* Disable the Input Capture channels 1
-    (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */  
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 
- 
-  
+  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+  /* Disable the Input Capture channel 1
+    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
   /* Disable the capture compare Interrupts 1 event */
   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- 
+
+  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- *  @brief    Timer Complementary Output Compare functions 
- *
-@verbatim   
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+  *  @brief   Timer Complementary Output Compare functions
+  *
+@verbatim
   ==============================================================================
               ##### Timer Complementary Output Compare functions #####
-  ==============================================================================  
-  [..]  
+  ==============================================================================
+  [..]
     This section provides functions allowing to:
     (+) Start the Complementary Output Compare/PWM.
     (+) Stop the Complementary Output Compare/PWM.
@@ -465,409 +489,399 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-               
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Starts the TIM Output Compare signal generation on the complementary
   *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.  
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-     /* Enable the Capture compare channel N */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-    
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Enable the Capture compare channel N */
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
   /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
 
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Stops the TIM Output Compare signal generation on the complementary
   *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
+{
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-    /* Disable the Capture compare channel N */
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  /* Disable the Capture compare channel N */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-    
+
   /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+  __HAL_TIM_MOE_DISABLE(htim);
 
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode 
+  * @brief  Starts the TIM Output Compare signal generation in interrupt mode
   *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM OC handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Enable the TIM Output Compare interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Enable the TIM Output Compare interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Enable the TIM Output Compare interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Output Compare interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
+
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Enable the TIM Break interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-  
+
   /* Enable the Capture compare channel N */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode 
+  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
   *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpccer;
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Output Compare interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Output Compare interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Output Compare interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
+
     default:
-    break; 
+      break;
   }
-  
+
   /* Disable the Capture compare channel N */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
 
   /* Disable the TIM Break interrupt (only if no more channel is active) */
-  if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
   {
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
   }
-  
+
   /* Disable the Main Output */
   __HAL_TIM_MOE_DISABLE(htim);
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode 
+  * @brief  Starts the TIM Output Compare signal generation in DMA mode
   *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    if (((uint32_t)pData == 0U) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }    
+  }
+  else
+  {
+    /* nothing to do  */
+  }
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Output Compare DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Output Compare DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
-{
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Output Compare DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Output Compare DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Enable the Capture compare channel N */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode 
+  * @brief  Stops the TIM Output Compare signal generation in DMA mode
   *         on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM Output Compare handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Output Compare DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Output Compare DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Output Compare DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Output Compare interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Disable the Capture compare channel N */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-  
+
   /* Disable the Main Output */
   __HAL_TIM_MOE_DISABLE(htim);
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- *  @brief    Timer Complementary PWM functions 
- *
-@verbatim   
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+  * @brief    Timer Complementary PWM functions
+  *
+@verbatim
   ==============================================================================
                  ##### Timer Complementary PWM functions #####
-  ==============================================================================  
-  [..]  
+  ==============================================================================
+  [..]
     This section provides functions allowing to:
     (+) Start the Complementary PWM.
     (+) Stop the Complementary PWM.
@@ -885,324 +899,318 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
     (+) Stop the Complementary One Pulse.
     (+) Start the Complementary One Pulse and enable interrupts.
     (+) Stop the Complementary One Pulse and disable interrupts.
-               
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Starts the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   /* Enable the complementary PWM output  */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
   * @brief  Stops the PWM signal generation on the complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{ 
+{
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);  
-  
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
   /* Disable the Main Output */
   __HAL_TIM_MOE_DISABLE(htim);
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Starts the PWM signal generation in interrupt mode on the 
+  * @brief  Starts the PWM signal generation in interrupt mode on the
   *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Enable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Enable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Enable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Enable the TIM Break interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-  
+
   /* Enable the complementary PWM output  */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-  
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-  
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Stops the PWM signal generation in interrupt mode on the 
+  * @brief  Stops the PWM signal generation in interrupt mode on the
   *         complementary output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  uint32_t tmpccer;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 interrupt */
       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-    
+
     default:
-    break; 
+      break;
   }
-  
+
   /* Disable the complementary PWM output  */
   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-  
+
   /* Disable the TIM Break interrupt (only if no more channel is active) */
-  if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+  tmpccer = htim->Instance->CCER;
+  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
   {
     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
   }
-  
+
   /* Disable the Main Output */
   __HAL_TIM_MOE_DISABLE(htim);
-  
+
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-} 
+}
 
 /**
-  * @brief  Starts the TIM PWM signal generation in DMA mode on the 
+  * @brief  Starts the TIM PWM signal generation in DMA mode on the
   *         complementary output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be enabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
-  if((htim->State == HAL_TIM_STATE_BUSY))
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+  if (htim->State == HAL_TIM_STATE_BUSY)
   {
-     return HAL_BUSY;
+    return HAL_BUSY;
   }
-  else if((htim->State == HAL_TIM_STATE_READY))
+  else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if(((uint32_t)pData == 0 ) && (Length > 0)) 
+    if (((uint32_t)pData == 0U) && (Length > 0U))
     {
-      return HAL_ERROR;                                    
+      return HAL_ERROR;
     }
     else
     {
       htim->State = HAL_TIM_STATE_BUSY;
     }
-  }    
+  }
+  else
+  {
+    /* nothing to do */
+  }
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {      
-      /* Set the DMA Period elapsed callback */
+    {
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
-      /* Set the DMA Period elapsed callback */
+      /* Set the DMA compare callbacks */
       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
+      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-      
+
+      /* Enable the DMA stream */
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      {
+        return HAL_ERROR;
+      }
       /* Enable the TIM Capture/Compare 3 DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-     
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-      
-      /* Enable the DMA Stream */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-      
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
+
     default:
-    break;
+      break;
   }
 
   /* Enable the complementary PWM output  */
-     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-    
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
   /* Enable the Main Output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim); 
-  
+  __HAL_TIM_MOE_ENABLE(htim);
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+  {
+    __HAL_TIM_ENABLE(htim);
+  }
+
   /* Return function status */
   return HAL_OK;
 }
@@ -1210,67 +1218,61 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
 /**
   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
   *         output
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Channel: TIM Channel to be disabled.
+  * @param  htim TIM handle
+  * @param  Channel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
-    {       
+    {
       /* Disable the TIM Capture/Compare 1 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_2:
     {
       /* Disable the TIM Capture/Compare 2 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+      break;
     }
-    break;
-    
+
     case TIM_CHANNEL_3:
     {
       /* Disable the TIM Capture/Compare 3 DMA request */
       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+      break;
     }
-    break;
-    
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-    
+
     default:
-    break;
-  } 
-  
+      break;
+  }
+
   /* Disable the complementary PWM output */
-    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-     
+  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
   /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+  __HAL_TIM_MOE_DISABLE(htim);
 
   /* Disable the Peripheral */
   __HAL_TIM_DISABLE(htim);
-  
+
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -1278,57 +1280,55 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
 /**
   * @}
   */
-  
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- *  @brief    Timer Complementary One Pulse functions 
- *
-@verbatim   
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+  * @brief    Timer Complementary One Pulse functions
+  *
+@verbatim
   ==============================================================================
                 ##### Timer Complementary One Pulse functions #####
-  ==============================================================================  
-  [..]  
+  ==============================================================================
+  [..]
     This section provides functions allowing to:
     (+) Start the Complementary One Pulse generation.
     (+) Stop the Complementary One Pulse.
     (+) Start the Complementary One Pulse and enable interrupts.
     (+) Stop the Complementary One Pulse and disable interrupts.
-               
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Starts the TIM One Pulse signal generation on the complementary 
+  * @brief  Starts the TIM One Pulse signal generation on the complementary
   *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-  {
+{
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
-  
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
   /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
-  
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Stops the TIM One Pulse signal generation on the complementary 
+  * @brief  Stops the TIM One Pulse signal generation on the complementary
   *         output.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1338,17 +1338,17 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
 {
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
   /* Disable the complementary One Pulse output */
-    TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-  
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
   /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
-  
+  __HAL_TIM_MOE_DISABLE(htim);
+
   /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim); 
-   
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
@@ -1356,9 +1356,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
 /**
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be enabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be enabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1367,30 +1366,29 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
   /* Enable the TIM Capture/Compare 1 interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-  
+
   /* Enable the TIM Capture/Compare 2 interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-  
+
   /* Enable the complementary One Pulse output */
-  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); 
-  
+  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
   /* Enable the Main Output */
   __HAL_TIM_MOE_ENABLE(htim);
-  
+
   /* Return function status */
   return HAL_OK;
-  } 
-  
+}
+
 /**
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  OutputChannel: TIM Channel to be disabled.
+  * @param  htim TIM One Pulse handle
+  * @param  OutputChannel TIM Channel to be disabled
   *          This parameter can be one of the following values:
   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1399,343 +1397,383 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); 
+  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
   /* Disable the TIM Capture/Compare 1 interrupt */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  
+
   /* Disable the TIM Capture/Compare 2 interrupt */
   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  
+
   /* Disable the complementary One Pulse output */
   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-  
+
   /* Disable the Main Output */
   __HAL_TIM_MOE_DISABLE(htim);
-  
+
   /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);  
-  
+  __HAL_TIM_DISABLE(htim);
+
   /* Return function status */
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- *  @brief   	Peripheral Control functions 
- *
-@verbatim   
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
   ==============================================================================
                     ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]  
+  ==============================================================================
+  [..]
     This section provides functions allowing to:
-    (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 
-    (+) Configure External Clock source.
-    (+) Configure Complementary channels, break features and dead time.
-    (+) Configure Master and the Slave synchronization.
-    (+) Configure the commutation event in case of use of the Hall sensor interface.
-    (+) Configure the DMA Burst Mode.
-      
+      (+) Configure the commutation event in case of use of the Hall sensor interface.
+      (+) Configure Output channels for OC and PWM mode.
+
+      (+) Configure Complementary channels, break features and dead time.
+      (+) Configure Master synchronization.
+      (+) Configure timer remapping capabilities.
+
 @endverbatim
   * @{
   */
+
 /**
   * @brief  Configure the TIM commutation event sequence.
-  * @note  This function is mandatory to use the commutation event in order to 
+  * @note  This function is mandatory to use the commutation event in order to
   *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_NONE: No trigger is needed  
-  * @param  CommutationSource: the Commutation Event source.
+  *            @arg TIM_TS_NONE: No trigger is needed
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                              uint32_t  CommutationSource)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
+
   __HAL_LOCK(htim);
-  
+
   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
+  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
   }
-    
+
   /* Select the Capture Compare preload feature */
   htim->Instance->CR2 |= TIM_CR2_CCPC;
   /* Select the Commutation event source */
   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
   htim->Instance->CR2 |= CommutationSource;
-    
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Configure the TIM commutation event sequence with interrupt.
-  * @note  This function is mandatory to use the commutation event in order to 
+  * @note  This function is mandatory to use the commutation event in order to
   *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
   *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                 uint32_t  CommutationSource)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
+
   __HAL_LOCK(htim);
-  
+
   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
+  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
   }
-  
+
   /* Select the Capture Compare preload feature */
   htim->Instance->CR2 |= TIM_CR2_CCPC;
   /* Select the Commutation event source */
   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
   htim->Instance->CR2 |= CommutationSource;
-    
-  /* Enable the Commutation Interrupt Request */
+
+  /* Disable Commutation DMA request */
+  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+  /* Enable the Commutation Interrupt */
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
 
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Configure the TIM commutation event sequence with DMA.
-  * @note  This function is mandatory to use the commutation event in order to 
+  * @note  This function is mandatory to use the commutation event in order to
   *        update the configuration at each commutation detection on the TRGI input of the Timer,
-  *        the typical use of this feature is with the use of another Timer(interface Timer) 
-  *        configured in Hall sensor interface, this interface Timer will generate the 
-  *        commutation at its TRGO output (connected to Timer used in this function) each time 
+  *        the typical use of this feature is with the use of another Timer(interface Timer)
+  *        configured in Hall sensor interface, this interface Timer will generate the
+  *        commutation at its TRGO output (connected to Timer used in this function) each time
   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
-  * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
+  * @param  htim TIM handle
+  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
   *          This parameter can be one of the following values:
   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
   *            @arg TIM_TS_NONE: No trigger is needed
-  * @param  CommutationSource: the Commutation Event source.
+  * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
+                                                  uint32_t  CommutationSource)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-  
+
   __HAL_LOCK(htim);
-  
+
   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
-  {    
+  {
     /* Select the Input trigger */
     htim->Instance->SMCR &= ~TIM_SMCR_TS;
     htim->Instance->SMCR |= InputTrigger;
   }
-  
+
   /* Select the Capture Compare preload feature */
   htim->Instance->CR2 |= TIM_CR2_CCPC;
   /* Select the Commutation event source */
   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
   htim->Instance->CR2 |= CommutationSource;
-  
+
   /* Enable the Commutation DMA Request */
   /* Set the DMA Commutation Callback */
-  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;     
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
   /* Set the DMA error callback */
   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
-  
+
+  /* Disable Commutation Interrupt */
+  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
   /* Enable the Commutation DMA Request */
   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
 
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Configures the TIM in master mode.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.   
-  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave 
-  *         mode. 
+  * @param  htim TIM handle.
+  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+  *         contains the selected trigger output (TRGO) and the Master/Slave
+  *         mode.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        TIM_MasterConfigTypeDef *sMasterConfig)
 {
+  uint32_t tmpcr2;
+  uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-  
+
+  /* Check input state */
   __HAL_LOCK(htim);
-  
+
+  /* Change the handler state */
   htim->State = HAL_TIM_STATE_BUSY;
 
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+
   /* Reset the MMS Bits */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
+  tmpcr2 &= ~TIM_CR2_MMS;
   /* Select the TRGO source */
-  htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 
   /* Reset the MSM Bit */
-  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
-  /* Set or Reset the MSM Bit */
-  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-  
+  tmpsmcr &= ~TIM_SMCR_MSM;
+  /* Set master mode */
+  tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+
+  /* Update TIMx SMCR */
+  htim->Instance->SMCR = tmpsmcr;
+
+  /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
-  
+
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
-} 
-                                                     
+}
+
 /**
-  * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
   *         and the AOE(automatic output enable).
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
-  *         contains the BDTR Register configuration  information for the TIM peripheral. 
+  * @param  htim TIM handle
+  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @note   Interrupts can be generated when an active level is detected on the
+  *         break input, the break 2 input or the system break input. Break
+  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
   * @retval HAL status
-  */    
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 
-                                              TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+  */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
 {
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+  uint32_t tmpbdtr = 0U;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
-  
-  /* Process Locked */
+
+  /* Check input state */
   __HAL_LOCK(htim);
-  
-  htim->State = HAL_TIM_STATE_BUSY;
 
   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
      the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode  | 
-                                   sBreakDeadTimeConfig->OffStateIDLEMode |
-                                   sBreakDeadTimeConfig->LockLevel        |
-                                   sBreakDeadTimeConfig->DeadTime         |
-                                   sBreakDeadTimeConfig->BreakState       |
-                                   sBreakDeadTimeConfig->BreakPolarity    |
-                                   sBreakDeadTimeConfig->AutomaticOutput;
-  
-                                   
-  htim->State = HAL_TIM_STATE_READY;                                 
-  
+
+  /* Set the BDTR bits */
+  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+
+  /* Set TIMx_BDTR */
+  htim->Instance->BDTR = tmpbdtr;
+
   __HAL_UNLOCK(htim);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
-  * @param  Remap: specifies the TIM input remapping source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
-  *            @arg TIM_TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trigger output.
-  *            @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. 
-  *            @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. 
-  *            @arg TIM_TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
-  *            @arg TIM_TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
-  *            @arg TIM_TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
-  *            @arg TIM_TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
-  *            @arg TIM_TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
-  *            @arg TIM_TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
-  *                                     (HSE divided by a programmable prescaler)  
+  * @brief  Configures the TIMx Remapping input capabilities.
+  * @param  htim TIM handle.
+  * @param  Remap specifies the TIM remapping source.
+  *         For TIM2, the parameter can have the following values:
+  *           @arg TIM_TIM2_TIM8_TRGO:  TIM2 ITR1 is connected to TIM8 TRGO
+  *           @arg TIM_TIM2_ETH_PTP:    TIM2 ITR1 is connected to PTP trigger output
+  *           @arg TIM_TIM2_USBFS_SOF:  TIM2 ITR1 is connected to OTG FS SOF
+  *           @arg TIM_TIM2_USBHS_SOF:  TIM2 ITR1 is connected to OTG FS SOF
+  *
+  *         For TIM5, the parameter can have the following values:
+  *           @arg TIM_TIM5_GPIO:       TIM5 TI4 is connected to GPIO
+  *           @arg TIM_TIM5_LSI:        TIM5 TI4 is connected to LSI
+  *           @arg TIM_TIM5_LSE:        TIM5 TI4 is connected to LSE
+  *           @arg TIM_TIM5_RTC:        TIM5 TI4 is connected to the RTC wakeup interrupt
+  *
+  *         For TIM11, the parameter can have the following values:
+  *           @arg TIM_TIM11_GPIO:     TIM11 TI1 is connected to GPIO
+  *           @arg TIM_TIM11_HSE:      TIM11 TI1 is connected to HSE_RTC clock
+  *
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
 {
   __HAL_LOCK(htim);
-    
+
   /* Check parameters */
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_REMAP(Remap));
-  
+  assert_param(IS_TIM_REMAP(htim->Instance, Remap));
+
   /* Set the Timer remapping configuration */
-  htim->Instance->OR = Remap;
-  
-  htim->State = HAL_TIM_STATE_READY;
-  
-  __HAL_UNLOCK(htim);  
-  
+  WRITE_REG(htim->Instance->OR, Remap);
+
+  __HAL_UNLOCK(htim);
+
   return HAL_OK;
 }
+
 /**
   * @}
   */
 
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions 
- *  @brief   Extension Callbacks functions 
- *
-@verbatim   
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+  * @brief    Extended Callbacks functions
+  *
+@verbatim
   ==============================================================================
-                    ##### Extension Callbacks functions #####
-  ==============================================================================  
-  [..]  
-    This section provides Extension TIM callback functions:
+                    ##### Extended Callbacks functions #####
+  ==============================================================================
+  [..]
+    This section provides Extended TIM callback functions:
     (+) Timer Commutation callback
     (+) Timer Break callback
 
@@ -1744,27 +1782,45 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
   */
 
 /**
-  * @brief  Hall commutation changed callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Hall commutation changed callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+/**
+  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @param  htim TIM handle
   * @retval None
   */
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_CommutationCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
-  * @brief  Hall Break detection callback in non blocking mode 
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Hall Break detection callback in non-blocking mode
+  * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
 {
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_TIMEx_BreakCallback could be implemented in the user file
    */
 }
@@ -1772,15 +1828,15 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
   * @}
   */
 
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions 
- *  @brief   Extension Peripheral State functions 
- *
-@verbatim   
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+  * @brief    Extended Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+                ##### Extended Peripheral State functions #####
   ==============================================================================
-                ##### Extension Peripheral State functions #####
-  ==============================================================================  
   [..]
-    This subsection permits to get in run-time the status of the peripheral 
+    This subsection permits to get in run-time the status of the peripheral
     and the data flow.
 
 @endverbatim
@@ -1788,9 +1844,8 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
   */
 
 /**
-  * @brief  Return the TIM Hall Sensor interface state
-  * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
-  *                the configuration information for TIM module.
+  * @brief  Return the TIM Hall Sensor interface handle state.
+  * @param  htim TIM Hall Sensor handle
   * @retval HAL state
   */
 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -1803,52 +1858,77 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
   */
 
 /**
-  * @brief  TIM DMA Commutation callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+  * @{
+  */
+
+/**
+  * @brief  TIM DMA Commutation callback.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
 {
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  htim->State= HAL_TIM_STATE_READY;
-    
-  HAL_TIMEx_CommutationCallback(htim); 
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationCallback(htim);
+#else
+  HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 }
+
 /**
-  * @}
+  * @brief  TIM DMA Commutation half complete callback.
+  * @param  hdma pointer to DMA handle.
+  * @retval None
   */
-  
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+  htim->CommutationHalfCpltCallback(htim);
+#else
+  HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
 /**
   * @brief  Enables or disables the TIM Capture Compare Channel xN.
   * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
+  * @param  Channel specifies the TIM Channel
   *          This parameter can be one of the following values:
-  *            @arg TIM_Channel_1: TIM Channel 1
-  *            @arg TIM_Channel_2: TIM Channel 2
-  *            @arg TIM_Channel_3: TIM Channel 3
-  * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
-  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. 
+  *            @arg TIM_CHANNEL_1: TIM Channel 1
+  *            @arg TIM_CHANNEL_2: TIM Channel 2
+  *            @arg TIM_CHANNEL_3: TIM Channel 3
+  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
   * @retval None
   */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
 {
-  uint32_t tmp = 0;
+  uint32_t tmp;
 
-  /* Check the parameters */
-  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
-
-  tmp = TIM_CCER_CC1NE << Channel;
+  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
 
   /* Reset the CCxNE Bit */
-  TIMx->CCER &= ~tmp;
+  TIMx->CCER &=  ~tmp;
 
-  /* Set or reset the CCxNE Bit */ 
-  TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+  /* Set or reset the CCxNE Bit */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
 }
-
 /**
   * @}
   */
@@ -1856,9 +1936,10 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
 #endif /* HAL_TIM_MODULE_ENABLED */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c
index 77e739a7..d064c6f2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c
@@ -2,30 +2,26 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions  
-  *           + Peripheral State and Errors functions  
-  *           
-  @verbatim       
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
   ==============================================================================
   [..]
     The UART HAL driver can be used as follows:
-    
-    (#) Declare a UART_HandleTypeDef handle structure.
-  
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
         (##) Enable the USARTx interface clock.
         (##) UART pins configuration:
             (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
+            (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input).
         (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
              and HAL_UART_Receive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
@@ -34,124 +30,190 @@
              and HAL_UART_Receive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx stream.
             (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required 
-                  Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx Stream.
+            (+++) Configure the declared DMA handle structure with the required
+                  Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx stream.
             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete 
-                  interrupt on the DMA Tx/Rx Stream.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx stream.
+            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+                  (used for last byte sending completion detection in DMA non circular mode)
 
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
-        flow control and Mode(Receiver/Transmitter) in the Init structure.
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
 
     (#) For the UART asynchronous mode, initialize the UART registers by calling
         the HAL_UART_Init() API.
-    
-    (#) For the UART Half duplex mode, initialize the UART registers by calling 
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
         the HAL_HalfDuplex_Init() API.
-    
+
     (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-    
-    (#) For the Multi-Processor mode, initialize the UART registers by calling 
+
+    (#) For the Multi-Processor mode, initialize the UART registers by calling
         the HAL_MultiProcessor_Init() API.
-        
-     [..] 
-       (@) The specific UART interrupts (Transmission complete interrupt, 
+
+     [..]
+       (@) The specific UART interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit 
+            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
             and receive process.
-          
-     [..] 
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the 
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized 
+
+     [..]
+       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
             HAL_UART_MspInit() API.
-          
-     [..] 
-        Three operation modes are available within this driver :     
-  
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+    or @ref HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+     [..]
+        Three operation modes are available within this driver :
+
      *** Polling mode IO operation ***
      =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit() 
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
        (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-       
-     *** Interrupt mode IO operation ***    
+
+     *** Interrupt mode IO operation ***
      ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
+       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_UART_ErrorCallback
 
-     *** DMA mode IO operation ***    
+     *** DMA mode IO operation ***
      ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()      
-    
+       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
      *** UART HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in UART HAL driver.
-       
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral 
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral     
+
+      (+) __HAL_UART_ENABLE: Enable the UART peripheral
+      (+) __HAL_UART_DISABLE: Disable the UART peripheral
       (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
       (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
       (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
       (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
       (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-      
-     [..] 
-       (@) You can refer to the UART HAL driver header file for more useful macros 
-      
+
+     [..]
+       (@) You can refer to the UART HAL driver header file for more useful macros
+
   @endverbatim
+     [..]
+       (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           the possible UART frame formats are as listed in the following table:
+    +-------------------------------------------------------------+
+    |   M bit |  PCE bit  |            UART frame                 |
+    |---------------------|---------------------------------------|
+    |    0    |    0      |    | SB | 8 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|-----------|---------------------------------------|
+    |    1    |    0      |    | SB | 9 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    +-------------------------------------------------------------+
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -165,32 +227,43 @@
   * @{
   */
 #ifdef HAL_UART_MODULE_ENABLED
-    
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @addtogroup UART_Private_Constants
   * @{
   */
-#define UART_TIMEOUT_VALUE  22000
 /**
   * @}
   */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions   UART Private Functions
+/** @addtogroup UART_Private_Functions  UART Private Functions
   * @{
   */
-static void UART_SetConfig (UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig(UART_HandleTypeDef *huart);
+
 /**
   * @}
   */
@@ -200,31 +273,31 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
   * @{
   */
 
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-@verbatim    
-===============================================================================
+@verbatim
+ ===============================================================================
             ##### Initialization and Configuration functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
     in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured: 
+      (+) For the asynchronous mode only these parameters can be configured:
         (++) Baud Rate
-        (++) Word Length 
+        (++) Word Length
         (++) Stop Bit
         (++) Parity: If the parity is enabled, then the MSB bit of the data written
              in the data register is transmitted but is changed by the parity bit.
              Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible UART frame formats.           
+             please refer to Reference manual for possible UART frame formats.
         (++) Hardware flow control
         (++) Receiver/transmitter modes
         (++) Over Sampling Method
     [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs 
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
-    configuration procedures (details for the procedures are available in reference manual (RM0329)).
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
+    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
+    procedures (details for the procedures are available in reference manual (RM0033)).
 
 @endverbatim
   * @{
@@ -233,21 +306,21 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
 /**
   * @brief  Initializes the UART mode according to the specified parameters in
   *         the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
 {
   /* Check the UART handle allocation */
-  if(huart == NULL)
+  if (huart == NULL)
   {
     return HAL_ERROR;
   }
 
   /* Check the parameters */
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  { 
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
     /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
     assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
@@ -258,100 +331,128 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
   }
   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-  
-  if(huart->State == HAL_UART_STATE_RESET)
-  {  
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
     /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
-  huart->State = HAL_UART_STATE_BUSY;
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
-  
+
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
-  
-  /* In asynchronous mode, the following bits must be kept cleared: 
+
+  /* In asynchronous mode, the following bits must be kept cleared:
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-  
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
-  
+
   /* Initialize the UART state */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the half-duplex mode according to the specified
   *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
 {
   /* Check the UART handle allocation */
-  if(huart == NULL)
+  if (huart == NULL)
   {
     return HAL_ERROR;
   }
- 
-  /* Check the parameters */ 
-  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Check the parameters */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
 
-  if(huart->State == HAL_UART_STATE_RESET)
-  { 
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
     /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
-  huart->State = HAL_UART_STATE_BUSY;
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
-  
+
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
-  
-  /* In half-duplex mode, the following bits must be kept cleared: 
+
+  /* In half-duplex mode, the following bits must be kept cleared:
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
-  
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  huart->Instance->CR3 |= USART_CR3_HDSEL;
- 
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
-  
+
   /* Initialize the UART state*/
   huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the LIN mode according to the specified
   *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
-  * @param  BreakDetectLength: Specifies the LIN break detection length.
+  * @param  BreakDetectLength Specifies the LIN break detection length.
   *         This parameter can be one of the following values:
   *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
   *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
@@ -360,64 +461,80 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
 {
   /* Check the UART handle allocation */
-  if(huart == NULL)
+  if (huart == NULL)
   {
     return HAL_ERROR;
   }
-   
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  /* Check the Break detection length parameter */
   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
   assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
   assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
-  
-  if(huart->State == HAL_UART_STATE_RESET)
+
+  if (huart->gState == HAL_UART_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
     /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
-  huart->State = HAL_UART_STATE_BUSY;
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
-  
+
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
-  
-  /* In LIN mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
-  
+
+  /* In LIN mode, the following bits must be kept cleared:
+     - CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  huart->Instance->CR2 |= USART_CR2_LINEN;
-  
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
   /* Set the USART LIN Break detection length. */
-  huart->Instance->CR2 &= ~(USART_CR2_LBDL);
-  huart->Instance->CR2 |= BreakDetectLength; 
-  
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
+  SET_BIT(huart->Instance->CR2, BreakDetectLength);
+
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
-  
+
   /* Initialize the UART state*/
   huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the Multi-Processor mode according to the specified
   *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
-  * @param  Address: USART address
-  * @param  WakeUpMethod: specifies the USART wake-up method.
-  *          This parameter can be one of the following values:
+  * @param  Address USART address
+  * @param  WakeUpMethod specifies the USART wake-up method.
+  *         This parameter can be one of the following values:
   *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
   *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
   * @retval HAL status
@@ -425,85 +542,113 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
 {
   /* Check the UART handle allocation */
-  if(huart == NULL)
+  if (huart == NULL)
   {
     return HAL_ERROR;
   }
 
   /* Check the parameters */
   assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Check the Address & wake up method parameters */
   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
   assert_param(IS_UART_ADDRESS(Address));
   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
 
-  if(huart->State == HAL_UART_STATE_RESET)
+  if (huart->gState == HAL_UART_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
     /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
   }
 
-  huart->State = HAL_UART_STATE_BUSY;
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /* Disable the peripheral */
   __HAL_UART_DISABLE(huart);
-  
+
   /* Set the UART Communication parameters */
   UART_SetConfig(huart);
-  
-  /* In Multi-Processor mode, the following bits must be kept cleared: 
+
+  /* In Multi-Processor mode, the following bits must be kept cleared:
      - LINEN and CLKEN bits in the USART_CR2 register,
      - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-  
-  /* Clear the USART address */
-  huart->Instance->CR2 &= ~(USART_CR2_ADD);
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
   /* Set the USART address node */
-  huart->Instance->CR2 |= Address;
-  
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
+  SET_BIT(huart->Instance->CR2, Address);
+
   /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  huart->Instance->CR1 &= ~(USART_CR1_WAKE);
-  huart->Instance->CR1 |= WakeUpMethod;
-  
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
+  SET_BIT(huart->Instance->CR1, WakeUpMethod);
+
   /* Enable the peripheral */
   __HAL_UART_ENABLE(huart);
-  
+
   /* Initialize the UART state */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the UART peripheral. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  DeInitializes the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
 {
   /* Check the UART handle allocation */
-  if(huart == NULL)
+  if (huart == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_UART_INSTANCE(huart->Instance));
 
-  huart->State = HAL_UART_STATE_BUSY;
-  
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
   /* DeInit the low level hardware */
   HAL_UART_MspDeInit(huart);
-  
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
   huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State = HAL_UART_STATE_RESET;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
 
-  /* Process Lock */
+  /* Process Unlock */
   __HAL_UNLOCK(huart);
 
   return HAL_OK;
@@ -511,249 +656,505 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
 
 /**
   * @brief  UART MSP Init.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  UART MSP DeInit.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_MspDeInit could be implemented in the user file
-   */ 
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
 }
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions 
-  *  @brief UART Transmit and Receive functions 
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  *  @brief UART Transmit and Receive functions
   *
-@verbatim   
-  ==============================================================================
+@verbatim
+ ===============================================================================
                       ##### IO operation functions #####
-  ==============================================================================  
-  [..]
+ ===============================================================================
     This subsection provides a set of functions allowing to manage the UART asynchronous
     and Half duplex data transfers.
 
     (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) Non blocking mode: The communication is performed using Interrupts 
-            or DMA, these APIs return the HAL status.
-            The end of the data processing will be indicated through the 
-            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks 
-            will be executed respectively at the end of the transmit or receive process.
-            The HAL_UART_ErrorCallback() user callback will be executed when 
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) HAL_UART_Transmit()
-        (++) HAL_UART_Receive() 
-        
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) HAL_UART_Transmit_IT()
-        (++) HAL_UART_Receive_IT()
-        (++) HAL_UART_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) HAL_UART_Transmit_DMA()
-        (++) HAL_UART_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
-        (++) HAL_UART_TxCpltCallback()
-        (++) HAL_UART_RxCpltCallback()
-        (++) HAL_UART_ErrorCallback()
-
-    [..] 
-      (@) In the Half duplex communication, it is forbidden to run the transmit 
-          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX 
-          can't be useful.
-      
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, these API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Sends an amount of data in blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration  
+  * @brief  Sends an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
 
     huart->TxXferSize = Size;
     huart->TxXferCount = Size;
-    while(huart->TxXferCount > 0)
+    while (huart->TxXferCount > 0U)
     {
       huart->TxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pData;
+        tmp = (uint16_t *) pData;
         huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if(huart->Init.Parity == UART_PARITY_NONE)
+        if (huart->Init.Parity == UART_PARITY_NONE)
         {
-          pData +=2;
+          pData += 2U;
         }
         else
-        { 
-          pData +=1;
+        {
+          pData += 1U;
         }
-      } 
+      }
       else
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
         huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
-      } 
-    }
-    
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-    
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
+      }
     }
-    else
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     {
-      huart->State = HAL_UART_STATE_READY;
+      return HAL_TIMEOUT;
     }
-    
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receives an amount of data in blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration
+  * @brief  Receives an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{ 
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
-  { 
-    if((pData == NULL ) || (Size == 0)) 
+{
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
     {
       return  HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    
-    huart->RxXferSize = Size; 
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize = Size;
     huart->RxXferCount = Size;
-    
+
     /* Check the remain data to be received */
-    while(huart->RxXferCount > 0)
+    while (huart->RxXferCount > 0U)
     {
       huart->RxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pData ;
-        if(huart->Init.Parity == UART_PARITY_NONE)
+        tmp = (uint16_t *) pData;
+        if (huart->Init.Parity == UART_PARITY_NONE)
         {
           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-          pData +=2;
+          pData += 2U;
         }
         else
         {
           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
-          pData +=1;
+          pData += 1U;
         }
 
-      } 
+      }
       else
       {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        if(huart->Init.Parity == UART_PARITY_NONE)
+        if (huart->Init.Parity == UART_PARITY_NONE)
         {
           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
         }
@@ -761,320 +1162,300 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
         {
           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
         }
-        
+
       }
     }
-    
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    } 
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
   * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tmp = 0;
-  
-  tmp = huart->State;
-  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX))
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->pTxBuffPtr = pData;
     huart->TxXferSize = Size;
     huart->TxXferCount = Size;
 
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+    huart->gState = HAL_UART_STATE_BUSY_TX;
 
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
 
     /* Enable the UART Transmit data register empty Interrupt */
     __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
+  * @brief  Receives an amount of data in non blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tmp = 0;
-  
-  tmp = huart->State;  
-  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX))
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->pRxBuffPtr = pData;
     huart->RxXferSize = Size;
     huart->RxXferCount = Size;
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
     /* Enable the UART Parity Error Interrupt */
     __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-    
+
     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
     __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
+
     /* Enable the UART Data Register not empty Interrupt */
     __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-    
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Sends an amount of data in non blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Sends an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;  
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->pTxBuffPtr = pData;
     huart->TxXferSize = Size;
     huart->TxXferCount = Size;
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
     /* Set the UART DMA transfer complete callback */
     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-    
+
     /* Set the UART DMA Half transfer complete callback */
     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-    
+
     /* Set the DMA error callback */
     huart->hdmatx->XferErrorCallback = UART_DMAError;
 
-    /* Enable the UART transmit DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
-    
+    /* Set the DMA abort callback */
+    huart->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the UART transmit DMA stream */
+    tmp = (uint32_t *)&pData;
+    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
+
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
-    
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY;   
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
+  * @brief  Receives an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
 {
   uint32_t *tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;    
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
   {
-    if((pData == NULL ) || (Size == 0)) 
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
-    
+
     /* Process Locked */
     __HAL_LOCK(huart);
-    
+
     huart->pRxBuffPtr = pData;
     huart->RxXferSize = Size;
-    
+
     huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+
     /* Set the UART DMA transfer complete callback */
     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-    
+
     /* Set the UART DMA Half transfer complete callback */
     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-    
+
     /* Set the DMA error callback */
     huart->hdmarx->XferErrorCallback = UART_DMAError;
 
-    /* Enable the DMA Stream */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-    in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-    
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA stream */
+    tmp = (uint32_t *)&pData;
+    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
+
+    /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+    __HAL_UART_CLEAR_OREFLAG(huart);
+
     /* Process Unlocked */
     __HAL_UNLOCK(huart);
-    
+
+    /* Enable the UART Parity Error Interrupt */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+    in the UART CR3 register */
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
-    
+
 /**
   * @brief Pauses the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
 {
+  uint32_t dmarequest = 0x00U;
+
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
   {
     /* Disable the UART DMA Tx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
   {
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
     /* Disable the UART DMA Rx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-  else if (huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Disable the UART DMA Tx & Rx requests */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief Resumes the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
@@ -1082,240 +1463,838 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
 {
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
   {
     /* Enable the UART DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
+
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
   {
     /* Clear the Overrun flag before resuming the Rx transfer*/
     __HAL_UART_CLEAR_OREFLAG(huart);
+
+    /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
     /* Enable the UART DMA Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    /* Enable the UART DMA Tx & Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-    huart->Instance->CR3 |= USART_CR3_DMAR;
+    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief Stops the DMA Transfer.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
      and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
      */
-  
-  /* Disable the UART Tx/Rx DMA requests */
-  huart->Instance->CR3 &= ~USART_CR3_DMAT;
-  huart->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  /* Abort the UART DMA tx Stream */
-  if(huart->hdmatx != NULL)
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream */
+    if (huart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream */
+    if (huart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->RxState and huart->gState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
   {
-    HAL_DMA_Abort(huart->hdmatx);
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (AbortCplt == 0x01U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0x00U;
+    huart->RxXferCount = 0x00U;
+
+    /* Reset ErrorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0x00U;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0x00U;
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0x00U;
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
   }
-  /* Abort the UART DMA rx Stream */
-  if(huart->hdmarx != NULL)
+  else
   {
-    HAL_DMA_Abort(huart->hdmarx);
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0x00U;
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
   }
-  
-  huart->State = HAL_UART_STATE_READY;
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  This function handles UART interrupt request.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
 {
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);  
-  /* UART parity error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_PEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_PE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART frame error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_FEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_FE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART noise error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_NEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_NE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART Over-Run interrupt occurred ----------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_ORE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
-  /* UART in mode Receiver ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    UART_Receive_IT(huart);
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
+  uint32_t isrflags   = READ_REG(huart->Instance->SR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if (errorflags == RESET)
+  {
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      UART_Receive_IT(huart);
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* UART parity error interrupt occurred ----------------------------------*/
+    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART noise error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART frame error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART Over-Run interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* Call UART Error Call back function if need be --------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver -----------------------------------------------*/
+      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        UART_Receive_IT(huart);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx stream */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
   /* UART in mode Transmitter ------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
     UART_Transmit_IT(huart);
+    return;
   }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+
   /* UART in mode Transmitter end --------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     UART_EndTransmit_IT(huart);
+    return;
   }
-
-  if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-  {
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-    
-    HAL_UART_ErrorCallback(huart);
-  }  
 }
 
 /**
   * @brief  Tx Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_TxCpltCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
+   */
 }
 
 /**
   * @brief  Rx Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  UART error callbacks.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_UART_ErrorCallback could be implemented in the user file
-   */ 
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions 
-  *  @brief   UART control functions 
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                       ##### Peripheral Control functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control the UART:
     (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
-    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. 
+    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
     (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
-    
+    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
+    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Transmits break characters.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
@@ -1323,26 +2302,26 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
 {
   /* Check the parameters */
   assert_param(IS_UART_INSTANCE(huart->Instance));
-  
+
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
   /* Send break characters */
-  huart->Instance->CR1 |= USART_CR1_SBK;
- 
-  huart->State = HAL_UART_STATE_READY;
-  
+  SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
+
+  huart->gState = HAL_UART_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Enters the UART in mute mode. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Enters the UART in mute mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
@@ -1350,26 +2329,26 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
 {
   /* Check the parameters */
   assert_param(IS_UART_INSTANCE(huart->Instance));
-  
+
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
   /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  huart->Instance->CR1 |= USART_CR1_RWU;
-  
-  huart->State = HAL_UART_STATE_READY;
-  
+  SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
-  * @brief  Exits the UART mute mode: wake up software. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Exits the UART mute mode: wake up software.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
@@ -1377,132 +2356,136 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
 {
   /* Check the parameters */
   assert_param(IS_UART_INSTANCE(huart->Instance));
-  
+
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
   /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU);
-  
-  huart->State = HAL_UART_STATE_READY;
-  
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
 {
-  uint32_t tmpreg = 0x00;
+  uint32_t tmpreg = 0x00U;
 
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
+
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = huart->Instance->CR1;
-  
+
   /* Clear TE and RE bits */
   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
+
   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
   tmpreg |= (uint32_t)USART_CR1_TE;
-  
+
   /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
- 
-  huart->State = HAL_UART_STATE_READY;
-  
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
 {
-  uint32_t tmpreg = 0x00;
+  uint32_t tmpreg = 0x00U;
 
   /* Process Locked */
   __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
+
+  huart->gState = HAL_UART_STATE_BUSY;
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = huart->Instance->CR1;
-  
+
   /* Clear TE and RE bits */
   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
+
   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
   tmpreg |= (uint32_t)USART_CR1_RE;
-  
+
   /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
-  
-  huart->State = HAL_UART_STATE_READY;
-  
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
   * @}
   */
 
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions 
-  *  @brief   UART State and Errors functions 
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   UART State and Errors functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                  ##### Peripheral State and Errors functions #####
-  ==============================================================================  
+  ==============================================================================
  [..]
-   This subsection provides a set of functions allowing to return the State of 
-   UART communication process, return Peripheral Errors occurred during communication 
+   This subsection provides a set of functions allowing to return the State of
+   UART communication process, return Peripheral Errors occurred during communication
    process
    (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. 
+   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Returns the UART state.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL state
   */
 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
 {
-  return huart->State;
+  uint32_t temp1 = 0x00U, temp2 = 0x00U;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
 }
 
 /**
-* @brief  Return the UART error code
-* @param  huart : pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-* @retval UART Error Code
-*/
+  * @brief  Return the UART error code
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
 {
   return huart->ErrorCode;
@@ -1513,211 +2496,449 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
   */
 
 /**
-  * @brief  DMA UART transmit process complete callback. 
-  * @param  hdma: DMA handle
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief  DMA UART transmit process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   /* DMA Normal mode*/
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    huart->TxXferCount = 0;
+    huart->TxXferCount = 0x00U;
 
     /* Disable the DMA transfer for transmit request by setting the DMAT bit
        in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Enable the UART Transmit Complete Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
   }
   /* DMA Circular mode */
   else
   {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
     HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
   }
 }
 
 /**
-  * @brief DMA UART transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief DMA UART transmit process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
   HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  DMA UART receive process complete callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA UART receive process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   /* DMA Normal mode*/
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    huart->RxXferCount = 0;
-  
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
+    huart->RxXferCount = 0U;
+
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
        in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
   }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx complete callback*/
+  huart->RxCpltCallback(huart);
+#else
+  /*Call legacy weak Rx complete callback*/
   HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief DMA UART receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief DMA UART receive process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_RxHalfCpltCallback(huart); 
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Rx Half complete callback*/
+  huart->RxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Rx Half complete callback*/
+  HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
 
 /**
   * @brief  DMA UART communication error callback.
-  * @param  hdma: DMA handle
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
   * @retval None
   */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)   
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
 {
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0;
-  huart->TxXferCount = 0;
-  huart->State= HAL_UART_STATE_READY;
+  uint32_t dmarequest = 0x00U;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    huart->TxXferCount = 0x00U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    huart->RxXferCount = 0x00U;
+    UART_EndRxTransfer(huart);
+  }
+
   huart->ErrorCode |= HAL_UART_ERROR_DMA;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
   HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
 
 /**
   * @brief  This function handles UART Communication Timeout.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
-  * @param  Flag: specifies the UART flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  Flag specifies the UART flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
-          huart->State= HAL_UART_STATE_READY;
+        huart->gState  = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
 
-          return HAL_TIMEOUT;
-        }
+        return HAL_TIMEOUT;
       }
     }
   }
-  else
+  return HAL_OK;
+}
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  huart->RxXferCount = 0x00U;
+  huart->TxXferCount = 0x00U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
   {
-    while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
+    if (huart->hdmarx->XferAbortCallback != NULL)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+      return;
+    }
+  }
 
-          huart->State= HAL_UART_STATE_READY;
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-        
-          return HAL_TIMEOUT;
-        }
-      }
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
     }
   }
-  return HAL_OK;
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
 
 /**
   * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
 {
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
+  uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
   {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) huart->pTxBuffPtr;
+      tmp = (uint16_t *) huart->pTxBuffPtr;
       huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      if(huart->Init.Parity == UART_PARITY_NONE)
+      if (huart->Init.Parity == UART_PARITY_NONE)
       {
-        huart->pTxBuffPtr += 2;
+        huart->pTxBuffPtr += 2U;
       }
       else
       {
-        huart->pTxBuffPtr += 1;
+        huart->pTxBuffPtr += 1U;
       }
-    } 
+    }
     else
     {
       huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
     }
 
-    if(--huart->TxXferCount == 0)
+    if (--huart->TxXferCount == 0U)
     {
       /* Disable the UART Transmit Complete Interrupt */
       __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
 
-      /* Enable the UART Transmit Complete Interrupt */    
+      /* Enable the UART Transmit Complete Interrupt */
       __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
     }
     return HAL_OK;
@@ -1728,70 +2949,61 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
   }
 }
 
-
 /**
   * @brief  Wraps up transmission in non blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
 {
-  /* Disable the UART Transmit Complete Interrupt */    
+  /* Disable the UART Transmit Complete Interrupt */
   __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-  {
-    huart->State = HAL_UART_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the UART Parity Error Interrupt */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 
-    /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
 
-    huart->State = HAL_UART_STATE_READY;
-  }
-  
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
   HAL_UART_TxCpltCallback(huart);
-  
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Receives an amount of data in non blocking mode
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
 {
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State; 
-  if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
+  uint16_t *tmp;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
   {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
+    if (huart->Init.WordLength == UART_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) huart->pRxBuffPtr;
-      if(huart->Init.Parity == UART_PARITY_NONE)
+      tmp = (uint16_t *) huart->pRxBuffPtr;
+      if (huart->Init.Parity == UART_PARITY_NONE)
       {
         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-        huart->pRxBuffPtr += 2;
+        huart->pRxBuffPtr += 2U;
       }
       else
       {
         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
-        huart->pRxBuffPtr += 1;
+        huart->pRxBuffPtr += 1U;
       }
     }
     else
     {
-      if(huart->Init.Parity == UART_PARITY_NONE)
+      if (huart->Init.Parity == UART_PARITY_NONE)
       {
         *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
       }
@@ -1801,26 +3013,27 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
       }
     }
 
-    if(--huart->RxXferCount == 0)
+    if (--huart->RxXferCount == 0U)
     {
+      /* Disable the UART Data Register not empty Interrupt */
       __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
 
-      /* Check if a transmit process is ongoing or not */
-      if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-      {
-        huart->State = HAL_UART_STATE_BUSY_TX;
-      }
-      else
-      {
-        /* Disable the UART Parity Error Interrupt */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+      /* Disable the UART Parity Error Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
 
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
 
-        huart->State = HAL_UART_STATE_READY;
-      }
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /*Call registered Rx complete callback*/
+      huart->RxCpltCallback(huart);
+#else
+      /*Call legacy weak Rx complete callback*/
       HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 
       return HAL_OK;
     }
@@ -1828,78 +3041,61 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Configures the UART peripheral. 
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
+  * @brief  Configures the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
   *                the configuration information for the specified UART module.
   * @retval None
   */
 static void UART_SetConfig(UART_HandleTypeDef *huart)
 {
-  uint32_t tmpreg = 0x00;
-  
+  uint32_t tmpreg;
+  uint32_t pclk;
+
   /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));  
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
   assert_param(IS_UART_PARITY(huart->Init.Parity));
   assert_param(IS_UART_MODE(huart->Init.Mode));
 
   /*-------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR2;
-
-  /* Clear STOP[13:12] bits */
-  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */
-  tmpreg |= (uint32_t)huart->Init.StopBits;
-  
-  /* Write to USART CR2 */
-  huart->Instance->CR2 = (uint32_t)tmpreg;
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits
+     according to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
-                                   USART_CR1_RE | USART_CR1_OVER8));
-
-  /* Configure the UART Word Length, Parity and mode: 
-     Set the M bits according to huart->Init.WordLength value 
+  /* Configure the UART Word Length, Parity and mode:
+     Set the M bits according to huart->Init.WordLength value
      Set PCE and PS bits according to huart->Init.Parity value
      Set TE and RE bits according to huart->Init.Mode value
      Set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
-  
-  /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
-  
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  tmpreg = huart->Instance->CR3;
-  
-  /* Clear CTSE and RTSE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-  
+
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+  MODIFY_REG(huart->Instance->CR1,
+             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+             tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  tmpreg |= huart->Init.HwFlowCtl;
-  
-  /* Write to USART CR3 */
-  huart->Instance->CR3 = (uint32_t)tmpreg;
-  
-  /* Check the Over Sampling */
+  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
+
+/* Check the Over Sampling */
   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
   {
     /*-------------------------- USART BRR Configuration ---------------------*/
     if((huart->Instance == USART1) || (huart->Instance == USART6))
     {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+      pclk = HAL_RCC_GetPCLK2Freq();
+      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
     }
     else
     {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+      pclk = HAL_RCC_GetPCLK1Freq();
+      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
     }
   }
   else
@@ -1907,11 +3103,13 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
     /*-------------------------- USART BRR Configuration ---------------------*/
     if((huart->Instance == USART1) || (huart->Instance == USART6))
     {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+      pclk = HAL_RCC_GetPCLK2Freq();
+      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
     }
     else
     {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+      pclk = HAL_RCC_GetPCLK1Freq();
+      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
     }
   }
 }
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c
index bb29216f..ac5b65b1 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c
@@ -2,14 +2,13 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   USART HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
+  *          Peripheral (USART).
   *           + Initialization and de-initialization functions
   *           + IO operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -17,117 +16,181 @@
   [..]
     The USART HAL driver can be used as follows:
 
-    (#) Declare a USART_HandleTypeDef handle structure.
-    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
+    (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
         (##) Enable the USARTx interface clock.
         (##) USART pins configuration:
              (+++) Enable the clock for the USART GPIOs.
-             (+++) Configure these USART pins as alternate function pull-up.
+             (+++) Configure the USART pins as alternate function pull-up.
         (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
              HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
              (+++) Configure the USARTx interrupt priority.
              (+++) Enable the NVIC USART IRQ handle.
         (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
-             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+             HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
              (+++) Declare a DMA handle structure for the Tx/Rx stream.
              (+++) Enable the DMAx interface clock.
              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-             (+++) Configure the DMA Tx/Rx Stream.
+             (+++) Configure the DMA Tx/Rx stream.
              (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
-             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx stream.
+             (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+                   (used for last byte sending completion detection in DMA non circular mode)
 
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
         flow control and Mode(Receiver/Transmitter) in the husart Init structure.
 
     (#) Initialize the USART registers by calling the HAL_USART_Init() API:
         (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_USART_MspInit(&husart) API.
-                    
-        -@@- The specific USART interrupts (Transmission complete interrupt, 
+
+        -@@- The specific USART interrupts (Transmission complete interrupt,
              RXNE interrupt and Error Interrupts) will be managed using the macros
              __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-          
-    (#) Three operation modes are available within this driver :     
-  
+
+    (#) Three operation modes are available within this driver :
+
      *** Polling mode IO operation ***
      =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_USART_Transmit() 
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
        (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-       
-     *** Interrupt mode IO operation ***    
+
+     *** Interrupt mode IO operation ***
      ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() 
-       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_USART_ErrorCallback
-    
-     *** DMA mode IO operation ***    
+
+     *** DMA mode IO operation ***
      ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
+     [..]
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
             add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_USART_RxCpltCallback
+       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
             add his own code by customization of function pointer HAL_USART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_USART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_USART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_USART_DMAStop()      
-     
+       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+       (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
      *** USART HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in USART HAL driver.
-       
-       (+) __HAL_USART_ENABLE: Enable the USART peripheral 
-       (+) __HAL_USART_DISABLE: Disable the USART peripheral     
+
+       (+) __HAL_USART_ENABLE: Enable the USART peripheral
+       (+) __HAL_USART_DISABLE: Disable the USART peripheral
        (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
        (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
        (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
        (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-      
-     [..] 
+
+     [..]
        (@) You can refer to the USART HAL driver header file for more useful macros
 
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
+    Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) MspInitCallback           : USART MspInit.
+    (+) MspDeInitCallback         : USART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) TxRxCpltCallback          : Tx Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) MspInitCallback           : USART MspInit.
+    (+) MspDeInitCallback         : USART MspDeInit.
+
+    [..]
+    By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
+    and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
+    or @ref HAL_USART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
   @endverbatim
+     [..]
+       (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           the possible USART frame formats are as listed in the following table:
+    +-------------------------------------------------------------+
+    |   M bit |  PCE bit  |            USART frame                 |
+    |---------------------|---------------------------------------|
+    |    0    |    0      |    | SB | 8 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|-----------|---------------------------------------|
+    |    1    |    0      |    | SB | 9 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    +-------------------------------------------------------------+
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -149,8 +212,8 @@
 /** @addtogroup USART_Private_Constants
   * @{
   */
-#define DUMMY_DATA           0xFFFF
-#define USART_TIMEOUT_VALUE  22000
+#define DUMMY_DATA           0xFFFFU
+#define USART_TIMEOUT_VALUE  22000U
 /**
   * @}
   */
@@ -161,17 +224,26 @@
 /** @addtogroup USART_Private_Functions
   * @{
   */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-static void USART_SetConfig (USART_HandleTypeDef *husart);
+static void USART_SetConfig(USART_HandleTypeDef *husart);
 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
 /**
   * @}
   */
@@ -181,48 +253,48 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
   * @{
   */
 
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
 @verbatim
   ==============================================================================
               ##### Initialization and Configuration functions #####
   ==============================================================================
   [..]
-  This subsection provides a set of functions allowing to initialize the USART 
+  This subsection provides a set of functions allowing to initialize the USART
   in asynchronous and in synchronous modes.
-  (+) For the asynchronous mode only these parameters can be configured: 
+  (+) For the asynchronous mode only these parameters can be configured:
       (++) Baud Rate
-      (++) Word Length 
+      (++) Word Length
       (++) Stop Bit
       (++) Parity: If the parity is enabled, then the MSB bit of the data written
            in the data register is transmitted but is changed by the parity bit.
            Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           please refer to Reference manual for possible USART frame formats.   
+           please refer to Reference manual for possible USART frame formats.
       (++) USART polarity
       (++) USART phase
       (++) USART LastBit
       (++) Receiver/transmitter modes
 
   [..]
-    The HAL_USART_Init() function follows the USART  synchronous configuration 
-    procedure (details for the procedure are available in reference manual (RM0329)).
+    The HAL_USART_Init() function follows the USART  synchronous configuration
+    procedures (details for the procedures are available in reference manual (RM0033)).
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the USART mode according to the specified
-  *         parameters in the USART_InitTypeDef and create the associated handle.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Initialize the USART mode according to the specified
+  *         parameters in the USART_InitTypeDef and initialize the associated handle.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
 {
   /* Check the USART handle allocation */
-  if(husart == NULL)
+  if (husart == NULL)
   {
     return HAL_ERROR;
   }
@@ -230,45 +302,58 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
   /* Check the parameters */
   assert_param(IS_USART_INSTANCE(husart->Instance));
 
-  if(husart->State == HAL_USART_STATE_RESET)
+  if (husart->State == HAL_USART_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     husart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    USART_InitCallbacksToDefault(husart);
+
+    if (husart->MspInitCallback == NULL)
+    {
+      husart->MspInitCallback = HAL_USART_MspInit;
+    }
+
     /* Init the low level hardware */
+    husart->MspInitCallback(husart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
     HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
   }
-  
-  husart->State = HAL_USART_STATE_BUSY;  
+
+  husart->State = HAL_USART_STATE_BUSY;
 
   /* Set the USART Communication parameters */
   USART_SetConfig(husart);
 
-  /* In USART mode, the following bits must be kept cleared: 
+  /* In USART mode, the following bits must be kept cleared:
      - LINEN bit in the USART_CR2 register
      - HDSEL, SCEN and IREN bits in the USART_CR3 register */
-  husart->Instance->CR2 &= ~USART_CR2_LINEN;
-  husart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL);
+  CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 
   /* Enable the Peripheral */
   __HAL_USART_ENABLE(husart);
 
   /* Initialize the USART state */
   husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State= HAL_USART_STATE_READY;
+  husart->State = HAL_USART_STATE_READY;
 
   return HAL_OK;
 }
 
 /**
   * @brief  DeInitializes the USART peripheral.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
 {
-   /* Check the USART handle allocation */
-  if(husart == NULL)
+  /* Check the USART handle allocation */
+  if (husart == NULL)
   {
     return HAL_ERROR;
   }
@@ -281,8 +366,17 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   /* Disable the Peripheral */
   __HAL_USART_DISABLE(husart);
 
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  if (husart->MspDeInitCallback == NULL)
+  {
+    husart->MspDeInitCallback = HAL_USART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  husart->MspDeInitCallback(husart);
+#else
   /* DeInit the low level hardware */
   HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 
   husart->ErrorCode = HAL_USART_ERROR_NONE;
   husart->State = HAL_USART_STATE_RESET;
@@ -295,36 +389,268 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
 
 /**
   * @brief  USART MSP Init.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  USART MSP DeInit.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_MspDeInit could be implemented in the user file
-   */ 
+   */
+}
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User USART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  husart usart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
++  */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(husart);
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+        husart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_TX_COMPLETE_CB_ID :
+        husart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+        husart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_RX_COMPLETE_CB_ID :
+        husart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_TX_RX_COMPLETE_CB_ID :
+        husart->TxRxCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_ERROR_CB_ID :
+        husart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_USART_ABORT_COMPLETE_CB_ID :
+        husart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (husart->State == HAL_USART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(husart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  husart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(husart);
+
+  if (husart->State == HAL_USART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+        husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_USART_TX_COMPLETE_CB_ID :
+        husart->TxCpltCallback = HAL_USART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+        husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_USART_RX_COMPLETE_CB_ID :
+        husart->RxCpltCallback = HAL_USART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_USART_TX_RX_COMPLETE_CB_ID :
+        husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback;                   /* Legacy weak TxRxCpltCallback            */
+        break;
+
+      case HAL_USART_ERROR_CB_ID :
+        husart->ErrorCallback = HAL_USART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_USART_ABORT_COMPLETE_CB_ID :
+        husart->AbortCpltCallback = HAL_USART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = HAL_USART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = HAL_USART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (husart->State == HAL_USART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_USART_MSPINIT_CB_ID :
+        husart->MspInitCallback = HAL_USART_MspInit;
+        break;
+
+      case HAL_USART_MSPDEINIT_CB_ID :
+        husart->MspDeInitCallback = HAL_USART_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(husart);
+
+  return status;
 }
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions 
-  *  @brief   USART Transmit and Receive functions 
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+  *  @brief   USART Transmit and Receive functions
   *
 @verbatim
   ==============================================================================
@@ -333,31 +659,31 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
   [..]
     This subsection provides a set of functions allowing to manage the USART synchronous
     data transfers.
-      
-  [..] 
+
+  [..]
     The USART supports master mode only: it cannot receive or send data related to an input
     clock (SCLK is always an output).
 
     (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode. 
-             The HAL status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode: The communication is performed using Interrupts 
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) No-Blocking mode: The communication is performed using Interrupts
              or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the 
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when 
+             The end of the data processing will be indicated through the
+             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
              using DMA mode.
-             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() 
-              user callbacks 
+             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
+              user callbacks
              will be executed respectively at the end of the transmit or Receive process
-             The HAL_USART_ErrorCallback() user callback will be executed when a communication 
+             The HAL_USART_ErrorCallback() user callback will be executed when a communication
              error is detected
 
     (#) Blocking mode APIs are :
         (++) HAL_USART_Transmit() in simplex mode
         (++) HAL_USART_Receive() in full duplex receive only
         (++) HAL_USART_TransmitReceive() in full duplex mode
-        
+
     (#) Non Blocking mode APIs with Interrupt are :
         (++) HAL_USART_Transmit_IT()in simplex mode
         (++) HAL_USART_Receive_IT() in full duplex receive only
@@ -367,7 +693,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
     (#) Non Blocking mode functions with DMA are :
         (++) HAL_USART_Transmit_DMA()in simplex mode
         (++) HAL_USART_Receive_DMA() in full duplex receive only
-        (++) HAL_USART_TransmitReceie_DMA() in full duplex mode
+        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
         (++) HAL_USART_DMAPause()
         (++) HAL_USART_DMAResume()
         (++) HAL_USART_DMAStop()
@@ -380,26 +706,48 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
         (++) HAL_USART_ErrorCallback()
         (++) HAL_USART_TxRxCpltCallback()
 
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (++) HAL_USART_Abort()
+        (++) HAL_USART_Abort_IT()
+
+    (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+        (++) HAL_USART_AbortCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+        (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+             to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+             Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+             and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+             If user wants to abort it, Abort services should be called by user.
+        (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+             This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+             Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Simplex Send an amount of data in blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration    
+  * @brief  Simplex Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be sent.
+  * @param  Timeout Timeout duration.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
 
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
@@ -410,32 +758,35 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_TX;
 
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
     husart->TxXferSize = Size;
     husart->TxXferCount = Size;
-    while(husart->TxXferCount > 0)
+    while (husart->TxXferCount > 0U)
     {
       husart->TxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      if (husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pTxData;
+        tmp = (uint16_t *) pTxData;
         husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
-          pTxData += 2;
+          pTxData += 2U;
         }
         else
         {
-          pTxData += 1;
+          pTxData += 1U;
         }
       }
       else
       {
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
@@ -443,8 +794,8 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
       }
     }
 
-    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
+    if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
       return HAL_TIMEOUT;
     }
 
@@ -462,21 +813,26 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
 }
 
 /**
-  * @brief  Full-Duplex Receive an amount of data in blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration    
+  * @brief  Full-Duplex Receive an amount of data in blocking mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be received.
+  * @param  Timeout Timeout duration.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
 
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0)) 
+    if ((pRxData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
@@ -486,44 +842,47 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_RX;
 
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
     husart->RxXferSize = Size;
     husart->RxXferCount = Size;
     /* Check the remain data to be received */
-    while(husart->RxXferCount > 0)
+    while (husart->RxXferCount > 0U)
     {
       husart->RxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      if (husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
         /* Send dummy byte in order to generate clock */
         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
-        
+
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pRxData ;
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        tmp = (uint16_t *) pRxData ;
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-          pRxData +=2;
+          pRxData += 2U;
         }
         else
         {
           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-          pRxData +=1;
+          pRxData += 1U;
         }
       }
       else
       {
         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+        {
           return HAL_TIMEOUT;
         }
 
@@ -531,11 +890,11 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
         husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
 
         /* Wait until RXNE flag is set to receive the byte */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
           /* Receive data */
           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
@@ -545,7 +904,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
           /* Receive data */
           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
         }
-        
+
       }
     }
 
@@ -563,22 +922,26 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer  
-  * @param  Size: Amount of data to be sent
-   * @param  Timeout: Timeout duration    
+  * @brief  Full-Duplex Send and Receive an amount of data in full-duplex mode (blocking mode).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be sent (same amount to be received).
+  * @param  Timeout Timeout duration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
+  uint16_t *tmp;
+  uint32_t tickstart = 0U;
 
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
     {
       return  HAL_ERROR;
     }
@@ -588,66 +951,69 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_RX;
 
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
     husart->RxXferSize = Size;
     husart->TxXferSize = Size;
     husart->TxXferCount = Size;
     husart->RxXferCount = Size;
 
     /* Check the remain data to be received */
-    while(husart->TxXferCount > 0)
+    while (husart->TxXferCount > 0U)
     {
       husart->TxXferCount--;
       husart->RxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+      if (husart->Init.WordLength == USART_WORDLENGTH_9B)
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pTxData;
+        tmp = (uint16_t *) pTxData;
         husart->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
-          pTxData += 2;
+          pTxData += 2U;
         }
         else
         {
-          pTxData += 1;
+          pTxData += 1U;
         }
-        
+
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        tmp = (uint16_t*) pRxData ;
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        tmp = (uint16_t *) pRxData ;
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-          pRxData += 2;
+          pRxData += 2U;
         }
         else
         {
           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-          pRxData += 1;
+          pRxData += 1U;
         }
-      } 
+      }
       else
       {
         /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
         husart->Instance->DR = (*pTxData++ & (uint8_t)0x00FF);
 
         /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+        if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
         {
           return HAL_TIMEOUT;
         }
-        if(husart->Init.Parity == USART_PARITY_NONE)
+        if (husart->Init.Parity == USART_PARITY_NONE)
         {
           /* Receive data */
           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
@@ -674,19 +1040,22 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
 }
 
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Simplex Send an amount of data in non-blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   * @note   The USART errors are not managed to avoid the overrun error.
   */
 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
 {
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
@@ -701,7 +1070,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
     husart->ErrorCode = HAL_USART_ERROR_NONE;
     husart->State = HAL_USART_STATE_BUSY_TX;
 
-    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) 
+    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
        are not managed by the USART transmit process to avoid the overrun interrupt
        when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
        to benefit for the frame error and noise interrupts the USART mode should be
@@ -713,7 +1082,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
     __HAL_UNLOCK(husart);
 
     /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
@@ -724,18 +1093,22 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
 }
 
 /**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
+  * @brief  Simplex Receive an amount of data in non-blocking mode.
+  * @note   To receive synchronous data, dummy data are simultaneously transmitted.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be received.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
 {
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0)) 
+    if ((pRxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
@@ -752,17 +1125,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
 
-    /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
-
-    /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+    /* Enable the USART Parity Error and Data Register not empty Interrupts */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
 
     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
     /* Send dummy byte in order to generate the clock for the slave to send data */
-    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);    
+    husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
 
     return HAL_OK;
   }
@@ -773,19 +1143,22 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
-  * @param  Size: Amount of data to be received
+  * @brief  Full-Duplex Send and Receive an amount of data in full-duplex mode (non-blocking).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be sent (same amount to be received).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
 {
-  if(husart->State == HAL_USART_STATE_READY)
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
@@ -804,47 +1177,50 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
-    
+
     /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
+    SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
     /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+    SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
+  * @brief  Simplex Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pTxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
-  if(husart->State == HAL_USART_STATE_READY)
+
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
     /* Process Locked */
-    __HAL_LOCK(husart);  
+    __HAL_LOCK(husart);
 
     husart->pTxBuffPtr = pTxData;
     husart->TxXferSize = Size;
@@ -862,20 +1238,23 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
     /* Set the DMA error callback */
     husart->hdmatx->XferErrorCallback = USART_DMAError;
 
-    /* Enable the USART transmit DMA Stream */
-    tmp = (uint32_t*)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+    /* Set the DMA abort callback */
+    husart->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the USART transmit DMA stream */
+    tmp = (uint32_t *)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
 
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-    
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
 
     /* Process Unlocked */
     __HAL_UNLOCK(husart);
 
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the USART CR3 register */
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
     return HAL_OK;
   }
   else
@@ -885,11 +1264,14 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
 }
 
 /**
-  * @brief  Full-Duplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
+  * @brief  Full-Duplex Receive an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pRxData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be received.
   * @retval HAL status
   * @note   The USART DMA transmit stream must be configured in order to generate the clock for the slave.
   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -897,10 +1279,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
-  if(husart->State == HAL_USART_STATE_READY)
+
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pRxData == NULL) || (Size == 0)) 
+    if ((pRxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
@@ -925,29 +1307,48 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
     /* Set the USART DMA Rx transfer error callback */
     husart->hdmarx->XferErrorCallback = USART_DMAError;
 
-    /* Enable the USART receive DMA Stream */
-    tmp = (uint32_t*)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+    /* Set the DMA abort callback */
+    husart->hdmarx->XferAbortCallback = NULL;
+
+    /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
+    is performed in DMA reception complete callback  */
+    husart->hdmatx->XferHalfCpltCallback = NULL;
+    husart->hdmatx->XferCpltCallback = NULL;
+
+    /* Set the DMA error callback */
+    husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+    /* Set the DMA AbortCpltCallback */
+    husart->hdmatx->XferAbortCallback = NULL;
 
-    /* Enable the USART transmit DMA Stream: the transmit stream is used in order
-       to generate in the non-blocking mode the clock to the slave device, 
+    /* Enable the USART receive DMA stream */
+    tmp = (uint32_t *)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
+
+    /* Enable the USART transmit DMA stream: the transmit stream is used in order
+       to generate in the non-blocking mode the clock to the slave device,
        this mode isn't a simplex receive mode but a full-duplex receive one */
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
 
-    /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
-       when using the USART in circular mode */
+    /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
     __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
        in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAR;
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
 
     /* Enable the DMA transfer for transmit request by setting the DMAT bit
        in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
 
     return HAL_OK;
   }
@@ -958,22 +1359,25 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
 }
 
 /**
-  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
-  * @param  Size: Amount of data to be received
+  * @brief  Full-Duplex Transmit Receive an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+  *         of u16 available through pTxData and through pRxData.
+  * @param  husart  Pointer to a USART_HandleTypeDef structure that contains
+  *                 the configuration information for the specified USART module.
+  * @param  pTxData Pointer to TX data buffer (u8 or u16 data elements).
+  * @param  pRxData Pointer to RX data buffer (u8 or u16 data elements).
+  * @param  Size    Amount of data elements (u8 or u16) to be received/sent.
   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 {
   uint32_t *tmp;
-  
-  if(husart->State == HAL_USART_STATE_READY)
+
+  if (husart->State == HAL_USART_STATE_READY)
   {
-    if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) 
+    if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
     {
       return HAL_ERROR;
     }
@@ -1006,30 +1410,39 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
     /* Set the USART DMA Rx transfer error callback */
     husart->hdmarx->XferErrorCallback = USART_DMAError;
 
-    /* Enable the USART receive DMA Stream */
-    tmp = (uint32_t*)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
+    /* Set the DMA abort callback */
+    husart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the USART receive DMA stream */
+    tmp = (uint32_t *)&pRxData;
+    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size);
+
+    /* Enable the USART transmit DMA stream */
+    tmp = (uint32_t *)&pTxData;
+    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size);
 
-    /* Enable the USART transmit DMA Stream */
-    tmp = (uint32_t*)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-    
     /* Clear the TC flag in the SR register by writing 0 to it */
     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
-    
+
     /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
     __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(husart);
+
+    /* Enable the USART Parity Error Interrupt */
+    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
        in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAR;
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
 
     /* Enable the DMA transfer for transmit request by setting the DMAT bit
        in the USART CR3 register */
-    husart->Instance->CR3 |= USART_CR3_DMAT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
+    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
 
     return HAL_OK;
   }
@@ -1040,8 +1453,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
 }
 
 /**
-  * @brief Pauses the DMA Transfer.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Pauses the DMA Transfer.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
@@ -1049,19 +1462,19 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
 {
   /* Process Locked */
   __HAL_LOCK(husart);
-  
+
   /* Disable the USART DMA Tx request */
-  husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-  
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
   /* Process Unlocked */
   __HAL_UNLOCK(husart);
-  
-  return HAL_OK; 
+
+  return HAL_OK;
 }
 
 /**
-  * @brief Resumes the DMA Transfer.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Resumes the DMA Transfer.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
@@ -1069,125 +1482,402 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
 {
   /* Process Locked */
   __HAL_LOCK(husart);
-  
+
   /* Enable the USART DMA Tx request */
-  husart->Instance->CR3 |= USART_CR3_DMAT;
-  
+  SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
   /* Process Unlocked */
   __HAL_UNLOCK(husart);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief Stops the DMA Transfer.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Stops the DMA Transfer.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
 {
+  uint32_t dmarequest = 0x00U;
   /* The Lock is not implemented on this API to allow the user application
      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
      and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
      */
 
-  /* Abort the USART DMA Tx Stream */
-  if(husart->hdmatx != NULL)
+  /* Stop USART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+  if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
   {
-    HAL_DMA_Abort(husart->hdmatx);
+    USART_EndTxTransfer(husart);
+
+    /* Abort the USART DMA Tx channel */
+    if (husart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(husart->hdmatx);
+    }
+
+    /* Disable the USART Tx DMA request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
   }
-  /* Abort the USART DMA Rx Stream */
-  if(husart->hdmarx != NULL)
-  {  
-    HAL_DMA_Abort(husart->hdmarx);
+
+  /* Stop USART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+  if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+  {
+    USART_EndRxTransfer(husart);
+
+    /* Abort the USART DMA Rx channel */
+    if (husart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(husart->hdmarx);
+    }
+
+    /* Disable the USART Rx DMA request */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
   }
-  
-  /* Disable the USART Tx/Rx DMA requests */
-  husart->Instance->CR3 &= ~USART_CR3_DMAT;
-  husart->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  husart->State = HAL_USART_STATE_READY;
 
   return HAL_OK;
 }
 
 /**
-  * @brief  This function handles USART interrupt request.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+  * @brief  Abort ongoing transfer (blocking mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+  *         as described by TransferType parameter) started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
 {
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
-  /* USART parity error interrupt occurred -----------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the USART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
   {
-    __HAL_USART_CLEAR_PEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_PE;
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (husart->hdmatx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      husart->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmatx);
+    }
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART frame error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (husart->hdmarx != NULL)
+    {
+      /* Set the USART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      husart->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(husart->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  husart->TxXferCount = 0x00U;
+  husart->RxXferCount = 0x00U;
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfer (Interrupt mode).
+  * @param  husart USART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+  *         as described by TransferType parameter) started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable PPP Interrupts (depending of transfer direction)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (husart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+    {
+      husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+    }
+    else
+    {
+      husart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (husart->hdmarx != NULL)
   {
-    __HAL_USART_CLEAR_FEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_FE;
+    /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+    {
+      husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+    }
+    else
+    {
+      husart->hdmarx->XferAbortCallback = NULL;
+    }
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART noise error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* Disable the USART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
   {
-    __HAL_USART_CLEAR_NEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_NE;
+    /* Disable DMA Tx at USART level */
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (husart->hdmatx != NULL)
+    {
+      /* USART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+      {
+        husart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART Over-Run interrupt occurred ---------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  /* Disable the USART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
   {
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_ORE;
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (husart->hdmarx != NULL)
+    {
+      /* USART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+      {
+        husart->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
   }
 
-  if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (AbortCplt  == 0x01U)
   {
-    /* Set the USART state ready to be able to start again the process */
-    husart->State = HAL_USART_STATE_READY;
-    
-    HAL_USART_ErrorCallback(husart);
+    /* Reset Tx and Rx transfer counters */
+    husart->TxXferCount = 0x00U;
+    husart->RxXferCount = 0x00U;
+
+    /* Reset errorCode */
+    husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+    /* Restore husart->State to Ready */
+    husart->State  = HAL_USART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Complete Callback */
+    husart->AbortCpltCallback(husart);
+#else
+    /* Call legacy weak Abort Complete Callback */
+    HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
-  /* USART in mode Receiver --------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles USART interrupt request.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART module.
+  * @retval None
+  */
+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
+{
+  uint32_t isrflags = READ_REG(husart->Instance->SR);
+  uint32_t cr1its   = READ_REG(husart->Instance->CR1);
+  uint32_t cr3its   = READ_REG(husart->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if (errorflags == RESET)
   {
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    /* USART in mode Receiver -------------------------------------------------*/
+    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
     {
-      USART_Receive_IT(husart);
+      if (husart->State == HAL_USART_STATE_BUSY_RX)
+      {
+        USART_Receive_IT(husart);
+      }
+      else
+      {
+        USART_TransmitReceive_IT(husart);
+      }
+      return;
     }
-    else
+  }
+  /* If some errors occur */
+  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* USART parity error interrupt occurred ----------------------------------*/
+    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
     {
-      USART_TransmitReceive_IT(husart);
+      husart->ErrorCode |= HAL_USART_ERROR_PE;
+    }
+
+    /* USART noise error interrupt occurred --------------------------------*/
+    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_NE;
+    }
+
+    /* USART frame error interrupt occurred --------------------------------*/
+    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_FE;
+    }
+
+    /* USART Over-Run interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      husart->ErrorCode |= HAL_USART_ERROR_ORE;
     }
+
+    if (husart->ErrorCode != HAL_USART_ERROR_NONE)
+    {
+      /* USART in mode Receiver -----------------------------------------------*/
+      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        if (husart->State == HAL_USART_STATE_BUSY_RX)
+        {
+          USART_Receive_IT(husart);
+        }
+        else
+        {
+          USART_TransmitReceive_IT(husart);
+        }
+      }
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+      consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+      if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Set the USART state ready to be able to start again the process,
+        Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        USART_EndRxTransfer(husart);
+
+        /* Disable the USART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the USART DMA Rx channel */
+          if (husart->hdmarx != NULL)
+          {
+            /* Set the USART DMA Abort callback :
+            will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+            husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+            if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              husart->hdmarx->XferAbortCallback(husart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+            /* Call registered Error Callback */
+            husart->ErrorCallback(husart);
+#else
+            /* Call legacy weak Error Callback */
+            HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+          /* Call registered Error Callback */
+          husart->ErrorCallback(husart);
+#else
+          /* Call legacy weak Error Callback */
+          HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+        /* Call registered Error Callback */
+        husart->ErrorCallback(husart);
+#else
+        /* Call legacy weak Error Callback */
+        HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+        husart->ErrorCode = HAL_USART_ERROR_NONE;
+      }
+    }
+    return;
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
   /* USART in mode Transmitter -----------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
   {
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    if (husart->State == HAL_USART_STATE_BUSY_TX)
     {
       USART_Transmit_IT(husart);
     }
@@ -1195,121 +1885,148 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
     {
       USART_TransmitReceive_IT(husart);
     }
+    return;
   }
 
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
   /* USART in mode Transmitter (transmission end) ----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
+  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
   {
     USART_EndTransmit_IT(husart);
+    return;
   }
 }
 
 /**
   * @brief  Tx Transfer completed callbacks.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_TxCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Tx Half Transfer completed callbacks.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_TxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Rx Transfer completed callbacks.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_RxCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Rx Half Transfer completed callbacks.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_RxHalfCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_USART_TxRxCpltCallback could be implemented in the user file
    */
 }
 
 /**
   * @brief  USART error callbacks.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
- __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_USART_ErrorCallback could be implemented in the user file
-   */ 
+   */
+}
+
+/**
+  * @brief  USART Abort Complete callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USART_AbortCpltCallback can be implemented in the user file.
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   USART State and Errors functions 
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   USART State and Errors functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                   ##### Peripheral State and Errors functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
-    This subsection provides a set of functions allowing to return the State of 
+    This subsection provides a set of functions allowing to return the State of
     USART communication
     process, return Peripheral Errors occurred during communication process
-     (+) HAL_USART_GetState() API can be helpful to check in run-time the state 
+     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
          of the USART peripheral.
-     (+) HAL_USART_GetError() check in run-time errors that could be occurred during 
-         communication. 
+     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+         communication.
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Returns the USART state.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL state
   */
@@ -1320,8 +2037,8 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
 
 /**
   * @brief  Return the USART error code
-  * @param  husart : pointer to a USART_HandleTypeDef structure that contains
-  *              the configuration information for the specified USART.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
+  *                the configuration information for the specified USART.
   * @retval USART Error Code
   */
 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
@@ -1332,240 +2049,439 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
 /**
   * @}
   */
-  
+
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  husart USART handle.
+  * @retval none
+  */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+  /* Init the USART Callback settings */
+  husart->TxHalfCpltCallback        = HAL_USART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  husart->TxCpltCallback            = HAL_USART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  husart->RxHalfCpltCallback        = HAL_USART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  husart->RxCpltCallback            = HAL_USART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  husart->TxRxCpltCallback          = HAL_USART_TxRxCpltCallback;          /* Legacy weak TxRxCpltCallback          */
+  husart->ErrorCallback             = HAL_USART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  husart->AbortCpltCallback         = HAL_USART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 
 /**
-  * @brief  DMA USART transmit process complete callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA USART transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
   * @retval None
   */
 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    husart->TxXferCount = 0;
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    husart->TxXferCount = 0U;
+    if (husart->State == HAL_USART_STATE_BUSY_TX)
     {
       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
          in the USART CR3 register */
       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-      
-      /* Enable the USART Transmit Complete Interrupt */    
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+
+      /* Enable the USART Transmit Complete Interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
     }
   }
   /* DMA Circular mode */
   else
   {
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
+    if (husart->State == HAL_USART_STATE_BUSY_TX)
     {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Complete Callback */
+      husart->TxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Complete Callback */
       HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
     }
   }
 }
 
 /**
-  * @brief DMA USART transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  DMA USART transmit process half complete callback
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
   * @retval None
   */
 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx Half Complete Callback */
+  husart->TxHalfCpltCallback(husart);
+#else
+  /* Call legacy weak Tx Half Complete Callback */
   HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  DMA USART receive process complete callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA USART receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
   * @retval None
   */
 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   /* DMA Normal mode */
-  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
   {
-    husart->RxXferCount = 0;
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
+    husart->RxXferCount = 0x00U;
+
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit
          in the USART CR3 register */
-      husart->Instance->CR3 &= ~(USART_CR3_DMAR);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+    CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+    husart->State = HAL_USART_STATE_READY;
 
-      husart->State= HAL_USART_STATE_READY;
+    /* The USART state is HAL_USART_STATE_BUSY_RX */
+    if (husart->State == HAL_USART_STATE_BUSY_RX)
+    {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx Complete Callback */
+      husart->RxCpltCallback(husart);
+#else
+      /* Call legacy weak Rx Complete Callback */
       HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
     }
     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
     else
     {
-      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
-         in the USART CR3 register */
-      husart->Instance->CR3 &= ~(USART_CR3_DMAR);
-      husart->Instance->CR3 &= ~(USART_CR3_DMAT);
- 
-      husart->State= HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Rx Complete Callback */
+      husart->TxRxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Rx Complete Callback */
       HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
     }
   }
   /* DMA circular mode */
   else
   {
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
+    if (husart->State == HAL_USART_STATE_BUSY_RX)
     {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx Complete Callback */
+      husart->RxCpltCallback(husart);
+#else
+      /* Call legacy weak Rx Complete Callback */
       HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
     }
     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
     else
     {
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Rx Complete Callback */
+      husart->TxRxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Rx Complete Callback */
       HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
     }
   }
 }
 
 /**
-  * @brief DMA USART receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
+  * @brief  DMA USART receive process half complete callback
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
   * @retval None
   */
 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_USART_RxHalfCpltCallback(husart); 
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Rx Half Complete Callback */
+  husart->RxHalfCpltCallback(husart);
+#else
+  /* Call legacy weak Rx Half Complete Callback */
+  HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 }
 
 /**
-  * @brief  DMA USART communication error callback. 
-  * @param  hdma: DMA handle
+  * @brief  DMA USART communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
   * @retval None
   */
 static void USART_DMAError(DMA_HandleTypeDef *hdma)
 {
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  uint32_t dmarequest = 0x00U;
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  husart->RxXferCount = 0x00U;
+  husart->TxXferCount = 0x00U;
+
+  /* Stop USART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+  if ((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+  {
+    USART_EndTxTransfer(husart);
+  }
+
+  /* Stop USART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+  if ((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+  {
+    USART_EndRxTransfer(husart);
+  }
 
-  husart->RxXferCount = 0;
-  husart->TxXferCount = 0;
   husart->ErrorCode |= HAL_USART_ERROR_DMA;
-  husart->State= HAL_USART_STATE_READY;
-  
+  husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Error Callback */
+  husart->ErrorCallback(husart);
+#else
+  /* Call legacy weak Error Callback */
   HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 }
 
 /**
   * @brief  This function handles USART Communication Timeout.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
-  * @param  Flag: specifies the USART flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
+  * @param  Flag specifies the USART flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value.
+  * @param  Timeout Timeout duration.
   * @retval HAL status
   */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set */
-  if(Status == RESET)
+  while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
   {
-    while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
       {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+        /* Disable the USART Transmit Complete Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
-          husart->State= HAL_USART_STATE_READY;
+        /* Disable the USART RXNE Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
+        /* Disable the USART Parity Error Interrupt */
+        CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
-          return HAL_TIMEOUT;
-        }
+        /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+        husart->State = HAL_USART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(husart);
+
+        return HAL_TIMEOUT;
       }
     }
   }
-  else
+  return HAL_OK;
+}
+
+/**
+  * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
+  * @param  husart USART handle.
+  * @retval None
+  */
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
+{
+  /* Disable RXNE, PE and ERR interrupts */
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore husart->State to Ready */
+  husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+  * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  husart->RxXferCount = 0x00U;
+  husart->TxXferCount = 0x00U;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Error Callback */
+  husart->ErrorCallback(husart);
+#else
+  /* Call legacy weak Error Callback */
+  HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA USART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  husart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (husart->hdmarx != NULL)
   {
-    while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
+    if (husart->hdmarx->XferAbortCallback != NULL)
     {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+      return;
+    }
+  }
 
-          husart->State= HAL_USART_STATE_READY;
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0x00U;
+  husart->RxXferCount = 0x00U;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
 
-          return HAL_TIMEOUT;
-        }
-      }
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Complete Callback */
+  husart->AbortCpltCallback(husart);
+#else
+  /* Call legacy weak Abort Complete Callback */
+  HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA USART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  USART_HandleTypeDef *husart = (USART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  husart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (husart->hdmatx != NULL)
+  {
+    if (husart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
     }
   }
-  return HAL_OK;
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  husart->TxXferCount = 0x00U;
+  husart->RxXferCount = 0x00U;
+
+  /* Reset errorCode */
+  husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+  /* Restore husart->State to Ready */
+  husart->State  = HAL_USART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Complete Callback */
+  husart->AbortCpltCallback(husart);
+#else
+  /* Call legacy weak Abort Complete Callback */
+  HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 }
 
-  
 /**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Simplex Send an amount of data in non-blocking mode.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   * @note   The USART errors are not managed to avoid the overrun error.
   */
 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
 {
-  uint16_t* tmp;
- 
-  if(husart->State == HAL_USART_STATE_BUSY_TX)
+  uint16_t *tmp;
+
+  if (husart->State == HAL_USART_STATE_BUSY_TX)
   {
-    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    if (husart->Init.WordLength == USART_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) husart->pTxBuffPtr;
+      tmp = (uint16_t *) husart->pTxBuffPtr;
       husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      if(husart->Init.Parity == USART_PARITY_NONE)
+      if (husart->Init.Parity == USART_PARITY_NONE)
       {
-        husart->pTxBuffPtr += 2;
+        husart->pTxBuffPtr += 2U;
       }
       else
       {
-        husart->pTxBuffPtr += 1;
+        husart->pTxBuffPtr += 1U;
       }
-    } 
+    }
     else
-    { 
+    {
       husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
     }
-    
-    if(--husart->TxXferCount == 0)
+
+    if (--husart->TxXferCount == 0U)
     {
       /* Disable the USART Transmit data register empty Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
 
-      /* Enable the USART Transmit Complete Interrupt */    
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+      /* Enable the USART Transmit Complete Interrupt */
+      SET_BIT(husart->Instance->CR1, USART_CR1_TCIE);
     }
     return HAL_OK;
   }
@@ -1577,58 +2493,64 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
 
 /**
   * @brief  Wraps up transmission in non blocking mode.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
 {
-  /* Disable the USART Transmit Complete Interrupt */    
-  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-  
+  /* Disable the USART Transmit Complete Interrupt */
+  CLEAR_BIT(husart->Instance->CR1, USART_CR1_TCIE);
+
   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-    
+  CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
   husart->State = HAL_USART_STATE_READY;
-   
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+  /* Call registered Tx Complete Callback */
+  husart->TxCpltCallback(husart);
+#else
+  /* Call legacy weak Tx Complete Callback */
   HAL_USART_TxCpltCallback(husart);
-  
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
   return HAL_OK;
 }
 
 /**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Simplex Receive an amount of data in non-blocking mode.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
 {
-  uint16_t* tmp;
-  if(husart->State == HAL_USART_STATE_BUSY_RX)
+  uint16_t *tmp;
+  if (husart->State == HAL_USART_STATE_BUSY_RX)
   {
-    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+    if (husart->Init.WordLength == USART_WORDLENGTH_9B)
     {
-      tmp = (uint16_t*) husart->pRxBuffPtr;
-      if(husart->Init.Parity == USART_PARITY_NONE)
+      tmp = (uint16_t *) husart->pRxBuffPtr;
+      if (husart->Init.Parity == USART_PARITY_NONE)
       {
         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-        husart->pRxBuffPtr += 2;
+        husart->pRxBuffPtr += 2U;
       }
       else
       {
         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-        husart->pRxBuffPtr += 1;
+        husart->pRxBuffPtr += 1U;
       }
-      if(--husart->RxXferCount != 0x00) 
+      if (--husart->RxXferCount != 0x00U)
       {
         /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF); 
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
       }
-    } 
+    }
     else
     {
-      if(husart->Init.Parity == USART_PARITY_NONE)
+      if (husart->Init.Parity == USART_PARITY_NONE)
       {
         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
       }
@@ -1637,66 +2559,72 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
       }
 
-      if(--husart->RxXferCount != 0x00) 
+      if (--husart->RxXferCount != 0x00U)
       {
         /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);  
+        husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
       }
     }
 
-    if(husart->RxXferCount == 0)
+    if (husart->RxXferCount == 0U)
     {
       /* Disable the USART RXNE Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
       /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
       husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Rx Complete Callback */
+      husart->RxCpltCallback(husart);
+#else
+      /* Call legacy weak Rx Complete Callback */
       HAL_USART_RxCpltCallback(husart);
-      
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
       return HAL_OK;
     }
     return HAL_OK;
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval HAL status
   */
 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
 {
-  uint16_t* tmp;
+  uint16_t *tmp;
 
-  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+  if (husart->State == HAL_USART_STATE_BUSY_TX_RX)
   {
-    if(husart->TxXferCount != 0x00)
+    if (husart->TxXferCount != 0x00U)
     {
-      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
+      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
       {
-        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+        if (husart->Init.WordLength == USART_WORDLENGTH_9B)
         {
-          tmp = (uint16_t*) husart->pTxBuffPtr;
+          tmp = (uint16_t *) husart->pTxBuffPtr;
           husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-          if(husart->Init.Parity == USART_PARITY_NONE)
+          if (husart->Init.Parity == USART_PARITY_NONE)
           {
-            husart->pTxBuffPtr += 2;
+            husart->pTxBuffPtr += 2U;
           }
           else
           {
-            husart->pTxBuffPtr += 1;
+            husart->pTxBuffPtr += 1U;
           }
-        } 
+        }
         else
         {
           husart->Instance->DR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF);
@@ -1704,34 +2632,34 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
         husart->TxXferCount--;
 
         /* Check the latest data transmitted */
-        if(husart->TxXferCount == 0)
+        if (husart->TxXferCount == 0U)
         {
-           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+          CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
         }
       }
     }
 
-    if(husart->RxXferCount != 0x00)
+    if (husart->RxXferCount != 0x00U)
     {
-      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
+      if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
       {
-        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
+        if (husart->Init.WordLength == USART_WORDLENGTH_9B)
         {
-          tmp = (uint16_t*) husart->pRxBuffPtr;
-          if(husart->Init.Parity == USART_PARITY_NONE)
+          tmp = (uint16_t *) husart->pRxBuffPtr;
+          if (husart->Init.Parity == USART_PARITY_NONE)
           {
             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-            husart->pRxBuffPtr += 2;
+            husart->pRxBuffPtr += 2U;
           }
           else
           {
             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-            husart->pRxBuffPtr += 1;
+            husart->pRxBuffPtr += 1U;
           }
-        } 
+        }
         else
         {
-          if(husart->Init.Parity == USART_PARITY_NONE)
+          if (husart->Init.Parity == USART_PARITY_NONE)
           {
             *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
           }
@@ -1745,19 +2673,26 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
     }
 
     /* Check the latest data received */
-    if(husart->RxXferCount == 0)
+    if (husart->RxXferCount == 0U)
     {
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+      /* Disable the USART RXNE Interrupt */
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
 
       /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+      CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
 
       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-      
+      CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
       husart->State = HAL_USART_STATE_READY;
 
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+      /* Call registered Tx Rx Complete Callback */
+      husart->TxRxCpltCallback(husart);
+#else
+      /* Call legacy weak Tx Rx Complete Callback */
       HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 
       return HAL_OK;
     }
@@ -1766,26 +2701,27 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
   }
   else
   {
-    return HAL_BUSY; 
+    return HAL_BUSY;
   }
 }
 
 /**
-  * @brief  Configures the USART peripheral. 
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
+  * @brief  Configures the USART peripheral.
+  * @param  husart Pointer to a USART_HandleTypeDef structure that contains
   *                the configuration information for the specified USART module.
   * @retval None
   */
 static void USART_SetConfig(USART_HandleTypeDef *husart)
 {
-  uint32_t tmpreg = 0x00;
+  uint32_t tmpreg = 0x00U;
+  uint32_t pclk;
 
   /* Check the parameters */
   assert_param(IS_USART_INSTANCE(husart->Instance));
   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
-  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));  
+  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
   assert_param(IS_USART_PARITY(husart->Init.Parity));
@@ -1793,7 +2729,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
 
   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  husart->Instance->CR1 &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+  CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
 
   /*---------------------------- USART CR2 Configuration ---------------------*/
   tmpreg = husart->Instance->CR2;
@@ -1804,10 +2740,10 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
   /* Set CPHA bit according to husart->Init.CLKPhase value */
   /* Set LBCL bit according to husart->Init.CLKLastBit value */
   /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
-  tmpreg |= (uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | 
-                      husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits);
+  tmpreg |= (uint32_t)(USART_CLOCK_ENABLE | husart->Init.CLKPolarity |
+                       husart->Init.CLKPhase | husart->Init.CLKLastBit | husart->Init.StopBits);
   /* Write to USART CR2 */
-  husart->Instance->CR2 = (uint32_t)tmpreg;
+  WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg);
 
   /*-------------------------- USART CR1 Configuration -----------------------*/
   tmpreg = husart->Instance->CR1;
@@ -1816,31 +2752,37 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
                                    USART_CR1_RE | USART_CR1_OVER8));
 
-  /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to husart->Init.WordLength value 
+  /* Configure the USART Word Length, Parity and mode:
+     Set the M bits according to husart->Init.WordLength value
      Set PCE and PS bits according to husart->Init.Parity value
-     Set TE and RE bits according to husart->Init.Mode value 
+     Set TE and RE bits according to husart->Init.Mode value
      Force OVER8 bit to 1 in order to reach the max USART frequencies */
   tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
 
   /* Write to USART CR1 */
-  husart->Instance->CR1 = (uint32_t)tmpreg;
+  WRITE_REG(husart->Instance->CR1, (uint32_t)tmpreg);
 
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
+  /*-------------------------- USART CR3 Configuration -----------------------*/
   /* Clear CTSE and RTSE bits */
-  husart->Instance->CR3 &= (uint32_t)~((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
 
   /*-------------------------- USART BRR Configuration -----------------------*/
   if((husart->Instance == USART1) || (husart->Instance == USART6))
   {
-    husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK2Freq();
+    husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
   }
   else
   {
-    husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
+    pclk = HAL_RCC_GetPCLK1Freq();
+    husart->Instance->BRR = USART_BRR(pclk, husart->Init.BaudRate);
   }
 }
 
+/**
+  * @}
+  */
+
 /**
   * @}
   */
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_wwdg.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_wwdg.c
index 15d99b0c..c958d85e 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_wwdg.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_wwdg.c
@@ -2,100 +2,121 @@
   ******************************************************************************
   * @file    stm32f2xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   WWDG HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Window Watchdog (WWDG) peripheral:
-  *           + Initialization and de-initialization functions
+  *           + Initialization and Configuration functions
   *           + IO operation functions
-  *           + Peripheral State functions       
   @verbatim
   ==============================================================================
-                      ##### WWDG specific features #####
+                      ##### WWDG Specific features #####
   ==============================================================================
-  [..] 
+  [..]
     Once enabled the WWDG generates a system reset on expiry of a programmed
-    time period, unless the program refreshes the counter (downcounter) 
+    time period, unless the program refreshes the counter (T[6;0] downcounter)
     before reaching 0x3F value (i.e. a reset is generated when the counter
-    value rolls over from 0x40 to 0x3F). 
-       
+    value rolls down from 0x40 to 0x3F).
+
     (+) An MCU reset is also generated if the counter value is refreshed
-        before the counter has reached the refresh window value. This 
+        before the counter has reached the refresh window value. This
         implies that the counter must be refreshed in a limited window.
     (+) Once enabled the WWDG cannot be disabled except by a system reset.
-    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
-        reset occurs.               
-    (+) The WWDG counter input clock is derived from the APB clock divided 
+    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+        reset occurs.
+    (+) The WWDG counter input clock is derived from the APB clock divided
         by a programmable prescaler.
     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
-    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
+    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+        where T[5;0] are the lowest 6 bits of Counter.
     (+) WWDG Counter refresh is allowed between the following limits :
-        (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
-        (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
-    
-    (+) Min-max timeout value at 50 MHz(PCLK1): 81.9 us / 41.9 ms 
-
+        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+    (+) Typical values:
+        (++) Counter min (T[5;0] = 0x00) @30MHz (PCLK1) with zero prescaler:
+             max timeout before reset: ~136.53µs
+        (++) Counter max (T[5;0] = 0x3F) @30MHz (PCLK1) with prescaler dividing by 128:
+             max timeout before reset: ~69.91ms
 
+  ==============================================================================
                      ##### How to use this driver #####
   ==============================================================================
+
+    *** Common driver usage ***
+    ===========================
+
   [..]
     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-    (+) Set the WWDG prescaler, refresh window and counter value 
+    (+) Set the WWDG prescaler, refresh window and counter value
         using HAL_WWDG_Init() function.
     (+) Start the WWDG using HAL_WWDG_Start() function.
-        When the WWDG is enabled the counter value should be configured to 
+        When the WWDG is enabled the counter value should be configured to
         a value greater than 0x40 to prevent generating an immediate reset.
-    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is 
+    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
         generated when the counter reaches 0x40, and then start the WWDG using
-        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can 
-        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
-        Once enabled, EWI interrupt cannot be disabled except by a system reset.          
+        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
+        add his own code by customization of callback HAL_WWDG_WakeupCallback.
+        Once enabled, EWI interrupt cannot be disabled except by a system reset.
     (+) Then the application program must refresh the WWDG counter at regular
         intervals during normal operation to prevent an MCU reset, using
         HAL_WWDG_Refresh() function. This operation must occur only when
         the counter is lower than the refresh window value already programmed.
-        
-     *** WWDG HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in WWDG HAL driver.
-       
-      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral 
+
+    *** Callback registration ***
+    =============================
+
+  [..]
+    The compilation define  USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+    the user to configure dynamically the driver callbacks. Use Functions
+    @ref HAL_WWDG_RegisterCallback() to register a user callback.
+
+    (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+        callbacks:
+        (++) EwiCallback : callback for Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
+    the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+    takes as parameters the HAL peripheral handle and the Callback ID.
+    This function allows to reset following callbacks:
+        (++) EwiCallback : callback for  Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+
+    [..]
+    When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+    corresponding legacy weak (surcharged) functions:
+    @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+    not been registered before.
+
+    [..]
+    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+    *** WWDG HAL driver macros list ***
+    ===================================
+    [..]
+      Below the list of most used macros in WWDG HAL driver.
+      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
-      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags 
-      (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wake-up interrupt 
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
 
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -104,53 +125,51 @@
   * @{
   */
 
+#ifdef HAL_WWDG_MODULE_ENABLED
 /** @defgroup WWDG WWDG
   * @brief WWDG HAL module driver.
   * @{
   */
 
-#ifdef HAL_WWDG_MODULE_ENABLED
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
+
 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
   * @{
   */
 
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions. 
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief    Initialization and Configuration functions.
   *
-@verbatim    
+@verbatim
   ==============================================================================
-          ##### Initialization and de-initialization functions #####
+          ##### Initialization and Configuration functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
-    (+) Initialize the WWDG according to the specified parameters 
-        in the WWDG_InitTypeDef and create the associated handle
-    (+) DeInitialize the WWDG peripheral
-    (+) Initialize the WWDG MSP
-    (+) DeInitialize the WWDG MSP 
- 
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the WWDG according to the specified
-  *         parameters in the WWDG_InitTypeDef and creates the associated handle.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
 {
   /* Check the WWDG handle allocation */
-  if(hwwdg == NULL)
+  if (hwwdg == NULL)
   {
     return HAL_ERROR;
   }
@@ -158,280 +177,221 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
   /* Check the parameters */
   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
-  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); 
-  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); 
-  
-  if(hwwdg->State == HAL_WWDG_STATE_RESET)
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+  /* Reset Callback pointers */
+  if (hwwdg->EwiCallback == NULL)
   {
-    /* Allocate lock resource and initialize it */
-    hwwdg->Lock = HAL_UNLOCKED;
-    /* Init the low level hardware */
-    HAL_WWDG_MspInit(hwwdg);
+    hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
   }
-  
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Set WWDG Prescaler and Window */
-  MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
-  /* Set WWDG Counter */
-  MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
 
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the WWDG peripheral. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
-{ 
-  /* Check the WWDG handle allocation */
-  if(hwwdg == NULL)
+  if (hwwdg->MspInitCallback == NULL)
   {
-    return HAL_ERROR;
+    hwwdg->MspInitCallback = HAL_WWDG_MspInit;
   }
 
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+  /* Init the low level hardware */
+  hwwdg->MspInitCallback(hwwdg);
+#else
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+#endif
 
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_WWDG_MspDeInit(hwwdg);
-  
-  /* Reset WWDG Control register */
-  hwwdg->Instance->CR  = (uint32_t)0x0000007F;
-  
-  /* Reset WWDG Configuration register */
-  hwwdg->Instance->CFR = (uint32_t)0x0000007F;
-  
-  /* Reset WWDG Status register */
-  hwwdg->Instance->SR  = 0; 
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hwwdg);
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+  /* Set WWDG Prescaler and Window */
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
 
   /* Return function status */
   return HAL_OK;
 }
 
+
 /**
-  * @brief  Initializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
   * @retval None
   */
 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_WWDG_MspInit could be implemented in the user file
    */
 }
 
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
 /**
-  * @brief  DeInitializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
+  * @brief  Register a User WWDG Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval status
   */
-__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
 {
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_MspDeInit could be implemented in the user file
-   */
-}
+  HAL_StatusTypeDef status = HAL_OK;
 
-/**
-  * @}
-  */
+  if (pCallback == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    switch (CallbackID)
+    {
+      case HAL_WWDG_EWI_CB_ID:
+        hwwdg->EwiCallback = pCallback;
+        break;
 
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions 
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-                       ##### IO operation functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Start the WWDG.
-    (+) Refresh the WWDG.
-    (+) Handle WWDG interrupt request. 
+      case HAL_WWDG_MSPINIT_CB_ID:
+        hwwdg->MspInitCallback = pCallback;
+        break;
 
-@endverbatim
-  * @{
-  */
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
 
-/**
-  * @brief  Starts the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
-  /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
+
 /**
-  * @brief  Starts the WWDG with interrupt enabled.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
+  * @brief  Unregister a WWDG Callback
+  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @retval status
   */
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
 {
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
+  HAL_StatusTypeDef status = HAL_OK;
 
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
+  switch (CallbackID)
+  {
+    case HAL_WWDG_EWI_CB_ID:
+      hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+      break;
 
-  /* Enable the Early Wakeup Interrupt */ 
-  __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
+    case HAL_WWDG_MSPINIT_CB_ID:
+      hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+      break;
 
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
+    default:
+      status = HAL_ERROR;
+      break;
+  }
 
-  /* Return function status */
-  return HAL_OK;
+  return status;
 }
+#endif
 
 /**
-  * @brief  Refreshes the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @param  Counter: value of counter to put in WWDG counter
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
 {
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  
   /* Write to WWDG CR the WWDG Counter value to refresh with */
-  MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
   /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Handles WWDG interrupt request.
-  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations 
-  *         or data logging must be performed before the actual reset is generated. 
-  *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
-  *         When the downcounter reaches the value 0x40, and EWI interrupt is 
-  *         generated and the corresponding Interrupt Service Routine (ISR) can 
-  *         be used to trigger specific actions (such as communications or data 
-  *         logging), before resetting the device. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
   * @retval None
   */
 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{ 
+{
   /* Check if Early Wakeup Interrupt is enable */
-  if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+  if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
   {
     /* Check if WWDG Early Wakeup Interrupt occurred */
-    if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+    if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
     {
-      /* Early Wakeup callback */ 
-      HAL_WWDG_WakeupCallback(hwwdg);
-      
-      /* Change WWDG peripheral state */
-      hwwdg->State = HAL_WWDG_STATE_READY; 
-      
       /* Clear the WWDG Early Wakeup flag */
       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hwwdg);
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+      /* Early Wakeup registered callback */
+      hwwdg->EwiCallback(hwwdg);
+#else
+      /* Early Wakeup callback */
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif
     }
   }
-} 
-
-/**
-  * @brief  Early Wakeup WWDG callback.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_WakeupCallback could be implemented in the user file
-   */
 }
 
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
 
 /**
-  * @brief  Returns the WWDG state.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL state
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
   */
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
 {
-  return hwwdg->State;
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_fsmc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_fsmc.c
index 36719a34..51872955 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_fsmc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_fsmc.c
@@ -2,74 +2,56 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_fsmc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   FSMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
+  *
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
   *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                         ##### FSMC peripheral features #####
-  ==============================================================================                  
-    [..] The Flexible static memory controller (FSMC) includes two memory controllers:
-         (+) The NOR/PSRAM memory controller
-         (+) The NAND/PC Card memory controller
-       
-    [..] The FSMC functional block makes the interface with synchronous and asynchronous static
-         memories and 16-bit PC memory cards. Its main purposes are:
-         (+) to translate AHB transactions into the appropriate external device protocol.
-         (+) to meet the access time requirements of the external memory devices.
-   
-    [..] All external memories share the addresses, data and control signals with the controller.
-         Each external device is accessed by means of a unique Chip Select. The FSMC performs
-         only one access at a time to an external device.
-         The main features of the FSMC controller are the following:
-          (+) Interface with static-memory mapped devices including:
-             (++) Static random access memory (SRAM).
-             (++) Read-only memory (ROM).
-             (++) NOR Flash memory/OneNAND Flash memory.
-             (++) PSRAM (4 memory banks).
-             (++) 16-bit PC Card compatible devices.
-             (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
-                  data.
-          (+) Independent Chip Select control for each memory bank.
-          (+) Independent configuration for each memory bank.          
-        
+  ==============================================================================
+  [..] The Flexible memory controller (FSMC) includes following memory controllers:
+       (+) The NOR/PSRAM memory controller
+       (+) The NAND/PC Card memory controller
+
+  [..] The FSMC functional block makes the interface with synchronous and asynchronous static
+       memories and 16-bit PC memory cards. Its main purposes are:
+       (+) to translate AHB transactions into the appropriate external device protocol
+       (+) to meet the access time requirements of the external memory devices
+
+  [..] All external memories share the addresses, data and control signals with the controller.
+       Each external device is accessed by means of a unique Chip Select. The FSMC performs
+       only one access at a time to an external device.
+       The main features of the FSMC controller are the following:
+        (+) Interface with static-memory mapped devices including:
+           (++) Static random access memory (SRAM)
+           (++) Read-only memory (ROM)
+           (++) NOR Flash memory/OneNAND Flash memory
+           (++) PSRAM (4 memory banks)
+           (++) 16-bit PC Card compatible devices
+           (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+                data
+        (+) Independent Chip Select control for each memory bank
+        (+) Independent configuration for each memory bank
+
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -77,40 +59,111 @@
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
+#if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_PCCARD_MODULE_ENABLED )
 
 /** @defgroup FSMC_LL  FSMC Low Layer
   * @brief FSMC driver modules
   * @{
   */
-
-#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
-
+	
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/    
+
+/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
+  * @{
+  */
+
+/* ----------------------- FSMC registers bit mask --------------------------- */
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK    ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD  |\
+                                      FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\
+                                      FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT  |\
+                                      FSMC_BTR1_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#if defined(FSMC_BWTR1_BUSTURN)
+#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD  |\
+                                      FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\
+                                      FSMC_BWTR1_ACCMOD))
+#else
+#define BWTR_CLEAR_MASK   ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD  |\
+                                      FSMC_BWTR1_DATAST | FSMC_BWTR1_ACCMOD))
+#endif /* FSMC_BWTR1_BUSTURN */
+
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK    ((uint32_t)(FSMC_PCR3_PWAITEN | FSMC_PCR3_PBKEN  | \
+                                      FSMC_PCR3_PTYP    | FSMC_PCR3_PWID   | \
+                                      FSMC_PCR3_ECCEN   | FSMC_PCR3_TCLR   | \
+                                      FSMC_PCR3_TAR     | FSMC_PCR3_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK   ((uint32_t)(FSMC_PMEM3_MEMSET3  | FSMC_PMEM3_MEMWAIT3 |\
+                                      FSMC_PMEM3_MEMHOLD3 | FSMC_PMEM3_MEMHIZ3))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK   ((uint32_t)(FSMC_PATT3_ATTSET3  | FSMC_PATT3_ATTWAIT3 |\
+                                      FSMC_PATT3_ATTHOLD3 | FSMC_PATT3_ATTHIZ3))
+
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR4_CLEAR_MASK   ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN  | \
+                                      FSMC_PCR4_PTYP    | FSMC_PCR4_PWID   | \
+                                      FSMC_PCR4_ECCEN   | FSMC_PCR4_TCLR   | \
+                                      FSMC_PCR4_TAR     | FSMC_PCR4_ECCPS))
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM4_CLEAR_MASK  ((uint32_t)(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 |\
+                                      FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT4_CLEAR_MASK  ((uint32_t)(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 |\
+                                      FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK   ((uint32_t)(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | \
+                                      FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
+
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup FSMC_LL_Private_Functions
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
   * @{
   */
 
-/** @addtogroup FSMC_LL_NORSRAM
-  * @brief    NORSRAM Controller functions 
+
+/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
+  * @brief  NORSRAM Controller functions
   *
-  @verbatim 
-  ==============================================================================   
+  @verbatim
+  ==============================================================================
                    ##### How to use NORSRAM device driver #####
   ==============================================================================
- 
-  [..] 
+
+  [..]
     This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
     to run the NORSRAM external devices.
-      
-    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() 
+
+    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
     (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
     (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
-    (+) FSMC NORSRAM bank extended timing configuration using the function 
+    (+) FSMC NORSRAM bank extended timing configuration using the function
         FSMC_NORSRAM_Extended_Timing_Init()
     (+) FSMC NORSRAM bank enable/disable write operation using the functions
         FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
@@ -118,36 +171,37 @@
 @endverbatim
   * @{
   */
-       
-/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
-  * @brief    Initialization and Configuration functions 
+
+/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ==============================================================================
               ##### Initialization and de_initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
     (+) Initialize and configure the FSMC NORSRAM interface
-    (+) De-initialize the FSMC NORSRAM interface 
-    (+) Configure the FSMC clock and associated GPIOs    
- 
+    (+) De-initialize the FSMC NORSRAM interface
+    (+) Configure the FSMC clock and associated GPIOs
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initialize the FSMC_NORSRAM device according to the specified
   *         control parameters in the FSMC_NORSRAM_InitTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Init: Pointer to NORSRAM Initialization structure   
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Init Pointer to NORSRAM Initialization structure
   * @retval HAL status
   */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
-{ 
-  uint32_t tmpr = 0;
-    
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
+{
+  uint32_t flashaccess;
+
   /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
   assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
   assert_param(IS_FSMC_MUX(Init->DataAddressMux));
   assert_param(IS_FSMC_MEMORY(Init->MemoryType));
@@ -161,47 +215,60 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_
   assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
   assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
   assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
-  
-  /* Get the BTCR register value */
-  tmpr = Device->BTCR[Init->NSBank];
-
-  /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
-           WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
-  tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN     | FSMC_BCR1_MUXEN    | FSMC_BCR1_MTYP     | \
-                       FSMC_BCR1_MWID      | FSMC_BCR1_FACCEN   | FSMC_BCR1_BURSTEN  | \
-                       FSMC_BCR1_WAITPOL   | FSMC_BCR1_WRAPMOD  | FSMC_BCR1_WAITCFG  | \
-                       FSMC_BCR1_WREN      | FSMC_BCR1_WAITEN   | FSMC_BCR1_EXTMOD   | \
-                       FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
+
+  /* Disable NORSRAM Device */
+  __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
   /* Set NORSRAM device control parameters */
-  tmpr |= (uint32_t)(Init->DataAddressMux       |\
-                     Init->MemoryType           |\
-                     Init->MemoryDataWidth      |\
-                     Init->BurstAccessMode      |\
-                     Init->WaitSignalPolarity   |\
-                     Init->WrapMode             |\
-                     Init->WaitSignalActive     |\
-                     Init->WriteOperation       |\
-                     Init->WaitSignal           |\
-                     Init->ExtendedMode         |\
-                     Init->AsynchronousWait     |\
-                     Init->WriteBurst
-                     );
-                    
-  if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
+  if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
+  {
+    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
+  }
+  else
   {
-    tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
+    flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
   }
-  
-  Device->BTCR[Init->NSBank] = tmpr;                   
-  
+
+  MODIFY_REG(Device->BTCR[Init->NSBank],
+             (FSMC_BCR1_MBKEN                |
+              FSMC_BCR1_MUXEN                |
+              FSMC_BCR1_MTYP                 |
+              FSMC_BCR1_MWID                 |
+              FSMC_BCR1_FACCEN               |
+              FSMC_BCR1_BURSTEN              |
+              FSMC_BCR1_WAITPOL              |
+              FSMC_BCR1_WRAPMOD              |
+              FSMC_BCR1_WAITCFG              |
+              FSMC_BCR1_WREN                 |
+              FSMC_BCR1_WAITEN               |
+              FSMC_BCR1_EXTMOD               |
+              FSMC_BCR1_ASYNCWAIT            |
+              FSMC_BCR1_CBURSTRW             |
+              0),
+             (flashaccess                   |
+              Init->DataAddressMux          |
+              Init->MemoryType              |
+              Init->MemoryDataWidth         |
+              Init->BurstAccessMode         |
+              Init->WaitSignalPolarity      |
+              Init->WrapMode                |
+              Init->WaitSignalActive        |
+              Init->WriteOperation          |
+              Init->WaitSignal              |
+              Init->ExtendedMode            |
+              Init->AsynchronousWait        |
+              Init->WriteBurst              |
+              0));
+
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitialize the FSMC_NORSRAM peripheral 
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
-  * @param  Bank: NORSRAM bank number  
+  * @brief  DeInitialize the FSMC_NORSRAM peripheral
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  ExDevice Pointer to NORSRAM extended mode device instance
+  * @param  Bank NORSRAM bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -209,42 +276,42 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM
   /* Check the parameters */
   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
   assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
 
   /* Disable the FSMC_NORSRAM device */
   __FSMC_NORSRAM_DISABLE(Device, Bank);
-  
+
   /* De-initialize the FSMC_NORSRAM device */
   /* FSMC_NORSRAM_BANK1 */
-  if(Bank == FSMC_NORSRAM_BANK1)
+  if (Bank == FSMC_NORSRAM_BANK1)
   {
-    Device->BTCR[Bank] = 0x000030DB;    
+    Device->BTCR[Bank] = 0x000030DBU;
   }
   /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
   else
-  {   
-    Device->BTCR[Bank] = 0x000030D2; 
+  {
+    Device->BTCR[Bank] = 0x000030D2U;
   }
-  
-  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
-  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
-   
+
+  Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+  ExDevice->BWTR[Bank]   = 0x0FFFFFFFU;
+
   return HAL_OK;
 }
 
-
 /**
   * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
   *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 {
-  uint32_t tmpr = 0;
-  
+
   /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
   assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
@@ -252,86 +319,71 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO
   assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
   assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
   assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-  
-  /* Get the BTCR register value */
-  tmpr = Device->BTCR[Bank + 1];
-
-  /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
-  tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET  | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
-                       FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
-                       FSMC_BTR1_ACCMOD));
-  
-  /* Set FSMC_NORSRAM device timing parameters */  
-  tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\
-                    ((Timing->AddressHoldTime) << 4)          |\
-                    ((Timing->DataSetupTime) << 8)            |\
-                    ((Timing->BusTurnAroundDuration) << 16)   |\
-                    (((Timing->CLKDivision)-1) << 20)         |\
-                    (((Timing->DataLatency)-2) << 24)         |\
-                    (Timing->AccessMode));
-  
-  Device->BTCR[Bank + 1] = tmpr; 
-  
-  return HAL_OK;   
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+  /* Set FSMC_NORSRAM device timing parameters */
+  MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                                  |
+                                                      ((Timing->AddressHoldTime)        << FSMC_BTR1_ADDHLD_Pos)  |
+                                                      ((Timing->DataSetupTime)          << FSMC_BTR1_DATAST_Pos)  |
+                                                      ((Timing->BusTurnAroundDuration)  << FSMC_BTR1_BUSTURN_Pos) |
+                                                      (((Timing->CLKDivision) - 1U)     << FSMC_BTR1_CLKDIV_Pos)  |
+                                                      (((Timing->DataLatency) - 2U)     << FSMC_BTR1_DATLAT_Pos)  |
+                                                      (Timing->AccessMode)));
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
   *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Timing Pointer to NORSRAM Timing structure
+  * @param  Bank NORSRAM bank number
+  * @param  ExtendedMode FSMC Extended Mode
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_EXTENDED_MODE_DISABLE
+  *            @arg FSMC_EXTENDED_MODE_ENABLE
   * @retval HAL status
   */
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 {
-  uint32_t tmpr = 0;
-  
+  /* Check the parameters */
+  assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
+
   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-  if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
+  if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
   {
-    /* Check the parameters */  
+    /* Check the parameters */
+    assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
     assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
     assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-    assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
-    assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
     assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-  
-    /* Get the BWTR register value */
-    tmpr = Device->BWTR[Bank];
-    
-    /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
-    tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET  | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
-                         FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
-                         FSMC_BWTR1_ACCMOD));
-
-    tmpr |= (uint32_t)(Timing->AddressSetupTime                 |\
-                     ((Timing->AddressHoldTime) << 4)          |\
-                     ((Timing->DataSetupTime) << 8)            |\
-                     ((Timing->BusTurnAroundDuration) << 16)   |\
-                     (((Timing->CLKDivision)-1) << 20)         |\
-                     (((Timing->DataLatency)-2) << 24)         |\
-                     (Timing->AccessMode));
-    
-    Device->BWTR[Bank] = tmpr; 
+    assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
+    /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+    MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                                    |
+                                                     ((Timing->AddressHoldTime)        << FSMC_BWTR1_ADDHLD_Pos)  |
+                                                     ((Timing->DataSetupTime)          << FSMC_BWTR1_DATAST_Pos)  |
+                                                     Timing->AccessMode                                          |
+                                                     ((Timing->BusTurnAroundDuration)  << FSMC_BWTR1_BUSTURN_Pos)));
   }
-  else                                        
+  else
   {
-    Device->BWTR[Bank] = 0x0FFFFFFF;
-  }   
-  
-  return HAL_OK;  
+    Device->BWTR[Bank] = 0x0FFFFFFFU;
+  }
+
+  return HAL_OK;
 }
 /**
   * @}
   */
-  
+
 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
-  *  @brief   management functions 
-  *
-@verbatim   
+ *  @brief   management functions
+ *
+@verbatim
   ==============================================================================
                       ##### FSMC_NORSRAM Control functions #####
   ==============================================================================
@@ -342,34 +394,43 @@ HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD
 @endverbatim
   * @{
   */
-    
+
 /**
   * @brief  Enables dynamically FSMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 {
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
   /* Enable write operation */
-  Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; 
+  SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically FSMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
+  * @param  Device Pointer to NORSRAM device instance
+  * @param  Bank NORSRAM bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{ 
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
+  assert_param(IS_FSMC_NORSRAM_BANK(Bank));
+
   /* Disable write operation */
-  Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; 
+  CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
 
-  return HAL_OK;  
+  return HAL_OK;
 }
+
 /**
   * @}
   */
@@ -377,578 +438,521 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi
 /**
   * @}
   */
-  
-/** @addtogroup FSMC_LL_NAND
-  * @brief    NAND Controller functions 
+
+
+/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
+  * @brief    NAND Controller functions
   *
-  @verbatim 
-  ==============================================================================   
+  @verbatim
+  ==============================================================================
                     ##### How to use NAND device driver #####
   ==============================================================================
   [..]
     This driver contains a set of APIs to interface with the FSMC NAND banks in order
     to run the NAND external devices.
-  
-    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() 
+
+    (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
     (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
-    (+) FSMC NAND bank common space timing configuration using the function 
+    (+) FSMC NAND bank common space timing configuration using the function
         FSMC_NAND_CommonSpace_Timing_Init()
-    (+) FSMC NAND bank attribute space timing configuration using the function 
+    (+) FSMC NAND bank attribute space timing configuration using the function
         FSMC_NAND_AttributeSpace_Timing_Init()
     (+) FSMC NAND bank enable/disable ECC correction feature using the functions
         FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
-    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()  
+    (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
 
 @endverbatim
   * @{
   */
-    
-/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
+
+/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
   ==============================================================================
               ##### Initialization and de_initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
     (+) Initialize and configure the FSMC NAND interface
-    (+) De-initialize the FSMC NAND interface 
+    (+) De-initialize the FSMC NAND interface
     (+) Configure the FSMC clock and associated GPIOs
-        
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the FSMC_NAND device according to the specified
   *         control parameters in the FSMC_NAND_HandleTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Init: Pointer to NAND Initialization structure
+  * @param  Device Pointer to NAND device instance
+  * @param  Init Pointer to NAND Initialization structure
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
 {
-  uint32_t tmpr  = 0; 
-    
   /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
   assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
   assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
   assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
   assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
-  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));   
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
 
-    if(Init->NandBank == FSMC_NAND_BANK2)
-  {
-    /* Get the NAND bank 2 register value */
-    tmpr = Device->PCR2;
-  }
-  else
-  {
-    /* Get the NAND bank 3 register value */
-    tmpr = Device->PCR3;
-  }
-  
-  /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
-  tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN  | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
-                       FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
-                       FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));  
-  
   /* Set NAND device control parameters */
-  tmpr |= (uint32_t)(Init->Waitfeature                |\
-                     FSMC_PCR_MEMORY_TYPE_NAND         |\
-                     Init->MemoryDataWidth            |\
-                     Init->EccComputation             |\
-                     Init->ECCPageSize                |\
-                     ((Init->TCLRSetupTime) << 9)     |\
-                     ((Init->TARSetupTime) << 13));   
-  
-  if(Init->NandBank == FSMC_NAND_BANK2)
+  if (Init->NandBank == FSMC_NAND_BANK2)
   {
     /* NAND bank 2 registers configuration */
-    Device->PCR2  = tmpr;
+    MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FSMC_PCR3_TCLR_Pos)  |
+                                              ((Init->TARSetupTime)  << FSMC_PCR3_TAR_Pos)));
   }
   else
   {
     /* NAND bank 3 registers configuration */
-    Device->PCR3  = tmpr;
+    MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |
+                                              FSMC_PCR_MEMORY_TYPE_NAND                               |
+                                              Init->MemoryDataWidth                                  |
+                                              Init->EccComputation                                   |
+                                              Init->ECCPageSize                                      |
+                                              ((Init->TCLRSetupTime) << FSMC_PCR3_TCLR_Pos)  |
+                                              ((Init->TARSetupTime)  << FSMC_PCR3_TAR_Pos)));
   }
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the FSMC_NAND Common space Timing according to the specified
   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Timing: Pointer to NAND timing structure
-  * @param  Bank: NAND bank number   
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 {
-  uint32_t tmpr = 0;  
-  
   /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
-  
-  if(Bank == FSMC_NAND_BANK2)
-  {
-    /* Get the NAND bank 2 register value */
-    tmpr = Device->PMEM2;
-  }
-  else
-  {
-    /* Get the NAND bank 3 register value */
-    tmpr = Device->PMEM3;
-  } 
-  
-  /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
-  tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2  | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
-                       FSMC_PMEM2_MEMHIZ2));
-  
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
   /* Set FSMC_NAND device timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                  |\
-                       ((Timing->WaitSetupTime) << 8)     |\
-                       ((Timing->HoldSetupTime) << 16)    |\
-                       ((Timing->HiZSetupTime) << 24)
-                       );
-                            
-  if(Bank == FSMC_NAND_BANK2)
+  if (Bank == FSMC_NAND_BANK2)
   {
     /* NAND bank 2 registers configuration */
-    Device->PMEM2 = tmpr;
+    MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PMEM3_MEMWAIT3_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PMEM3_MEMHOLD3_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PMEM3_MEMHIZ3_Pos)));
   }
   else
   {
     /* NAND bank 3 registers configuration */
-    Device->PMEM3 = tmpr;
-  }  
-  
-  return HAL_OK;  
+    MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PMEM3_MEMWAIT3_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PMEM3_MEMHOLD3_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PMEM3_MEMHIZ3_Pos)));
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Initializes the FSMC_NAND Attribute space Timing according to the specified
   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to NAND device instance
-  * @param  Timing: Pointer to NAND timing structure
-  * @param  Bank: NAND bank number 
+  * @param  Device Pointer to NAND device instance
+  * @param  Timing Pointer to NAND timing structure
+  * @param  Bank NAND bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 {
-  uint32_t tmpr = 0;  
-  
-  /* Check the parameters */  
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
-  
-  if(Bank == FSMC_NAND_BANK2)
-  {
-    /* Get the NAND bank 2 register value */
-    tmpr = Device->PATT2;
-  }
-  else
-  {
-    /* Get the NAND bank 3 register value */
-    tmpr = Device->PATT3;
-  } 
-  
-  /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
-  tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2  | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
-                       FSMC_PATT2_ATTHIZ2));
-  
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
   /* Set FSMC_NAND device timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                  |\
-                       ((Timing->WaitSetupTime) << 8)     |\
-                       ((Timing->HoldSetupTime) << 16)    |\
-                       ((Timing->HiZSetupTime) << 24)
-                       );
-                       
-  if(Bank == FSMC_NAND_BANK2)
+  if (Bank == FSMC_NAND_BANK2)
   {
     /* NAND bank 2 registers configuration */
-    Device->PATT2 = tmpr;
+    MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PATT3_ATTWAIT3_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PATT3_ATTHOLD3_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PATT3_ATTHIZ3_Pos)));
   }
   else
   {
     /* NAND bank 3 registers configuration */
-    Device->PATT3 = tmpr;
-  }   
-  
+    MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                             |
+                                                ((Timing->WaitSetupTime) << FSMC_PATT3_ATTWAIT3_Pos) |
+                                                ((Timing->HoldSetupTime) << FSMC_PATT3_ATTHOLD3_Pos) |
+                                                ((Timing->HiZSetupTime)  << FSMC_PATT3_ATTHIZ3_Pos)));
+  }
+
   return HAL_OK;
 }
 
 /**
-  * @brief  DeInitializes the FSMC_NAND device 
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
+  * @brief  DeInitializes the FSMC_NAND device
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 {
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
   /* Disable the NAND Bank */
   __FSMC_NAND_DISABLE(Device, Bank);
- 
+
   /* De-initialize the NAND Bank */
-  if(Bank == FSMC_NAND_BANK2)
+  if (Bank == FSMC_NAND_BANK2)
   {
     /* Set the FSMC_NAND_BANK2 registers to their reset values */
-    Device->PCR2  = 0x00000018;
-    Device->SR2   = 0x00000040;
-    Device->PMEM2 = 0xFCFCFCFC;
-    Device->PATT2 = 0xFCFCFCFC;  
+    WRITE_REG(Device->PCR2,  0x00000018U);
+    WRITE_REG(Device->SR2,   0x00000040U);
+    WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
   }
-  /* FSMC_Bank3_NAND */  
+  /* FSMC_Bank3_NAND */
   else
   {
     /* Set the FSMC_NAND_BANK3 registers to their reset values */
-    Device->PCR3  = 0x00000018;
-    Device->SR3   = 0x00000040;
-    Device->PMEM3 = 0xFCFCFCFC;
-    Device->PATT3 = 0xFCFCFCFC; 
+    WRITE_REG(Device->PCR3,  0x00000018U);
+    WRITE_REG(Device->SR3,   0x00000040U);
+    WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
+    WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
   }
-  
+
   return HAL_OK;
 }
+
 /**
   * @}
   */
-  
-/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
-  *  @brief   management functions 
+
+/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
+  *  @brief   management functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
                        ##### FSMC_NAND Control functions #####
-  ==============================================================================  
+  ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control dynamically
     the FSMC NAND interface.
 
 @endverbatim
   * @{
-  */ 
-    
+  */
+
+
 /**
   * @brief  Enables dynamically FSMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
   * @retval HAL status
-  */    
-HAL_StatusTypeDef  FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+  */
+HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
 {
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
   /* Enable ECC feature */
-  if(Bank == FSMC_NAND_BANK2)
+  if (Bank == FSMC_NAND_BANK2)
   {
-    Device->PCR2 |= FSMC_PCR2_ECCEN;
+    SET_BIT(Device->PCR2, FSMC_PCR3_ECCEN);
   }
   else
   {
-    Device->PCR3 |= FSMC_PCR3_ECCEN;
-  } 
-  
-  return HAL_OK;  
+    SET_BIT(Device->PCR3, FSMC_PCR3_ECCEN);
+  }
+
+  return HAL_OK;
 }
 
+
 /**
   * @brief  Disables dynamically FSMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  Bank: NAND bank number
+  * @param  Device Pointer to NAND device instance
+  * @param  Bank NAND bank number
   * @retval HAL status
-  */  
-HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  
-{  
+  */
+HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
+  assert_param(IS_FSMC_NAND_BANK(Bank));
+
   /* Disable ECC feature */
-  if(Bank == FSMC_NAND_BANK2)
+  if (Bank == FSMC_NAND_BANK2)
   {
-    Device->PCR2 &= ~FSMC_PCR2_ECCEN;
+    CLEAR_BIT(Device->PCR2, FSMC_PCR3_ECCEN);
   }
   else
   {
-    Device->PCR3 &= ~FSMC_PCR3_ECCEN;
-  } 
+    CLEAR_BIT(Device->PCR3, FSMC_PCR3_ECCEN);
+  }
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @brief  Disables dynamically FSMC_NAND ECC feature.
-  * @param  Device: Pointer to NAND device instance
-  * @param  ECCval: Pointer to ECC value
-  * @param  Bank: NAND bank number
-  * @param  Timeout: Timeout wait value  
+  * @param  Device Pointer to NAND device instance
+  * @param  ECCval Pointer to ECC value
+  * @param  Bank NAND bank number
+  * @param  Timeout Timeout wait value
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 {
-  uint32_t tickstart = 0;
-  
-  /* Check the parameters */ 
-  assert_param(IS_FSMC_NAND_DEVICE(Device)); 
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_FSMC_NAND_DEVICE(Device));
   assert_param(IS_FSMC_NAND_BANK(Bank));
 
-  /* Get tick */ 
+  /* Get tick */
   tickstart = HAL_GetTick();
 
   /* Wait until FIFO is empty */
-  while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
+  while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
   {
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
         return HAL_TIMEOUT;
       }
-    }   
+    }
   }
-     
-  if(Bank == FSMC_NAND_BANK2)
-  {    
+
+  if (Bank == FSMC_NAND_BANK2)
+  {
     /* Get the ECCR2 register value */
     *ECCval = (uint32_t)Device->ECCR2;
   }
   else
-  {    
+  {
     /* Get the ECCR3 register value */
     *ECCval = (uint32_t)Device->ECCR3;
   }
 
-  return HAL_OK;  
+  return HAL_OK;
 }
 
 /**
   * @}
   */
-  
-/**
-  * @}
-  */
-    
+
+
 /** @addtogroup FSMC_LL_PCCARD
-  * @brief    PCCARD Controller functions 
+  * @brief    PCCARD Controller functions
   *
-  @verbatim 
-  ==============================================================================  
+  @verbatim
+  ==============================================================================
                     ##### How to use PCCARD device driver #####
   ==============================================================================
   [..]
     This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
     to run the PCCARD/compact flash external devices.
-  
-    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() 
+
+    (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
     (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
-    (+) FSMC PCCARD bank common space timing configuration using the function 
+    (+) FSMC PCCARD bank common space timing configuration using the function
         FSMC_PCCARD_CommonSpace_Timing_Init()
-    (+) FSMC PCCARD bank attribute space timing configuration using the function 
+    (+) FSMC PCCARD bank attribute space timing configuration using the function
         FSMC_PCCARD_AttributeSpace_Timing_Init()
-    (+) FSMC PCCARD bank IO space timing configuration using the function 
+    (+) FSMC PCCARD bank IO space timing configuration using the function
         FSMC_PCCARD_IOSpace_Timing_Init()
-       
 @endverbatim
   * @{
   */
-  
+
 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
-  *  @brief   Initialization and Configuration functions 
+  *  @brief    Initialization and Configuration functions
   *
-@verbatim    
+@verbatim
   ==============================================================================
               ##### Initialization and de_initialization functions #####
   ==============================================================================
-  [..]  
+  [..]
     This section provides functions allowing to:
     (+) Initialize and configure the FSMC PCCARD interface
-    (+) De-initialize the FSMC PCCARD interface 
+    (+) De-initialize the FSMC PCCARD interface
     (+) Configure the FSMC clock and associated GPIOs
-        
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initializes the FSMC_PCCARD device according to the specified
   *         control parameters in the FSMC_PCCARD_HandleTypeDef
-  * @param  Device: Pointer to PCCARD device instance
-  * @param  Init: Pointer to PCCARD Initialization structure   
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Init Pointer to PCCARD Initialization structure
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
 {
-  uint32_t tmpr = 0;
-  
-  /* Check the parameters */ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
   assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
   assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
-  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));     
-  
-  /* Get PCCARD control register value */
-  tmpr = Device->PCR4;
-  
-  /* Clear TAR, TCLR, PWAITEN and PWID bits */
-  tmpr &= ((uint32_t)~(FSMC_PCR4_TAR  | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
-                       FSMC_PCR4_PWID));
-  
+  assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
+
   /* Set FSMC_PCCARD device control parameters */
-  tmpr |= (uint32_t)(Init->Waitfeature               |\
-                     FSMC_NAND_PCC_MEM_BUS_WIDTH_16  |\
-                     (Init->TCLRSetupTime << 9)      |\
-                     (Init->TARSetupTime << 13));
-  
-  Device->PCR4 = tmpr;
-  
+  MODIFY_REG(Device->PCR4,
+             (FSMC_PCR4_PTYP                                          |
+              FSMC_PCR4_PWAITEN                                       |
+              FSMC_PCR4_PWID                                          |
+              FSMC_PCR4_TCLR                                          |
+              FSMC_PCR4_TAR),
+             (FSMC_PCR_MEMORY_TYPE_PCCARD                             |
+              Init->Waitfeature                                      |
+              FSMC_NAND_PCC_MEM_BUS_WIDTH_16                          |
+              (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos)   |
+              (Init->TARSetupTime  << FSMC_PCR4_TAR_Pos)));
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the FSMC_PCCARD Common space Timing according to the specified
   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to PCCARD device instance
-  * @param  Timing: Pointer to PCCARD timing structure 
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 {
-  uint32_t tmpr = 0;
-  
   /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 
-  /* Get PCCARD common space timing register value */
-  tmpr = Device->PMEM4;
-  
-  /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
-  tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4  | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
-                       FSMC_PMEM4_MEMHIZ4));
   /* Set PCCARD timing parameters */
-  tmpr |= (uint32_t)((Timing->SetupTime                 |\
-                    ((Timing->WaitSetupTime) << 8)     |\
-                    (Timing->HoldSetupTime) << 16)    |\
-                    ((Timing->HiZSetupTime) << 24));
-  
-  Device->PMEM4 = tmpr;
-  
-  return HAL_OK;  
+  MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FSMC_PMEM4_MEMHIZ4_Pos)));
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Initializes the FSMC_PCCARD Attribute space Timing according to the specified
   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to PCCARD device instance
-  * @param  Timing: Pointer to PCCARD timing structure  
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 {
-  uint32_t tmpr = 0;
-
-  /* Check the parameters */  
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 
-  /* Get PCCARD timing parameters */
-  tmpr = Device->PATT4;
-
-  /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
-  tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4  | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
-                       FSMC_PATT4_ATTHIZ4));
-  
   /* Set PCCARD timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                |\
-                   ((Timing->WaitSetupTime) << 8)     |\
-                   ((Timing->HoldSetupTime) << 16)    |\
-                   ((Timing->HiZSetupTime) << 24));
-  Device->PATT4 = tmpr; 
-                                        
+  MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
+             (Timing->SetupTime                                              |
+              ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos)  |
+              ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos)  |
+              ((Timing->HiZSetupTime)  << FSMC_PATT4_ATTHIZ4_Pos)));
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initializes the FSMC_PCCARD IO space Timing according to the specified
   *         parameters in the FSMC_NAND_PCC_TimingTypeDef
-  * @param  Device: Pointer to PCCARD device instance
-  * @param  Timing: Pointer to PCCARD timing structure  
+  * @param  Device Pointer to PCCARD device instance
+  * @param  Timing Pointer to PCCARD timing structure
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
 {
-  uint32_t tmpr = 0;
-  
-  /* Check the parameters */  
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
   assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
   assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
   assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
   assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
 
-  /* Get FSMC_PCCARD device timing parameters */
-  tmpr = Device->PIO4;
-
-  /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
-  tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4  | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
-                       FSMC_PIO4_IOHIZ4));
-  
   /* Set FSMC_PCCARD device timing parameters */
-  tmpr |= (uint32_t)(Timing->SetupTime                  |\
-                     ((Timing->WaitSetupTime) << 8)     |\
-                     ((Timing->HoldSetupTime) << 16)    |\
-                     ((Timing->HiZSetupTime) << 24));   
-  
-  Device->PIO4 = tmpr;
-  
+  MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
+             (Timing->SetupTime                                           |
+              (Timing->WaitSetupTime   << FSMC_PIO4_IOWAIT4_Pos) |
+              (Timing->HoldSetupTime   << FSMC_PIO4_IOHOLD4_Pos) |
+              (Timing->HiZSetupTime    << FSMC_PIO4_IOHIZ4_Pos)));
+
   return HAL_OK;
 }
-                                           
+
 /**
-  * @brief  DeInitializes the FSMC_PCCARD device 
-  * @param  Device: Pointer to PCCARD device instance
+  * @brief  DeInitializes the FSMC_PCCARD device
+  * @param  Device Pointer to PCCARD device instance
   * @retval HAL status
   */
 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
 {
+  /* Check the parameters */
+  assert_param(IS_FSMC_PCCARD_DEVICE(Device));
+
   /* Disable the FSMC_PCCARD device */
   __FSMC_PCCARD_DISABLE(Device);
-  
+
   /* De-initialize the FSMC_PCCARD device */
-  Device->PCR4    = 0x00000018; 
-  Device->SR4     = 0x00000000;	
-  Device->PMEM4   = 0xFCFCFCFC;
-  Device->PATT4   = 0xFCFCFCFC;
-  Device->PIO4    = 0xFCFCFCFC;
-  
+  Device->PCR4    = 0x00000018U;
+  Device->SR4     = 0x00000040U;
+  Device->PMEM4   = 0xFCFCFCFCU;
+  Device->PATT4   = 0xFCFCFCFCU;
+  Device->PIO4    = 0xFCFCFCFCU;
+
   return HAL_OK;
 }
-/**
-  * @}
-  */
 
 /**
   * @}
   */
 
+
 /**
   * @}
   */
-#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
 
 /**
   * @}
   */
 
+#endif /* HAL_NOR_MODULE_ENABLED */
 /**
   * @}
   */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
index e5f4a722..b060eae2 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_sdmmc.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_sdmmc.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   SDMMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -17,11 +15,11 @@
   ==============================================================================
                        ##### SDMMC peripheral features #####
   ==============================================================================        
-    [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
          devices.
-
-    [..] The SDIO features include the following:
+    
+    [..] The SDMMC features include the following:
          (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
              for three different databus modes: 1-bit (default), 4-bit and 8-bit
          (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
@@ -31,41 +29,40 @@
          (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
              Rev1.1)
          (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers.
-                 
+         (+) Data and command output enable signals to control external bidirectional drivers
    
                            ##### How to use this driver #####
   ==============================================================================
     [..]
       This driver is a considered as a driver of service for external devices drivers 
-      that interfaces with the SDIO peripheral.
-      According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs 
-      is used in the device's driver to perform SDIO operations and functionalities.
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+      is used in the device's driver to perform SDMMC operations and functionalities.
    
       This driver is almost transparent for the final user, it is only used to implement other
       functionalities of the external device.
    
     [..]
-      (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL 
-          (PLL48CLK). Before start working with SDIO peripheral make sure that the
+      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
           PLL is well configured.
-          The SDIO peripheral uses two clock signals:
-          (++) SDIO adapter clock (SDIOCLK = 48 MHz)
+          The SDMMC peripheral uses two clock signals:
+          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
           (++) APB2 bus clock (PCLK2)
        
-          -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
+          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
   
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
           peripheral.
 
-      (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) 
-          function and disable it using the function SDIO_PowerState_OFF(SDIOx).
+      (+) Enable the Power ON State using the SDIO_PowerState_ON() 
+          function and disable it using the function SDIO_PowerState_OFF().
                 
       (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
   
-      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) 
-          and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. 
+      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT() 
+          and __SDIO_DISABLE_IT() if you need to use interrupt mode. 
   
       (+) When using the DMA mode 
           (++) Configure the DMA in the MSP layer of the external device
@@ -74,7 +71,7 @@
                __SDIO_DMA_DISABLE().
   
       (+) To control the CPSM (Command Path State Machine) and send 
-          commands to the card use the SDIO_SendCommand(SDIOx), 
+          commands to the card use the SDIO_SendCommand(), 
           SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
           to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
           to the selected command to be sent.
@@ -87,12 +84,12 @@
   
           -@@- To check if the command is well received, read the SDIO_CMDRESP
               register using the SDIO_GetCommandResponse().
-              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+              The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
               SDIO_GetResponse() function.
   
       (+) To control the DPSM (Data Path State Machine) and send/receive 
            data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
-          SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
+          SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
   
     *** Read Operations ***
     =======================
@@ -100,14 +97,14 @@
       (#) First, user has to fill the data structure (pointer to
           SDIO_DataInitTypeDef) according to the selected data type to be received.
           The parameters that should be filled are:
-           (++) Data Timeout
+           (++) Data TimeOut
            (++) Data Length
            (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDIO)
+           (++) Data Transfer direction: should be from card (To SDMMC)
            (++) Data Transfer mode
            (++) DPSM Status (Enable or Disable)
                                      
-      (#) Configure the SDIO resources to receive the data from the card
+      (#) Configure the SDMMC resources to receive the data from the card
           according to selected transfer mode (Refer to Step 8, 9 and 10).
   
       (#) Send the selected Read command (refer to step 11).
@@ -120,47 +117,40 @@
      (#) First, user has to fill the data structure (pointer to
          SDIO_DataInitTypeDef) according to the selected data type to be received.
          The parameters that should be filled are:
-          (++) Data Timeout
+          (++) Data TimeOut
           (++) Data Length
           (++) Data Block size
           (++) Data Transfer direction:  should be to card (To CARD)
           (++) Data Transfer mode
           (++) DPSM Status (Enable or Disable)
   
-     (#) Configure the SDIO resources to send the data to the card according to 
+     (#) Configure the SDMMC resources to send the data to the card according to 
          selected transfer mode.
                      
      (#) Send the selected Write command.
                     
      (#) Use the SDIO flags/interrupts to check the transfer status.
+       
+    *** Command management operations ***
+    =====================================
+    [..]
+     (#) The commands used for Read/Write/Erase operations are managed in 
+         separate functions. 
+         Each function allows to send the needed command with the related argument,
+         then check the response.
+         By the same approach, you could implement a command and check the response.
   
   @endverbatim
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */ 
@@ -168,29 +158,38 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
 
+#if defined(SDIO)
+
 /** @addtogroup STM32F2xx_HAL_Driver
   * @{
   */
 
 /** @defgroup SDMMC_LL SDMMC Low Layer
-  * @brief Low layer module for SD and MMC driver
+  * @brief Low layer module for SD
   * @{
   */
 
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
+
+/* Exported functions --------------------------------------------------------*/
 
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
   * @{
   */
 
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions 
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
  *  @brief    Initialization and Configuration functions 
  *
 @verbatim    
@@ -204,15 +203,15 @@
   */
 
 /**
-  * @brief  Initializes the SDIO according to the specified
-  *         parameters in the SDIO_InitTypeDef and create the associated handle.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  Init: SDIO initialization structure   
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and create the associated handle.
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure   
   * @retval HAL status
   */
 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
 {
-  uint32_t tmpreg = 0; 
+  uint32_t tmpreg = 0;
 
   /* Check the parameters */
   assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
@@ -223,7 +222,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
   assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
   assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
   
-  /* Set SDIO configuration parameters */
+  /* Set SDMMC configuration parameters */
   tmpreg |= (Init.ClockEdge           |\
              Init.ClockBypass         |\
              Init.ClockPowerSave      |\
@@ -232,17 +231,18 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
              Init.ClockDiv
              ); 
   
-  /* Write to SDIO CLKCR */
+  /* Write to SDMMC CLKCR */
   MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
 
   return HAL_OK;
 }
 
+
 /**
   * @}
   */
 
-/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions 
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
  *  @brief   Data transfers functions 
  *
 @verbatim   
@@ -250,7 +250,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
                       ##### I/O operation functions #####
  ===============================================================================  
     [..]
-    This subsection provides a set of functions allowing to manage the SDIO data 
+    This subsection provides a set of functions allowing to manage the SDMMC data 
     transfers.
 
 @endverbatim
@@ -259,7 +259,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
 
 /**
   * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
+  * @param  SDIOx: Pointer to SDMMC register base
   * @retval HAL status
   */
 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -270,7 +270,7 @@ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
 
 /**
   * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
+  * @param  SDIOx: Pointer to SDMMC register base
   * @param  pWriteData: pointer to data to write
   * @retval HAL status
   */
@@ -294,7 +294,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
                       ##### Peripheral Control functions #####
  ===============================================================================  
     [..]
-    This subsection provides a set of functions allowing to control the SDIO data 
+    This subsection provides a set of functions allowing to control the SDMMC data 
     transfers.
 
 @endverbatim
@@ -302,21 +302,25 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
   */
 
 /**
-  * @brief  Set SDIO Power state to ON. 
-  * @param  SDIOx: Pointer to SDIO register base
+  * @brief  Set SDMMC Power state to ON. 
+  * @param  SDIOx: Pointer to SDMMC register base
   * @retval HAL status
   */
 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
 {  
   /* Set power state to ON */ 
   SDIOx->POWER = SDIO_POWER_PWRCTRL;
+
+  /* 1ms: required power up waiting time before starting the SD initialization
+  sequence */
+  HAL_Delay(2);
   
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
-  * @brief  Set SDIO Power state to OFF. 
-  * @param  SDIOx: Pointer to SDIO register base
+  * @brief  Set SDMMC Power state to OFF. 
+  * @param  SDIOx: Pointer to SDMMC register base
   * @retval HAL status
   */
 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
@@ -328,8 +332,8 @@ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
 }
 
 /**
-  * @brief  Get SDIO Power state. 
-  * @param  SDIOx: Pointer to SDIO register base
+  * @brief  Get SDMMC Power state. 
+  * @param  SDIOx: Pointer to SDMMC register base
   * @retval Power status of the controller. The returned value can be one of the 
   *         following values:
   *            - 0x00: Power OFF
@@ -342,33 +346,33 @@ uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
 }
 
 /**
-  * @brief  Configure the SDIO command path according to the specified parameters in
+  * @brief  Configure the SDMMC command path according to the specified parameters in
   *         SDIO_CmdInitTypeDef structure and send the command 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains 
-  *         the configuration information for the SDIO command
+  * @param  SDIOx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDIO_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDMMC command
   * @retval HAL status
   */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
 {
   uint32_t tmpreg = 0;
   
   /* Check the parameters */
-  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
-  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
-  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
-  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
+  assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(Command->Response));
+  assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDIO_CPSM(Command->CPSM));
 
-  /* Set the SDIO Argument value */
-  SDIOx->ARG = SDIO_CmdInitStruct->Argument;
+  /* Set the SDMMC Argument value */
+  SDIOx->ARG = Command->Argument;
 
-  /* Set SDIO command parameters */
-  tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex         |\
-                       SDIO_CmdInitStruct->Response         |\
-                       SDIO_CmdInitStruct->WaitForInterrupt |\
-                       SDIO_CmdInitStruct->CPSM);
+  /* Set SDMMC command parameters */
+  tmpreg |= (uint32_t)(Command->CmdIndex         |\
+                       Command->Response         |\
+                       Command->WaitForInterrupt |\
+                       Command->CPSM);
   
-  /* Write to SDIO CMD register */
+  /* Write to SDMMC CMD register */
   MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 
   
   return HAL_OK;  
@@ -376,7 +380,7 @@ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDI
 
 /**
   * @brief  Return the command index of last command for which response received
-  * @param  SDIOx: Pointer to SDIO register base
+  * @param  SDIOx: Pointer to SDMMC register base
   * @retval Command index of the last command response received
   */
 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
@@ -387,7 +391,8 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
 
 /**
   * @brief  Return the response received from the card for the last command
-  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  * @param  SDIOx: Pointer to SDMMC register base    
+  * @param  Response: Specifies the SDMMC response register. 
   *          This parameter can be one of the following values:
   *            @arg SDIO_RESP1: Response Register 1
   *            @arg SDIO_RESP2: Response Register 2
@@ -395,51 +400,51 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
   *            @arg SDIO_RESP4: Response Register 4  
   * @retval The Corresponding response register value
   */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
 {
-  __IO uint32_t tmp = 0;
+  uint32_t tmp;
 
   /* Check the parameters */
-  assert_param(IS_SDIO_RESP(SDIO_RESP));
-
+  assert_param(IS_SDIO_RESP(Response));
+  
   /* Get the response */
-  tmp = SDIO_RESP_ADDR + SDIO_RESP;
+  tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;
   
   return (*(__IO uint32_t *) tmp);
 }  
 
 /**
-  * @brief  Configure the SDIO data path according to the specified 
+  * @brief  Configure the SDMMC data path according to the specified 
   *         parameters in the SDIO_DataInitTypeDef.
   * @param  SDIOx: Pointer to SDIO register base  
-  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
-  *         that contains the configuration information for the SDIO command.
+  * @param  Data : pointer to a SDIO_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDMMC data.
   * @retval HAL status
   */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
 {
   uint32_t tmpreg = 0;
   
   /* Check the parameters */
-  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
-  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
-  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
-  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
-  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
+  assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDIO_DPSM(Data->DPSM));
 
-  /* Set the SDIO Data Timeout value */
-  SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
+  /* Set the SDMMC Data TimeOut value */
+  SDIOx->DTIMER = Data->DataTimeOut;
 
-  /* Set the SDIO DataLength value */
-  SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
+  /* Set the SDMMC DataLength value */
+  SDIOx->DLEN = Data->DataLength;
 
-  /* Set the SDIO data configuration parameters */
-  tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
-                       SDIO_DataInitStruct->TransferDir   |\
-                       SDIO_DataInitStruct->TransferMode  |\
-                       SDIO_DataInitStruct->DPSM);
+  /* Set the SDMMC data configuration parameters */
+  tmpreg |= (uint32_t)(Data->DataBlockSize |\
+                       Data->TransferDir   |\
+                       Data->TransferMode  |\
+                       Data->DPSM);
   
-  /* Write to SDIO DCTRL */
+  /* Write to SDMMC DCTRL */
   MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
 
   return HAL_OK;
@@ -466,21 +471,22 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
   return (SDIOx->FIFO);
 }
 
-
 /**
   * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  * @param  SDIOx: Pointer to SDIO register base   
+  * @param  SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
   *          This parameter can be:
-  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
-  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
+  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
   * @retval None
   */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
 {
   /* Check the parameters */
   assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-  
-  *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
   
   return HAL_OK;  
 }
@@ -489,11 +495,1019 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
   * @}
   */
 
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                   ##### Commands management functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send the Data Block Lenght command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Single Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Read Multi Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Single Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Write Multi Block command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command for SD and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command for SD and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Start Address Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the End Address Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Erase command and check the response
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Set Block Size for Card */ 
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Stop Transfer command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD12 STOP_TRANSMISSION  */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Select Deselect command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  addr: Address of the card to be selected  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+  sdmmc_cmdinit.Argument         = (uint32_t)Addr;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Go Idle State command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_NO;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdError(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Operating Condition command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD8 to verify SD card interface operating condition */
+  /* Argument: - [31:12]: Reserved (shall be set to '0')
+  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+  - [7:0]: Check Pattern (recommended 0xAA) */
+  /* CMD Response: R7 */
+  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp7(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Application command to verify that that the next command 
+  *         is an application specific com-mand rather than a standard command
+  *         and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  /* If there is a HAL_ERROR, it is a MMC card, else
+  it is a SD card: SD card 2.0 (voltage range mismatch)
+     or SD card 1.x */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the command asking the accessed card to send its operating 
+  *         condition register (OCR)
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Bus Width command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  BusWidth: BusWidth
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send SCR command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD51 SD_APP_SEND_SCR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CID command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD2 ALL_SEND_CID */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD9 SEND_CSD */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Send CSD command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  pRCA: Card RCA  
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD3 SD_CMD_SET_REL_ADDR */
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @param  Argument: Command Argument
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Send the Status register command and check the response.
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = 0U;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Sends host capacity support information and activates the card's 
+  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+  return errorstate;
+}
+
+/**
+  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+  * @param  SDIOx: Pointer to SDIO register base 
+  * @parame Argument: Argument used for the command
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+  SDIO_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+  
+  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
+  /* CMD Response: R1 */
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
+  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
+  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+  
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
+
+  return errorstate;
+}
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/  
+/** @addtogroup SD_Private_Functions
+  * @{
+  */
+    
+/**
+  * @brief  Checks for error conditions for CMD0.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
+{
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    
+  }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R1 response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index  
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+  
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The Timeout is expressed in ms */
+  register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* We have received response, retrieve it for analysis  */
+  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+  
+  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+  {
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+  {
+    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+  }
+  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+  {
+    return SDMMC_ERROR_ADDR_MISALIGNED;
+  }
+  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+  {
+    return SDMMC_ERROR_BLOCK_LEN_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+  {
+    return SDMMC_ERROR_ERASE_SEQ_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+  {
+    return SDMMC_ERROR_BAD_ERASE_PARAM;
+  }
+  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+  {
+    return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+  }
+  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+  {
+    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+  {
+    return SDMMC_ERROR_CARD_ECC_FAILED;
+  }
+  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+  {
+    return SDMMC_ERROR_CC_ERR;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+  {
+    return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+  {
+    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+  }
+  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+  {
+    return SDMMC_ERROR_CID_CSD_OVERWRITE;
+  }
+  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+  {
+    return SDMMC_ERROR_WP_ERASE_SKIP;
+  }
+  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+  {
+    return SDMMC_ERROR_CARD_ECC_DISABLED;
+  }
+  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+  {
+    return SDMMC_ERROR_ERASE_RESET;
+  }
+  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+  {
+    return SDMMC_ERROR_AKE_SEQ_ERR;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R2 (CID or CSD) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* No error flag set */
+    /* Clear all the static flags */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  }
+
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R3 (OCR) response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else
+  {  
+    /* Clear all the static flags */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  }
+  
+  return SDMMC_ERROR_NONE;
+}
+
+/**
+  * @brief  Checks for error conditions for R6 (RCA) response.
+  * @param  hsd: SD handle
+  * @param  SD_CMD: The sent command index
+  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
+  *         address RCA   
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+  uint32_t response_r1;
+  uint32_t sta_reg;
+
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  /* Check response received is of desired command */
+  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+  {
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  
+  /* Clear all the static flags */
+  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
+  
+  /* We have received response, retrieve it.  */
+  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+  
+  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+  {
+    *pRCA = (uint16_t) (response_r1 >> 16);
+    
+    return SDMMC_ERROR_NONE;
+  }
+  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+  {
+    return SDMMC_ERROR_ILLEGAL_CMD;
+  }
+  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+  {
+    return SDMMC_ERROR_COM_CRC_FAILED;
+  }
+  else
+  {
+    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+  }
+}
+
+/**
+  * @brief  Checks for error conditions for R7 response.
+  * @param  hsd: SD handle
+  * @retval SD Card error state
+  */
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
+{
+  uint32_t sta_reg;
+  /* 8 is the number of required instructions cycles for the below loop statement.
+  The SDIO_CMDTIMEOUT is expressed in ms */
+  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+  
+  do
+  {
+    if (count-- == 0U)
+    {
+      return SDMMC_ERROR_TIMEOUT;
+    }
+    sta_reg = SDIOx->STA;
+  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
+         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
+    
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+    
+    return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+  }
+  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+    
+    return SDMMC_ERROR_CMD_CRC_FAIL;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+  
+  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
+  {
+    /* Card is SD V2.0 compliant */
+    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+  }
+  
+  return SDMMC_ERROR_NONE;
+  
+}
+
 /**
   * @}
   */
 
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
+#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
 /**
   * @}
   */
@@ -502,4 +1516,6 @@ HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
   * @}
   */
 
+#endif /* SDIO */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usb.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usb.c
index 074c9f00..884a450b 100644
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usb.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usb.c
@@ -2,24 +2,22 @@
   ******************************************************************************
   * @file    stm32f2xx_ll_usb.c
   * @author  MCD Application Team
-  * @version V1.1.0
-  * @date    09-October-2015
   * @brief   USB Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
+  *
+  *          This file provides firmware functions to manage the following
   *          functionalities of the USB Peripheral Controller:
   *           + Initialization/de-initialization functions
   *           + I/O operation functions
-  *           + Peripheral Control functions 
+  *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
   ==============================================================================
     [..]
       (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-  
+
       (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
 
       (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@@ -28,32 +26,16 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f2xx_hal.h"
@@ -63,77 +45,161 @@
   */
 
 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
-
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
 
 /* Exported functions --------------------------------------------------------*/
-
-/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
+/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
   * @{
   */
 
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
  ===============================================================================
-              ##### Initialization/de-initialization functions #####
+                      ##### Initialization/de-initialization functions #####
  ===============================================================================
-    [..]  This section provides functions allowing to:
- 
+
 @endverbatim
   * @{
   */
 
 /**
   * @brief  Initializes the USB Core
-  * @param  USBx: USB Instance
-  * @param  cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+  * @param  USBx USB Instance
+  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains
   *         the configuration information for the specified USBx peripheral.
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
 {
+  HAL_StatusTypeDef ret;
+
   if (cfg.phy_itface == USB_OTG_ULPI_PHY)
   {
-    
     USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
 
     /* Init The ULPI Interface */
     USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-   
+
     /* Select vbus source */
     USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-    if(cfg.use_external_vbus == 1)
+    if (cfg.use_external_vbus == 1U)
     {
       USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
     }
     /* Reset after a PHY select  */
-    USB_CoreReset(USBx); 
+    ret = USB_CoreReset(USBx);
   }
   else /* FS interface (embedded Phy) */
   {
     /* Select FS Embedded PHY */
     USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-    
+
     /* Reset after a PHY select and set Host mode */
-    USB_CoreReset(USBx);
-    
-    /* Deactivate the power down*/
-    USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
+    ret = USB_CoreReset(USBx);
+
+    /* Activate the USB Transceiver */
+    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
   }
- 
-  if(cfg.dma_enable == ENABLE)
+
+  if (cfg.dma_enable == 1U)
   {
-    USBx->GAHBCFG |= (USB_OTG_GAHBCFG_HBSTLEN_1 | USB_OTG_GAHBCFG_HBSTLEN_2);
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
     USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-  }  
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief  Set the USB turnaround time
+  * @param  USBx USB Instance
+  * @param  hclk: AHB clock frequency
+  * @retval USB turnaround time In PHY Clocks number
+  */
+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
+                                        uint32_t hclk, uint8_t speed)
+{
+  uint32_t UsbTrd;
+
+  /* The USBTRD is configured according to the tables below, depending on AHB frequency
+  used by application. In the low AHB frequency range it is used to stretch enough the USB response
+  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+  latency to the Data FIFO */
+  if (speed == USBD_FS_SPEED)
+  {
+    if ((hclk >= 14200000U) && (hclk < 15000000U))
+    {
+      /* hclk Clock Range between 14.2-15 MHz */
+      UsbTrd = 0xFU;
+    }
+    else if ((hclk >= 15000000U) && (hclk < 16000000U))
+    {
+      /* hclk Clock Range between 15-16 MHz */
+      UsbTrd = 0xEU;
+    }
+    else if ((hclk >= 16000000U) && (hclk < 17200000U))
+    {
+      /* hclk Clock Range between 16-17.2 MHz */
+      UsbTrd = 0xDU;
+    }
+    else if ((hclk >= 17200000U) && (hclk < 18500000U))
+    {
+      /* hclk Clock Range between 17.2-18.5 MHz */
+      UsbTrd = 0xCU;
+    }
+    else if ((hclk >= 18500000U) && (hclk < 20000000U))
+    {
+      /* hclk Clock Range between 18.5-20 MHz */
+      UsbTrd = 0xBU;
+    }
+    else if ((hclk >= 20000000U) && (hclk < 21800000U))
+    {
+      /* hclk Clock Range between 20-21.8 MHz */
+      UsbTrd = 0xAU;
+    }
+    else if ((hclk >= 21800000U) && (hclk < 24000000U))
+    {
+      /* hclk Clock Range between 21.8-24 MHz */
+      UsbTrd = 0x9U;
+    }
+    else if ((hclk >= 24000000U) && (hclk < 27700000U))
+    {
+      /* hclk Clock Range between 24-27.7 MHz */
+      UsbTrd = 0x8U;
+    }
+    else if ((hclk >= 27700000U) && (hclk < 32000000U))
+    {
+      /* hclk Clock Range between 27.7-32 MHz */
+      UsbTrd = 0x7U;
+    }
+    else /* if(hclk >= 32000000) */
+    {
+      /* hclk Clock Range between 32-200 MHz */
+      UsbTrd = 0x6U;
+    }
+  }
+  else if (speed == USBD_HS_SPEED)
+  {
+    UsbTrd = USBD_HS_TRDT_VALUE;
+  }
+  else
+  {
+    UsbTrd = USBD_DEFAULT_TRDT_VALUE;
+  }
+
+  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
 
   return HAL_OK;
 }
@@ -141,7 +207,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
 /**
   * @brief  USB_EnableGlobalInt
   *         Enables the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -150,11 +216,10 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
   return HAL_OK;
 }
 
-
 /**
   * @brief  USB_DisableGlobalInt
   *         Disable the controller's Global Int in the AHB Config reg
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
 */
 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -162,403 +227,466 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
   USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
   return HAL_OK;
 }
-   
+
 /**
   * @brief  USB_SetCurrentMode : Set functional mode
-  * @param  USBx : Selected device
-  * @param  mode :  current core mode
+  * @param  USBx  Selected device
+  * @param  mode   current core mode
   *          This parameter can be one of these values:
-  *            @arg USB_OTG_DEVICE_MODE: Peripheral mode
-  *            @arg USB_OTG_HOST_MODE: Host mode
-  *            @arg USB_OTG_DRD_MODE: Dual Role Device mode  
+  *            @arg USB_DEVICE_MODE: Peripheral mode
+  *            @arg USB_HOST_MODE: Host mode
+  *            @arg USB_DRD_MODE: Dual Role Device mode
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
 {
-  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 
-  
-  if ( mode == USB_OTG_HOST_MODE)
+  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
+  if (mode == USB_HOST_MODE)
   {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
   }
-  else if ( mode == USB_OTG_DEVICE_MODE)
+  else if (mode == USB_DEVICE_MODE)
   {
-    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 
+    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
   }
-  HAL_Delay(50);
-  
+  else
+  {
+    return HAL_ERROR;
+  }
+  HAL_Delay(50U);
+
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_DevInit : Initializes the USB_OTG controller registers 
+  * @brief  USB_DevInit : Initializes the USB_OTG controller registers
   *         for device mode
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
   *         the configuration information for the specified USBx peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
 {
-  uint32_t i = 0;
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t i;
 
-  /*Activate VBUS Sensing B */
-  USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-  
-  if (cfg.vbus_sensing_enable == 0)
+  for (i = 0U; i < 15U; i++)
   {
+    USBx->DIEPTXF[i] = 0U;
+  }
+
+  /* VBUS Sensing setup */
+  if (cfg.vbus_sensing_enable == 0U)
+  {
+    /*
+     * disable HW VBUS sensing. VBUS is internally considered to be always
+     * at VBUS-Valid level (5V).
+     */
     USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+  }
+  else
+  {
+    /* Enable HW VBUS sensing */
+    USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+    USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
   }
-   
+
   /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
+  USBx_PCGCCTL = 0U;
 
   /* Device mode configuration */
   USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-  
-  if(cfg.phy_itface  == USB_OTG_ULPI_PHY)
+
+  if (cfg.phy_itface == USB_OTG_ULPI_PHY)
   {
-    if(cfg.speed == USB_OTG_SPEED_HIGH)
-    {      
-      /* Set High speed phy */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
+    if (cfg.speed == USBD_HS_SPEED)
+    {
+      /* Set Core speed to High speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
     }
-    else 
+    else
     {
-      /* set High speed phy in Full speed mode */
-      USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
+      /* Set Core speed to Full speed mode */
+      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
     }
   }
   else
   {
-    /* Set Full speed phy */
-    USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
+    /* Set Core speed to Full speed mode */
+    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
   }
 
   /* Flush the FIFOs */
-  USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
-  
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
+
   /* Clear all pending Device Interrupts */
-  USBx_DEVICE->DIEPMSK = 0;
-  USBx_DEVICE->DOEPMSK = 0;
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-  USBx_DEVICE->DAINTMSK = 0;
-  
-  for (i = 0; i < cfg.dev_endpoints; i++)
+  USBx_DEVICE->DIEPMSK = 0U;
+  USBx_DEVICE->DOEPMSK = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
   {
     if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
     {
-      USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
+      if (i == 0U)
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
+      }
     }
     else
     {
-      USBx_INEP(i)->DIEPCTL = 0;
+      USBx_INEP(i)->DIEPCTL = 0U;
     }
-    
-    USBx_INEP(i)->DIEPTSIZ = 0;
-    USBx_INEP(i)->DIEPINT  = 0xFF;
+
+    USBx_INEP(i)->DIEPTSIZ = 0U;
+    USBx_INEP(i)->DIEPINT  = 0xFB7FU;
   }
-  
-  for (i = 0; i < cfg.dev_endpoints; i++)
+
+  for (i = 0U; i < cfg.dev_endpoints; i++)
   {
     if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
     {
-      USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
+      if (i == 0U)
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
+      }
+      else
+      {
+        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
+      }
     }
     else
     {
-      USBx_OUTEP(i)->DOEPCTL = 0;
+      USBx_OUTEP(i)->DOEPCTL = 0U;
     }
-    
-    USBx_OUTEP(i)->DOEPTSIZ = 0;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
+
+    USBx_OUTEP(i)->DOEPTSIZ = 0U;
+    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;
   }
-  
+
   USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-  
-  if (cfg.dma_enable == 1)
+
+  if (cfg.dma_enable == 1U)
   {
     /*Set threshold parameters */
-    USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
-    USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
-    
-    i= USBx_DEVICE->DTHRCTL;
+    USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 |
+                           USB_OTG_DTHRCTL_RXTHRLEN_6;
+
+    USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN |
+                            USB_OTG_DTHRCTL_ISOTHREN |
+                            USB_OTG_DTHRCTL_NONISOTHREN;
   }
-  
+
   /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-  
+  USBx->GINTMSK = 0U;
+
   /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xBFFFFFFF;
+  USBx->GINTSTS = 0xBFFFFFFFU;
 
   /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
+  if (cfg.dma_enable == 0U)
   {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
   }
-  
+
   /* Enable interrupts matching to the Device mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
-                    USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
-                    USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM|\
-                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-  
-  if(cfg.Sof_enable)
+  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
+                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
+                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |
+                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
+
+  if (cfg.Sof_enable != 0U)
   {
     USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
   }
 
-  if (cfg.vbus_sensing_enable == ENABLE)
+  if (cfg.vbus_sensing_enable == 1U)
   {
-    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 
+    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
   }
-  
-  return HAL_OK;
-}
 
+  return ret;
+}
 
 /**
   * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
-  * @param  USBx : Selected device
-  * @param  num : FIFO number
+  * @param  USBx  Selected device
+  * @param  num  FIFO number
   *         This parameter can be a value from 1 to 15
             15 means Flush all Tx FIFOs
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
 {
-  uint32_t count = 0;
- 
-  USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); 
- 
+  uint32_t count = 0U;
+
+  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
+
   do
   {
-    if (++count > 200000)
+    if (++count > 200000U)
     {
       return HAL_TIMEOUT;
     }
   }
   while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-  
+
   return HAL_OK;
 }
 
-
 /**
   * @brief  USB_FlushRxFifo : Flush Rx FIFO
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t count = 0;
-  
+
   USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-  
+
   do
   {
-    if (++count > 200000)
+    if (++count > 200000U)
     {
       return HAL_TIMEOUT;
     }
   }
   while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-  
+
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 
+  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register
   *         depending the PHY type and the enumeration speed of the device.
-  * @param  USBx : Selected device
-  * @param  speed : device speed
+  * @param  USBx  Selected device
+  * @param  speed  device speed
   *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
   * @retval  Hal status
   */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
   USBx_DEVICE->DCFG |= speed;
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_GetDevSpeed :Return the  Dev Speed 
-  * @param  USBx : Selected device
-  * @retval speed : device speed
+  * @brief  USB_GetDevSpeed  Return the Dev Speed
+  * @param  USBx  Selected device
+  * @retval speed  device speed
   *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  *            @arg PCD_SPEED_HIGH: High speed mode
+  *            @arg PCD_SPEED_FULL: Full speed mode
   */
 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint8_t speed = 0;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint8_t speed;
+  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
+
+  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
   {
-    speed = USB_OTG_SPEED_HIGH;
+    speed = USBD_HS_SPEED;
   }
-  else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
-           ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
+  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
+           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
   {
-    speed = USB_OTG_SPEED_FULL;
+    speed = USBD_FS_SPEED;
   }
-  else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  else
   {
-    speed = USB_OTG_SPEED_LOW;
+    speed = 0xFU;
   }
-  
+
   return speed;
 }
 
 /**
   * @brief  Activate and configure an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
-  if (ep->is_in == 1)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
   {
-   USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-   
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
-    {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
 
+    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
+    {
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
   }
   else
   {
-     USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-     
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
+
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
     {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-       (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
-    } 
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) |
+                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
   }
   return HAL_OK;
 }
+
 /**
   * @brief  Activate and configure a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
-  static __IO uint32_t debug = 0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
   /* Read DEPCTLn register */
-  if (ep->is_in == 1)
+  if (ep->is_in == 1U)
   {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
+    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
     {
-      USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    } 
-    
-    
-    debug  |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 
-    
-   USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
+      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
+                                   ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
   }
   else
   {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
+    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
     {
-      USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-      
-      debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
-      debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
-      debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
-        ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 
-    } 
-    
-     USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
+      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
+                                    ((uint32_t)ep->type << 18) | (epnum << 22) |
+                                    USB_OTG_DOEPCTL_USBAEP;
+    }
+
+    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
   }
 
   return HAL_OK;
 }
+
 /**
   * @brief  De-activate and de-initialize an endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
   /* Read DEPCTLn register */
-  if (ep->is_in == 1)
+  if (ep->is_in == 1U)
   {
-   USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));   
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;   
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
+    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
+                                   USB_OTG_DIEPCTL_MPSIZ |
+                                   USB_OTG_DIEPCTL_TXFNUM |
+                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
+                                   USB_OTG_DIEPCTL_EPTYP);
   }
   else
   {
-     USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));     
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;      
+    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
+                                    USB_OTG_DOEPCTL_MPSIZ |
+                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
+                                    USB_OTG_DOEPCTL_EPTYP);
   }
+
   return HAL_OK;
 }
 
 /**
   * @brief  De-activate and de-initialize a dedicated endpoint
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
   /* Read DEPCTLn register */
-  if (ep->is_in == 1)
+  if (ep->is_in == 1U)
   {
-   USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
-   USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
   }
   else
   {
-     USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 
-     USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
   }
+
   return HAL_OK;
 }
 
 /**
   * @brief  USB_EPStartXfer : setup and starts a transfer over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
   *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
 {
-  uint16_t pktcnt = 0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+  uint16_t pktcnt;
+
   /* IN endpoint */
-  if (ep->is_in == 1)
+  if (ep->is_in == 1U)
   {
     /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
+    if (ep->xfer_len == 0U)
     {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
     }
     else
     {
@@ -567,118 +695,139 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
       * short_packet pktcnt = N + (short_packet
       * exist ? 1 : 0)
       */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-      
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
       if (ep->type == EP_TYPE_ISOC)
       {
-        USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 
-        USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); 
-      }       
+        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
+      }
     }
 
-    if (dma == 1)
+    if (dma == 1U)
     {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
     }
     else
     {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
       if (ep->type != EP_TYPE_ISOC)
       {
         /* Enable the Tx FIFO Empty Interrupt for this EP */
-        if (ep->xfer_len > 0)
+        if (ep->xfer_len > 0U)
         {
-          USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
+          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
         }
       }
-    }
-
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
-      {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
-      }
       else
       {
-        USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
+        }
+        else
+        {
+          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+        }
+
+        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
       }
-    } 
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-    
-    if (ep->type == EP_TYPE_ISOC)
-    {
-      USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);   
-    }    
+    }
   }
   else /* OUT endpoint */
   {
     /* Program the transfer size and packet count as follows:
     * pktcnt = N
     * xfersize = N * maxpacket
-    */  
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-      
-    if (ep->xfer_len == 0)
+    */
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len == 0U)
     {
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;      
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
     }
     else
     {
-      pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; 
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ;
-      USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); 
+      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
     }
 
-    if (dma == 1)
+    if (dma == 1U)
     {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
     }
-    
+
     if (ep->type == EP_TYPE_ISOC)
     {
-      if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
+      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
       {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
       }
       else
       {
-        USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
       }
     }
     /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
   }
+
   return HAL_OK;
 }
 
 /**
   * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure
-  * @param  dma: USB dma enabled or disabled 
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
+  * @param  dma USB dma enabled or disabled
   *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
   /* IN endpoint */
-  if (ep->is_in == 1)
+  if (ep->is_in == 1U)
   {
     /* Zero Length Packet? */
-    if (ep->xfer_len == 0)
+    if (ep->xfer_len == 0U)
     {
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
     }
     else
     {
@@ -687,33 +836,38 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
       * short_packet pktcnt = N + (short_packet
       * exist ? 1 : 0)
       */
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 
-      
-      if(ep->xfer_len > ep->maxpacket)
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
+      if (ep->xfer_len > ep->maxpacket)
       {
         ep->xfer_len = ep->maxpacket;
       }
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
-      USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 
-    
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
     }
-    
-    if (dma == 1)
+
+    if (dma == 1U)
     {
-      USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      if ((uint32_t)ep->dma_addr != 0U)
+      {
+        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
+      }
+
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
     }
     else
     {
+      /* EP enable, IN data in FIFO */
+      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
       /* Enable the Tx FIFO Empty Interrupt for this EP */
-      if (ep->xfer_len > 0)
+      if (ep->xfer_len > 0U)
       {
-        USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
+        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
       }
     }
-    
-    /* EP enable, IN data in FIFO */
-    USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);   
   }
   else /* OUT endpoint */
   {
@@ -721,599 +875,671 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
     * pktcnt = N
     * xfersize = N * maxpacket
     */
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 
-    USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 
-      
-    if (ep->xfer_len > 0)
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
+    if (ep->xfer_len > 0U)
     {
       ep->xfer_len = ep->maxpacket;
     }
-    
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
-    USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 
-    
 
-    if (dma == 1)
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
+    if (dma == 1U)
     {
-      USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      if ((uint32_t)ep->xfer_buff != 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
+      }
     }
-    
+
     /* EP enable */
-    USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);    
+    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
   }
+
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated 
+  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
   *         with the EP/channel
-  * @param  USBx : Selected device           
-  * @param  src :  pointer to source buffer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to write
-  * @param  dma: USB dma enabled or disabled 
+  * @param  USBx  Selected device
+  * @param  src   pointer to source buffer
+  * @param  ch_ep_num  endpoint or host channel number
+  * @param  len  Number of bytes to write
+  * @param  dma USB dma enabled or disabled
   *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
 {
-  uint32_t count32b= 0 , i= 0;
-  
-  if (dma == 0)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pSrc = (uint32_t *)src;
+  uint32_t count32b, i;
+
+  if (dma == 0U)
   {
-    count32b =  (len + 3) / 4;
-    for (i = 0; i < count32b; i++, src += 4)
+    count32b = ((uint32_t)len + 3U) / 4U;
+    for (i = 0U; i < count32b; i++)
     {
-      USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
+      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
+      pSrc++;
     }
   }
+
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_ReadPacket : read a packet from the Tx FIFO associated 
-  *         with the EP/channel
-  * @param  USBx : Selected device  
-  * @param  src : source pointer
-  * @param  ch_ep_num : endpoint or host channel number
-  * @param  len : Number of bytes to read
-  * @param  dma: USB dma enabled or disabled 
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
+  * @brief  USB_ReadPacket : read a packet from the RX FIFO
+  * @param  USBx  Selected device
+  * @param  dest  source pointer
+  * @param  len  Number of bytes to read
   * @retval pointer to destination buffer
   */
 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
 {
-  uint32_t i=0;
-  uint32_t count32b = (len + 3) / 4;
-  
-  for ( i = 0; i < count32b; i++, dest += 4 )
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t *pDest = (uint32_t *)dest;
+  uint32_t i;
+  uint32_t count32b = ((uint32_t)len + 3U) / 4U;
+
+  for (i = 0U; i < count32b; i++)
   {
-    *(__packed uint32_t *)dest = USBx_DFIFO(0);
-    
+    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
+    pDest++;
   }
-  return ((void *)dest);
+
+  return ((void *)pDest);
 }
 
 /**
   * @brief  USB_EPSetStall : set a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure   
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
-  if (ep->is_in == 1)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
   {
-    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
+    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
     {
-      USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 
-    } 
-    USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
+      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+    }
+    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
   }
   else
   {
-    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
+    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
     {
-      USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 
-    } 
-    USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
+      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+    }
+    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
   }
+
   return HAL_OK;
 }
 
-
 /**
   * @brief  USB_EPClearStall : Clear a stall condition over an EP
-  * @param  USBx : Selected device
-  * @param  ep: pointer to endpoint structure   
+  * @param  USBx  Selected device
+  * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
-  if (ep->is_in == 1)
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t epnum = (uint32_t)ep->num;
+
+  if (ep->is_in == 1U)
   {
-    USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
     {
-       USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
+      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
   }
   else
   {
-    USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
     {
-      USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-    }    
+      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
+    }
   }
   return HAL_OK;
 }
 
 /**
   * @brief  USB_StopDevice : Stop the usb device mode
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
 {
+  HAL_StatusTypeDef ret;
+  uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t i;
-  
+
   /* Clear Pending interrupt */
-  for (i = 0; i < 15 ; i++)
+  for (i = 0U; i < 15U; i++)
   {
-    USBx_INEP(i)->DIEPINT  = 0xFF;
-    USBx_OUTEP(i)->DOEPINT  = 0xFF;
+    USBx_INEP(i)->DIEPINT = 0xFB7FU;
+    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
   }
-  USBx_DEVICE->DAINT = 0xFFFFFFFF;
-  
+
   /* Clear interrupt masks */
-  USBx_DEVICE->DIEPMSK  = 0;
-  USBx_DEVICE->DOEPMSK  = 0;
-  USBx_DEVICE->DAINTMSK = 0;
-  
+  USBx_DEVICE->DIEPMSK  = 0U;
+  USBx_DEVICE->DOEPMSK  = 0U;
+  USBx_DEVICE->DAINTMSK = 0U;
+
   /* Flush the FIFO */
-  USB_FlushRxFifo(USBx);
-  USB_FlushTxFifo(USBx ,  0x10 );  
-  
-  return HAL_OK;
+  ret = USB_FlushRxFifo(USBx);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  ret = USB_FlushTxFifo(USBx,  0x10U);
+  if (ret != HAL_OK)
+  {
+    return ret;
+  }
+
+  return ret;
 }
 
 /**
   * @brief  USB_SetDevAddress : Stop the usb device mode
-  * @param  USBx : Selected device
-  * @param  address : new device address to be assigned
+  * @param  USBx  Selected device
+  * @param  address  new device address to be assigned
   *          This parameter can be a value from 0 to 255
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
 {
-  USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
-  USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
-  
-  return HAL_OK;  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
+  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
+
+  return HAL_OK;
 }
 
 /**
   * @brief  USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
 {
-  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3);
-  
-  return HAL_OK;  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
 }
 
 /**
   * @brief  USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
 {
-  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
-  HAL_Delay(3);
-  
-  return HAL_OK;  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
+  HAL_Delay(3U);
+
+  return HAL_OK;
 }
 
 /**
   * @brief  USB_ReadInterrupts: return the global USB interrupt status
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-uint32_t  USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
+uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t v = 0;
-  
-  v = USBx->GINTSTS;
-  v &= USBx->GINTMSK;
-  return v;  
+  uint32_t tmpreg;
+
+  tmpreg = USBx->GINTSTS;
+  tmpreg &= USBx->GINTMSK;
+
+  return tmpreg;
 }
 
 /**
   * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xffff0000) >> 16);
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xffff0000U) >> 16);
 }
 
 /**
   * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t v;
-  v  = USBx_DEVICE->DAINT;
-  v &= USBx_DEVICE->DAINTMSK;
-  return ((v & 0xFFFF));
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_DEVICE->DAINT;
+  tmpreg &= USBx_DEVICE->DAINTMSK;
+
+  return ((tmpreg & 0xFFFFU));
 }
 
 /**
   * @brief  Returns Device OUT EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
   *          This parameter can be a value from 0 to 15
   * @retval Device OUT EP Interrupt register
   */
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
 {
-  uint32_t v;
-  v  = USBx_OUTEP(epnum)->DOEPINT;
-  v &= USBx_DEVICE->DOEPMSK;
-  return v;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
+  tmpreg &= USBx_DEVICE->DOEPMSK;
+
+  return tmpreg;
 }
 
 /**
   * @brief  Returns Device IN EP Interrupt register
-  * @param  USBx : Selected device
-  * @param  epnum : endpoint number
+  * @param  USBx  Selected device
+  * @param  epnum  endpoint number
   *          This parameter can be a value from 0 to 15
   * @retval Device IN EP Interrupt register
   */
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
 {
-  uint32_t v, msk, emp;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg, msk, emp;
+
   msk = USBx_DEVICE->DIEPMSK;
   emp = USBx_DEVICE->DIEPEMPMSK;
-  msk |= ((emp >> epnum) & 0x1) << 7;
-  v = USBx_INEP(epnum)->DIEPINT & msk;
-  return v;
+  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
+  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
+
+  return tmpreg;
 }
 
 /**
   * @brief  USB_ClearInterrupts: clear a USB interrupt
-  * @param  USBx : Selected device
-  * @param  interrupt : interrupt flag
+  * @param  USBx  Selected device
+  * @param  interrupt  interrupt flag
   * @retval None
   */
-void  USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
+void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
 {
-  USBx->GINTSTS |= interrupt; 
+  USBx->GINTSTS |= interrupt;
 }
 
 /**
   * @brief  Returns USB core mode
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval return core mode : Host or Device
   *          This parameter can be one of these values:
-  *           0 : Host 
+  *           0 : Host
   *           1 : Device
   */
 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
 {
-  return ((USBx->GINTSTS ) & 0x1);
+  return ((USBx->GINTSTS) & 0x1U);
 }
 
-
 /**
   * @brief  Activate EP0 for Setup transactions
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
   /* Set the MPS of the IN EP based on the enumeration speed */
-  USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-  
-  if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
+  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
   {
-    USBx_INEP(0)->DIEPCTL |= 3;
+    USBx_INEP(0U)->DIEPCTL |= 3U;
   }
   USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
 
   return HAL_OK;
 }
 
-
 /**
   * @brief  Prepare the EP0 to start the first control setup
-  * @param  USBx : Selected device
-  * @param  dma: USB dma enabled or disabled 
+  * @param  USBx  Selected device
+  * @param  dma USB dma enabled or disabled
   *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
-  * @param  psetup : pointer to setup packet
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
+  * @param  psetup  pointer to setup packet
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
 {
-  USBx_OUTEP(0)->DOEPTSIZ = 0;
-  USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
-  USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
-  USBx_OUTEP(0)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;  
-  
-  if (dma == 1)
-  {
-    USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+
+  if (gSNPSiD > USB_OTG_CORE_ID_300A)
+  {
+    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
+    {
+      return HAL_OK;
+    }
+  }
+
+  USBx_OUTEP(0U)->DOEPTSIZ = 0U;
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
+  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
+
+  if (dma == 1U)
+  {
+    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
     /* EP enable */
-    USBx_OUTEP(0)->DOEPCTL = 0x80008000;
+    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
   }
-  
-  return HAL_OK;  
-}
 
+  return HAL_OK;
+}
 
 /**
   * @brief  Reset the USB Core (needed after USB clock settings change)
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
   */
 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t count = 0;
+  uint32_t count = 0U;
 
   /* Wait for AHB master IDLE state. */
   do
   {
-    if (++count > 200000)
+    if (++count > 200000U)
     {
       return HAL_TIMEOUT;
     }
   }
-  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-  
+  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
   /* Core Soft Reset */
-  count = 0;
+  count = 0U;
   USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
 
   do
   {
-    if (++count > 200000)
+    if (++count > 200000U)
     {
       return HAL_TIMEOUT;
     }
   }
   while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-  
+
   return HAL_OK;
 }
 
-
 /**
-  * @brief  USB_HostInit : Initializes the USB OTG controller registers 
-  *         for Host mode 
-  * @param  USBx : Selected device
-  * @param  cfg  : pointer to a USB_OTG_CfgTypeDef structure that contains
+  * @brief  USB_HostInit : Initializes the USB OTG controller registers
+  *         for Host mode
+  * @param  USBx  Selected device
+  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains
   *         the configuration information for the specified USBx peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t i;
-  
+
   /* Restart the Phy Clock */
-  USBx_PCGCCTL = 0;
-  
-  /* no VBUS sensing*/
-  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
-  USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
+  USBx_PCGCCTL = 0U;
+
+  /* Disable VBUS sensing */
   USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
-  
-  /* Disable the FS/LS support mode only */
-  if((cfg.speed == USB_OTG_SPEED_FULL)&&
-     (USBx != USB_OTG_FS))
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSASEN);
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBUSBSEN);
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
   {
-    USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 
+    if (cfg.speed == USB_OTG_SPEED_FULL)
+    {
+      /* Force Device Enumeration to FS/LS mode only */
+      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+    }
+    else
+    {
+      /* Set default Max speed support */
+      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+    }
   }
   else
   {
-    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);  
+    /* Set default Max speed support */
+    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
   }
 
   /* Make sure the FIFOs are flushed. */
-  USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
-  USB_FlushRxFifo(USBx);
+  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
+  (void)USB_FlushRxFifo(USBx);
 
   /* Clear all pending HC Interrupts */
-  for (i = 0; i < cfg.Host_channels; i++)
+  for (i = 0U; i < cfg.Host_channels; i++)
   {
-    USBx_HC(i)->HCINT = 0xFFFFFFFF;
-    USBx_HC(i)->HCINTMSK = 0;
+    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+    USBx_HC(i)->HCINTMSK = 0U;
   }
-  
+
   /* Enable VBUS driving */
-  USB_DriveVbus(USBx, 1);
-  
-  HAL_Delay(200);
-  
+  (void)USB_DriveVbus(USBx, 1U);
+
+  HAL_Delay(200U);
+
   /* Disable all interrupts. */
-  USBx->GINTMSK = 0;
-  
+  USBx->GINTMSK = 0U;
+
   /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xFFFFFFFF;
-  
-  if(USBx == USB_OTG_FS)
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  if ((USBx->CID & (0x1U << 8)) != 0U)
   {
     /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x80; 
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
-    USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
+    USBx->GRXFSIZ  = 0x200U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
   }
   else
   {
     /* set Rx FIFO size */
-    USBx->GRXFSIZ  = (uint32_t )0x200; 
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
-    USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
+    USBx->GRXFSIZ  = 0x80U;
+    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
+    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
   }
-  
+
   /* Enable the common interrupts */
-  if (cfg.dma_enable == DISABLE)
+  if (cfg.dma_enable == 0U)
   {
-    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 
+    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
   }
-  
+
   /* Enable interrupts matching to the Host mode ONLY */
-  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM |\
-                    USB_OTG_GINTMSK_SOFM             |USB_OTG_GINTSTS_DISCINT|\
+  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \
+                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
                     USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
 
   return HAL_OK;
 }
 
 /**
-  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
+  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
   *         HCFG register on the PHY type and set the right frame interval
-  * @param  USBx : Selected device
-  * @param  freq : clock frequency
+  * @param  USBx  Selected device
+  * @param  freq  clock frequency
   *          This parameter can be one of these values:
-  *           HCFG_48_MHZ : Full Speed 48 MHz Clock 
-  *           HCFG_6_MHZ : Low Speed 6 MHz Clock 
+  *           HCFG_48_MHZ : Full Speed 48 MHz Clock
+  *           HCFG_6_MHZ : Low Speed 6 MHz Clock
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
   USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
-  USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-  
-  if (freq ==  HCFG_48_MHZ)
+  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
+
+  if (freq == HCFG_48_MHZ)
   {
-    USBx_HOST->HFIR = (uint32_t)48000;
+    USBx_HOST->HFIR = 48000U;
   }
-  else if (freq ==  HCFG_6_MHZ)
+  else if (freq == HCFG_6_MHZ)
   {
-    USBx_HOST->HFIR = (uint32_t)6000;
-  } 
-  return HAL_OK;  
+    USBx_HOST->HFIR = 6000U;
+  }
+  else
+  {
+    /* ... */
+  }
+
+  return HAL_OK;
 }
 
 /**
 * @brief  USB_OTG_ResetPort : Reset Host Port
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL status
-  * @note   (1)The application must wait at least 10 ms
+  * @note (1)The application must wait at least 10 ms
   *   before clearing the reset bit.
   */
 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
 {
-  __IO uint32_t hprt0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  __IO uint32_t hprt0 = 0U;
+
   hprt0 = USBx_HPRT0;
-  
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-    USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);  
-  HAL_Delay (10);                                /* See Note #1 */
-  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+  HAL_Delay(100U);                                 /* See Note #1 */
+  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+  HAL_Delay(10U);
+
   return HAL_OK;
 }
 
 /**
   * @brief  USB_DriveVbus : activate or de-activate vbus
-  * @param  state : VBUS state
+  * @param  state  VBUS state
   *          This parameter can be one of these values:
-  *           0 : VBUS Active 
+  *           0 : VBUS Active
   *           1 : VBUS Inactive
   * @retval HAL status
 */
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
 {
-  __IO uint32_t hprt0;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
 
   hprt0 = USBx_HPRT0;
-  hprt0 &= ~(USB_OTG_HPRT_PENA    | USB_OTG_HPRT_PCDET |\
-                         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-  
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
+
+  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
+             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
+
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
   {
-    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 
+    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
   }
-  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
+  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
   {
-    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 
+    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
   }
-  return HAL_OK; 
+  return HAL_OK;
 }
 
 /**
   * @brief  Return Host Core speed
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval speed : Host speed
   *          This parameter can be one of these values:
-  *            @arg USB_OTG_SPEED_HIGH: High speed mode
-  *            @arg USB_OTG_SPEED_FULL: Full speed mode
-  *            @arg USB_OTG_SPEED_LOW: Low speed mode
+  *            @arg HCD_SPEED_HIGH: High speed mode
+  *            @arg HCD_SPEED_FULL: Full speed mode
+  *            @arg HCD_SPEED_LOW: Low speed mode
   */
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
 {
-  __IO uint32_t hprt0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  __IO uint32_t hprt0 = 0U;
+
   hprt0 = USBx_HPRT0;
   return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
 }
 
 /**
   * @brief  Return Host Current Frame number
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval current frame number
 */
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
 {
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
   return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
 }
 
 /**
   * @brief  Initialize a host channel
-  * @param  USBx : Selected device
-  * @param  ch_num : Channel number
+  * @param  USBx  Selected device
+  * @param  ch_num  Channel number
   *         This parameter can be a value from 1 to 15
-  * @param  epnum : Endpoint number
+  * @param  epnum  Endpoint number
   *          This parameter can be a value from 1 to 15
-  * @param  dev_address : Current device address
+  * @param  dev_address  Current device address
   *          This parameter can be a value from 0 to 255
-  * @param  speed : Current device speed
+  * @param  speed  Current device speed
   *          This parameter can be one of these values:
   *            @arg USB_OTG_SPEED_HIGH: High speed mode
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
   *            @arg USB_OTG_SPEED_LOW: Low speed mode
-  * @param  ep_type : Endpoint Type
+  * @param  ep_type  Endpoint Type
   *          This parameter can be one of these values:
   *            @arg EP_TYPE_CTRL: Control type
   *            @arg EP_TYPE_ISOC: Isochronous type
   *            @arg EP_TYPE_BULK: Bulk type
   *            @arg EP_TYPE_INTR: Interrupt type
-  * @param  mps : Max Packet Size
+  * @param  mps  Max Packet Size
   *          This parameter can be a value from 0 to32K
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
                               uint8_t ch_num,
                               uint8_t epnum,
                               uint8_t dev_address,
@@ -1321,363 +1547,444 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
                               uint8_t ep_type,
                               uint16_t mps)
 {
-    
+  HAL_StatusTypeDef ret = HAL_OK;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t HCcharEpDir, HCcharLowSpeed;
+
   /* Clear old interrupt conditions for this host channel. */
-  USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-  
+  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+
   /* Enable channel interrupts required for this transfer. */
-  switch (ep_type) 
-  {
-  case EP_TYPE_CTRL:
-  case EP_TYPE_BULK:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_NAKM ;
- 
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    } 
-    else 
-    {
-      if(USBx != USB_OTG_FS)
+  switch (ep_type)
+  {
+    case EP_TYPE_CTRL:
+    case EP_TYPE_BULK:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_NAKM;
+
+      if ((epnum & 0x80U) == 0x80U)
       {
-        USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
       }
-    }
-    break;
-    
-  case EP_TYPE_INTR:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_STALLM |\
-                                USB_OTG_HCINTMSK_TXERRM |\
-                                USB_OTG_HCINTMSK_DTERRM |\
-                                USB_OTG_HCINTMSK_NAKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;    
-    
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
-    }
-    
-    break;
-  case EP_TYPE_ISOC:
-    
-    USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\
-                                USB_OTG_HCINTMSK_ACKM   |\
-                                USB_OTG_HCINTMSK_AHBERR |\
-                                USB_OTG_HCINTMSK_FRMORM ;   
-    
-    if (epnum & 0x80) 
-    {
-      USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);      
-    }
-    break;
+      else
+      {
+        if ((USBx->CID & (0x1U << 8)) != 0U)
+        {
+          USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+        }
+      }
+      break;
+
+    case EP_TYPE_INTR:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_STALLM |
+                                            USB_OTG_HCINTMSK_TXERRM |
+                                            USB_OTG_HCINTMSK_DTERRM |
+                                            USB_OTG_HCINTMSK_NAKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
+      }
+
+      break;
+
+    case EP_TYPE_ISOC:
+      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |
+                                            USB_OTG_HCINTMSK_ACKM   |
+                                            USB_OTG_HCINTMSK_AHBERR |
+                                            USB_OTG_HCINTMSK_FRMORM;
+
+      if ((epnum & 0x80U) == 0x80U)
+      {
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+      }
+      break;
+
+    default:
+      ret = HAL_ERROR;
+      break;
   }
-  
+
   /* Enable the top level host channel interrupt. */
-  USBx_HOST->HAINTMSK |= (1 << ch_num);
-  
+  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
+
   /* Make sure host channel interrupts are enabled. */
   USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-  
+
   /* Program the HCCHAR register */
-  USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD)  |\
-                             (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
-                             ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
-                             (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
-                             ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
-                             (mps & USB_OTG_HCCHAR_MPSIZ));
-    
+  if ((epnum & 0x80U) == 0x80U)
+  {
+    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    HCcharEpDir = 0U;
+  }
+
+  if (speed == HPRT0_PRTSPD_LOW_SPEED)
+  {
+    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+  }
+  else
+  {
+    HCcharLowSpeed = 0U;
+  }
+
+  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
+                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
+                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+
   if (ep_type == EP_TYPE_INTR)
   {
-    USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
   }
 
-  return HAL_OK; 
+  return ret;
 }
 
 /**
   * @brief  Start a transfer over a host channel
-  * @param  USBx : Selected device
-  * @param  hc : pointer to host channel structure
-  * @param  dma: USB dma enabled or disabled 
+  * @param  USBx  Selected device
+  * @param  hc  pointer to host channel structure
+  * @param  dma USB dma enabled or disabled
   *          This parameter can be one of these values:
-  *           0 : DMA feature not used 
-  *           1 : DMA feature used  
+  *           0 : DMA feature not used
+  *           1 : DMA feature used
   * @retval HAL state
   */
-#if defined   (__CC_ARM) /*!< ARM Compiler */
-#pragma O0
-#elif defined (__GNUC__) /*!< GNU Compiler */
-#pragma GCC optimize ("O0")
-#endif /* __CC_ARM */
 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
 {
-  uint8_t  is_oddframe = 0; 
-  uint16_t len_words = 0;   
-  uint16_t num_packets = 0;
-  uint16_t max_hc_pkt_count = 256;
-  uint32_t tmpreg = 0;
-    
-  if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
-  {
-    if((dma == 0) && (hc->do_ping == 1))
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t ch_num = (uint32_t)hc->ch_num;
+  static __IO uint32_t tmpreg = 0U;
+  uint8_t  is_oddframe;
+  uint16_t len_words;
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count = 256U;
+
+  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
+  {
+    if ((dma == 0U) && (hc->do_ping == 1U))
     {
-      USB_DoPing(USBx, hc->ch_num);
+      (void)USB_DoPing(USBx, hc->ch_num);
       return HAL_OK;
     }
-    else if(dma == 1)
+    else if (dma == 1U)
     {
-      USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
-      hc->do_ping = 0;
+      USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
+      hc->do_ping = 0U;
+    }
+    else
+    {
+      /* ... */
     }
   }
-  
+
   /* Compute the expected number of packets associated to the transfer */
-  if (hc->xfer_len > 0)
+  if (hc->xfer_len > 0U)
   {
-    num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-    
+    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+
     if (num_packets > max_hc_pkt_count)
     {
       num_packets = max_hc_pkt_count;
-      hc->xfer_len = num_packets * hc->max_packet;
+      hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
     }
   }
   else
   {
-    num_packets = 1;
+    num_packets = 1U;
   }
-  if (hc->ep_is_in)
+  if (hc->ep_is_in != 0U)
   {
-    hc->xfer_len = num_packets * hc->max_packet;
+    hc->xfer_len = (uint32_t)num_packets * hc->max_packet;
   }
-  
+
   /* Initialize the HCTSIZn register */
-  USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
-    ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-      (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-  
-  if (dma)
+  USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) |
+                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
+
+  if (dma != 0U)
   {
     /* xfer_buff MUST be 32-bits aligned */
-    USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
+    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
   }
-  
-  is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
-  USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
-  USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-  
+
+  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
+  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
+  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+
   /* Set host channel enable */
-  tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
+  tmpreg = USBx_HC(ch_num)->HCCHAR;
   tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+  /* make sure to set the correct ep direction */
+  if (hc->ep_is_in != 0U)
+  {
+    tmpreg |= USB_OTG_HCCHAR_EPDIR;
+  }
+  else
+  {
+    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+  }
   tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-  
-  if (dma == 0) /* Slave mode */
-  {  
-    if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
+  USBx_HC(ch_num)->HCCHAR = tmpreg;
+
+  if (dma == 0U) /* Slave mode */
+  {
+    if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
     {
-      switch(hc->ep_type) 
+      switch (hc->ep_type)
       {
         /* Non periodic transfer */
-      case EP_TYPE_CTRL:
-      case EP_TYPE_BULK:
-        
-        len_words = (hc->xfer_len + 3) / 4;
-        
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx->HNPTXSTS & 0xFFFF))
-        {
-          /* need to process data in nptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
-        }
-        break;
+        case EP_TYPE_CTRL:
+        case EP_TYPE_BULK:
+
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
+          {
+            /* need to process data in nptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
+          }
+          break;
+
         /* Periodic transfer */
-      case EP_TYPE_INTR:
-      case EP_TYPE_ISOC:
-        len_words = (hc->xfer_len + 3) / 4;
-        /* check if there is enough space in FIFO space */
-        if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
-        {
-          /* need to process data in ptxfempty interrupt */
-          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;          
-        }
-        break;
-        
-      default:
-        break;
+        case EP_TYPE_INTR:
+        case EP_TYPE_ISOC:
+          len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
+          /* check if there is enough space in FIFO space */
+          if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
+          {
+            /* need to process data in ptxfempty interrupt */
+            USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+          }
+          break;
+
+        default:
+          break;
       }
-      
+
       /* Write packet into the Tx FIFO. */
-      USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+      (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
     }
   }
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief Read all host channel interrupts status
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL state
   */
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
 {
-  return ((USBx_HOST->HAINT) & 0xFFFF);
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  return ((USBx_HOST->HAINT) & 0xFFFFU);
 }
 
 /**
   * @brief  Halt a host channel
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
   *         This parameter can be a value from 1 to 15
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
 {
-  uint32_t count = 0;
-  
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t hcnum = (uint32_t)hc_num;
+  uint32_t count = 0U;
+  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
+
   /* Check for space in the request queue to issue the halt. */
-  if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
+  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
   {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx->HNPTXSTS & 0xFFFF) == 0)
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
     {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do 
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
       {
-        if (++count > 1000) 
+        if (++count > 1000U)
         {
           break;
         }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
     }
     else
     {
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
     }
   }
   else
   {
-    USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-    
-    if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
+    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
+
+    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
     {
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;  
-      USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
-      do 
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
+      do
       {
-        if (++count > 1000) 
+        if (++count > 1000U)
         {
           break;
         }
-      } 
-      while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);     
+      }
+      while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
     }
     else
     {
-       USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
     }
   }
-  
+
   return HAL_OK;
 }
 
 /**
   * @brief  Initiate Do Ping protocol
-  * @param  USBx : Selected device
-  * @param  hc_num : Host Channel number
+  * @param  USBx  Selected device
+  * @param  hc_num  Host Channel number
   *         This parameter can be a value from 1 to 15
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
 {
-  uint8_t  num_packets = 1;
-  uint32_t tmpreg = 0;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t chnum = (uint32_t)ch_num;
+  uint32_t num_packets = 1U;
+  uint32_t tmpreg;
+
+  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
+                           USB_OTG_HCTSIZ_DOPING;
 
-  USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
-                                USB_OTG_HCTSIZ_DOPING;
-  
   /* Set host channel enable */
-  tmpreg = USBx_HC(ch_num)->HCCHAR;
+  tmpreg = USBx_HC(chnum)->HCCHAR;
   tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
   tmpreg |= USB_OTG_HCCHAR_CHENA;
-  USBx_HC(ch_num)->HCCHAR = tmpreg;
-  
-  return HAL_OK;  
+  USBx_HC(chnum)->HCCHAR = tmpreg;
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Stop Host Core
-  * @param  USBx : Selected device
+  * @param  USBx  Selected device
   * @retval HAL state
   */
 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint8_t i;
-  uint32_t count = 0;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t count = 0U;
   uint32_t value;
-  
-  USB_DisableGlobalInt(USBx);
-  
-    /* Flush FIFO */
-  USB_FlushTxFifo(USBx, 0x10);
-  USB_FlushRxFifo(USBx);
-  
-  /* Flush out any leftover queued requests. */
-  for (i = 0; i <= 15; i++)
-  {   
+  uint32_t i;
+
+  (void)USB_DisableGlobalInt(USBx);
 
-    value = USBx_HC(i)->HCCHAR ;
+  /* Flush FIFO */
+  (void)USB_FlushTxFifo(USBx, 0x10U);
+  (void)USB_FlushRxFifo(USBx);
+
+  /* Flush out any leftover queued requests. */
+  for (i = 0U; i <= 15U; i++)
+  {
+    value = USBx_HC(i)->HCCHAR;
     value |=  USB_OTG_HCCHAR_CHDIS;
-    value &= ~USB_OTG_HCCHAR_CHENA;  
+    value &= ~USB_OTG_HCCHAR_CHENA;
     value &= ~USB_OTG_HCCHAR_EPDIR;
     USBx_HC(i)->HCCHAR = value;
   }
-  
-  /* Halt all channels to put them into a known state. */  
-  for (i = 0; i <= 15; i++)
+
+  /* Halt all channels to put them into a known state. */
+  for (i = 0U; i <= 15U; i++)
   {
-    value = USBx_HC(i)->HCCHAR ;
-    
+    value = USBx_HC(i)->HCCHAR;
     value |= USB_OTG_HCCHAR_CHDIS;
-    value |= USB_OTG_HCCHAR_CHENA;  
+    value |= USB_OTG_HCCHAR_CHENA;
     value &= ~USB_OTG_HCCHAR_EPDIR;
-    
     USBx_HC(i)->HCCHAR = value;
-    do 
+
+    do
     {
-      if (++count > 1000) 
+      if (++count > 1000U)
       {
         break;
       }
-    } 
+    }
     while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
   }
 
-  /* Clear any pending Host interrupts */  
-  USBx_HOST->HAINT = 0xFFFFFFFF;
-  USBx->GINTSTS = 0xFFFFFFFF;
-  USB_EnableGlobalInt(USBx);
-  return HAL_OK;  
+  /* Clear any pending Host interrupts */
+  USBx_HOST->HAINT = 0xFFFFFFFFU;
+  USBx->GINTSTS = 0xFFFFFFFFU;
+
+  (void)USB_EnableGlobalInt(USBx);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
+  {
+    /* active Remote wakeup signalling */
+    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
+  }
+
+  return HAL_OK;
 }
+
+/**
+  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling
+  * @param  USBx Selected device
+  * @retval HAL status
+  */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  /* active Remote wakeup signalling */
+  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
 
 /**
diff --git a/STM32CubeMX/2020c/Inc/main.h b/STM32CubeMX/2020c/Inc/main.h
index 83bb8bc8..69e1b3c6 100644
--- a/STM32CubeMX/2020c/Inc/main.h
+++ b/STM32CubeMX/2020c/Inc/main.h
@@ -7,7 +7,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
© Copyright (c) 2020 STMicroelectronics.
+  * 
© Copyright (c) 2021 STMicroelectronics.
   * All rights reserved.

   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/STM32CubeMX/2020c/Inc/mxconstants.h b/STM32CubeMX/2020c/Inc/mxconstants.h
deleted file mode 100644
index 9f8f8240..00000000
--- a/STM32CubeMX/2020c/Inc/mxconstants.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
-  ******************************************************************************
-  * File Name          : mxconstants.h
-  * Description        : This file contains the common defines of the application
-  ******************************************************************************
-  *
-  * COPYRIGHT(c) 2019 STMicroelectronics
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-/* Includes ------------------------------------------------------------------*/
-
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private define ------------------------------------------------------------*/
-
-#define FPGA_GPIO2_Pin GPIO_PIN_2
-#define FPGA_GPIO2_GPIO_Port GPIOE
-#define FPGA_GPIO3_Pin GPIO_PIN_3
-#define FPGA_GPIO3_GPIO_Port GPIOE
-#define USB_ID_PASSTHRU_Pin GPIO_PIN_5
-#define USB_ID_PASSTHRU_GPIO_Port GPIOE
-#define UNUSED_PE6_Pin GPIO_PIN_6
-#define UNUSED_PE6_GPIO_Port GPIOE
-#define nULPI_RESET_Pin GPIO_PIN_2
-#define nULPI_RESET_GPIO_Port GPIOA
-#define nSPICFG_CS_Pin GPIO_PIN_4
-#define nSPICFG_CS_GPIO_Port GPIOA
-#define VER_ID1_Pin GPIO_PIN_4
-#define VER_ID1_GPIO_Port GPIOC
-#define VER_ID2_Pin GPIO_PIN_5
-#define VER_ID2_GPIO_Port GPIOC
-#define BOOT1_Pin GPIO_PIN_2
-#define BOOT1_GPIO_Port GPIOB
-#define nTERM_EN_Pin GPIO_PIN_14
-#define nTERM_EN_GPIO_Port GPIOB
-#define LED_IO_Pin GPIO_PIN_15
-#define LED_IO_GPIO_Port GPIOB
-#define FPGA_RST_Pin GPIO_PIN_13
-#define FPGA_RST_GPIO_Port GPIOD
-#define nFGPA_CRESET_B_Pin GPIO_PIN_6
-#define nFGPA_CRESET_B_GPIO_Port GPIOC
-#define nFGPA_CDONE_Pin GPIO_PIN_7
-#define nFGPA_CDONE_GPIO_Port GPIOC
-#define OTG_FS_VBUS_UNUSED_Pin GPIO_PIN_9
-#define OTG_FS_VBUS_UNUSED_GPIO_Port GPIOA
-#define FSMC_UNUSED_CLK_Pin GPIO_PIN_3
-#define FSMC_UNUSED_CLK_GPIO_Port GPIOD
-#define NWAIT_UNUSED_Pin GPIO_PIN_6
-#define NWAIT_UNUSED_GPIO_Port GPIOD
-#define nSD_WP_Pin GPIO_PIN_8
-#define nSD_WP_GPIO_Port GPIOB
-#define nSD_CD_Pin GPIO_PIN_9
-#define nSD_CD_GPIO_Port GPIOB
-/* USER CODE BEGIN Private defines */
-
-/* USER CODE END Private defines */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Inc/usbd_storage_if.h b/STM32CubeMX/2020c/Inc/usbd_storage_if.h
index 95dfdecb..06ab1b24 100644
--- a/STM32CubeMX/2020c/Inc/usbd_storage_if.h
+++ b/STM32CubeMX/2020c/Inc/usbd_storage_if.h
@@ -7,7 +7,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
© Copyright (c) 2020 STMicroelectronics.
+  * 
© Copyright (c) 2021 STMicroelectronics.
   * All rights reserved.

   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h
deleted file mode 100644
index 3ea825e6..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbd_hid.h
-  * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
-  * @brief   Header file for the usbd_hid_core.c file.
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_H
-#define __USB_HID_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include  "usbd_ioreq.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
-  * @{
-  */
-  
-/** @defgroup USBD_HID
-  * @brief This file is the Header file for usbd_hid.c
-  * @{
-  */ 
-
-
-/** @defgroup USBD_HID_Exported_Defines
-  * @{
-  */ 
-#define HID_EPIN_ADDR                 0x81
-#define HID_EPIN_SIZE                 0x04
-
-#define USB_HID_CONFIG_DESC_SIZ       34
-#define USB_HID_DESC_SIZ              9
-#define HID_MOUSE_REPORT_DESC_SIZE    74
-
-#define HID_DESCRIPTOR_TYPE           0x21
-#define HID_REPORT_DESC               0x22
-
-#define HID_HS_BINTERVAL               0x07
-#define HID_FS_BINTERVAL               0x0A
-#define HID_POLLING_INTERVAL           0x0A
-
-#define HID_REQ_SET_PROTOCOL          0x0B
-#define HID_REQ_GET_PROTOCOL          0x03
-
-#define HID_REQ_SET_IDLE              0x0A
-#define HID_REQ_GET_IDLE              0x02
-
-#define HID_REQ_SET_REPORT            0x09
-#define HID_REQ_GET_REPORT            0x01
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBD_CORE_Exported_TypesDefinitions
-  * @{
-  */
-typedef enum
-{
-  HID_IDLE = 0,
-  HID_BUSY,
-}
-HID_StateTypeDef; 
-
-
-typedef struct
-{
-  uint32_t             Protocol;   
-  uint32_t             IdleState;  
-  uint32_t             AltSetting;
-  HID_StateTypeDef     state;  
-}
-USBD_HID_HandleTypeDef; 
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup USBD_CORE_Exported_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBD_CORE_Exported_Variables
-  * @{
-  */ 
-
-extern USBD_ClassTypeDef  USBD_HID;
-#define USBD_HID_CLASS    &USBD_HID
-/**
-  * @}
-  */ 
-
-/** @defgroup USB_CORE_Exported_Functions
-  * @{
-  */ 
-uint8_t USBD_HID_SendReport (USBD_HandleTypeDef *pdev, 
-                                 uint8_t *report,
-                                 uint16_t len);
-
-uint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev);
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __USB_HID_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
deleted file mode 100644
index ad88b68e..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbd_hid.c
-  * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
-  * @brief   This file provides the HID core functions.
-  *
-  * @verbatim
-  *      
-  *          ===================================================================      
-  *                                HID Class  Description
-  *          =================================================================== 
-  *           This module manages the HID class V1.11 following the "Device Class Definition
-  *           for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
-  *           This driver implements the following aspects of the specification:
-  *             - The Boot Interface Subclass
-  *             - The Mouse protocol
-  *             - Usage Page : Generic Desktop
-  *             - Usage : Joystick
-  *             - Collection : Application 
-  *      
-  * @note     In HS mode and when the DMA is used, all variables and data structures
-  *           dealing with the DMA during the transaction process should be 32-bit aligned.
-  *           
-  *      
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid.h"
-#include "usbd_desc.h"
-#include "usbd_ctlreq.h"
-
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
-  * @{
-  */
-
-
-/** @defgroup USBD_HID 
-  * @brief usbd core module
-  * @{
-  */ 
-
-/** @defgroup USBD_HID_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBD_HID_Private_Defines
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBD_HID_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-
-
-/** @defgroup USBD_HID_Private_FunctionPrototypes
-  * @{
-  */
-
-
-static uint8_t  USBD_HID_Init (USBD_HandleTypeDef *pdev, 
-                               uint8_t cfgidx);
-
-static uint8_t  USBD_HID_DeInit (USBD_HandleTypeDef *pdev, 
-                                 uint8_t cfgidx);
-
-static uint8_t  USBD_HID_Setup (USBD_HandleTypeDef *pdev, 
-                                USBD_SetupReqTypedef *req);
-
-static uint8_t  *USBD_HID_GetCfgDesc (uint16_t *length);
-
-static uint8_t  *USBD_HID_GetDeviceQualifierDesc (uint16_t *length);
-
-static uint8_t  USBD_HID_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum);
-/**
-  * @}
-  */ 
-
-/** @defgroup USBD_HID_Private_Variables
-  * @{
-  */ 
-
-USBD_ClassTypeDef  USBD_HID = 
-{
-  USBD_HID_Init,
-  USBD_HID_DeInit,
-  USBD_HID_Setup,
-  NULL, /*EP0_TxSent*/  
-  NULL, /*EP0_RxReady*/
-  USBD_HID_DataIn, /*DataIn*/
-  NULL, /*DataOut*/
-  NULL, /*SOF */
-  NULL,
-  NULL,      
-  USBD_HID_GetCfgDesc,
-  USBD_HID_GetCfgDesc, 
-  USBD_HID_GetCfgDesc,
-  USBD_HID_GetDeviceQualifierDesc,
-};
-
-/* USB HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ]  __ALIGN_END =
-{
-  0x09, /* bLength: Configuration Descriptor size */
-  USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
-  USB_HID_CONFIG_DESC_SIZ,
-  /* wTotalLength: Bytes returned */
-  0x00,
-  0x01,         /*bNumInterfaces: 1 interface*/
-  0x01,         /*bConfigurationValue: Configuration value*/
-  0x00,         /*iConfiguration: Index of string descriptor describing
-  the configuration*/
-  0xE0,         /*bmAttributes: bus powered and Support Remote Wake-up */
-  0x32,         /*MaxPower 100 mA: this current is used for detecting Vbus*/
-  
-  /************** Descriptor of Joystick Mouse interface ****************/
-  /* 09 */
-  0x09,         /*bLength: Interface Descriptor size*/
-  USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/
-  0x00,         /*bInterfaceNumber: Number of Interface*/
-  0x00,         /*bAlternateSetting: Alternate setting*/
-  0x01,         /*bNumEndpoints*/
-  0x03,         /*bInterfaceClass: HID*/
-  0x01,         /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
-  0x02,         /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
-  0,            /*iInterface: Index of string descriptor*/
-  /******************** Descriptor of Joystick Mouse HID ********************/
-  /* 18 */
-  0x09,         /*bLength: HID Descriptor size*/
-  HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
-  0x11,         /*bcdHID: HID Class Spec release number*/
-  0x01,
-  0x00,         /*bCountryCode: Hardware target country*/
-  0x01,         /*bNumDescriptors: Number of HID class descriptors to follow*/
-  0x22,         /*bDescriptorType*/
-  HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
-  0x00,
-  /******************** Descriptor of Mouse endpoint ********************/
-  /* 27 */
-  0x07,          /*bLength: Endpoint Descriptor size*/
-  USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/
-  
-  HID_EPIN_ADDR,     /*bEndpointAddress: Endpoint Address (IN)*/
-  0x03,          /*bmAttributes: Interrupt endpoint*/
-  HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */
-  0x00,
-  HID_FS_BINTERVAL,          /*bInterval: Polling Interval (10 ms)*/
-  /* 34 */
-} ;
-
-/* USB HID device Configuration Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ]  __ALIGN_END  =
-{
-  /* 18 */
-  0x09,         /*bLength: HID Descriptor size*/
-  HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
-  0x11,         /*bcdHID: HID Class Spec release number*/
-  0x01,
-  0x00,         /*bCountryCode: Hardware target country*/
-  0x01,         /*bNumDescriptors: Number of HID class descriptors to follow*/
-  0x22,         /*bDescriptorType*/
-  HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
-  0x00,
-};
-
-/* USB Standard Device Descriptor */
-__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]  __ALIGN_END =
-{
-  USB_LEN_DEV_QUALIFIER_DESC,
-  USB_DESC_TYPE_DEVICE_QUALIFIER,
-  0x00,
-  0x02,
-  0x00,
-  0x00,
-  0x00,
-  0x40,
-  0x01,
-  0x00,
-};
-
-__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE]  __ALIGN_END =
-{
-  0x05,   0x01,
-  0x09,   0x02,
-  0xA1,   0x01,
-  0x09,   0x01,
-  
-  0xA1,   0x00,
-  0x05,   0x09,
-  0x19,   0x01,
-  0x29,   0x03,
-  
-  0x15,   0x00,
-  0x25,   0x01,
-  0x95,   0x03,
-  0x75,   0x01,
-  
-  0x81,   0x02,
-  0x95,   0x01,
-  0x75,   0x05,
-  0x81,   0x01,
-  
-  0x05,   0x01,
-  0x09,   0x30,
-  0x09,   0x31,
-  0x09,   0x38,
-  
-  0x15,   0x81,
-  0x25,   0x7F,
-  0x75,   0x08,
-  0x95,   0x03,
-  
-  0x81,   0x06,
-  0xC0,   0x09,
-  0x3c,   0x05,
-  0xff,   0x09,
-  
-  0x01,   0x15,
-  0x00,   0x25,
-  0x01,   0x75,
-  0x01,   0x95,
-  
-  0x02,   0xb1,
-  0x22,   0x75,
-  0x06,   0x95,
-  0x01,   0xb1,
-  
-  0x01,   0xc0
-}; 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBD_HID_Private_Functions
-  * @{
-  */ 
-
-/**
-  * @brief  USBD_HID_Init
-  *         Initialize the HID interface
-  * @param  pdev: device instance
-  * @param  cfgidx: Configuration index
-  * @retval status
-  */
-static uint8_t  USBD_HID_Init (USBD_HandleTypeDef *pdev, 
-                               uint8_t cfgidx)
-{
-  uint8_t ret = 0;
-  
-  /* Open EP IN */
-  USBD_LL_OpenEP(pdev,
-                 HID_EPIN_ADDR,
-                 USBD_EP_TYPE_INTR,
-                 HID_EPIN_SIZE);  
-  
-  pdev->pClassData = USBD_malloc(sizeof (USBD_HID_HandleTypeDef));
-  
-  if(pdev->pClassData == NULL)
-  {
-    ret = 1; 
-  }
-  else
-  {
-    ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;
-  }
-  return ret;
-}
-
-/**
-  * @brief  USBD_HID_Init
-  *         DeInitialize the HID layer
-  * @param  pdev: device instance
-  * @param  cfgidx: Configuration index
-  * @retval status
-  */
-static uint8_t  USBD_HID_DeInit (USBD_HandleTypeDef *pdev, 
-                                 uint8_t cfgidx)
-{
-  /* Close HID EPs */
-  USBD_LL_CloseEP(pdev,
-                  HID_EPIN_ADDR);
-  
-  /* FRee allocated memory */
-  if(pdev->pClassData != NULL)
-  {
-    USBD_free(pdev->pClassData);
-    pdev->pClassData = NULL;
-  } 
-  
-  return USBD_OK;
-}
-
-/**
-  * @brief  USBD_HID_Setup
-  *         Handle the HID specific requests
-  * @param  pdev: instance
-  * @param  req: usb requests
-  * @retval status
-  */
-static uint8_t  USBD_HID_Setup (USBD_HandleTypeDef *pdev, 
-                                USBD_SetupReqTypedef *req)
-{
-  uint16_t len = 0;
-  uint8_t  *pbuf = NULL;
-  USBD_HID_HandleTypeDef     *hhid = (USBD_HID_HandleTypeDef*) pdev->pClassData;
-  
-  switch (req->bmRequest & USB_REQ_TYPE_MASK)
-  {
-  case USB_REQ_TYPE_CLASS :  
-    switch (req->bRequest)
-    {
-      
-      
-    case HID_REQ_SET_PROTOCOL:
-      hhid->Protocol = (uint8_t)(req->wValue);
-      break;
-      
-    case HID_REQ_GET_PROTOCOL:
-      USBD_CtlSendData (pdev, 
-                        (uint8_t *)&hhid->Protocol,
-                        1);    
-      break;
-      
-    case HID_REQ_SET_IDLE:
-      hhid->IdleState = (uint8_t)(req->wValue >> 8);
-      break;
-      
-    case HID_REQ_GET_IDLE:
-      USBD_CtlSendData (pdev, 
-                        (uint8_t *)&hhid->IdleState,
-                        1);        
-      break;      
-      
-    default:
-      USBD_CtlError (pdev, req);
-      return USBD_FAIL; 
-    }
-    break;
-    
-  case USB_REQ_TYPE_STANDARD:
-    switch (req->bRequest)
-    {
-    case USB_REQ_GET_DESCRIPTOR: 
-      if( req->wValue >> 8 == HID_REPORT_DESC)
-      {
-        len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);
-        pbuf = HID_MOUSE_ReportDesc;
-      }
-      else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
-      {
-        pbuf = USBD_HID_Desc;   
-        len = MIN(USB_HID_DESC_SIZ , req->wLength);
-      }
-      
-      USBD_CtlSendData (pdev, 
-                        pbuf,
-                        len);
-      
-      break;
-      
-    case USB_REQ_GET_INTERFACE :
-      USBD_CtlSendData (pdev,
-                        (uint8_t *)&hhid->AltSetting,
-                        1);
-      break;
-      
-    case USB_REQ_SET_INTERFACE :
-      hhid->AltSetting = (uint8_t)(req->wValue);
-      break;
-    }
-  }
-  return USBD_OK;
-}
-
-/**
-  * @brief  USBD_HID_SendReport 
-  *         Send HID Report
-  * @param  pdev: device instance
-  * @param  buff: pointer to report
-  * @retval status
-  */
-uint8_t USBD_HID_SendReport     (USBD_HandleTypeDef  *pdev, 
-                                 uint8_t *report,
-                                 uint16_t len)
-{
-  USBD_HID_HandleTypeDef     *hhid = (USBD_HID_HandleTypeDef*)pdev->pClassData;
-  
-  if (pdev->dev_state == USBD_STATE_CONFIGURED )
-  {
-    if(hhid->state == HID_IDLE)
-    {
-      hhid->state = HID_BUSY;
-      USBD_LL_Transmit (pdev, 
-                        HID_EPIN_ADDR,                                      
-                        report,
-                        len);
-    }
-  }
-  return USBD_OK;
-}
-
-/**
-  * @brief  USBD_HID_GetPollingInterval 
-  *         return polling interval from endpoint descriptor
-  * @param  pdev: device instance
-  * @retval polling interval
-  */
-uint32_t USBD_HID_GetPollingInterval (USBD_HandleTypeDef *pdev)
-{
-  uint32_t polling_interval = 0;
-
-  /* HIGH-speed endpoints */
-  if(pdev->dev_speed == USBD_SPEED_HIGH)
-  {
-   /* Sets the data transfer polling interval for high speed transfers. 
-    Values between 1..16 are allowed. Values correspond to interval 
-    of 2 ^ (bInterval-1). This option (8 ms, corresponds to HID_HS_BINTERVAL */
-    polling_interval = (((1 <<(HID_HS_BINTERVAL - 1)))/8);
-  }
-  else   /* LOW and FULL-speed endpoints */
-  {
-    /* Sets the data transfer polling interval for low and full 
-    speed transfers */
-    polling_interval =  HID_FS_BINTERVAL;
-  }
-  
-  return ((uint32_t)(polling_interval));
-}
-
-/**
-  * @brief  USBD_HID_GetCfgDesc 
-  *         return configuration descriptor
-  * @param  speed : current device speed
-  * @param  length : pointer data length
-  * @retval pointer to descriptor buffer
-  */
-static uint8_t  *USBD_HID_GetCfgDesc (uint16_t *length)
-{
-  *length = sizeof (USBD_HID_CfgDesc);
-  return USBD_HID_CfgDesc;
-}
-
-
-/**
-  * @brief  USBD_HID_DataIn
-  *         handle data IN Stage
-  * @param  pdev: device instance
-  * @param  epnum: endpoint index
-  * @retval status
-  */
-static uint8_t  USBD_HID_DataIn (USBD_HandleTypeDef *pdev, 
-                              uint8_t epnum)
-{
-  
-  /* Ensure that the FIFO is empty before a new transfer, this condition could 
-  be caused by  a new transfer before the end of the previous transfer */
-  ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE;
-  return USBD_OK;
-}
-
-
-/**
-* @brief  DeviceQualifierDescriptor 
-*         return Device Qualifier descriptor
-* @param  length : pointer data length
-* @retval pointer to descriptor buffer
-*/
-static uint8_t  *USBD_HID_GetDeviceQualifierDesc (uint16_t *length)
-{
-  *length = sizeof (USBD_HID_DeviceQualifierDesc);
-  return USBD_HID_DeviceQualifierDesc;
-}
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h
index d40db8c6..932bbba8 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_msc.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header for the usbd_msc.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_MSC_H
 #define __USBD_MSC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -41,84 +33,89 @@
 /** @addtogroup USBD_MSC_BOT
   * @{
   */
-  
+
 /** @defgroup USBD_MSC
   * @brief This file is the Header file for usbd_msc.c
   * @{
-  */ 
+  */
 
 
 /** @defgroup USBD_BOT_Exported_Defines
   * @{
-  */ 
-#define MSC_MAX_FS_PACKET            0x40
-#define MSC_MAX_HS_PACKET            0x200
+  */
+/* MSC Class Config */
+#ifndef MSC_MEDIA_PACKET
+#define MSC_MEDIA_PACKET             512U
+#endif /* MSC_MEDIA_PACKET */
+
+#define MSC_MAX_FS_PACKET            0x40U
+#define MSC_MAX_HS_PACKET            0x200U
 
 #define BOT_GET_MAX_LUN              0xFE
 #define BOT_RESET                    0xFF
 #define USB_MSC_CONFIG_DESC_SIZ      32
- 
 
-#define MSC_EPIN_ADDR                0x81 
-#define MSC_EPOUT_ADDR               0x01 
+
+#define MSC_EPIN_ADDR                0x81U
+#define MSC_EPOUT_ADDR               0x01U
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USB_CORE_Exported_Types
   * @{
-  */ 
+  */
 typedef struct _USBD_STORAGE
 {
-  int8_t (* Init) (uint8_t lun);
-  int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint16_t *block_size);
-  int8_t (* IsReady) (uint8_t lun);
-  int8_t (* IsWriteProtected) (uint8_t lun);
-  int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
+  int8_t (* Init)(uint8_t lun);
+  int8_t (* GetCapacity)(uint8_t lun, uint32_t *block_num, uint16_t *block_size);
+  int8_t (* IsReady)(uint8_t lun);
+  int8_t (* IsWriteProtected)(uint8_t lun);
+  int8_t (* Read)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
   int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
   int8_t (* GetMaxLun)(void);
   int8_t *pInquiry;
-  
-}USBD_StorageTypeDef;
+
+} USBD_StorageTypeDef;
 
 
 typedef struct
 {
-  uint32_t                 max_lun;   
-  uint32_t                 interface; 
+  uint32_t                 max_lun;
+  uint32_t                 interface;
   uint8_t                  bot_state;
-  uint8_t                  bot_status;  
+  uint8_t                  bot_status;
   uint16_t                 bot_data_length;
-  uint8_t                  bot_data[MSC_MEDIA_PACKET];  
+  uint8_t                  bot_data[MSC_MEDIA_PACKET];
   USBD_MSC_BOT_CBWTypeDef  cbw;
   USBD_MSC_BOT_CSWTypeDef  csw;
-  
+
   USBD_SCSI_SenseTypeDef   scsi_sense [SENSE_LIST_DEEPTH];
   uint8_t                  scsi_sense_head;
   uint8_t                  scsi_sense_tail;
-  
+
   uint16_t                 scsi_blk_size;
   uint32_t                 scsi_blk_nbr;
-  
+
   uint32_t                 scsi_blk_addr;
   uint32_t                 scsi_blk_len;
 }
-USBD_MSC_BOT_HandleTypeDef; 
+USBD_MSC_BOT_HandleTypeDef;
 
 /* Structure for MSC process */
 extern USBD_ClassTypeDef  USBD_MSC;
 #define USBD_MSC_CLASS    &USBD_MSC
 
-uint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev, 
-                                    USBD_StorageTypeDef *fops);
+uint8_t  USBD_MSC_RegisterStorage(USBD_HandleTypeDef   *pdev,
+                                  USBD_StorageTypeDef *fops);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -127,6 +124,6 @@ uint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev,
 #endif  /* __USBD_MSC_H */
 /**
   * @}
-  */ 
-  
+  */
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h
index 61b4f6cd..f5b1b6d4 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_bot.h
@@ -2,25 +2,17 @@
   ******************************************************************************
   * @file    usbd_msc_bot.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header for the usbd_msc_bot.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
   */
@@ -30,7 +22,7 @@
 #define __USBD_MSC_BOT_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -39,51 +31,51 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup MSC_BOT
   * @brief This file is the Header file for usbd_msc_bot.c
   * @{
-  */ 
+  */
 
 
 /** @defgroup USBD_CORE_Exported_Defines
   * @{
-  */ 
-#define USBD_BOT_IDLE                      0       /* Idle state */
-#define USBD_BOT_DATA_OUT                  1       /* Data Out state */
-#define USBD_BOT_DATA_IN                   2       /* Data In state */
-#define USBD_BOT_LAST_DATA_IN              3       /* Last Data In Last */
-#define USBD_BOT_SEND_DATA                 4       /* Send Immediate data */
-#define USBD_BOT_NO_DATA                   5       /* No data Stage */
-
-#define USBD_BOT_CBW_SIGNATURE             0x43425355
-#define USBD_BOT_CSW_SIGNATURE             0x53425355
-#define USBD_BOT_CBW_LENGTH                31
-#define USBD_BOT_CSW_LENGTH                13
-#define USBD_BOT_MAX_DATA                  256
+  */
+#define USBD_BOT_IDLE                      0U       /* Idle state */
+#define USBD_BOT_DATA_OUT                  1U       /* Data Out state */
+#define USBD_BOT_DATA_IN                   2U       /* Data In state */
+#define USBD_BOT_LAST_DATA_IN              3U       /* Last Data In Last */
+#define USBD_BOT_SEND_DATA                 4U       /* Send Immediate data */
+#define USBD_BOT_NO_DATA                   5U       /* No data Stage */
+
+#define USBD_BOT_CBW_SIGNATURE             0x43425355U
+#define USBD_BOT_CSW_SIGNATURE             0x53425355U
+#define USBD_BOT_CBW_LENGTH                31U
+#define USBD_BOT_CSW_LENGTH                13U
+#define USBD_BOT_MAX_DATA                  256U
 
 /* CSW Status Definitions */
-#define USBD_CSW_CMD_PASSED                0x00
-#define USBD_CSW_CMD_FAILED                0x01
-#define USBD_CSW_PHASE_ERROR               0x02
+#define USBD_CSW_CMD_PASSED                0x00U
+#define USBD_CSW_CMD_FAILED                0x01U
+#define USBD_CSW_PHASE_ERROR               0x02U
 
 /* BOT Status */
-#define USBD_BOT_STATUS_NORMAL             0
-#define USBD_BOT_STATUS_RECOVERY           1
-#define USBD_BOT_STATUS_ERROR              2
+#define USBD_BOT_STATUS_NORMAL             0U
+#define USBD_BOT_STATUS_RECOVERY           1U
+#define USBD_BOT_STATUS_ERROR              2U
 
 
-#define USBD_DIR_IN                        0
-#define USBD_DIR_OUT                       1
-#define USBD_BOTH_DIR                      2
+#define USBD_DIR_IN                        0U
+#define USBD_DIR_OUT                       1U
+#define USBD_BOTH_DIR                      2U
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup MSC_CORE_Private_TypesDefinitions
   * @{
-  */ 
+  */
 
 typedef struct
 {
@@ -105,13 +97,13 @@ typedef struct
   uint32_t dTag;
   uint32_t dDataResidue;
   uint8_t  bStatus;
-  uint8_t  ReservedForAlign[3];  
+  uint8_t  ReservedForAlign[3];
 }
 USBD_MSC_BOT_CSWTypeDef;
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_CORE_Exported_Types
@@ -120,27 +112,27 @@ USBD_MSC_BOT_CSWTypeDef;
 
 /**
   * @}
-  */ 
+  */
 /** @defgroup USBD_CORE_Exported_FunctionsPrototypes
   * @{
-  */ 
-void MSC_BOT_Init (USBD_HandleTypeDef  *pdev);
-void MSC_BOT_Reset (USBD_HandleTypeDef  *pdev);
-void MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev);
-void MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev, 
-                     uint8_t epnum);
+  */
+void MSC_BOT_Init(USBD_HandleTypeDef  *pdev);
+void MSC_BOT_Reset(USBD_HandleTypeDef  *pdev);
+void MSC_BOT_DeInit(USBD_HandleTypeDef  *pdev);
+void MSC_BOT_DataIn(USBD_HandleTypeDef  *pdev,
+                    uint8_t epnum);
 
-void MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev, 
-                      uint8_t epnum);
+void MSC_BOT_DataOut(USBD_HandleTypeDef  *pdev,
+                     uint8_t epnum);
 
-void MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,
-                             uint8_t CSW_Status);
+void MSC_BOT_SendCSW(USBD_HandleTypeDef  *pdev,
+                     uint8_t CSW_Status);
 
-void  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev, 
-                             uint8_t epnum);
+void  MSC_BOT_CplClrFeature(USBD_HandleTypeDef  *pdev,
+                            uint8_t epnum);
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -149,10 +141,10 @@ void  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev,
 #endif /* __USBD_MSC_BOT_H */
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h
index d895068e..79dafbd6 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_msc_data.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header for the usbd_msc_data.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_MSC_DATA_H
 #define __USBD_MSC_DATA_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -39,23 +31,23 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USB_INFO
   * @brief general defines for the usb device library file
   * @{
-  */ 
+  */
 
 /** @defgroup USB_INFO_Exported_Defines
   * @{
-  */ 
-#define MODE_SENSE6_LEN			 8
-#define MODE_SENSE10_LEN		 8
-#define LENGTH_INQUIRY_PAGE00		 7
-#define LENGTH_FORMAT_CAPACITIES    	20
+  */
+#define MODE_SENSE6_LEN                    8U
+#define MODE_SENSE10_LEN                   8U
+#define LENGTH_INQUIRY_PAGE00              7U
+#define LENGTH_FORMAT_CAPACITIES           20U
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_INFO_Exported_TypesDefinitions
@@ -63,36 +55,36 @@
   */
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_INFO_Exported_Macros
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_INFO_Exported_Variables
   * @{
-  */ 
-extern const uint8_t MSC_Page00_Inquiry_Data[];  
+  */
+extern const uint8_t MSC_Page00_Inquiry_Data[];
 extern const uint8_t MSC_Mode_Sense6_data[];
 extern const uint8_t MSC_Mode_Sense10_data[] ;
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_INFO_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -102,10 +94,10 @@ extern const uint8_t MSC_Mode_Sense10_data[] ;
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h
index 05db26cb..1629d786 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_msc_scsi.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header for the usbd_msc_scsi.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_MSC_SCSI_H
 #define __USBD_MSC_SCSI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -39,83 +31,83 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_SCSI
   * @brief header file for the storage disk file
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_SCSI_Exported_Defines
   * @{
-  */ 
+  */
 
-#define SENSE_LIST_DEEPTH                           4
+#define SENSE_LIST_DEEPTH                           4U
 
 /* SCSI Commands */
-#define SCSI_FORMAT_UNIT                            0x04
-#define SCSI_INQUIRY                                0x12
-#define SCSI_MODE_SELECT6                           0x15
-#define SCSI_MODE_SELECT10                          0x55
-#define SCSI_MODE_SENSE6                            0x1A
-#define SCSI_MODE_SENSE10                           0x5A
-#define SCSI_ALLOW_MEDIUM_REMOVAL                   0x1E
-#define SCSI_READ6                                  0x08
-#define SCSI_READ10                                 0x28
-#define SCSI_READ12                                 0xA8
-#define SCSI_READ16                                 0x88
-
-#define SCSI_READ_CAPACITY10                        0x25
-#define SCSI_READ_CAPACITY16                        0x9E
-
-#define SCSI_REQUEST_SENSE                          0x03
-#define SCSI_START_STOP_UNIT                        0x1B
-#define SCSI_TEST_UNIT_READY                        0x00
-#define SCSI_WRITE6                                 0x0A
-#define SCSI_WRITE10                                0x2A
-#define SCSI_WRITE12                                0xAA
-#define SCSI_WRITE16                                0x8A
-
-#define SCSI_VERIFY10                               0x2F
-#define SCSI_VERIFY12                               0xAF
-#define SCSI_VERIFY16                               0x8F
-
-#define SCSI_SEND_DIAGNOSTIC                        0x1D
-#define SCSI_READ_FORMAT_CAPACITIES                 0x23
-
-#define NO_SENSE                                    0
-#define RECOVERED_ERROR                             1
-#define NOT_READY                                   2
-#define MEDIUM_ERROR                                3
-#define HARDWARE_ERROR                              4
-#define ILLEGAL_REQUEST                             5
-#define UNIT_ATTENTION                              6
-#define DATA_PROTECT                                7
-#define BLANK_CHECK                                 8
-#define VENDOR_SPECIFIC                             9
-#define COPY_ABORTED                                10
-#define ABORTED_COMMAND                             11
-#define VOLUME_OVERFLOW                             13
-#define MISCOMPARE                                  14
-
-
-#define INVALID_CDB                                 0x20
-#define INVALID_FIELED_IN_COMMAND                   0x24
-#define PARAMETER_LIST_LENGTH_ERROR                 0x1A
-#define INVALID_FIELD_IN_PARAMETER_LIST             0x26
-#define ADDRESS_OUT_OF_RANGE                        0x21
-#define MEDIUM_NOT_PRESENT                          0x3A
-#define MEDIUM_HAVE_CHANGED                         0x28
-#define WRITE_PROTECTED                             0x27 
-#define UNRECOVERED_READ_ERROR			    0x11
-#define WRITE_FAULT				    0x03 
-
-#define READ_FORMAT_CAPACITY_DATA_LEN               0x0C
-#define READ_CAPACITY10_DATA_LEN                    0x08
-#define MODE_SENSE10_DATA_LEN                       0x08
-#define MODE_SENSE6_DATA_LEN                        0x04
-#define REQUEST_SENSE_DATA_LEN                      0x12
-#define STANDARD_INQUIRY_DATA_LEN                   0x24
-#define BLKVFY                                      0x04
+#define SCSI_FORMAT_UNIT                            0x04U
+#define SCSI_INQUIRY                                0x12U
+#define SCSI_MODE_SELECT6                           0x15U
+#define SCSI_MODE_SELECT10                          0x55U
+#define SCSI_MODE_SENSE6                            0x1AU
+#define SCSI_MODE_SENSE10                           0x5AU
+#define SCSI_ALLOW_MEDIUM_REMOVAL                   0x1EU
+#define SCSI_READ6                                  0x08U
+#define SCSI_READ10                                 0x28U
+#define SCSI_READ12                                 0xA8U
+#define SCSI_READ16                                 0x88U
+
+#define SCSI_READ_CAPACITY10                        0x25U
+#define SCSI_READ_CAPACITY16                        0x9EU
+
+#define SCSI_REQUEST_SENSE                          0x03U
+#define SCSI_START_STOP_UNIT                        0x1BU
+#define SCSI_TEST_UNIT_READY                        0x00U
+#define SCSI_WRITE6                                 0x0AU
+#define SCSI_WRITE10                                0x2AU
+#define SCSI_WRITE12                                0xAAU
+#define SCSI_WRITE16                                0x8AU
+
+#define SCSI_VERIFY10                               0x2FU
+#define SCSI_VERIFY12                               0xAFU
+#define SCSI_VERIFY16                               0x8FU
+
+#define SCSI_SEND_DIAGNOSTIC                        0x1DU
+#define SCSI_READ_FORMAT_CAPACITIES                 0x23U
+
+#define NO_SENSE                                    0U
+#define RECOVERED_ERROR                             1U
+#define NOT_READY                                   2U
+#define MEDIUM_ERROR                                3U
+#define HARDWARE_ERROR                              4U
+#define ILLEGAL_REQUEST                             5U
+#define UNIT_ATTENTION                              6U
+#define DATA_PROTECT                                7U
+#define BLANK_CHECK                                 8U
+#define VENDOR_SPECIFIC                             9U
+#define COPY_ABORTED                                10U
+#define ABORTED_COMMAND                             11U
+#define VOLUME_OVERFLOW                             13U
+#define MISCOMPARE                                  14U
+
+
+#define INVALID_CDB                                 0x20U
+#define INVALID_FIELED_IN_COMMAND                   0x24U
+#define PARAMETER_LIST_LENGTH_ERROR                 0x1AU
+#define INVALID_FIELD_IN_PARAMETER_LIST             0x26U
+#define ADDRESS_OUT_OF_RANGE                        0x21U
+#define MEDIUM_NOT_PRESENT                          0x3AU
+#define MEDIUM_HAVE_CHANGED                         0x28U
+#define WRITE_PROTECTED                             0x27U
+#define UNRECOVERED_READ_ERROR                      0x11U
+#define WRITE_FAULT                                 0x03U
+
+#define READ_FORMAT_CAPACITY_DATA_LEN               0x0CU
+#define READ_CAPACITY10_DATA_LEN                    0x08U
+#define MODE_SENSE10_DATA_LEN                       0x08U
+#define MODE_SENSE6_DATA_LEN                        0x04U
+#define REQUEST_SENSE_DATA_LEN                      0x12U
+#define STANDARD_INQUIRY_DATA_LEN                   0x24U
+#define BLKVFY                                      0x04U
 
 extern  uint8_t Page00_Inquiry_Data[];
 extern  uint8_t Standard_Inquiry_Data[];
@@ -127,58 +119,57 @@ extern  uint8_t ReadCapacity10_Data[];
 extern  uint8_t ReadFormatCapacity_Data [];
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_SCSI_Exported_TypesDefinitions
   * @{
   */
 
-typedef struct _SENSE_ITEM {                
+typedef struct _SENSE_ITEM
+{
   char Skey;
-  union {
-    struct _ASCs {
+  union
+  {
+    struct _ASCs
+    {
       char ASC;
       char ASCQ;
-    }b;
-    unsigned int	ASC;
+    } b;
+    uint8_t ASC;
     char *pData;
   } w;
-} USBD_SCSI_SenseTypeDef; 
+} USBD_SCSI_SenseTypeDef;
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_SCSI_Exported_Macros
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_SCSI_Exported_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 /** @defgroup USBD_SCSI_Exported_FunctionsPrototype
   * @{
-  */ 
-int8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,
-                           uint8_t lun, 
-                           uint8_t *cmd);
+  */
+int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *cmd);
 
-void   SCSI_SenseCode(USBD_HandleTypeDef  *pdev,
-                      uint8_t lun, 
-                      uint8_t sKey, 
-                      uint8_t ASC);
+void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey,
+                    uint8_t ASC);
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -187,15 +178,15 @@ void   SCSI_SenseCode(USBD_HandleTypeDef  *pdev,
 #endif /* __USBD_MSC_SCSI_H */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h
index a7ed3502..0288c308 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_storage_template.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_msc_storage.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header file for the usbd_msc_storage.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_MSC_STORAGE_H
 #define __USBD_MSC_STORAGE_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -39,18 +31,18 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_STORAGE
   * @brief header file for the usbd_msc_storage.c file
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_STORAGE_Exported_Defines
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_STORAGE_Exported_Types
@@ -60,34 +52,34 @@
 
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_STORAGE_Exported_Macros
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_STORAGE_Exported_Variables
   * @{
-  */ 
+  */
 extern USBD_StorageTypeDef  USBD_MSC_Template_fops;
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_STORAGE_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -97,9 +89,9 @@ extern USBD_StorageTypeDef  USBD_MSC_Template_fops;
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
index e351cdff..fdf53148 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c
@@ -2,43 +2,41 @@
   ******************************************************************************
   * @file    usbd_msc.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides all the MSC core functions.
   *
   * @verbatim
-  *      
-  *          ===================================================================      
+  *
+  *          ===================================================================
   *                                MSC Class  Description
-  *          =================================================================== 
-  *           This module manages the MSC class V1.0 following the "Universal 
+  *          ===================================================================
+  *           This module manages the MSC class V1.0 following the "Universal
   *           Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
   *           Sep. 31, 1999".
   *           This driver implements the following aspects of the specification:
   *             - Bulk-Only Transport protocol
   *             - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
-  *      
+  *
   *  @endverbatim
   *
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+EndBSPDependencies */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_msc.h"
@@ -49,88 +47,74 @@
   */
 
 
-/** @defgroup MSC_CORE 
+/** @defgroup MSC_CORE
   * @brief Mass storage core module
   * @{
-  */ 
+  */
 
 /** @defgroup MSC_CORE_Private_TypesDefinitions
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_CORE_Private_Defines
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_CORE_Private_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_CORE_Private_FunctionPrototypes
   * @{
-  */ 
-uint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, 
-                            uint8_t cfgidx);
-
-uint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, 
-                              uint8_t cfgidx);
-
-uint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, 
-                             USBD_SetupReqTypedef *req);
-
-uint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, 
-                              uint8_t epnum);
-
-
-uint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, 
-                               uint8_t epnum);
-
-uint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length);
-
-uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length);
+  */
+uint8_t  USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+uint8_t  USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+uint8_t  USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
+uint8_t  USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum);
+uint8_t  USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum);
 
+uint8_t  *USBD_MSC_GetHSCfgDesc(uint16_t *length);
+uint8_t  *USBD_MSC_GetFSCfgDesc(uint16_t *length);
+uint8_t  *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length);
+uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length);
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_CORE_Private_Variables
   * @{
-  */ 
+  */
 
 
-USBD_ClassTypeDef  USBD_MSC = 
+USBD_ClassTypeDef  USBD_MSC =
 {
   USBD_MSC_Init,
   USBD_MSC_DeInit,
   USBD_MSC_Setup,
-  NULL, /*EP0_TxSent*/  
+  NULL, /*EP0_TxSent*/
   NULL, /*EP0_RxReady*/
   USBD_MSC_DataIn,
   USBD_MSC_DataOut,
-  NULL, /*SOF */ 
-  NULL,  
-  NULL,     
+  NULL, /*SOF */
+  NULL,
+  NULL,
   USBD_MSC_GetHSCfgDesc,
-  USBD_MSC_GetFSCfgDesc,  
+  USBD_MSC_GetFSCfgDesc,
   USBD_MSC_GetOtherSpeedCfgDesc,
   USBD_MSC_GetDeviceQualifierDescriptor,
 };
@@ -139,18 +123,18 @@ USBD_ClassTypeDef  USBD_MSC =
 /*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
 __ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
 {
-  
+
   0x09,   /* bLength: Configuation Descriptor size */
   USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */
   USB_MSC_CONFIG_DESC_SIZ,
-  
+
   0x00,
   0x01,   /* bNumInterfaces: 1 interface */
   0x01,   /* bConfigurationValue: */
   0x04,   /* iConfiguration: */
   0xC0,   /* bmAttributes: */
   0x32,   /* MaxPower 100 mA */
-  
+
   /********************  Mass Storage interface ********************/
   0x09,   /* bLength: Interface Descriptor size */
   0x04,   /* bDescriptorType: */
@@ -169,7 +153,7 @@ __ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
   LOBYTE(MSC_MAX_HS_PACKET),
   HIBYTE(MSC_MAX_HS_PACKET),
   0x00,   /*Polling interval in milliseconds */
-  
+
   0x07,   /*Endpoint descriptor length = 7 */
   0x05,   /*Endpoint descriptor type */
   MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
@@ -181,20 +165,19 @@ __ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
 
 /* USB Mass storage device Configuration Descriptor */
 /*   All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
+__ALIGN_BEGIN uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
 {
-  
   0x09,   /* bLength: Configuation Descriptor size */
   USB_DESC_TYPE_CONFIGURATION,   /* bDescriptorType: Configuration */
   USB_MSC_CONFIG_DESC_SIZ,
-  
+
   0x00,
   0x01,   /* bNumInterfaces: 1 interface */
   0x01,   /* bConfigurationValue: */
   0x04,   /* iConfiguration: */
   0xC0,   /* bmAttributes: */
   0x32,   /* MaxPower 100 mA */
-  
+
   /********************  Mass Storage interface ********************/
   0x09,   /* bLength: Interface Descriptor size */
   0x04,   /* bDescriptorType: */
@@ -213,7 +196,7 @@ uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
   LOBYTE(MSC_MAX_FS_PACKET),
   HIBYTE(MSC_MAX_FS_PACKET),
   0x00,   /*Polling interval in milliseconds */
-  
+
   0x07,   /*Endpoint descriptor length = 7 */
   0x05,   /*Endpoint descriptor type */
   MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
@@ -225,18 +208,17 @@ uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ]  __ALIGN_END =
 
 __ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ]   __ALIGN_END  =
 {
-  
   0x09,   /* bLength: Configuation Descriptor size */
-  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,   
+  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
   USB_MSC_CONFIG_DESC_SIZ,
-  
+
   0x00,
   0x01,   /* bNumInterfaces: 1 interface */
   0x01,   /* bConfigurationValue: */
   0x04,   /* iConfiguration: */
   0xC0,   /* bmAttributes: */
   0x32,   /* MaxPower 100 mA */
-  
+
   /********************  Mass Storage interface ********************/
   0x09,   /* bLength: Interface Descriptor size */
   0x04,   /* bDescriptorType: */
@@ -255,7 +237,7 @@ __ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ]   __AL
   0x40,
   0x00,
   0x00,   /*Polling interval in milliseconds */
-  
+
   0x07,   /*Endpoint descriptor length = 7 */
   0x05,   /*Endpoint descriptor type */
   MSC_EPOUT_ADDR,   /*Endpoint address (OUT, address 1) */
@@ -281,12 +263,12 @@ __ALIGN_BEGIN  uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]
 };
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_CORE_Private_Functions
   * @{
-  */ 
+  */
 
 /**
   * @brief  USBD_MSC_Init
@@ -295,53 +277,39 @@ __ALIGN_BEGIN  uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]
   * @param  cfgidx: configuration index
   * @retval status
   */
-uint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev, 
-                            uint8_t cfgidx)
+uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
 {
-  int16_t ret = 0;
-   
-  if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
+  if (pdev->dev_speed == USBD_SPEED_HIGH)
   {
     /* Open EP OUT */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPOUT_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_HS_PACKET);
-    
+    USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET);
+    pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U;
+
     /* Open EP IN */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPIN_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_HS_PACKET);  
+    USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET);
+    pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U;
   }
   else
   {
     /* Open EP OUT */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPOUT_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_FS_PACKET);
-    
+    USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET);
+    pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U;
+
     /* Open EP IN */
-    USBD_LL_OpenEP(pdev,
-                   MSC_EPIN_ADDR,
-                   USBD_EP_TYPE_BULK,
-                   MSC_MAX_FS_PACKET);  
+    USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET);
+    pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U;
   }
-  pdev->pClassData = USBD_malloc(sizeof (USBD_MSC_BOT_HandleTypeDef));
-  
-  if(pdev->pClassData == NULL)
-  {
-    ret = 1; 
-  }
-  else
+  pdev->pClassData = USBD_malloc(sizeof(USBD_MSC_BOT_HandleTypeDef));
+
+  if (pdev->pClassData == NULL)
   {
-    /* Init the BOT  layer */
-    MSC_BOT_Init(pdev); 
-    ret = 0;
+    return USBD_FAIL;
   }
-  
-  return ret;
+
+  /* Init the BOT  layer */
+  MSC_BOT_Init(pdev);
+
+  return USBD_OK;
 }
 
 /**
@@ -351,28 +319,28 @@ uint8_t  USBD_MSC_Init (USBD_HandleTypeDef *pdev,
   * @param  cfgidx: configuration index
   * @retval status
   */
-uint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev, 
-                              uint8_t cfgidx)
+uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev,
+                         uint8_t cfgidx)
 {
   /* Close MSC EPs */
-  USBD_LL_CloseEP(pdev,
-                  MSC_EPOUT_ADDR);
-  
-  /* Open EP IN */
-  USBD_LL_CloseEP(pdev,
-                  MSC_EPIN_ADDR);
-  
-  
-    /* De-Init the BOT layer */
+  USBD_LL_CloseEP(pdev, MSC_EPOUT_ADDR);
+  pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 0U;
+
+  /* Close EP IN */
+  USBD_LL_CloseEP(pdev, MSC_EPIN_ADDR);
+  pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 0U;
+
+  /* De-Init the BOT layer */
   MSC_BOT_DeInit(pdev);
-  
+
   /* Free MSC Class Resources */
-  if(pdev->pClassData != NULL)
+  if (pdev->pClassData != NULL)
   {
     USBD_free(pdev->pClassData);
-    pdev->pClassData  = NULL; 
+    pdev->pClassData  = NULL;
   }
-  return 0;
+
+  return USBD_OK;
 }
 /**
 * @brief  USBD_MSC_Setup
@@ -381,125 +349,151 @@ uint8_t  USBD_MSC_DeInit (USBD_HandleTypeDef *pdev,
 * @param  req: USB request
 * @retval status
 */
-uint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
+uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
 {
-  USBD_MSC_BOT_HandleTypeDef     *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;
-  
+  USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+  uint8_t ret = USBD_OK;
+  uint16_t status_info = 0U;
+
   switch (req->bmRequest & USB_REQ_TYPE_MASK)
   {
-
-  /* Class request */
-  case USB_REQ_TYPE_CLASS :
-    switch (req->bRequest)
-    {
-    case BOT_GET_MAX_LUN :
-
-      if((req->wValue  == 0) && 
-         (req->wLength == 1) &&
-         ((req->bmRequest & 0x80) == 0x80))
-      {
-        hmsc->max_lun = ((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun();
-        USBD_CtlSendData (pdev,
-                          (uint8_t *)&hmsc->max_lun,
-                          1);
-      }
-      else
+    /* Class request */
+    case USB_REQ_TYPE_CLASS:
+      switch (req->bRequest)
       {
-         USBD_CtlError(pdev , req);
-         return USBD_FAIL; 
+        case BOT_GET_MAX_LUN:
+          if ((req->wValue  == 0U) && (req->wLength == 1U) &&
+              ((req->bmRequest & 0x80U) == 0x80U))
+          {
+            hmsc->max_lun = (uint32_t)((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun();
+            USBD_CtlSendData(pdev, (uint8_t *)(void *)&hmsc->max_lun, 1U);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case BOT_RESET :
+          if ((req->wValue  == 0U) && (req->wLength == 0U) &&
+              ((req->bmRequest & 0x80U) != 0x80U))
+          {
+            MSC_BOT_Reset(pdev);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          ret = USBD_FAIL;
+          break;
       }
       break;
-      
-    case BOT_RESET :
-      if((req->wValue  == 0) && 
-         (req->wLength == 0) &&
-        ((req->bmRequest & 0x80) != 0x80))
-      {      
-         MSC_BOT_Reset(pdev);
-      }
-      else
+    /* Interface & Endpoint request */
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
       {
-         USBD_CtlError(pdev , req);
-         return USBD_FAIL; 
+        case USB_REQ_GET_STATUS:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_GET_INTERFACE:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            USBD_CtlSendData(pdev, (uint8_t *)(void *)&hmsc->interface, 1U);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_SET_INTERFACE:
+          if (pdev->dev_state == USBD_STATE_CONFIGURED)
+          {
+            hmsc->interface = (uint8_t)(req->wValue);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            ret = USBD_FAIL;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+
+          /* Flush the FIFO and Clear the stall status */
+          USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);
+
+          /* Reactivate the EP */
+          USBD_LL_CloseEP(pdev, (uint8_t)req->wIndex);
+          if ((((uint8_t)req->wIndex) & 0x80U) == 0x80U)
+          {
+            pdev->ep_in[(uint8_t)req->wIndex & 0xFU].is_used = 0U;
+            if (pdev->dev_speed == USBD_SPEED_HIGH)
+            {
+              /* Open EP IN */
+              USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK,
+                             MSC_MAX_HS_PACKET);
+            }
+            else
+            {
+              /* Open EP IN */
+              USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK,
+                             MSC_MAX_FS_PACKET);
+            }
+            pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U;
+          }
+          else
+          {
+            pdev->ep_out[(uint8_t)req->wIndex & 0xFU].is_used = 0U;
+            if (pdev->dev_speed == USBD_SPEED_HIGH)
+            {
+              /* Open EP OUT */
+              USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK,
+                             MSC_MAX_HS_PACKET);
+            }
+            else
+            {
+              /* Open EP OUT */
+              USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK,
+                             MSC_MAX_FS_PACKET);
+            }
+            pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U;
+          }
+
+          /* Handle BOT error */
+          MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          ret = USBD_FAIL;
+          break;
       }
       break;
 
     default:
-       USBD_CtlError(pdev , req);
-       return USBD_FAIL; 
-    }
-    break;
-  /* Interface & Endpoint request */
-  case USB_REQ_TYPE_STANDARD:
-    switch (req->bRequest)
-    {
-    case USB_REQ_GET_INTERFACE :
-      USBD_CtlSendData (pdev,
-                        (uint8_t *)&hmsc->interface,
-                        1);
+      USBD_CtlError(pdev, req);
+      ret = USBD_FAIL;
       break;
-      
-    case USB_REQ_SET_INTERFACE :
-      hmsc->interface = (uint8_t)(req->wValue);
-      break;
-    
-    case USB_REQ_CLEAR_FEATURE:  
-      
-      /* Flush the FIFO and Clear the stall status */    
-      USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex);
-      
-      /* Reactivate the EP */      
-      USBD_LL_CloseEP (pdev , (uint8_t)req->wIndex);
-      if((((uint8_t)req->wIndex) & 0x80) == 0x80)
-      {
-        if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
-        {
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPIN_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_HS_PACKET);  
-        }
-        else
-        {   
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPIN_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_FS_PACKET);  
-        }
-      }
-      else
-      {
-        if(pdev->dev_speed == USBD_SPEED_HIGH  ) 
-        {
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPOUT_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_HS_PACKET);  
-        }
-        else
-        {   
-          /* Open EP IN */
-          USBD_LL_OpenEP(pdev,
-                         MSC_EPOUT_ADDR,
-                         USBD_EP_TYPE_BULK,
-                         MSC_MAX_FS_PACKET);  
-        }
-      }
-      
-      /* Handle BOT error */
-      MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
-      break;
-      
-    }  
-    break;
-   
-  default:
-    break;
   }
-  return 0;
+
+  return ret;
 }
 
 /**
@@ -509,11 +503,11 @@ uint8_t  USBD_MSC_Setup (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
 * @param  epnum: endpoint index
 * @retval status
 */
-uint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev, 
-                              uint8_t epnum)
+uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum)
 {
-  MSC_BOT_DataIn(pdev , epnum);
-  return 0;
+  MSC_BOT_DataIn(pdev, epnum);
+
+  return USBD_OK;
 }
 
 /**
@@ -523,57 +517,61 @@ uint8_t  USBD_MSC_DataIn (USBD_HandleTypeDef *pdev,
 * @param  epnum: endpoint index
 * @retval status
 */
-uint8_t  USBD_MSC_DataOut (USBD_HandleTypeDef *pdev, 
-                               uint8_t epnum)
+uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum)
 {
-  MSC_BOT_DataOut(pdev , epnum);
-  return 0;
+  MSC_BOT_DataOut(pdev, epnum);
+
+  return USBD_OK;
 }
 
 /**
-* @brief  USBD_MSC_GetHSCfgDesc 
+* @brief  USBD_MSC_GetHSCfgDesc
 *         return configuration descriptor
 * @param  length : pointer data length
 * @retval pointer to descriptor buffer
 */
-uint8_t  *USBD_MSC_GetHSCfgDesc (uint16_t *length)
+uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length)
 {
-  *length = sizeof (USBD_MSC_CfgHSDesc);
+  *length = sizeof(USBD_MSC_CfgHSDesc);
+
   return USBD_MSC_CfgHSDesc;
 }
 
 /**
-* @brief  USBD_MSC_GetFSCfgDesc 
+* @brief  USBD_MSC_GetFSCfgDesc
 *         return configuration descriptor
 * @param  length : pointer data length
 * @retval pointer to descriptor buffer
 */
-uint8_t  *USBD_MSC_GetFSCfgDesc (uint16_t *length)
+uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length)
 {
-  *length = sizeof (USBD_MSC_CfgFSDesc);
+  *length = sizeof(USBD_MSC_CfgFSDesc);
+
   return USBD_MSC_CfgFSDesc;
 }
 
 /**
-* @brief  USBD_MSC_GetOtherSpeedCfgDesc 
+* @brief  USBD_MSC_GetOtherSpeedCfgDesc
 *         return other speed configuration descriptor
 * @param  length : pointer data length
 * @retval pointer to descriptor buffer
 */
-uint8_t  *USBD_MSC_GetOtherSpeedCfgDesc (uint16_t *length)
+uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length)
 {
-  *length = sizeof (USBD_MSC_OtherSpeedCfgDesc);
+  *length = sizeof(USBD_MSC_OtherSpeedCfgDesc);
+
   return USBD_MSC_OtherSpeedCfgDesc;
 }
 /**
-* @brief  DeviceQualifierDescriptor 
+* @brief  DeviceQualifierDescriptor
 *         return Device Qualifier descriptor
 * @param  length : pointer data length
 * @retval pointer to descriptor buffer
 */
-uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length)
+uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length)
 {
-  *length = sizeof (USBD_MSC_DeviceQualifierDesc);
+  *length = sizeof(USBD_MSC_DeviceQualifierDesc);
+
   return USBD_MSC_DeviceQualifierDesc;
 }
 
@@ -582,28 +580,29 @@ uint8_t  *USBD_MSC_GetDeviceQualifierDescriptor (uint16_t *length)
 * @param  fops: storage callback
 * @retval status
 */
-uint8_t  USBD_MSC_RegisterStorage  (USBD_HandleTypeDef   *pdev, 
-                                    USBD_StorageTypeDef *fops)
+uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev,
+                                 USBD_StorageTypeDef *fops)
 {
-  if(fops != NULL)
+  if (fops != NULL)
   {
-    pdev->pUserData= fops;
+    pdev->pUserData = fops;
   }
-  return 0;
+
+  return USBD_OK;
 }
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
index 86025fb3..f8c1be8c 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c
@@ -2,28 +2,26 @@
   ******************************************************************************
   * @file    usbd_msc_bot.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides all the BOT protocol core functions.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+EndBSPDependencies */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_msc_bot.h"
@@ -36,63 +34,61 @@
   */
 
 
-/** @defgroup MSC_BOT 
+/** @defgroup MSC_BOT
   * @brief BOT protocol module
   * @{
-  */ 
+  */
 
 /** @defgroup MSC_BOT_Private_TypesDefinitions
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_BOT_Private_Defines
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_BOT_Private_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_BOT_Private_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_BOT_Private_FunctionPrototypes
   * @{
-  */ 
-static void MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev);
-
-static void MSC_BOT_SendData (USBD_HandleTypeDef  *pdev, 
-                              uint8_t* pbuf, 
-                              uint16_t len);
+  */
+static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef  *pdev);
+static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf,
+                             uint16_t len);
 
 static void MSC_BOT_Abort(USBD_HandleTypeDef  *pdev);
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_BOT_Private_Functions
   * @{
-  */ 
+  */
 
 
 
@@ -102,26 +98,24 @@ static void MSC_BOT_Abort(USBD_HandleTypeDef  *pdev);
 * @param  pdev: device instance
 * @retval None
 */
-void MSC_BOT_Init (USBD_HandleTypeDef  *pdev)
+void MSC_BOT_Init(USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-    
-  hmsc->bot_state  = USBD_BOT_IDLE;
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  hmsc->bot_state = USBD_BOT_IDLE;
   hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
-  
-  hmsc->scsi_sense_tail = 0;
-  hmsc->scsi_sense_head = 0;
-  
-  ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0);
-  
+
+  hmsc->scsi_sense_tail = 0U;
+  hmsc->scsi_sense_head = 0U;
+
+  ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0U);
+
   USBD_LL_FlushEP(pdev, MSC_EPOUT_ADDR);
   USBD_LL_FlushEP(pdev, MSC_EPIN_ADDR);
-  
+
   /* Prapare EP to Receive First BOT Cmd */
-  USBD_LL_PrepareReceive (pdev,
-                          MSC_EPOUT_ADDR,
-                          (uint8_t *)&hmsc->cbw,
-                          USBD_BOT_CBW_LENGTH);    
+  USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw,
+                         USBD_BOT_CBW_LENGTH);
 }
 
 /**
@@ -130,18 +124,16 @@ void MSC_BOT_Init (USBD_HandleTypeDef  *pdev)
 * @param  pdev: device instance
 * @retval  None
 */
-void MSC_BOT_Reset (USBD_HandleTypeDef  *pdev)
+void MSC_BOT_Reset(USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-    
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   hmsc->bot_state  = USBD_BOT_IDLE;
-  hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;  
-  
+  hmsc->bot_status = USBD_BOT_STATUS_RECOVERY;
+
   /* Prapare EP to Receive First BOT Cmd */
-  USBD_LL_PrepareReceive (pdev,
-                          MSC_EPOUT_ADDR,
-                          (uint8_t *)&hmsc->cbw,
-                          USBD_BOT_CBW_LENGTH);   
+  USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw,
+                         USBD_BOT_CBW_LENGTH);
 }
 
 /**
@@ -150,10 +142,10 @@ void MSC_BOT_Reset (USBD_HandleTypeDef  *pdev)
 * @param  pdev: device instance
 * @retval None
 */
-void MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev)
+void MSC_BOT_DeInit(USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  
-  hmsc->bot_state  = USBD_BOT_IDLE;
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+  hmsc->bot_state = USBD_BOT_IDLE;
 }
 
 /**
@@ -163,30 +155,27 @@ void MSC_BOT_DeInit (USBD_HandleTypeDef  *pdev)
 * @param  epnum: endpoint index
 * @retval None
 */
-void MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev, 
-                     uint8_t epnum)
+void MSC_BOT_DataIn(USBD_HandleTypeDef  *pdev,
+                    uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   switch (hmsc->bot_state)
   {
-  case USBD_BOT_DATA_IN:
-    if(SCSI_ProcessCmd(pdev,
-                        hmsc->cbw.bLUN,
-                        &hmsc->cbw.CB[0]) < 0)
-    {
-      MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
-    }
-    break;
-    
-  case USBD_BOT_SEND_DATA:
-  case USBD_BOT_LAST_DATA_IN:
-    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);
-    
-    break;
-    
-  default:
-    break;
+    case USBD_BOT_DATA_IN:
+      if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
+      {
+        MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
+      }
+      break;
+
+    case USBD_BOT_SEND_DATA:
+    case USBD_BOT_LAST_DATA_IN:
+      MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED);
+      break;
+
+    default:
+      break;
   }
 }
 /**
@@ -196,72 +185,61 @@ void MSC_BOT_DataIn (USBD_HandleTypeDef  *pdev,
 * @param  epnum: endpoint index
 * @retval None
 */
-void MSC_BOT_DataOut (USBD_HandleTypeDef  *pdev, 
-                      uint8_t epnum)
+void MSC_BOT_DataOut(USBD_HandleTypeDef  *pdev,
+                     uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   switch (hmsc->bot_state)
   {
-  case USBD_BOT_IDLE:
-    MSC_BOT_CBW_Decode(pdev);
-    break;
-    
-  case USBD_BOT_DATA_OUT:
-    
-    if(SCSI_ProcessCmd(pdev,
-                        hmsc->cbw.bLUN,
-                        &hmsc->cbw.CB[0]) < 0)
-    {
-      MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
-    }
+    case USBD_BOT_IDLE:
+      MSC_BOT_CBW_Decode(pdev);
+      break;
+
+    case USBD_BOT_DATA_OUT:
+
+      if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
+      {
+        MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
+      }
+      break;
 
-    break;
-    
-  default:
-    break;
+    default:
+      break;
   }
 }
 
 /**
 * @brief  MSC_BOT_CBW_Decode
-*         Decode the CBW command and set the BOT state machine accordingly  
+*         Decode the CBW command and set the BOT state machine accordingly
 * @param  pdev: device instance
 * @retval None
 */
-static void  MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev)
+static void  MSC_BOT_CBW_Decode(USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   hmsc->csw.dTag = hmsc->cbw.dTag;
   hmsc->csw.dDataResidue = hmsc->cbw.dDataLength;
-  
-  if ((USBD_LL_GetRxDataSize (pdev ,MSC_EPOUT_ADDR) != USBD_BOT_CBW_LENGTH) ||
-      (hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE)||
-        (hmsc->cbw.bLUN > 1) || 
-          (hmsc->cbw.bCBLength < 1) || 
-            (hmsc->cbw.bCBLength > 16))
+
+  if ((USBD_LL_GetRxDataSize(pdev, MSC_EPOUT_ADDR) != USBD_BOT_CBW_LENGTH) ||
+      (hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE) ||
+      (hmsc->cbw.bLUN > 1U) ||
+      (hmsc->cbw.bCBLength < 1U) || (hmsc->cbw.bCBLength > 16U))
   {
-    
-    SCSI_SenseCode(pdev,
-                   hmsc->cbw.bLUN, 
-                   ILLEGAL_REQUEST, 
-                   INVALID_CDB);
-    
-    hmsc->bot_status = USBD_BOT_STATUS_ERROR;   
+
+    SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
+
+    hmsc->bot_status = USBD_BOT_STATUS_ERROR;
     MSC_BOT_Abort(pdev);
- 
   }
   else
   {
-    if(SCSI_ProcessCmd(pdev,
-                       hmsc->cbw.bLUN,
-                       &hmsc->cbw.CB[0]) < 0)
+    if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0)
     {
-      if(hmsc->bot_state == USBD_BOT_NO_DATA)
+      if (hmsc->bot_state == USBD_BOT_NO_DATA)
       {
-       MSC_BOT_SendCSW (pdev,
-                         USBD_CSW_CMD_FAILED); 
+        MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
       }
       else
       {
@@ -269,22 +247,27 @@ static void  MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev)
       }
     }
     /*Burst xfer handled internally*/
-    else if ((hmsc->bot_state != USBD_BOT_DATA_IN) && 
+    else if ((hmsc->bot_state != USBD_BOT_DATA_IN) &&
              (hmsc->bot_state != USBD_BOT_DATA_OUT) &&
-             (hmsc->bot_state != USBD_BOT_LAST_DATA_IN)) 
+             (hmsc->bot_state != USBD_BOT_LAST_DATA_IN))
     {
-      if (hmsc->bot_data_length > 0)
+      if (hmsc->bot_data_length > 0U)
       {
-        MSC_BOT_SendData(pdev,
-                         hmsc->bot_data, 
-                         hmsc->bot_data_length);
+        MSC_BOT_SendData(pdev, hmsc->bot_data, hmsc->bot_data_length);
       }
-      else if (hmsc->bot_data_length == 0) 
+      else if (hmsc->bot_data_length == 0U)
       {
-        MSC_BOT_SendCSW (pdev,
-                         USBD_CSW_CMD_PASSED);
+        MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED);
+      }
+      else
+      {
+        MSC_BOT_Abort(pdev);
       }
     }
+    else
+    {
+      return;
+    }
   }
 }
 
@@ -296,18 +279,18 @@ static void  MSC_BOT_CBW_Decode (USBD_HandleTypeDef  *pdev)
 * @param  len: Data Length
 * @retval None
 */
-static void  MSC_BOT_SendData(USBD_HandleTypeDef  *pdev,
-                              uint8_t* buf, 
+static void  MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf,
                               uint16_t len)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  len = MIN (hmsc->cbw.dDataLength, len);
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  uint16_t length = (uint16_t)MIN(hmsc->cbw.dDataLength, len);
+
   hmsc->csw.dDataResidue -= len;
   hmsc->csw.bStatus = USBD_CSW_CMD_PASSED;
   hmsc->bot_state = USBD_BOT_SEND_DATA;
-  
-  USBD_LL_Transmit (pdev, MSC_EPIN_ADDR, buf, len);  
+
+  USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, pbuf, length);
 }
 
 /**
@@ -317,26 +300,21 @@ static void  MSC_BOT_SendData(USBD_HandleTypeDef  *pdev,
 * @param  status : CSW status
 * @retval None
 */
-void  MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,
-                              uint8_t CSW_Status)
+void  MSC_BOT_SendCSW(USBD_HandleTypeDef  *pdev,
+                      uint8_t CSW_Status)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE;
   hmsc->csw.bStatus = CSW_Status;
   hmsc->bot_state = USBD_BOT_IDLE;
-  
-  USBD_LL_Transmit (pdev, 
-             MSC_EPIN_ADDR, 
-             (uint8_t *)&hmsc->csw, 
-             USBD_BOT_CSW_LENGTH);
-  
+
+  USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, (uint8_t *)(void *)&hmsc->csw,
+                   USBD_BOT_CSW_LENGTH);
+
   /* Prepare EP to Receive next Cmd */
-  USBD_LL_PrepareReceive (pdev,
-                    MSC_EPOUT_ADDR,
-                    (uint8_t *)&hmsc->cbw, 
-                    USBD_BOT_CBW_LENGTH);  
-  
+  USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw,
+                         USBD_BOT_CBW_LENGTH);
 }
 
 /**
@@ -346,24 +324,23 @@ void  MSC_BOT_SendCSW (USBD_HandleTypeDef  *pdev,
 * @retval status
 */
 
-static void  MSC_BOT_Abort (USBD_HandleTypeDef  *pdev)
+static void  MSC_BOT_Abort(USBD_HandleTypeDef  *pdev)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  if ((hmsc->cbw.bmFlags == 0) && 
-      (hmsc->cbw.dDataLength != 0) &&
-      (hmsc->bot_status == USBD_BOT_STATUS_NORMAL) )
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  if ((hmsc->cbw.bmFlags == 0U) &&
+      (hmsc->cbw.dDataLength != 0U) &&
+      (hmsc->bot_status == USBD_BOT_STATUS_NORMAL))
   {
-    USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR );
+    USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR);
   }
+
   USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);
-  
-  if(hmsc->bot_status == USBD_BOT_STATUS_ERROR)
+
+  if (hmsc->bot_status == USBD_BOT_STATUS_ERROR)
   {
-    USBD_LL_PrepareReceive (pdev,
-                      MSC_EPOUT_ADDR,
-                      (uint8_t *)&hmsc->cbw, 
-                      USBD_BOT_CBW_LENGTH);    
+    USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw,
+                           USBD_BOT_CBW_LENGTH);
   }
 }
 
@@ -375,33 +352,36 @@ static void  MSC_BOT_Abort (USBD_HandleTypeDef  *pdev)
 * @retval None
 */
 
-void  MSC_BOT_CplClrFeature (USBD_HandleTypeDef  *pdev, uint8_t epnum)
+void  MSC_BOT_CplClrFeature(USBD_HandleTypeDef  *pdev, uint8_t epnum)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  if(hmsc->bot_status == USBD_BOT_STATUS_ERROR )/* Bad CBW Signature */
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  if (hmsc->bot_status == USBD_BOT_STATUS_ERROR) /* Bad CBW Signature */
   {
     USBD_LL_StallEP(pdev, MSC_EPIN_ADDR);
-    hmsc->bot_status = USBD_BOT_STATUS_NORMAL;    
+    hmsc->bot_status = USBD_BOT_STATUS_NORMAL;
+  }
+  else if (((epnum & 0x80U) == 0x80U) && (hmsc->bot_status != USBD_BOT_STATUS_RECOVERY))
+  {
+    MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED);
   }
-  else if(((epnum & 0x80) == 0x80) && ( hmsc->bot_status != USBD_BOT_STATUS_RECOVERY))
+  else
   {
-    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_FAILED);
+    return;
   }
-  
 }
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
index 3180a5d9..aaafc3aa 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c
@@ -2,28 +2,26 @@
   ******************************************************************************
   * @file    usbd_msc_data.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides all the vital inquiry pages and sense data.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+EndBSPDependencies */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_msc_data.h"
@@ -34,101 +32,104 @@
   */
 
 
-/** @defgroup MSC_DATA 
+/** @defgroup MSC_DATA
   * @brief Mass storage info/data module
   * @{
-  */ 
+  */
 
 /** @defgroup MSC_DATA_Private_TypesDefinitions
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_DATA_Private_Defines
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_DATA_Private_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_DATA_Private_Variables
   * @{
-  */ 
+  */
 
 
 /* USB Mass storage Page 0 Inquiry Data */
-const uint8_t  MSC_Page00_Inquiry_Data[] = {//7						
-	0x00,		
-	0x00, 
-	0x00, 
-	(LENGTH_INQUIRY_PAGE00 - 4),
-	0x00, 
-	0x80, 
-	0x83 
-};  
+const uint8_t  MSC_Page00_Inquiry_Data[] =
+{
+  0x00,
+  0x00,
+  0x00,
+  (LENGTH_INQUIRY_PAGE00 - 4U),
+  0x00,
+  0x80,
+  0x83
+};
 /* USB Mass storage sense 6  Data */
-const uint8_t  MSC_Mode_Sense6_data[] = {
-	0x00,
-	0x00,
-	0x00,
-	0x00,
-	0x00,
-	0x00, 
-	0x00,
-	0x00
-};	
+const uint8_t  MSC_Mode_Sense6_data[] =
+{
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00
+};
 /* USB Mass storage sense 10  Data */
-const uint8_t  MSC_Mode_Sense10_data[] = {
-	0x00,
-	0x06, 
-	0x00, 
-	0x00, 
-	0x00, 
-	0x00, 
-	0x00, 
-	0x00
+const uint8_t  MSC_Mode_Sense10_data[] =
+{
+  0x00,
+  0x06,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00
 };
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_DATA_Private_FunctionPrototypes
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_DATA_Private_Functions
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
index 62f78cbb..78032c76 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c
@@ -2,28 +2,26 @@
   ******************************************************************************
   * @file    usbd_msc_scsi.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides all the USBD SCSI layer functions.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
+
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+EndBSPDependencies */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_msc_bot.h"
@@ -38,76 +36,72 @@
   */
 
 
-/** @defgroup MSC_SCSI 
+/** @defgroup MSC_SCSI
   * @brief Mass storage SCSI layer module
   * @{
-  */ 
+  */
 
 /** @defgroup MSC_SCSI_Private_TypesDefinitions
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_SCSI_Private_Defines
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_SCSI_Private_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_SCSI_Private_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_SCSI_Private_FunctionPrototypes
   * @{
-  */ 
-static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_Write10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params);
-static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params);
-static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params);
-static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, 
-                                      uint8_t lun , 
-                                      uint32_t blk_offset , 
-                                      uint16_t blk_nbr);
-static int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev,
-                                uint8_t lun);
-
-static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev,
-                                 uint8_t lun);
+  */
+static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_ModeSense6(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_ModeSense10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params);
+static int8_t SCSI_CheckAddressRange(USBD_HandleTypeDef *pdev, uint8_t lun,
+                                     uint32_t blk_offset, uint32_t blk_nbr);
+
+static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun);
+static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun);
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup MSC_SCSI_Private_Functions
   * @{
-  */ 
+  */
 
 
 /**
@@ -118,55 +112,63 @@ static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev,
 * @param  params: Command parameters
 * @retval status
 */
-int8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,
-                           uint8_t lun, 
-                           uint8_t *params)
+int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *cmd)
 {
-  
-  switch (params[0])
+  switch (cmd[0])
   {
-  case SCSI_TEST_UNIT_READY:
-    return SCSI_TestUnitReady(pdev, lun, params);
-    
-  case SCSI_REQUEST_SENSE:
-    return SCSI_RequestSense (pdev, lun, params);
-  case SCSI_INQUIRY:
-    return SCSI_Inquiry(pdev, lun, params);
-    
-  case SCSI_START_STOP_UNIT:
-    return SCSI_StartStopUnit(pdev, lun, params);
-    
-  case SCSI_ALLOW_MEDIUM_REMOVAL:
-    return SCSI_StartStopUnit(pdev, lun, params);
-    
-  case SCSI_MODE_SENSE6:
-    return SCSI_ModeSense6 (pdev, lun, params);
-    
-  case SCSI_MODE_SENSE10:
-    return SCSI_ModeSense10 (pdev, lun, params);
-    
-  case SCSI_READ_FORMAT_CAPACITIES:
-    return SCSI_ReadFormatCapacity(pdev, lun, params);
-    
-  case SCSI_READ_CAPACITY10:
-    return SCSI_ReadCapacity10(pdev, lun, params);
-    
-  case SCSI_READ10:
-    return SCSI_Read10(pdev, lun, params); 
-    
-  case SCSI_WRITE10:
-    return SCSI_Write10(pdev, lun, params);
-    
-  case SCSI_VERIFY10:
-    return SCSI_Verify10(pdev, lun, params);
-    
-  default:
-    SCSI_SenseCode(pdev, 
-                   lun,
-                   ILLEGAL_REQUEST, 
-                   INVALID_CDB);    
-    return -1;
+    case SCSI_TEST_UNIT_READY:
+      SCSI_TestUnitReady(pdev, lun, cmd);
+      break;
+
+    case SCSI_REQUEST_SENSE:
+      SCSI_RequestSense(pdev, lun, cmd);
+      break;
+    case SCSI_INQUIRY:
+      SCSI_Inquiry(pdev, lun, cmd);
+      break;
+
+    case SCSI_START_STOP_UNIT:
+      SCSI_StartStopUnit(pdev, lun, cmd);
+      break;
+
+    case SCSI_ALLOW_MEDIUM_REMOVAL:
+      SCSI_StartStopUnit(pdev, lun, cmd);
+      break;
+
+    case SCSI_MODE_SENSE6:
+      SCSI_ModeSense6(pdev, lun, cmd);
+      break;
+
+    case SCSI_MODE_SENSE10:
+      SCSI_ModeSense10(pdev, lun, cmd);
+      break;
+
+    case SCSI_READ_FORMAT_CAPACITIES:
+      SCSI_ReadFormatCapacity(pdev, lun, cmd);
+      break;
+
+    case SCSI_READ_CAPACITY10:
+      SCSI_ReadCapacity10(pdev, lun, cmd);
+      break;
+
+    case SCSI_READ10:
+      SCSI_Read10(pdev, lun, cmd);
+      break;
+
+    case SCSI_WRITE10:
+      SCSI_Write10(pdev, lun, cmd);
+      break;
+
+    case SCSI_VERIFY10:
+      SCSI_Verify10(pdev, lun, cmd);
+      break;
+
+    default:
+      SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, INVALID_CDB);
+      return -1;
   }
+
+  return 0;
 }
 
 
@@ -179,29 +181,25 @@ int8_t SCSI_ProcessCmd(USBD_HandleTypeDef  *pdev,
 */
 static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;  
-    
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   /* case 9 : Hi > D0 */
-  if (hmsc->cbw.dDataLength != 0)
+  if (hmsc->cbw.dDataLength != 0U)
   {
-    SCSI_SenseCode(pdev,
-                   hmsc->cbw.bLUN, 
-                   ILLEGAL_REQUEST, 
-                   INVALID_CDB);
+    SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
+
     return -1;
-  }  
-  
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+  }
+
+  if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0)
   {
-    SCSI_SenseCode(pdev,
-                   lun,
-                   NOT_READY, 
-                   MEDIUM_NOT_PRESENT);
-    
+    SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
     hmsc->bot_state = USBD_BOT_NO_DATA;
+
     return -1;
-  } 
-  hmsc->bot_data_length = 0;
+  }
+  hmsc->bot_data_length = 0U;
+
   return 0;
 }
 
@@ -214,33 +212,39 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 */
 static int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  uint8_t* pPage;
+  uint8_t *pPage;
   uint16_t len;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  if (params[1] & 0x01)/*Evpd is set*/
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  if (params[1] & 0x01U)/*Evpd is set*/
   {
-    pPage = (uint8_t *)MSC_Page00_Inquiry_Data;
     len = LENGTH_INQUIRY_PAGE00;
+    hmsc->bot_data_length = len;
+
+    while (len)
+    {
+      len--;
+      hmsc->bot_data[len] = MSC_Page00_Inquiry_Data[len];
+    }
   }
   else
   {
-    
-    pPage = (uint8_t *)&((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];
-    len = pPage[4] + 5;
-    
+    pPage = (uint8_t *)(void *) & ((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN];
+    len = (uint16_t)pPage[4] + 5U;
+
     if (params[4] <= len)
     {
       len = params[4];
     }
+    hmsc->bot_data_length = len;
+
+    while (len)
+    {
+      len--;
+      hmsc->bot_data[len] = pPage[len];
+    }
   }
-  hmsc->bot_data_length = len;
-  
-  while (len) 
-  {
-    len--;
-    hmsc->bot_data[len] = pPage[len];
-  }
+
   return 0;
 }
 
@@ -253,30 +257,27 @@ static int8_t  SCSI_Inquiry(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *par
 */
 static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  if (((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0)
   {
-    SCSI_SenseCode(pdev,
-                   lun,
-                   NOT_READY, 
-                   MEDIUM_NOT_PRESENT);
+    SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
     return -1;
-  } 
+  }
   else
   {
-    
-    hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 24);
-    hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >> 16);
-    hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1) >>  8);
-    hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1);
-    
+
+    hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 24);
+    hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 16);
+    hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >>  8);
+    hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1U);
+
     hmsc->bot_data[4] = (uint8_t)(hmsc->scsi_blk_size >>  24);
     hmsc->bot_data[5] = (uint8_t)(hmsc->scsi_blk_size >>  16);
     hmsc->bot_data[6] = (uint8_t)(hmsc->scsi_blk_size >>  8);
     hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_size);
-    
-    hmsc->bot_data_length = 8;
+
+    hmsc->bot_data_length = 8U;
     return 0;
   }
 }
@@ -289,39 +290,36 @@ static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_
 */
 static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   uint16_t blk_size;
   uint32_t blk_nbr;
   uint16_t i;
-  
-  for(i=0 ; i < 12 ; i++) 
+
+  for (i = 0U; i < 12U ; i++)
   {
-    hmsc->bot_data[i] = 0;
+    hmsc->bot_data[i] = 0U;
   }
-  
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
+
+  if (((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0U)
   {
-    SCSI_SenseCode(pdev,
-                   lun,
-                   NOT_READY, 
-                   MEDIUM_NOT_PRESENT);
+    SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
     return -1;
-  } 
+  }
   else
   {
-    hmsc->bot_data[3] = 0x08;
-    hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1) >> 24);
-    hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1) >> 16);
-    hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1) >>  8);
-    hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1);
-    
-    hmsc->bot_data[8] = 0x02;
+    hmsc->bot_data[3] = 0x08U;
+    hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1U) >> 24);
+    hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1U) >> 16);
+    hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1U) >>  8);
+    hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1U);
+
+    hmsc->bot_data[8] = 0x02U;
     hmsc->bot_data[9] = (uint8_t)(blk_size >>  16);
     hmsc->bot_data[10] = (uint8_t)(blk_size >>  8);
     hmsc->bot_data[11] = (uint8_t)(blk_size);
-    
-    hmsc->bot_data_length = 12;
+
+    hmsc->bot_data_length = 12U;
     return 0;
   }
 }
@@ -332,13 +330,13 @@ static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef  *pdev, uint8_t lun, ui
 * @param  params: Command parameters
 * @retval status
 */
-static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
+static int8_t SCSI_ModeSense6(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  uint16_t len = 8 ;
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+  uint16_t len = 8U;
   hmsc->bot_data_length = len;
-  
-  while (len) 
+
+  while (len)
   {
     len--;
     hmsc->bot_data[len] = MSC_Mode_Sense6_data[len];
@@ -353,18 +351,19 @@ static int8_t SCSI_ModeSense6 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *
 * @param  params: Command parameters
 * @retval status
 */
-static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
+static int8_t SCSI_ModeSense10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  uint16_t len = 8;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
+  uint16_t len = 8U;
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   hmsc->bot_data_length = len;
 
-  while (len) 
+  while (len)
   {
     len--;
     hmsc->bot_data[len] = MSC_Mode_Sense10_data[len];
   }
+
   return 0;
 }
 
@@ -376,33 +375,34 @@ static int8_t SCSI_ModeSense10 (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 * @retval status
 */
 
-static int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
+static int8_t SCSI_RequestSense(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
   uint8_t i;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
-  for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) 
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
+  for (i = 0U ; i < REQUEST_SENSE_DATA_LEN; i++)
   {
-    hmsc->bot_data[i] = 0;
+    hmsc->bot_data[i] = 0U;
   }
-  
-  hmsc->bot_data[0]	= 0x70;		
-  hmsc->bot_data[7]	= REQUEST_SENSE_DATA_LEN - 6;	
-  
-  if((hmsc->scsi_sense_head != hmsc->scsi_sense_tail)) {
-    
-    hmsc->bot_data[2]     = hmsc->scsi_sense[hmsc->scsi_sense_head].Skey;		
-    hmsc->bot_data[12]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ;	
-    hmsc->bot_data[13]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC;	
+
+  hmsc->bot_data[0] = 0x70U;
+  hmsc->bot_data[7] = REQUEST_SENSE_DATA_LEN - 6U;
+
+  if ((hmsc->scsi_sense_head != hmsc->scsi_sense_tail))
+  {
+
+    hmsc->bot_data[2]     = hmsc->scsi_sense[hmsc->scsi_sense_head].Skey;
+    hmsc->bot_data[12]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ;
+    hmsc->bot_data[13]    = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC;
     hmsc->scsi_sense_head++;
-    
+
     if (hmsc->scsi_sense_head == SENSE_LIST_DEEPTH)
     {
-      hmsc->scsi_sense_head = 0;
+      hmsc->scsi_sense_head = 0U;
     }
   }
-  hmsc->bot_data_length = REQUEST_SENSE_DATA_LEN;  
-  
+  hmsc->bot_data_length = REQUEST_SENSE_DATA_LEN;
+
   if (params[4] <= REQUEST_SENSE_DATA_LEN)
   {
     hmsc->bot_data_length = params[4];
@@ -421,14 +421,14 @@ static int8_t SCSI_RequestSense (USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 */
 void SCSI_SenseCode(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData; 
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+
   hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey  = sKey;
   hmsc->scsi_sense[hmsc->scsi_sense_tail].w.ASC = ASC << 8;
   hmsc->scsi_sense_tail++;
   if (hmsc->scsi_sense_tail == SENSE_LIST_DEEPTH)
   {
-    hmsc->scsi_sense_tail = 0;
+    hmsc->scsi_sense_tail = 0U;
   }
 }
 /**
@@ -440,8 +440,8 @@ void SCSI_SenseCode(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t sKey, uint8_
 */
 static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData;   
-  hmsc->bot_data_length = 0;
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+  hmsc->bot_data_length = 0U;
   return 0;
 }
 
@@ -452,64 +452,49 @@ static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t
 * @param  params: Command parameters
 * @retval status
 */
-static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
+static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; 
-  
-  if(hmsc->bot_state == USBD_BOT_IDLE)  /* Idle */
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+
+  if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */
   {
-    
     /* case 10 : Ho <> Di */
-    
-    if ((hmsc->cbw.bmFlags & 0x80) != 0x80)
+    if ((hmsc->cbw.bmFlags & 0x80U) != 0x80U)
     {
-      SCSI_SenseCode(pdev,
-                     hmsc->cbw.bLUN, 
-                     ILLEGAL_REQUEST, 
-                     INVALID_CDB);
+      SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
       return -1;
-    }    
-    
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+    }
+
+    if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0)
     {
-      SCSI_SenseCode(pdev,
-                     lun,
-                     NOT_READY, 
-                     MEDIUM_NOT_PRESENT);
+      SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
       return -1;
-    } 
-    
-    hmsc->scsi_blk_addr = (params[2] << 24) | \
-      (params[3] << 16) | \
-        (params[4] <<  8) | \
-          params[5];
-    
-    hmsc->scsi_blk_len =  (params[7] <<  8) | \
-      params[8];  
-    
-    
-    
-    if( SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, hmsc->scsi_blk_len) < 0)
+    }
+
+    hmsc->scsi_blk_addr = ((uint32_t)params[2] << 24) |
+                          ((uint32_t)params[3] << 16) |
+                          ((uint32_t)params[4] <<  8) |
+                          (uint32_t)params[5];
+
+    hmsc->scsi_blk_len = ((uint32_t)params[7] <<  8) | (uint32_t)params[8];
+
+    if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr,
+                               hmsc->scsi_blk_len) < 0)
     {
       return -1; /* error */
     }
-    
+
     hmsc->bot_state = USBD_BOT_DATA_IN;
-    hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;
-    hmsc->scsi_blk_len  *= hmsc->scsi_blk_size;
-    
+
     /* cases 4,5 : Hi <> Dn */
-    if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)
+    if (hmsc->cbw.dDataLength != (hmsc->scsi_blk_len * hmsc->scsi_blk_size))
     {
-      SCSI_SenseCode(pdev,
-                     hmsc->cbw.bLUN, 
-                     ILLEGAL_REQUEST, 
-                     INVALID_CDB);
+      SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
       return -1;
     }
   }
-  hmsc->bot_data_length = MSC_MEDIA_PACKET;  
-  
+  hmsc->bot_data_length = MSC_MEDIA_PACKET;
+
   return SCSI_ProcessRead(pdev, lun);
 }
 
@@ -521,80 +506,63 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *para
 * @retval status
 */
 
-static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
+static int8_t SCSI_Write10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; 
-  
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+  uint32_t len;
+
   if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */
   {
-    
     /* case 8 : Hi <> Do */
-    
-    if ((hmsc->cbw.bmFlags & 0x80) == 0x80)
+    if ((hmsc->cbw.bmFlags & 0x80U) == 0x80U)
     {
-      SCSI_SenseCode(pdev,
-                     hmsc->cbw.bLUN, 
-                     ILLEGAL_REQUEST, 
-                     INVALID_CDB);
+      SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
       return -1;
     }
-    
+
     /* Check whether Media is ready */
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) !=0 )
+    if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0)
     {
-      SCSI_SenseCode(pdev,
-                     lun,
-                     NOT_READY, 
-                     MEDIUM_NOT_PRESENT);
+      SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT);
       return -1;
-    } 
-    
+    }
+
     /* Check If media is write-protected */
-    if(((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) !=0 )
+    if (((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) != 0)
     {
-      SCSI_SenseCode(pdev,
-                     lun,
-                     NOT_READY, 
-                     WRITE_PROTECTED);
+      SCSI_SenseCode(pdev, lun, NOT_READY, WRITE_PROTECTED);
       return -1;
-    } 
-    
-    
-    hmsc->scsi_blk_addr = (params[2] << 24) | \
-      (params[3] << 16) | \
-        (params[4] <<  8) | \
-          params[5];
-    hmsc->scsi_blk_len = (params[7] <<  8) | \
-      params[8];  
-    
+    }
+
+    hmsc->scsi_blk_addr = ((uint32_t)params[2] << 24) |
+                          ((uint32_t)params[3] << 16) |
+                          ((uint32_t)params[4] << 8) |
+                          (uint32_t)params[5];
+
+    hmsc->scsi_blk_len = ((uint32_t)params[7] << 8) |
+                         (uint32_t)params[8];
+
     /* check if LBA address is in the right range */
-    if(SCSI_CheckAddressRange(pdev,
-                              lun,
-                              hmsc->scsi_blk_addr,
-                              hmsc->scsi_blk_len) < 0)
+    if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr,
+                               hmsc->scsi_blk_len) < 0)
     {
-      return -1; /* error */      
+      return -1; /* error */
     }
-    
-    hmsc->scsi_blk_addr *= hmsc->scsi_blk_size;
-    hmsc->scsi_blk_len  *= hmsc->scsi_blk_size;
-    
+
+    len = hmsc->scsi_blk_len * hmsc->scsi_blk_size;
+
     /* cases 3,11,13 : Hn,Ho <> D0 */
-    if (hmsc->cbw.dDataLength != hmsc->scsi_blk_len)
+    if (hmsc->cbw.dDataLength != len)
     {
-      SCSI_SenseCode(pdev,
-                     hmsc->cbw.bLUN, 
-                     ILLEGAL_REQUEST, 
-                     INVALID_CDB);
+      SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB);
       return -1;
     }
-    
+
+    len = MIN(len, MSC_MEDIA_PACKET);
+
     /* Prepare EP to receive first data packet */
-    hmsc->bot_state = USBD_BOT_DATA_OUT;  
-    USBD_LL_PrepareReceive (pdev,
-                      MSC_EPOUT_ADDR,
-                      hmsc->bot_data, 
-                      MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET));  
+    hmsc->bot_state = USBD_BOT_DATA_OUT;
+    USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len);
   }
   else /* Write Process ongoing */
   {
@@ -612,27 +580,22 @@ static int8_t SCSI_Write10 (USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
 * @retval status
 */
 
-static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *params)
+static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun, uint8_t *params)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; 
-  
-  if ((params[1]& 0x02) == 0x02) 
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+
+  if ((params[1] & 0x02U) == 0x02U)
   {
-    SCSI_SenseCode (pdev,
-                    lun, 
-                    ILLEGAL_REQUEST, 
-                    INVALID_FIELED_IN_COMMAND);
+    SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
     return -1; /* Error, Verify Mode Not supported*/
   }
-  
-  if(SCSI_CheckAddressRange(pdev,
-                            lun, 
-                            hmsc->scsi_blk_addr, 
-                            hmsc->scsi_blk_len) < 0)
+
+  if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr,
+                             hmsc->scsi_blk_len) < 0)
   {
-    return -1; /* error */      
+    return -1; /* error */
   }
-  hmsc->bot_data_length = 0;
+  hmsc->bot_data_length = 0U;
   return 0;
 }
 
@@ -644,16 +607,14 @@ static int8_t SCSI_Verify10(USBD_HandleTypeDef  *pdev, uint8_t lun , uint8_t *pa
 * @param  blk_nbr: number of block to be processed
 * @retval status
 */
-static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
+static int8_t SCSI_CheckAddressRange(USBD_HandleTypeDef *pdev, uint8_t lun,
+                                     uint32_t blk_offset, uint32_t blk_nbr)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; 
-  
-  if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr )
+  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+
+  if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr)
   {
-    SCSI_SenseCode(pdev,
-                   lun, 
-                   ILLEGAL_REQUEST, 
-                   ADDRESS_OUT_OF_RANGE);
+    SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
     return -1;
   }
   return 0;
@@ -665,40 +626,31 @@ static int8_t SCSI_CheckAddressRange (USBD_HandleTypeDef  *pdev, uint8_t lun , u
 * @param  lun: Logical unit number
 * @retval status
 */
-static int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev, uint8_t lun)
+static int8_t SCSI_ProcessRead(USBD_HandleTypeDef  *pdev, uint8_t lun)
 {
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*)pdev->pClassData;   
-  uint32_t len;
-  
-  len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); 
-  
-  if( ((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun ,
-                              hmsc->bot_data, 
-                              hmsc->scsi_blk_addr / hmsc->scsi_blk_size, 
-                              len / hmsc->scsi_blk_size) < 0)
+  USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData;
+  uint32_t len = hmsc->scsi_blk_len * hmsc->scsi_blk_size;
+
+  len = MIN(len, MSC_MEDIA_PACKET);
+
+  if (((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun,
+                                                     hmsc->bot_data,
+                                                     hmsc->scsi_blk_addr,
+                                                     (len / hmsc->scsi_blk_size)) < 0)
   {
-    
-    SCSI_SenseCode(pdev,
-                   lun, 
-                   HARDWARE_ERROR, 
-                   UNRECOVERED_READ_ERROR);
-    return -1; 
+    SCSI_SenseCode(pdev, lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
+    return -1;
   }
-  
-  
-  USBD_LL_Transmit (pdev, 
-             MSC_EPIN_ADDR,
-             hmsc->bot_data,
-             len);
-  
-  
-  hmsc->scsi_blk_addr   += len; 
-  hmsc->scsi_blk_len    -= len;  
-  
+
+  USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, hmsc->bot_data, len);
+
+  hmsc->scsi_blk_addr += (len / hmsc->scsi_blk_size);
+  hmsc->scsi_blk_len -= (len / hmsc->scsi_blk_size);
+
   /* case 6 : Hi = Di */
   hmsc->csw.dDataResidue -= len;
-  
-  if (hmsc->scsi_blk_len == 0)
+
+  if (hmsc->scsi_blk_len == 0U)
   {
     hmsc->bot_state = USBD_BOT_LAST_DATA_IN;
   }
@@ -712,59 +664,53 @@ static int8_t SCSI_ProcessRead (USBD_HandleTypeDef  *pdev, uint8_t lun)
 * @retval status
 */
 
-static int8_t SCSI_ProcessWrite (USBD_HandleTypeDef  *pdev, uint8_t lun)
+static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef  *pdev, uint8_t lun)
 {
-  uint32_t len;
-  USBD_MSC_BOT_HandleTypeDef  *hmsc = (USBD_MSC_BOT_HandleTypeDef*) pdev->pClassData; 
-  
-  len = MIN(hmsc->scsi_blk_len , MSC_MEDIA_PACKET); 
-  
-  if(((USBD_StorageTypeDef *)pdev->pUserData)->Write(lun ,
-                              hmsc->bot_data, 
-                              hmsc->scsi_blk_addr / hmsc->scsi_blk_size, 
-                              len / hmsc->scsi_blk_size) < 0)
+  USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData;
+  uint32_t len = hmsc->scsi_blk_len * hmsc->scsi_blk_size;
+
+  len = MIN(len, MSC_MEDIA_PACKET);
+
+  if (((USBD_StorageTypeDef *)pdev->pUserData)->Write(lun, hmsc->bot_data,
+                                                      hmsc->scsi_blk_addr,
+                                                      (len / hmsc->scsi_blk_size)) < 0)
   {
-    SCSI_SenseCode(pdev,
-                   lun, 
-                   HARDWARE_ERROR, 
-                   WRITE_FAULT);     
-    return -1; 
+    SCSI_SenseCode(pdev, lun, HARDWARE_ERROR, WRITE_FAULT);
+
+    return -1;
   }
-  
-  
-  hmsc->scsi_blk_addr  += len; 
-  hmsc->scsi_blk_len   -= len; 
-  
+
+  hmsc->scsi_blk_addr += (len / hmsc->scsi_blk_size);
+  hmsc->scsi_blk_len -= (len / hmsc->scsi_blk_size);
+
   /* case 12 : Ho = Do */
   hmsc->csw.dDataResidue -= len;
-  
-  if (hmsc->scsi_blk_len == 0)
+
+  if (hmsc->scsi_blk_len == 0U)
   {
-    MSC_BOT_SendCSW (pdev, USBD_CSW_CMD_PASSED);
+    MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED);
   }
   else
   {
+    len = MIN((hmsc->scsi_blk_len * hmsc->scsi_blk_size), MSC_MEDIA_PACKET);
     /* Prepare EP to Receive next packet */
-    USBD_LL_PrepareReceive (pdev,
-                            MSC_EPOUT_ADDR,
-                            hmsc->bot_data, 
-                            MIN (hmsc->scsi_blk_len, MSC_MEDIA_PACKET)); 
+    USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len);
   }
-  
+
   return 0;
 }
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c
index c5ade746..dc6cc3de 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_storage_template.c
@@ -2,29 +2,26 @@
   ******************************************************************************
   * @file    usbd_msc_storage_template.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Memory management layer
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
+/* BSPDependencies
+- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c"
+- "stm32xxxxx_{eval}{discovery}_io.c"
+- "stm32xxxxx_{eval}{discovery}{adafruit}_sd.c"
+EndBSPDependencies */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_msc_storage_template.h"
@@ -38,49 +35,45 @@
 /* Extern function prototypes ------------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
-#define STORAGE_LUN_NBR                  1  
-#define STORAGE_BLK_NBR                  0x10000  
-#define STORAGE_BLK_SIZ                  0x200
+#define STORAGE_LUN_NBR                  1U
+#define STORAGE_BLK_NBR                  0x10000U
+#define STORAGE_BLK_SIZ                  0x200U
 
-int8_t STORAGE_Init (uint8_t lun);
+int8_t STORAGE_Init(uint8_t lun);
 
-int8_t STORAGE_GetCapacity (uint8_t lun, 
-                           uint32_t *block_num, 
+int8_t STORAGE_GetCapacity(uint8_t lun, uint32_t *block_num,
                            uint16_t *block_size);
 
-int8_t  STORAGE_IsReady (uint8_t lun);
+int8_t  STORAGE_IsReady(uint8_t lun);
 
-int8_t  STORAGE_IsWriteProtected (uint8_t lun);
+int8_t  STORAGE_IsWriteProtected(uint8_t lun);
 
-int8_t STORAGE_Read (uint8_t lun, 
-                        uint8_t *buf, 
-                        uint32_t blk_addr,
-                        uint16_t blk_len);
+int8_t STORAGE_Read(uint8_t lun, uint8_t *buf, uint32_t blk_addr,
+                    uint16_t blk_len);
 
-int8_t STORAGE_Write (uint8_t lun, 
-                        uint8_t *buf, 
-                        uint32_t blk_addr,
-                        uint16_t blk_len);
+int8_t STORAGE_Write(uint8_t lun, uint8_t *buf, uint32_t blk_addr,
+                     uint16_t blk_len);
 
-int8_t STORAGE_GetMaxLun (void);
+int8_t STORAGE_GetMaxLun(void);
 
 /* USB Mass storage Standard Inquiry Data */
-int8_t  STORAGE_Inquirydata[] = {//36
-  
+int8_t  STORAGE_Inquirydata[] =  /* 36 */
+{
+
   /* LUN 0 */
-  0x00,		
-  0x80,		
-  0x02,		
+  0x00,
+  0x80,
+  0x02,
   0x02,
   (STANDARD_INQUIRY_DATA_LEN - 5),
   0x00,
-  0x00,	
+  0x00,
   0x00,
   'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
   'P', 'r', 'o', 'd', 'u', 'c', 't', ' ', /* Product      : 16 Bytes */
   ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
-  '0', '.', '0' ,'1',                     /* Version      : 4 Bytes */
-}; 
+  '0', '.', '0', '1',                     /* Version      : 4 Bytes */
+};
 
 USBD_StorageTypeDef USBD_MSC_Template_fops =
 {
@@ -92,7 +85,7 @@ USBD_StorageTypeDef USBD_MSC_Template_fops =
   STORAGE_Write,
   STORAGE_GetMaxLun,
   STORAGE_Inquirydata,
-  
+
 };
 /*******************************************************************************
 * Function Name  : Read_Memory
@@ -101,7 +94,7 @@ USBD_StorageTypeDef USBD_MSC_Template_fops =
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t STORAGE_Init (uint8_t lun)
+int8_t STORAGE_Init(uint8_t lun)
 {
   return (0);
 }
@@ -113,7 +106,7 @@ int8_t STORAGE_Init (uint8_t lun)
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size)
+int8_t STORAGE_GetCapacity(uint8_t lun, uint32_t *block_num, uint16_t *block_size)
 {
   *block_num  = STORAGE_BLK_NBR;
   *block_size = STORAGE_BLK_SIZ;
@@ -127,7 +120,7 @@ int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_si
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t  STORAGE_IsReady (uint8_t lun)
+int8_t  STORAGE_IsReady(uint8_t lun)
 {
   return (0);
 }
@@ -139,7 +132,7 @@ int8_t  STORAGE_IsReady (uint8_t lun)
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t  STORAGE_IsWriteProtected (uint8_t lun)
+int8_t  STORAGE_IsWriteProtected(uint8_t lun)
 {
   return  0;
 }
@@ -151,10 +144,8 @@ int8_t  STORAGE_IsWriteProtected (uint8_t lun)
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t STORAGE_Read (uint8_t lun, 
-                 uint8_t *buf, 
-                 uint32_t blk_addr,                       
-                 uint16_t blk_len)
+int8_t STORAGE_Read(uint8_t lun, uint8_t *buf,
+                    uint32_t blk_addr, uint16_t blk_len)
 {
   return 0;
 }
@@ -165,10 +156,8 @@ int8_t STORAGE_Read (uint8_t lun,
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t STORAGE_Write (uint8_t lun, 
-                  uint8_t *buf, 
-                  uint32_t blk_addr,
-                  uint16_t blk_len)
+int8_t STORAGE_Write(uint8_t lun, uint8_t *buf,
+                     uint32_t blk_addr, uint16_t blk_len)
 {
   return (0);
 }
@@ -179,7 +168,7 @@ int8_t STORAGE_Write (uint8_t lun,
 * Output         : None.
 * Return         : None.
 *******************************************************************************/
-int8_t STORAGE_GetMaxLun (void)
+int8_t STORAGE_GetMaxLun(void)
 {
   return (STORAGE_LUN_NBR - 1);
 }
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h
index e1dfcee1..e47c41c2 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h
@@ -2,25 +2,17 @@
   ******************************************************************************
   * @file    usbd_conf_template.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header file for the usbd_conf_template.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
   */
@@ -30,7 +22,7 @@
 #define __USBD_CONF_TEMPLATE_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -42,114 +34,116 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_CONF
   * @brief USB device low level driver configuration file
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_CONF_Exported_Defines
   * @{
-  */ 
+  */
 
-#define USBD_MAX_NUM_INTERFACES               1
-#define USBD_MAX_NUM_CONFIGURATION            1
-#define USBD_MAX_STR_DESC_SIZ                 0x100
-#define USBD_SUPPORT_USER_STRING              0 
-#define USBD_SELF_POWERED                     1
-#define USBD_DEBUG_LEVEL                      2
+#define USBD_MAX_NUM_INTERFACES               1U
+#define USBD_MAX_NUM_CONFIGURATION            1U
+#define USBD_MAX_STR_DESC_SIZ                 0x100U
+#define USBD_SUPPORT_USER_STRING_DESC         0U
+#define USBD_SELF_POWERED                     1U
+#define USBD_DEBUG_LEVEL                      2U
 
 /* MSC Class Config */
-#define MSC_MEDIA_PACKET                       8192   
+#define MSC_MEDIA_PACKET                       8192U
 
 /* CDC Class Config */
-#define USBD_CDC_INTERVAL                      2000  
+#define USBD_CDC_INTERVAL                      2000U
 
- /* DFU Class Config */
-#define USBD_DFU_MAX_ITF_NUM                   1
-#define USBD_DFU_XFERS_IZE                     1024
+/* DFU Class Config */
+#define USBD_DFU_MAX_ITF_NUM                   1U
+#define USBD_DFU_XFERS_IZE                     1024U
 
- /* AUDIO Class Config */
-#define USBD_AUDIO_FREQ                       22100 
+/* AUDIO Class Config */
+#define USBD_AUDIO_FREQ                       22100U
 
 /** @defgroup USBD_Exported_Macros
   * @{
-  */ 
+  */
 
- /* Memory management macros */   
+/* Memory management macros */
 #define USBD_malloc               malloc
 #define USBD_free                 free
 #define USBD_memset               memset
 #define USBD_memcpy               memcpy
-    
- /* DEBUG macros */  
 
-  
-#if (USBD_DEBUG_LEVEL > 0)
-#define  USBD_UsrLog(...)   printf(__VA_ARGS__);\
-                            printf("\n");
+/* DEBUG macros */
+#if (USBD_DEBUG_LEVEL > 0U)
+#define  USBD_UsrLog(...)   do { \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
 #else
-#define USBD_UsrLog(...)   
-#endif 
-                            
-                            
-#if (USBD_DEBUG_LEVEL > 1)
-
-#define  USBD_ErrLog(...)   printf("ERROR: ") ;\
-                            printf(__VA_ARGS__);\
-                            printf("\n");
+#define USBD_UsrLog(...) do {} while (0)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 1U)
+
+#define  USBD_ErrLog(...) do { \
+                            printf("ERROR: ") ; \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
 #else
-#define USBD_ErrLog(...)   
-#endif 
-                            
-                            
-#if (USBD_DEBUG_LEVEL > 2)                         
-#define  USBD_DbgLog(...)   printf("DEBUG : ") ;\
-                            printf(__VA_ARGS__);\
-                            printf("\n");
+#define USBD_ErrLog(...) do {} while (0)
+#endif
+
+#if (USBD_DEBUG_LEVEL > 2U)
+#define  USBD_DbgLog(...)   do { \
+                            printf("DEBUG : ") ; \
+                            printf(__VA_ARGS__); \
+                            printf("\n"); \
+} while (0)
 #else
-#define USBD_DbgLog(...)                         
+#define USBD_DbgLog(...) do {} while (0)
 #endif
-                            
+
 /**
   * @}
-  */ 
- 
-    
-    
+  */
+
+
+
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_CONF_Exported_Types
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_CONF_Exported_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_CONF_Exported_Variables
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_CONF_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -160,10 +154,9 @@
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
index 8fc6b20e..23928158 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_core.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header file for usbd_core.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_CORE_H
 #define __USBD_CORE_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -42,65 +34,67 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_CORE
   * @brief This file is the Header file for usbd_core.c file
   * @{
-  */ 
+  */
 
 
 /** @defgroup USBD_CORE_Exported_Defines
   * @{
-  */ 
-
+  */
+#ifndef USBD_DEBUG_LEVEL
+#define USBD_DEBUG_LEVEL           0U
+#endif /* USBD_DEBUG_LEVEL */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_CORE_Exported_TypesDefinitions
   * @{
   */
- 
+
 
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_CORE_Exported_Macros
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_CORE_Exported_Variables
   * @{
-  */ 
+  */
 #define USBD_SOF          USBD_LL_SOF
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_CORE_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
 USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_Start  (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef USBD_Stop   (USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
 USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
 
-USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef  *pdev); 
+USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef  *pdev);
 USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
 USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);
 
 USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
-USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);
-USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
 
 USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);
 USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);
@@ -115,37 +109,37 @@ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);
 USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);
 
 /* USBD Low Level Driver */
-USBD_StatusTypeDef  USBD_LL_Init (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef  USBD_LL_DeInit (USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_Init(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
 USBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef  USBD_LL_Stop (USBD_HandleTypeDef *pdev);
-USBD_StatusTypeDef  USBD_LL_OpenEP  (USBD_HandleTypeDef *pdev, 
-                                      uint8_t  ep_addr,                                      
-                                      uint8_t  ep_type,
-                                      uint16_t ep_mps);
-
-USBD_StatusTypeDef  USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   
-USBD_StatusTypeDef  USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   
-USBD_StatusTypeDef  USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   
-USBD_StatusTypeDef  USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   
-uint8_t             USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   
-USBD_StatusTypeDef  USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr);   
-USBD_StatusTypeDef  USBD_LL_Transmit (USBD_HandleTypeDef *pdev, 
-                                      uint8_t  ep_addr,                                      
-                                      uint8_t  *pbuf,
-                                      uint16_t  size);
-
-USBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, 
-                                           uint8_t  ep_addr,                                      
+USBD_StatusTypeDef  USBD_LL_Stop(USBD_HandleTypeDef *pdev);
+USBD_StatusTypeDef  USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
+                                   uint8_t  ep_addr,
+                                   uint8_t  ep_type,
+                                   uint16_t ep_mps);
+
+USBD_StatusTypeDef  USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+uint8_t             USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
+USBD_StatusTypeDef  USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
+USBD_StatusTypeDef  USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
+                                     uint8_t  ep_addr,
+                                     uint8_t  *pbuf,
+                                     uint16_t  size);
+
+USBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
+                                           uint8_t  ep_addr,
                                            uint8_t  *pbuf,
                                            uint16_t  size);
 
-uint32_t USBD_LL_GetRxDataSize  (USBD_HandleTypeDef *pdev, uint8_t  ep_addr);  
-void  USBD_LL_Delay (uint32_t Delay);
+uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t  ep_addr);
+void  USBD_LL_Delay(uint32_t Delay);
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -155,11 +149,11 @@ void  USBD_LL_Delay (uint32_t Delay);
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
index d2d36c82..047fe2ef 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_req.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header file for the usbd_req.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USB_REQUEST_H
 #define __USB_REQUEST_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -40,18 +32,18 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_REQ
   * @brief header file for the usbd_req.c file
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_REQ_Exported_Defines
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Exported_Types
@@ -59,41 +51,41 @@
   */
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_REQ_Exported_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_REQ_Exported_Variables
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_REQ_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 
-USBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
-USBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
-USBD_StatusTypeDef  USBD_StdEPReq  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);
 
 
-void USBD_CtlError  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);
+void USBD_CtlError(USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);
 
-void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata);
+void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
 
-void USBD_GetString         (uint8_t *desc, uint8_t *unicode, uint16_t *len);
+void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -103,11 +95,11 @@ void USBD_GetString         (uint8_t *desc, uint8_t *unicode, uint16_t *len);
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
index 52bb19b0..a805e8b7 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_def.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
-  * @brief   General defines for the usb device library 
+  * @brief   General defines for the usb device library
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_DEF_H
 #define __USBD_DEF_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -39,186 +31,206 @@
 /** @addtogroup STM32_USBD_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USB_DEF
   * @brief general defines for the usb device library file
   * @{
-  */ 
+  */
 
 /** @defgroup USB_DEF_Exported_Defines
   * @{
-  */ 
+  */
 
 #ifndef NULL
-#define NULL  0
-#endif
-
-
-#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0A
-#define  USB_LEN_DEV_DESC                               0x12
-#define  USB_LEN_CFG_DESC                               0x09
-#define  USB_LEN_IF_DESC                                0x09
-#define  USB_LEN_EP_DESC                                0x07
-#define  USB_LEN_OTG_DESC                               0x03
-#define  USB_LEN_LANGID_STR_DESC                        0x04
-#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09
-
-#define  USBD_IDX_LANGID_STR                            0x00 
-#define  USBD_IDX_MFC_STR                               0x01 
-#define  USBD_IDX_PRODUCT_STR                           0x02
-#define  USBD_IDX_SERIAL_STR                            0x03 
-#define  USBD_IDX_CONFIG_STR                            0x04 
-#define  USBD_IDX_INTERFACE_STR                         0x05 
-
-#define  USB_REQ_TYPE_STANDARD                          0x00
-#define  USB_REQ_TYPE_CLASS                             0x20
-#define  USB_REQ_TYPE_VENDOR                            0x40
-#define  USB_REQ_TYPE_MASK                              0x60
-
-#define  USB_REQ_RECIPIENT_DEVICE                       0x00
-#define  USB_REQ_RECIPIENT_INTERFACE                    0x01
-#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02
-#define  USB_REQ_RECIPIENT_MASK                         0x03
-
-#define  USB_REQ_GET_STATUS                             0x00
-#define  USB_REQ_CLEAR_FEATURE                          0x01
-#define  USB_REQ_SET_FEATURE                            0x03
-#define  USB_REQ_SET_ADDRESS                            0x05
-#define  USB_REQ_GET_DESCRIPTOR                         0x06
-#define  USB_REQ_SET_DESCRIPTOR                         0x07
-#define  USB_REQ_GET_CONFIGURATION                      0x08
-#define  USB_REQ_SET_CONFIGURATION                      0x09
-#define  USB_REQ_GET_INTERFACE                          0x0A
-#define  USB_REQ_SET_INTERFACE                          0x0B
-#define  USB_REQ_SYNCH_FRAME                            0x0C
-
-#define  USB_DESC_TYPE_DEVICE                              1
-#define  USB_DESC_TYPE_CONFIGURATION                       2
-#define  USB_DESC_TYPE_STRING                              3
-#define  USB_DESC_TYPE_INTERFACE                           4
-#define  USB_DESC_TYPE_ENDPOINT                            5
-#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    6
-#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           7
-#define  USB_DESC_TYPE_BOS                                 0x0F
-
-#define USB_CONFIG_REMOTE_WAKEUP                           2
-#define USB_CONFIG_SELF_POWERED                            1
-
-#define USB_FEATURE_EP_HALT                                0
-#define USB_FEATURE_REMOTE_WAKEUP                          1
-#define USB_FEATURE_TEST_MODE                              2
-
-#define USB_DEVICE_CAPABITY_TYPE                           0x10
-
-#define USB_HS_MAX_PACKET_SIZE                            512
-#define USB_FS_MAX_PACKET_SIZE                            64
-#define USB_MAX_EP0_SIZE                                  64
+#define NULL                                            0U
+#endif /* NULL */
+
+#ifndef USBD_MAX_NUM_INTERFACES
+#define USBD_MAX_NUM_INTERFACES                         1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_MAX_NUM_CONFIGURATION
+#define USBD_MAX_NUM_CONFIGURATION                      1U
+#endif /* USBD_MAX_NUM_CONFIGURATION */
+
+#ifndef USBD_LPM_ENABLED
+#define USBD_LPM_ENABLED                                0U
+#endif /* USBD_LPM_ENABLED */
+
+#ifndef USBD_SELF_POWERED
+#define USBD_SELF_POWERED                               1U
+#endif /*USBD_SELF_POWERED */
+
+#ifndef USBD_SUPPORT_USER_STRING_DESC
+#define USBD_SUPPORT_USER_STRING_DESC                   0U
+#endif /* USBD_SUPPORT_USER_STRING_DESC */
+
+#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0AU
+#define  USB_LEN_DEV_DESC                               0x12U
+#define  USB_LEN_CFG_DESC                               0x09U
+#define  USB_LEN_IF_DESC                                0x09U
+#define  USB_LEN_EP_DESC                                0x07U
+#define  USB_LEN_OTG_DESC                               0x03U
+#define  USB_LEN_LANGID_STR_DESC                        0x04U
+#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09U
+
+#define  USBD_IDX_LANGID_STR                            0x00U
+#define  USBD_IDX_MFC_STR                               0x01U
+#define  USBD_IDX_PRODUCT_STR                           0x02U
+#define  USBD_IDX_SERIAL_STR                            0x03U
+#define  USBD_IDX_CONFIG_STR                            0x04U
+#define  USBD_IDX_INTERFACE_STR                         0x05U
+
+#define  USB_REQ_TYPE_STANDARD                          0x00U
+#define  USB_REQ_TYPE_CLASS                             0x20U
+#define  USB_REQ_TYPE_VENDOR                            0x40U
+#define  USB_REQ_TYPE_MASK                              0x60U
+
+#define  USB_REQ_RECIPIENT_DEVICE                       0x00U
+#define  USB_REQ_RECIPIENT_INTERFACE                    0x01U
+#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02U
+#define  USB_REQ_RECIPIENT_MASK                         0x03U
+
+#define  USB_REQ_GET_STATUS                             0x00U
+#define  USB_REQ_CLEAR_FEATURE                          0x01U
+#define  USB_REQ_SET_FEATURE                            0x03U
+#define  USB_REQ_SET_ADDRESS                            0x05U
+#define  USB_REQ_GET_DESCRIPTOR                         0x06U
+#define  USB_REQ_SET_DESCRIPTOR                         0x07U
+#define  USB_REQ_GET_CONFIGURATION                      0x08U
+#define  USB_REQ_SET_CONFIGURATION                      0x09U
+#define  USB_REQ_GET_INTERFACE                          0x0AU
+#define  USB_REQ_SET_INTERFACE                          0x0BU
+#define  USB_REQ_SYNCH_FRAME                            0x0CU
+
+#define  USB_DESC_TYPE_DEVICE                           0x01U
+#define  USB_DESC_TYPE_CONFIGURATION                    0x02U
+#define  USB_DESC_TYPE_STRING                           0x03U
+#define  USB_DESC_TYPE_INTERFACE                        0x04U
+#define  USB_DESC_TYPE_ENDPOINT                         0x05U
+#define  USB_DESC_TYPE_DEVICE_QUALIFIER                 0x06U
+#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION        0x07U
+#define  USB_DESC_TYPE_BOS                              0x0FU
+
+#define USB_CONFIG_REMOTE_WAKEUP                        0x02U
+#define USB_CONFIG_SELF_POWERED                         0x01U
+
+#define USB_FEATURE_EP_HALT                             0x00U
+#define USB_FEATURE_REMOTE_WAKEUP                       0x01U
+#define USB_FEATURE_TEST_MODE                           0x02U
+
+#define USB_DEVICE_CAPABITY_TYPE                        0x10U
+
+#define USB_HS_MAX_PACKET_SIZE                          512U
+#define USB_FS_MAX_PACKET_SIZE                          64U
+#define USB_MAX_EP0_SIZE                                64U
 
 /*  Device Status */
-#define USBD_STATE_DEFAULT                                1
-#define USBD_STATE_ADDRESSED                              2
-#define USBD_STATE_CONFIGURED                             3
-#define USBD_STATE_SUSPENDED                              4
+#define USBD_STATE_DEFAULT                              0x01U
+#define USBD_STATE_ADDRESSED                            0x02U
+#define USBD_STATE_CONFIGURED                           0x03U
+#define USBD_STATE_SUSPENDED                            0x04U
 
 
-/*  EP0 State */    
-#define USBD_EP0_IDLE                                     0
-#define USBD_EP0_SETUP                                    1
-#define USBD_EP0_DATA_IN                                  2
-#define USBD_EP0_DATA_OUT                                 3
-#define USBD_EP0_STATUS_IN                                4
-#define USBD_EP0_STATUS_OUT                               5
-#define USBD_EP0_STALL                                    6    
+/*  EP0 State */
+#define USBD_EP0_IDLE                                   0x00U
+#define USBD_EP0_SETUP                                  0x01U
+#define USBD_EP0_DATA_IN                                0x02U
+#define USBD_EP0_DATA_OUT                               0x03U
+#define USBD_EP0_STATUS_IN                              0x04U
+#define USBD_EP0_STATUS_OUT                             0x05U
+#define USBD_EP0_STALL                                  0x06U
 
-#define USBD_EP_TYPE_CTRL                                 0
-#define USBD_EP_TYPE_ISOC                                 1
-#define USBD_EP_TYPE_BULK                                 2
-#define USBD_EP_TYPE_INTR                                 3
+#define USBD_EP_TYPE_CTRL                               0x00U
+#define USBD_EP_TYPE_ISOC                               0x01U
+#define USBD_EP_TYPE_BULK                               0x02U
+#define USBD_EP_TYPE_INTR                               0x03U
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_DEF_Exported_TypesDefinitions
   * @{
   */
 
-typedef  struct  usb_setup_req 
+typedef  struct  usb_setup_req
 {
-    
-    uint8_t   bmRequest;                      
-    uint8_t   bRequest;                           
-    uint16_t  wValue;                             
-    uint16_t  wIndex;                             
-    uint16_t  wLength;                            
-}USBD_SetupReqTypedef;
+  uint8_t   bmRequest;
+  uint8_t   bRequest;
+  uint16_t  wValue;
+  uint16_t  wIndex;
+  uint16_t  wLength;
+} USBD_SetupReqTypedef;
 
 struct _USBD_HandleTypeDef;
-    
+
 typedef struct _Device_cb
 {
-  uint8_t  (*Init)             (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);
-  uint8_t  (*DeInit)           (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);
- /* Control Endpoints*/
-  uint8_t  (*Setup)            (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req);  
-  uint8_t  (*EP0_TxSent)       (struct _USBD_HandleTypeDef *pdev );    
-  uint8_t  (*EP0_RxReady)      (struct _USBD_HandleTypeDef *pdev );  
+  uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
+  /* Control Endpoints*/
+  uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef  *req);
+  uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
   /* Class Specific Endpoints*/
-  uint8_t  (*DataIn)           (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   
-  uint8_t  (*DataOut)          (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); 
-  uint8_t  (*SOF)              (struct _USBD_HandleTypeDef *pdev); 
-  uint8_t  (*IsoINIncomplete)  (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); 
-  uint8_t  (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   
-
-  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length); 
-  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);   
+  uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
+  uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+  uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
+
+  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length);
+  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);
   uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
   uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);
-#if (USBD_SUPPORT_USER_STRING == 1)
-  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index,  uint16_t *length);   
-#endif  
-  
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);
+#endif
+
 } USBD_ClassTypeDef;
 
 /* Following USB Device Speed */
-typedef enum 
+typedef enum
 {
-  USBD_SPEED_HIGH  = 0,
-  USBD_SPEED_FULL  = 1,
-  USBD_SPEED_LOW   = 2,  
-}USBD_SpeedTypeDef;
+  USBD_SPEED_HIGH  = 0U,
+  USBD_SPEED_FULL  = 1U,
+  USBD_SPEED_LOW   = 2U,
+} USBD_SpeedTypeDef;
 
 /* Following USB Device status */
-typedef enum {
-  USBD_OK   = 0,
+typedef enum
+{
+  USBD_OK   = 0U,
   USBD_BUSY,
   USBD_FAIL,
-}USBD_StatusTypeDef;
+} USBD_StatusTypeDef;
 
 /* USB Device descriptors structure */
 typedef struct
 {
-  uint8_t  *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); 
-  uint8_t  *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  
-  uint8_t  *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); 
-#if (USBD_LPM_ENABLED == 1)
-  uint8_t  *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); 
-#endif  
+  uint8_t  *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+  uint8_t  *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#if (USBD_LPM_ENABLED == 1U)
+  uint8_t  *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
+#endif
 } USBD_DescriptorsTypeDef;
 
 /* USB Device handle structure */
 typedef struct
-{ 
+{
   uint32_t                status;
-  uint32_t                total_length;    
-  uint32_t                rem_length; 
-  uint32_t                maxpacket;   
+  uint32_t                is_used;
+  uint32_t                total_length;
+  uint32_t                rem_length;
+  uint32_t                maxpacket;
 } USBD_EndpointTypeDef;
 
 /* USB Device handle structure */
@@ -227,92 +239,98 @@ typedef struct _USBD_HandleTypeDef
   uint8_t                 id;
   uint32_t                dev_config;
   uint32_t                dev_default_config;
-  uint32_t                dev_config_status; 
-  USBD_SpeedTypeDef       dev_speed; 
-  USBD_EndpointTypeDef    ep_in[15];
-  USBD_EndpointTypeDef    ep_out[15];  
-  uint32_t                ep0_state;  
-  uint32_t                ep0_data_len;     
+  uint32_t                dev_config_status;
+  USBD_SpeedTypeDef       dev_speed;
+  USBD_EndpointTypeDef    ep_in[16];
+  USBD_EndpointTypeDef    ep_out[16];
+  uint32_t                ep0_state;
+  uint32_t                ep0_data_len;
   uint8_t                 dev_state;
   uint8_t                 dev_old_state;
   uint8_t                 dev_address;
-  uint8_t                 dev_connection_status;  
+  uint8_t                 dev_connection_status;
   uint8_t                 dev_test_mode;
   uint32_t                dev_remote_wakeup;
 
   USBD_SetupReqTypedef    request;
   USBD_DescriptorsTypeDef *pDesc;
   USBD_ClassTypeDef       *pClass;
-  void                    *pClassData;  
-  void                    *pUserData;    
-  void                    *pData;    
+  void                    *pClassData;
+  void                    *pUserData;
+  void                    *pData;
 } USBD_HandleTypeDef;
 
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_DEF_Exported_Macros
   * @{
-  */ 
+  */
 #define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \
-                               (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
+                               (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
 
-#define LOBYTE(x)  ((uint8_t)(x & 0x00FF))
-#define HIBYTE(x)  ((uint8_t)((x & 0xFF00) >>8))
+#define LOBYTE(x)  ((uint8_t)((x) & 0x00FFU))
+#define HIBYTE(x)  ((uint8_t)(((x) & 0xFF00U) >> 8U))
 #define MIN(a, b)  (((a) < (b)) ? (a) : (b))
 #define MAX(a, b)  (((a) > (b)) ? (a) : (b))
 
 
 #if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
 #endif /* __GNUC__ */
 
 
 /* In HS mode and when the DMA is used, all variables and data structures dealing
-   with the DMA during the transaction process should be 4-bytes aligned */    
-
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #define __ALIGN_BEGIN         
-#else                           
-  #define __ALIGN_END
-  #if defined   (__CC_ARM)      /* ARM Compiler */
-    #define __ALIGN_BEGIN    __align(4)  
-  #elif defined (__ICCARM__)    /* IAR Compiler */
-    #define __ALIGN_BEGIN 
-  #elif defined  (__TASKING__)  /* TASKING Compiler */
-    #define __ALIGN_BEGIN    __align(4) 
-  #endif /* __CC_ARM */  
-#endif /* __GNUC__ */ 
-  
+   with the DMA during the transaction process should be 4-bytes aligned */
+
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+#ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4U)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#else
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined   (__CC_ARM)      /* ARM Compiler */
+#define __ALIGN_BEGIN    __align(4U)
+#elif defined (__ICCARM__)    /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_DEF_Exported_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_DEF_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -322,9 +340,9 @@ typedef struct _USBD_HandleTypeDef
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
index 3cd921ea..629369ea 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
@@ -2,35 +2,27 @@
   ******************************************************************************
   * @file    usbd_ioreq.h
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   Header file for the usbd_ioreq.c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __USBD_IOREQ_H
 #define __USBD_IOREQ_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -40,18 +32,18 @@
 /** @addtogroup STM32_USB_DEVICE_LIBRARY
   * @{
   */
-  
+
 /** @defgroup USBD_IOREQ
   * @brief header file for the usbd_ioreq.c file
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_IOREQ_Exported_Defines
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Exported_Types
@@ -61,56 +53,55 @@
 
 /**
   * @}
-  */ 
+  */
 
 
 
 /** @defgroup USBD_IOREQ_Exported_Macros
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_IOREQ_Exported_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
   * @{
-  */ 
+  */
 
-USBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, 
-                               uint8_t *buf,
-                               uint16_t len);
+USBD_StatusTypeDef  USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
 
-USBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, 
-                               uint8_t *pbuf,
-                               uint16_t len);
+USBD_StatusTypeDef  USBD_CtlContinueSendData(USBD_HandleTypeDef  *pdev,
+                                             uint8_t *pbuf,
+                                             uint16_t len);
 
-USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev, 
-                               uint8_t *pbuf,                                 
-                               uint16_t len);
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef  *pdev,
+                                     uint8_t *pbuf,
+                                     uint16_t len);
 
-USBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, 
-                              uint8_t *pbuf,                                          
-                              uint16_t len);
+USBD_StatusTypeDef  USBD_CtlContinueRx(USBD_HandleTypeDef  *pdev,
+                                       uint8_t *pbuf,
+                                       uint16_t len);
 
-USBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef  USBD_CtlSendStatus(USBD_HandleTypeDef  *pdev);
 
-USBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev);
+USBD_StatusTypeDef  USBD_CtlReceiveStatus(USBD_HandleTypeDef  *pdev);
 
-uint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , 
-                           uint8_t epnum);
+uint32_t  USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
 
 /**
   * @}
-  */ 
+  */
 
 #ifdef __cplusplus
 }
@@ -120,9 +111,9 @@ uint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev ,
 
 /**
   * @}
-  */ 
+  */
 
 /**
 * @}
-*/ 
+*/
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
index 67fba120..dbc75d89 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c
@@ -2,30 +2,22 @@
   ******************************************************************************
   * @file    usbd_conf_template.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   USB Device configuration and interface file
-  *          This template should be copied to the user folder, renamed and customized
-  *          following user needs.  
+  *          This template should be copied to the user folder,
+  *          renamed and customized following user needs.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_core.h"
@@ -41,7 +33,7 @@
   * @retval USBD Status
   */
 USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
-{    
+{
   return USBD_OK;
 }
 
@@ -56,7 +48,7 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
 }
 
 /**
-  * @brief  Starts the Low Level portion of the Device driver. 
+  * @brief  Starts the Low Level portion of the Device driver.
   * @param  pdev: Device handle
   * @retval USBD Status
   */
@@ -83,10 +75,8 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
   * @param  ep_mps: Endpoint Max Packet Size
   * @retval USBD Status
   */
-USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
-                                  uint8_t ep_addr,
-                                  uint8_t ep_type,
-                                  uint16_t ep_mps)
+USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
+                                  uint8_t ep_type, uint16_t ep_mps)
 {
   return USBD_OK;
 }
@@ -130,9 +120,10 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
   * @param  ep_addr: Endpoint Number
   * @retval USBD Status
   */
-USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
+USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev,
+                                        uint8_t ep_addr)
 {
-  return USBD_OK; 
+  return USBD_OK;
 }
 
 /**
@@ -143,7 +134,7 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add
   */
 uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
-   return 0;
+  return 0;
 }
 
 /**
@@ -152,9 +143,10 @@ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
   * @param  ep_addr: Endpoint Number
   * @retval USBD Status
   */
-USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
+USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev,
+                                         uint8_t dev_addr)
 {
-  return USBD_OK; 
+  return USBD_OK;
 }
 
 /**
@@ -162,13 +154,11 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a
   * @param  pdev: Device handle
   * @param  ep_addr: Endpoint Number
   * @param  pbuf: Pointer to data to be sent
-  * @param  size: Data size    
+  * @param  size: Data size
   * @retval USBD Status
   */
-USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, 
-                                    uint8_t ep_addr,
-                                    uint8_t *pbuf,
-                                    uint16_t size)
+USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr,
+                                    uint8_t *pbuf, uint16_t size)
 {
   return USBD_OK;
 }
@@ -181,9 +171,8 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
   * @param  size: Data size
   * @retval USBD Status
   */
-USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, 
-                                          uint8_t ep_addr,
-                                          uint8_t *pbuf,
+USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
+                                          uint8_t ep_addr, uint8_t *pbuf,
                                           uint16_t size)
 {
   return USBD_OK;
@@ -197,7 +186,7 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
   */
 uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
-  return 0;
+  return 0U;
 }
 
 /**
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
index 3af2b7c7..ca879777 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c
@@ -2,28 +2,20 @@
   ******************************************************************************
   * @file    usbd_core.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides all the USBD core functions.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_core.h"
@@ -33,57 +25,58 @@
 */
 
 
-/** @defgroup USBD_CORE 
+/** @defgroup USBD_CORE
 * @brief usbd core module
 * @{
-*/ 
+*/
 
 /** @defgroup USBD_CORE_Private_TypesDefinitions
 * @{
-*/ 
+*/
+
 /**
 * @}
-*/ 
+*/
 
 
 /** @defgroup USBD_CORE_Private_Defines
 * @{
-*/ 
+*/
 
 /**
 * @}
-*/ 
+*/
 
 
 /** @defgroup USBD_CORE_Private_Macros
 * @{
-*/ 
+*/
+
 /**
 * @}
-*/ 
-
-
+*/
 
 
 /** @defgroup USBD_CORE_Private_FunctionPrototypes
 * @{
-*/ 
+*/
 
 /**
 * @}
-*/ 
+*/
 
 /** @defgroup USBD_CORE_Private_Variables
 * @{
-*/ 
+*/
 
 /**
 * @}
-*/ 
+*/
+
 
 /** @defgroup USBD_CORE_Private_Functions
 * @{
-*/ 
+*/
 
 /**
 * @brief  USBD_Init
@@ -93,38 +86,41 @@
 * @param  id: Low level core index
 * @retval None
 */
-USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id)
+USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
+                             USBD_DescriptorsTypeDef *pdesc, uint8_t id)
 {
   /* Check whether the USB Host handle is valid */
-  if(pdev == NULL)
+  if (pdev == NULL)
   {
+#if (USBD_DEBUG_LEVEL > 1U)
     USBD_ErrLog("Invalid Device handle");
-    return USBD_FAIL; 
+#endif
+    return USBD_FAIL;
   }
-  
+
   /* Unlink previous class*/
-  if(pdev->pClass != NULL)
+  if (pdev->pClass != NULL)
   {
     pdev->pClass = NULL;
   }
-  
+
   /* Assign USBD Descriptors */
-  if(pdesc != NULL)
+  if (pdesc != NULL)
   {
     pdev->pDesc = pdesc;
   }
-  
+
   /* Set Device initial State */
-  pdev->dev_state  = USBD_STATE_DEFAULT;
+  pdev->dev_state = USBD_STATE_DEFAULT;
   pdev->id = id;
   /* Initialize low level driver */
   USBD_LL_Init(pdev);
-  
-  return USBD_OK; 
+
+  return USBD_OK;
 }
 
 /**
-* @brief  USBD_DeInit 
+* @brief  USBD_DeInit
 *         Re-Initialize th device library
 * @param  pdev: device instance
 * @retval status: status
@@ -132,23 +128,22 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *
 USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
 {
   /* Set Default State */
-  pdev->dev_state  = USBD_STATE_DEFAULT;
-  
+  pdev->dev_state = USBD_STATE_DEFAULT;
+
   /* Free Class Resources */
-  pdev->pClass->DeInit(pdev, pdev->dev_config);  
-  
-    /* Stop the low level driver  */
-  USBD_LL_Stop(pdev); 
-  
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
+  /* Stop the low level driver  */
+  USBD_LL_Stop(pdev);
+
   /* Initialize low level driver */
   USBD_LL_DeInit(pdev);
-  
+
   return USBD_OK;
 }
 
-
 /**
-  * @brief  USBD_RegisterClass 
+  * @brief  USBD_RegisterClass
   *         Link class driver to Device Core.
   * @param  pDevice : Device Handle
   * @param  pclass: Class handle
@@ -156,8 +151,8 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
   */
 USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
 {
-  USBD_StatusTypeDef   status = USBD_OK;
-  if(pclass != 0)
+  USBD_StatusTypeDef status = USBD_OK;
+  if (pclass != NULL)
   {
     /* link the class to the USB Device handle */
     pdev->pClass = pclass;
@@ -165,59 +160,62 @@ USBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeD
   }
   else
   {
+#if (USBD_DEBUG_LEVEL > 1U)
     USBD_ErrLog("Invalid Class handle");
-    status = USBD_FAIL; 
+#endif
+    status = USBD_FAIL;
   }
-  
+
   return status;
 }
 
 /**
-  * @brief  USBD_Start 
+  * @brief  USBD_Start
   *         Start the USB Device Core.
   * @param  pdev: Device Handle
   * @retval USBD Status
   */
-USBD_StatusTypeDef  USBD_Start  (USBD_HandleTypeDef *pdev)
+USBD_StatusTypeDef  USBD_Start(USBD_HandleTypeDef *pdev)
 {
-  
   /* Start the low level driver  */
-  USBD_LL_Start(pdev); 
-  
-  return USBD_OK;  
+  USBD_LL_Start(pdev);
+
+  return USBD_OK;
 }
 
 /**
-  * @brief  USBD_Stop 
+  * @brief  USBD_Stop
   *         Stop the USB Device Core.
   * @param  pdev: Device Handle
   * @retval USBD Status
   */
-USBD_StatusTypeDef  USBD_Stop   (USBD_HandleTypeDef *pdev)
+USBD_StatusTypeDef  USBD_Stop(USBD_HandleTypeDef *pdev)
 {
   /* Free Class Resources */
-  pdev->pClass->DeInit(pdev, pdev->dev_config);  
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
 
-  /* Stop the low level driver  */
-  USBD_LL_Stop(pdev); 
-  
-  return USBD_OK;  
+  /* Stop the low level driver */
+  USBD_LL_Stop(pdev);
+
+  return USBD_OK;
 }
 
 /**
-* @brief  USBD_RunTestMode 
+* @brief  USBD_RunTestMode
 *         Launch test mode process
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev) 
+USBD_StatusTypeDef  USBD_RunTestMode(USBD_HandleTypeDef  *pdev)
 {
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
   return USBD_OK;
 }
 
-
 /**
-* @brief  USBD_SetClassConfig 
+* @brief  USBD_SetClassConfig
 *        Configure device and start the interface
 * @param  pdev: device instance
 * @param  cfgidx: configuration index
@@ -226,21 +224,22 @@ USBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev)
 
 USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
 {
-  USBD_StatusTypeDef   ret = USBD_FAIL;
-  
-  if(pdev->pClass != NULL)
+  USBD_StatusTypeDef ret = USBD_FAIL;
+
+  if (pdev->pClass != NULL)
   {
     /* Set configuration  and Start the Class*/
-    if(pdev->pClass->Init(pdev, cfgidx) == 0)
+    if (pdev->pClass->Init(pdev, cfgidx) == 0U)
     {
       ret = USBD_OK;
     }
   }
-  return ret; 
+
+  return ret;
 }
 
 /**
-* @brief  USBD_ClrClassConfig 
+* @brief  USBD_ClrClassConfig
 *         Clear current configuration
 * @param  pdev: device instance
 * @param  cfgidx: configuration index
@@ -249,317 +248,364 @@ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx
 USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)
 {
   /* Clear configuration  and De-initialize the Class process*/
-  pdev->pClass->DeInit(pdev, cfgidx);  
+  pdev->pClass->DeInit(pdev, cfgidx);
+
   return USBD_OK;
 }
 
 
 /**
-* @brief  USBD_SetupStage 
+* @brief  USBD_SetupStage
 *         Handle the setup stage
 * @param  pdev: device instance
 * @retval status
 */
 USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
 {
-
   USBD_ParseSetupRequest(&pdev->request, psetup);
-  
+
   pdev->ep0_state = USBD_EP0_SETUP;
+
   pdev->ep0_data_len = pdev->request.wLength;
-  
-  switch (pdev->request.bmRequest & 0x1F) 
+
+  switch (pdev->request.bmRequest & 0x1FU)
   {
-  case USB_REQ_RECIPIENT_DEVICE:   
-    USBD_StdDevReq (pdev, &pdev->request);
-    break;
-    
-  case USB_REQ_RECIPIENT_INTERFACE:     
-    USBD_StdItfReq(pdev, &pdev->request);
-    break;
-    
-  case USB_REQ_RECIPIENT_ENDPOINT:        
-    USBD_StdEPReq(pdev, &pdev->request);   
-    break;
-    
-  default:           
-    USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80);
-    break;
-  }  
-  return USBD_OK;  
+    case USB_REQ_RECIPIENT_DEVICE:
+      USBD_StdDevReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_INTERFACE:
+      USBD_StdItfReq(pdev, &pdev->request);
+      break;
+
+    case USB_REQ_RECIPIENT_ENDPOINT:
+      USBD_StdEPReq(pdev, &pdev->request);
+      break;
+
+    default:
+      USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
+      break;
+  }
+
+  return USBD_OK;
 }
 
 /**
-* @brief  USBD_DataOutStage 
+* @brief  USBD_DataOutStage
 *         Handle data OUT stage
 * @param  pdev: device instance
 * @param  epnum: endpoint index
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata)
+USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
+                                        uint8_t epnum, uint8_t *pdata)
 {
-  USBD_EndpointTypeDef    *pep;
-  
-  if(epnum == 0) 
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
   {
     pep = &pdev->ep_out[0];
-    
-    if ( pdev->ep0_state == USBD_EP0_DATA_OUT)
+
+    if (pdev->ep0_state == USBD_EP0_DATA_OUT)
     {
-      if(pep->rem_length > pep->maxpacket)
+      if (pep->rem_length > pep->maxpacket)
       {
-        pep->rem_length -=  pep->maxpacket;
-       
-        USBD_CtlContinueRx (pdev, 
-                            pdata,
-                            MIN(pep->rem_length ,pep->maxpacket));
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueRx(pdev, pdata,
+                           (uint16_t)MIN(pep->rem_length, pep->maxpacket));
       }
       else
       {
-        if((pdev->pClass->EP0_RxReady != NULL)&&
-           (pdev->dev_state == USBD_STATE_CONFIGURED))
+        if ((pdev->pClass->EP0_RxReady != NULL) &&
+            (pdev->dev_state == USBD_STATE_CONFIGURED))
         {
-          pdev->pClass->EP0_RxReady(pdev); 
+          pdev->pClass->EP0_RxReady(pdev);
         }
         USBD_CtlSendStatus(pdev);
       }
     }
+    else
+    {
+      if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
+      {
+        /*
+         * STATUS PHASE completed, update ep0_state to idle
+         */
+        pdev->ep0_state = USBD_EP0_IDLE;
+        USBD_LL_StallEP(pdev, 0U);
+      }
+    }
   }
-  else if((pdev->pClass->DataOut != NULL)&&
-          (pdev->dev_state == USBD_STATE_CONFIGURED))
+  else if ((pdev->pClass->DataOut != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
+  {
+    pdev->pClass->DataOut(pdev, epnum);
+  }
+  else
   {
-    pdev->pClass->DataOut(pdev, epnum); 
-  }  
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_DataInStage 
+* @brief  USBD_DataInStage
 *         Handle data in stage
 * @param  pdev: device instance
 * @param  epnum: endpoint index
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata)
+USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
+                                       uint8_t epnum, uint8_t *pdata)
 {
-  USBD_EndpointTypeDef    *pep;
-    
-  if(epnum == 0) 
+  USBD_EndpointTypeDef *pep;
+
+  if (epnum == 0U)
   {
     pep = &pdev->ep_in[0];
-    
-    if ( pdev->ep0_state == USBD_EP0_DATA_IN)
+
+    if (pdev->ep0_state == USBD_EP0_DATA_IN)
     {
-      if(pep->rem_length > pep->maxpacket)
+      if (pep->rem_length > pep->maxpacket)
       {
-        pep->rem_length -=  pep->maxpacket;
-        
-        USBD_CtlContinueSendData (pdev, 
-                                  pdata, 
-                                  pep->rem_length);
-        
+        pep->rem_length -= pep->maxpacket;
+
+        USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
+
         /* Prepare endpoint for premature end of transfer */
-        USBD_LL_PrepareReceive (pdev,
-                                0,
-                                NULL,
-                                0);  
+        USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
       }
       else
-      { /* last packet is MPS multiple, so send ZLP packet */
-        if((pep->total_length % pep->maxpacket == 0) &&
-           (pep->total_length >= pep->maxpacket) &&
-             (pep->total_length < pdev->ep0_data_len ))
+      {
+        /* last packet is MPS multiple, so send ZLP packet */
+        if ((pep->total_length % pep->maxpacket == 0U) &&
+            (pep->total_length >= pep->maxpacket) &&
+            (pep->total_length < pdev->ep0_data_len))
         {
-          
-          USBD_CtlContinueSendData(pdev , NULL, 0);
-          pdev->ep0_data_len = 0;
-          
-        /* Prepare endpoint for premature end of transfer */
-        USBD_LL_PrepareReceive (pdev,
-                                0,
-                                NULL,
-                                0);
+          USBD_CtlContinueSendData(pdev, NULL, 0U);
+          pdev->ep0_data_len = 0U;
+
+          /* Prepare endpoint for premature end of transfer */
+          USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
         }
         else
         {
-          if((pdev->pClass->EP0_TxSent != NULL)&&
-             (pdev->dev_state == USBD_STATE_CONFIGURED))
+          if ((pdev->pClass->EP0_TxSent != NULL) &&
+              (pdev->dev_state == USBD_STATE_CONFIGURED))
           {
-            pdev->pClass->EP0_TxSent(pdev); 
-          }          
+            pdev->pClass->EP0_TxSent(pdev);
+          }
+          USBD_LL_StallEP(pdev, 0x80U);
           USBD_CtlReceiveStatus(pdev);
         }
       }
     }
-    if (pdev->dev_test_mode == 1)
+    else
+    {
+      if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
+          (pdev->ep0_state == USBD_EP0_IDLE))
+      {
+        USBD_LL_StallEP(pdev, 0x80U);
+      }
+    }
+
+    if (pdev->dev_test_mode == 1U)
     {
-      USBD_RunTestMode(pdev); 
-      pdev->dev_test_mode = 0;
+      USBD_RunTestMode(pdev);
+      pdev->dev_test_mode = 0U;
     }
   }
-  else if((pdev->pClass->DataIn != NULL)&& 
-          (pdev->dev_state == USBD_STATE_CONFIGURED))
+  else if ((pdev->pClass->DataIn != NULL) &&
+           (pdev->dev_state == USBD_STATE_CONFIGURED))
   {
-    pdev->pClass->DataIn(pdev, epnum); 
-  }  
+    pdev->pClass->DataIn(pdev, epnum);
+  }
+  else
+  {
+    /* should never be in this condition */
+    return USBD_FAIL;
+  }
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_LL_Reset 
+* @brief  USBD_LL_Reset
 *         Handle Reset event
 * @param  pdev: device instance
 * @retval status
 */
 
-USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
 {
   /* Open EP0 OUT */
-  USBD_LL_OpenEP(pdev,
-              0x00,
-              USBD_EP_TYPE_CTRL,
-              USB_MAX_EP0_SIZE);
-  
+  USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_out[0x00U & 0xFU].is_used = 1U;
+
   pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
-  
+
   /* Open EP0 IN */
-  USBD_LL_OpenEP(pdev,
-              0x80,
-              USBD_EP_TYPE_CTRL,
-              USB_MAX_EP0_SIZE);
-  
+  USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
+  pdev->ep_in[0x80U & 0xFU].is_used = 1U;
+
   pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
+
   /* Upon Reset call user call back */
   pdev->dev_state = USBD_STATE_DEFAULT;
-  
-  if (pdev->pClassData) 
-    pdev->pClass->DeInit(pdev, pdev->dev_config);  
- 
-  
-  return USBD_OK;
-}
-
+  pdev->ep0_state = USBD_EP0_IDLE;
+  pdev->dev_config = 0U;
+  pdev->dev_remote_wakeup = 0U;
 
+  if (pdev->pClassData)
+  {
+    pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+  }
 
+  return USBD_OK;
+}
 
 /**
-* @brief  USBD_LL_Reset 
+* @brief  USBD_LL_Reset
 *         Handle Reset event
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed)
+USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
+                                    USBD_SpeedTypeDef speed)
 {
   pdev->dev_speed = speed;
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_Suspend 
+* @brief  USBD_Suspend
 *         Handle Suspend event
 * @param  pdev: device instance
 * @retval status
 */
 
-USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
 {
   pdev->dev_old_state =  pdev->dev_state;
   pdev->dev_state  = USBD_STATE_SUSPENDED;
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_Resume 
+* @brief  USBD_Resume
 *         Handle Resume event
 * @param  pdev: device instance
 * @retval status
 */
 
-USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
 {
-  pdev->dev_state = pdev->dev_old_state;  
+  if (pdev->dev_state == USBD_STATE_SUSPENDED)
+  {
+    pdev->dev_state = pdev->dev_old_state;
+  }
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_SOF 
+* @brief  USBD_SOF
 *         Handle SOF event
 * @param  pdev: device instance
 * @retval status
 */
 
-USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
 {
-  if(pdev->dev_state == USBD_STATE_CONFIGURED)
+  if (pdev->dev_state == USBD_STATE_CONFIGURED)
   {
-    if(pdev->pClass->SOF != NULL)
+    if (pdev->pClass->SOF != NULL)
     {
       pdev->pClass->SOF(pdev);
     }
   }
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_IsoINIncomplete 
+* @brief  USBD_IsoINIncomplete
 *         Handle iso in incomplete event
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)
+USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
+                                           uint8_t epnum)
 {
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_IsoOUTIncomplete 
+* @brief  USBD_IsoOUTIncomplete
 *         Handle iso out incomplete event
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)
+USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
+                                            uint8_t epnum)
 {
+  /* Prevent unused arguments compilation warning */
+  UNUSED(pdev);
+  UNUSED(epnum);
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_DevConnected 
+* @brief  USBD_DevConnected
 *         Handle device connection event
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
 {
+  /* Prevent unused argument compilation warning */
+  UNUSED(pdev);
+
   return USBD_OK;
 }
 
 /**
-* @brief  USBD_DevDisconnected 
+* @brief  USBD_DevDisconnected
 *         Handle device disconnection event
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
 {
   /* Free Class Resources */
   pdev->dev_state = USBD_STATE_DEFAULT;
-  pdev->pClass->DeInit(pdev, pdev->dev_config);  
-   
+  pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
+
   return USBD_OK;
 }
 /**
 * @}
-*/ 
+*/
 
 
 /**
 * @}
-*/ 
+*/
 
 
 /**
 * @}
-*/ 
+*/
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
index cd61d2f5..4561c8d6 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
@@ -2,28 +2,20 @@
   ******************************************************************************
   * @file    usbd_req.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015 
   * @brief   This file provides the standard USB requests following chapter 9.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_ctlreq.h"
@@ -35,78 +27,81 @@
   */
 
 
-/** @defgroup USBD_REQ 
+/** @defgroup USBD_REQ
   * @brief USB standard requests module
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_REQ_Private_TypesDefinitions
   * @{
-  */ 
+  */
+
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Private_Defines
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Private_Macros
   * @{
-  */ 
+  */
+
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Private_Variables
   * @{
-  */ 
+  */
+
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Private_FunctionPrototypes
   * @{
-  */ 
-static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , 
+  */
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
                                USBD_SetupReqTypedef *req);
 
-static void USBD_SetAddress(USBD_HandleTypeDef *pdev , 
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req);
 
-static void USBD_SetConfig(USBD_HandleTypeDef *pdev , 
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev,
                            USBD_SetupReqTypedef *req);
 
-static void USBD_GetConfig(USBD_HandleTypeDef *pdev , 
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev,
                            USBD_SetupReqTypedef *req);
 
-static void USBD_GetStatus(USBD_HandleTypeDef *pdev , 
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev,
                            USBD_SetupReqTypedef *req);
 
-static void USBD_SetFeature(USBD_HandleTypeDef *pdev , 
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req);
 
-static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , 
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req);
 
 static uint8_t USBD_GetLen(uint8_t *buf);
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_REQ_Private_Functions
   * @{
-  */ 
+  */
 
 
 /**
@@ -116,47 +111,60 @@ static uint8_t USBD_GetLen(uint8_t *buf);
 * @param  req: usb request
 * @retval status
 */
-USBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)
+USBD_StatusTypeDef  USBD_StdDevReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef *req)
 {
-  USBD_StatusTypeDef ret = USBD_OK;  
-  
-  switch (req->bRequest) 
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
   {
-  case USB_REQ_GET_DESCRIPTOR: 
-    
-    USBD_GetDescriptor (pdev, req) ;
-    break;
-    
-  case USB_REQ_SET_ADDRESS:                      
-    USBD_SetAddress(pdev, req);
-    break;
-    
-  case USB_REQ_SET_CONFIGURATION:                    
-    USBD_SetConfig (pdev , req);
-    break;
-    
-  case USB_REQ_GET_CONFIGURATION:                 
-    USBD_GetConfig (pdev , req);
-    break;
-    
-  case USB_REQ_GET_STATUS:                                  
-    USBD_GetStatus (pdev , req);
-    break;
-    
-    
-  case USB_REQ_SET_FEATURE:   
-    USBD_SetFeature (pdev , req);    
-    break;
-    
-  case USB_REQ_CLEAR_FEATURE:                                   
-    USBD_ClrFeature (pdev , req);
-    break;
-    
-  default:  
-    USBD_CtlError(pdev , req);
-    break;
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
+      break;
+
+    case USB_REQ_TYPE_STANDARD:
+      switch (req->bRequest)
+      {
+        case USB_REQ_GET_DESCRIPTOR:
+          USBD_GetDescriptor(pdev, req);
+          break;
+
+        case USB_REQ_SET_ADDRESS:
+          USBD_SetAddress(pdev, req);
+          break;
+
+        case USB_REQ_SET_CONFIGURATION:
+          USBD_SetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_CONFIGURATION:
+          USBD_GetConfig(pdev, req);
+          break;
+
+        case USB_REQ_GET_STATUS:
+          USBD_GetStatus(pdev, req);
+          break;
+
+        case USB_REQ_SET_FEATURE:
+          USBD_SetFeature(pdev, req);
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+          USBD_ClrFeature(pdev, req);
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
   }
-  
+
   return ret;
 }
 
@@ -167,33 +175,48 @@ USBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqType
 * @param  req: usb request
 * @retval status
 */
-USBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)
+USBD_StatusTypeDef  USBD_StdItfReq(USBD_HandleTypeDef *pdev,
+                                   USBD_SetupReqTypedef  *req)
 {
-  USBD_StatusTypeDef ret = USBD_OK; 
-  
-  switch (pdev->dev_state) 
+  USBD_StatusTypeDef ret = USBD_OK;
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
   {
-  case USBD_STATE_CONFIGURED:
-    
-    if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) 
-    {
-      pdev->pClass->Setup (pdev, req); 
-      
-      if((req->wLength == 0)&& (ret == USBD_OK))
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+    case USB_REQ_TYPE_STANDARD:
+      switch (pdev->dev_state)
       {
-         USBD_CtlSendStatus(pdev);
+        case USBD_STATE_DEFAULT:
+        case USBD_STATE_ADDRESSED:
+        case USBD_STATE_CONFIGURED:
+
+          if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES)
+          {
+            ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+            if ((req->wLength == 0U) && (ret == USBD_OK))
+            {
+              USBD_CtlSendStatus(pdev);
+            }
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
       }
-    } 
-    else 
-    {                                               
-       USBD_CtlError(pdev , req);
-    }
-    break;
-    
-  default:
-     USBD_CtlError(pdev , req);
-    break;
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
   }
+
   return USBD_OK;
 }
 
@@ -204,123 +227,174 @@ USBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqType
 * @param  req: usb request
 * @retval status
 */
-USBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)
+USBD_StatusTypeDef  USBD_StdEPReq(USBD_HandleTypeDef *pdev,
+                                  USBD_SetupReqTypedef  *req)
 {
-  
+  USBD_EndpointTypeDef *pep;
   uint8_t   ep_addr;
-  USBD_StatusTypeDef ret = USBD_OK; 
-  USBD_EndpointTypeDef   *pep;
-  ep_addr  = LOBYTE(req->wIndex);   
-  
-  /* Check if it is a class request */
-  if ((req->bmRequest & 0x60) == 0x20)
-  {
-    pdev->pClass->Setup (pdev, req);
-    
-    return USBD_OK;
-  }
-  
-  switch (req->bRequest) 
+  USBD_StatusTypeDef ret = USBD_OK;
+  ep_addr  = LOBYTE(req->wIndex);
+
+  switch (req->bmRequest & USB_REQ_TYPE_MASK)
   {
-    
-  case USB_REQ_SET_FEATURE :
-    
-    switch (pdev->dev_state) 
-    {
-    case USBD_STATE_ADDRESSED:          
-      if ((ep_addr != 0x00) && (ep_addr != 0x80)) 
-      {
-        USBD_LL_StallEP(pdev , ep_addr);
-      }
-      break;	
-      
-    case USBD_STATE_CONFIGURED:   
-      if (req->wValue == USB_FEATURE_EP_HALT)
-      {
-        if ((ep_addr != 0x00) && (ep_addr != 0x80)) 
-        { 
-          USBD_LL_StallEP(pdev , ep_addr);
-          
-        }
-      }
-      pdev->pClass->Setup (pdev, req);   
-      USBD_CtlSendStatus(pdev);
-      
-      break;
-      
-    default:                         
-      USBD_CtlError(pdev , req);
-      break;    
-    }
-    break;
-    
-  case USB_REQ_CLEAR_FEATURE :
-    
-    switch (pdev->dev_state) 
-    {
-    case USBD_STATE_ADDRESSED:          
-      if ((ep_addr != 0x00) && (ep_addr != 0x80)) 
-      {
-        USBD_LL_StallEP(pdev , ep_addr);
-      }
-      break;	
-      
-    case USBD_STATE_CONFIGURED:   
-      if (req->wValue == USB_FEATURE_EP_HALT)
-      {
-        if ((ep_addr & 0x7F) != 0x00) 
-        {        
-          USBD_LL_ClearStallEP(pdev , ep_addr);
-          pdev->pClass->Setup (pdev, req);
-        }
-        USBD_CtlSendStatus(pdev);
-      }
+    case USB_REQ_TYPE_CLASS:
+    case USB_REQ_TYPE_VENDOR:
+      pdev->pClass->Setup(pdev, req);
       break;
-      
-    default:                         
-      USBD_CtlError(pdev , req);
-      break;    
-    }
-    break;
-    
-  case USB_REQ_GET_STATUS:                  
-    switch (pdev->dev_state) 
-    {
-    case USBD_STATE_ADDRESSED:          
-      if ((ep_addr & 0x7F) != 0x00) 
-      {
-        USBD_LL_StallEP(pdev , ep_addr);
-      }
-      break;	
-      
-    case USBD_STATE_CONFIGURED:
-      pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\
-                                         &pdev->ep_out[ep_addr & 0x7F];
-      if(USBD_LL_IsStallEP(pdev, ep_addr))
+
+    case USB_REQ_TYPE_STANDARD:
+      /* Check if it is a class request */
+      if ((req->bmRequest & 0x60U) == 0x20U)
       {
-        pep->status = 0x0001;     
+        ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req);
+
+        return ret;
       }
-      else
+
+      switch (req->bRequest)
       {
-        pep->status = 0x0000;  
+        case USB_REQ_SET_FEATURE:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr != 0x00U) &&
+                    (ep_addr != 0x80U) && (req->wLength == 0x00U))
+                {
+                  USBD_LL_StallEP(pdev, ep_addr);
+                }
+              }
+              USBD_CtlSendStatus(pdev);
+
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_CLEAR_FEATURE:
+
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_LL_StallEP(pdev, ep_addr);
+                USBD_LL_StallEP(pdev, 0x80U);
+              }
+              else
+              {
+                USBD_CtlError(pdev, req);
+              }
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if (req->wValue == USB_FEATURE_EP_HALT)
+              {
+                if ((ep_addr & 0x7FU) != 0x00U)
+                {
+                  USBD_LL_ClearStallEP(pdev, ep_addr);
+                }
+                USBD_CtlSendStatus(pdev);
+              }
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        case USB_REQ_GET_STATUS:
+          switch (pdev->dev_state)
+          {
+            case USBD_STATE_ADDRESSED:
+              if ((ep_addr != 0x00U) && (ep_addr != 0x80U))
+              {
+                USBD_CtlError(pdev, req);
+                break;
+              }
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              pep->status = 0x0000U;
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            case USBD_STATE_CONFIGURED:
+              if ((ep_addr & 0x80U) == 0x80U)
+              {
+                if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+              else
+              {
+                if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U)
+                {
+                  USBD_CtlError(pdev, req);
+                  break;
+                }
+              }
+
+              pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \
+                    &pdev->ep_out[ep_addr & 0x7FU];
+
+              if ((ep_addr == 0x00U) || (ep_addr == 0x80U))
+              {
+                pep->status = 0x0000U;
+              }
+              else if (USBD_LL_IsStallEP(pdev, ep_addr))
+              {
+                pep->status = 0x0001U;
+              }
+              else
+              {
+                pep->status = 0x0000U;
+              }
+
+              USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U);
+              break;
+
+            default:
+              USBD_CtlError(pdev, req);
+              break;
+          }
+          break;
+
+        default:
+          USBD_CtlError(pdev, req);
+          break;
       }
-      
-      USBD_CtlSendData (pdev,
-                        (uint8_t *)&pep->status,
-                        2);
       break;
-      
-    default:                         
-      USBD_CtlError(pdev , req);
+
+    default:
+      USBD_CtlError(pdev, req);
       break;
-    }
-    break;
-    
-  default:
-    break;
   }
+
   return ret;
 }
+
+
 /**
 * @brief  USBD_GetDescriptor
 *         Handle Get Descriptor requests
@@ -328,115 +402,187 @@ USBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTyped
 * @param  req: usb request
 * @retval status
 */
-static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , 
+static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev,
                                USBD_SetupReqTypedef *req)
 {
-  uint16_t len;
-  uint8_t *pbuf;
-  
-    
+  uint16_t len = 0U;
+  uint8_t *pbuf = NULL;
+  uint8_t err = 0U;
+
   switch (req->wValue >> 8)
-  { 
-#if (USBD_LPM_ENABLED == 1)
-  case USB_DESC_TYPE_BOS:
-    pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
-    break;
-#endif    
-  case USB_DESC_TYPE_DEVICE:
-    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
-    break;
-    
-  case USB_DESC_TYPE_CONFIGURATION:     
-    if(pdev->dev_speed == USBD_SPEED_HIGH )   
-    {
-      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);
-      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
-    }
-    else
-    {
-      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);
-      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
-    }
-    break;
-    
-  case USB_DESC_TYPE_STRING:
-    switch ((uint8_t)(req->wValue))
-    {
-    case USBD_IDX_LANGID_STR:
-     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);        
+  {
+#if (USBD_LPM_ENABLED == 1U)
+    case USB_DESC_TYPE_BOS:
+      if (pdev->pDesc->GetBOSDescriptor != NULL)
+      {
+        pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
       break;
-      
-    case USBD_IDX_MFC_STR:
-      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+#endif
+    case USB_DESC_TYPE_DEVICE:
+      pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);
       break;
-      
-    case USBD_IDX_PRODUCT_STR:
-      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+
+    case USB_DESC_TYPE_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetHSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
+      else
+      {
+        pbuf = pdev->pClass->GetFSConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
+      }
       break;
-      
-    case USBD_IDX_SERIAL_STR:
-      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+
+    case USB_DESC_TYPE_STRING:
+      switch ((uint8_t)(req->wValue))
+      {
+        case USBD_IDX_LANGID_STR:
+          if (pdev->pDesc->GetLangIDStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_MFC_STR:
+          if (pdev->pDesc->GetManufacturerStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_PRODUCT_STR:
+          if (pdev->pDesc->GetProductStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_SERIAL_STR:
+          if (pdev->pDesc->GetSerialStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_CONFIG_STR:
+          if (pdev->pDesc->GetConfigurationStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        case USBD_IDX_INTERFACE_STR:
+          if (pdev->pDesc->GetInterfaceStrDescriptor != NULL)
+          {
+            pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+
+        default:
+#if (USBD_SUPPORT_USER_STRING_DESC == 1U)
+          if (pdev->pClass->GetUsrStrDescriptor != NULL)
+          {
+            pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len);
+          }
+          else
+          {
+            USBD_CtlError(pdev, req);
+            err++;
+          }
+          break;
+#else
+          USBD_CtlError(pdev, req);
+          err++;
+#endif
+      }
       break;
-      
-    case USBD_IDX_CONFIG_STR:
-      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);
+
+    case USB_DESC_TYPE_DEVICE_QUALIFIER:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len);
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
       break;
-      
-    case USBD_IDX_INTERFACE_STR:
-      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);
+
+    case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
+      if (pdev->dev_speed == USBD_SPEED_HIGH)
+      {
+        pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
+        pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
+      }
+      else
+      {
+        USBD_CtlError(pdev, req);
+        err++;
+      }
       break;
-      
+
     default:
-#if (USBD_SUPPORT_USER_STRING == 1)
-      pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len);
+      USBD_CtlError(pdev, req);
+      err++;
       break;
-#else      
-       USBD_CtlError(pdev , req);
-      return;
-#endif   
-    }
-    break;
-  case USB_DESC_TYPE_DEVICE_QUALIFIER:                   
+  }
 
-    if(pdev->dev_speed == USBD_SPEED_HIGH  )   
+  if (err != 0U)
+  {
+    return;
+  }
+  else
+  {
+    if ((len != 0U) && (req->wLength != 0U))
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);
-      break;
+      len = MIN(len, req->wLength);
+      (void)USBD_CtlSendData(pdev, pbuf, len);
     }
-    else
-    {
-      USBD_CtlError(pdev , req);
-      return;
-    } 
 
-  case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
-    if(pdev->dev_speed == USBD_SPEED_HIGH  )   
+    if (req->wLength == 0U)
     {
-      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);
-      pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
-      break; 
+      (void)USBD_CtlSendStatus(pdev);
     }
-    else
-    {
-      USBD_CtlError(pdev , req);
-      return;
-    }
-
-  default: 
-     USBD_CtlError(pdev , req);
-    return;
-  }
-  
-  if((len != 0)&& (req->wLength != 0))
-  {
-    
-    len = MIN(len , req->wLength);
-    
-    USBD_CtlSendData (pdev, 
-                      pbuf,
-                      len);
   }
-  
 }
 
 /**
@@ -446,39 +592,39 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_SetAddress(USBD_HandleTypeDef *pdev , 
+static void USBD_SetAddress(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req)
 {
-  uint8_t  dev_addr; 
-  
-  if ((req->wIndex == 0) && (req->wLength == 0)) 
+  uint8_t  dev_addr;
+
+  if ((req->wIndex == 0U) && (req->wLength == 0U) && (req->wValue < 128U))
   {
-    dev_addr = (uint8_t)(req->wValue) & 0x7F;     
-    
-    if (pdev->dev_state == USBD_STATE_CONFIGURED) 
+    dev_addr = (uint8_t)(req->wValue) & 0x7FU;
+
+    if (pdev->dev_state == USBD_STATE_CONFIGURED)
     {
-      USBD_CtlError(pdev , req);
-    } 
-    else 
+      USBD_CtlError(pdev, req);
+    }
+    else
     {
       pdev->dev_address = dev_addr;
-      USBD_LL_SetUSBAddress(pdev, dev_addr);               
-      USBD_CtlSendStatus(pdev);                         
-      
-      if (dev_addr != 0) 
+      USBD_LL_SetUSBAddress(pdev, dev_addr);
+      USBD_CtlSendStatus(pdev);
+
+      if (dev_addr != 0U)
       {
-        pdev->dev_state  = USBD_STATE_ADDRESSED;
-      } 
-      else 
+        pdev->dev_state = USBD_STATE_ADDRESSED;
+      }
+      else
       {
-        pdev->dev_state  = USBD_STATE_DEFAULT; 
+        pdev->dev_state = USBD_STATE_DEFAULT;
       }
     }
-  } 
-  else 
+  }
+  else
   {
-     USBD_CtlError(pdev , req);                        
-  } 
+    USBD_CtlError(pdev, req);
+  }
 }
 
 /**
@@ -488,72 +634,70 @@ static void USBD_SetAddress(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_SetConfig(USBD_HandleTypeDef *pdev , 
-                           USBD_SetupReqTypedef *req)
+static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
 {
-  
-  static uint8_t  cfgidx;
-  
-  cfgidx = (uint8_t)(req->wValue);                 
-  
-  if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) 
-  {            
-     USBD_CtlError(pdev , req);                              
-  } 
-  else 
+  static uint8_t cfgidx;
+
+  cfgidx = (uint8_t)(req->wValue);
+
+  if (cfgidx > USBD_MAX_NUM_CONFIGURATION)
+  {
+    USBD_CtlError(pdev, req);
+  }
+  else
   {
-    switch (pdev->dev_state) 
+    switch (pdev->dev_state)
     {
-    case USBD_STATE_ADDRESSED:
-      if (cfgidx) 
-      {                                			   							   							   				
-        pdev->dev_config = cfgidx;
-        pdev->dev_state = USBD_STATE_CONFIGURED;
-        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)
+      case USBD_STATE_ADDRESSED:
+        if (cfgidx)
         {
-          USBD_CtlError(pdev , req);  
-          return;
+          pdev->dev_config = cfgidx;
+          pdev->dev_state = USBD_STATE_CONFIGURED;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
         }
-        USBD_CtlSendStatus(pdev);
-      }
-      else 
-      {
-         USBD_CtlSendStatus(pdev);
-      }
-      break;
-      
-    case USBD_STATE_CONFIGURED:
-      if (cfgidx == 0) 
-      {                           
-        pdev->dev_state = USBD_STATE_ADDRESSED;
-        pdev->dev_config = cfgidx;          
-        USBD_ClrClassConfig(pdev , cfgidx);
-        USBD_CtlSendStatus(pdev);
-        
-      } 
-      else  if (cfgidx != pdev->dev_config) 
-      {
-        /* Clear old configuration */
-        USBD_ClrClassConfig(pdev , pdev->dev_config);
-        
-        /* set new configuration */
-        pdev->dev_config = cfgidx;
-        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)
+        else
         {
-          USBD_CtlError(pdev , req);  
-          return;
+          USBD_CtlSendStatus(pdev);
         }
-        USBD_CtlSendStatus(pdev);
-      }
-      else
-      {
-        USBD_CtlSendStatus(pdev);
-      }
-      break;
-      
-    default:					
-       USBD_CtlError(pdev , req);                     
-      break;
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        if (cfgidx == 0U)
+        {
+          pdev->dev_state = USBD_STATE_ADDRESSED;
+          pdev->dev_config = cfgidx;
+          USBD_ClrClassConfig(pdev, cfgidx);
+          USBD_CtlSendStatus(pdev);
+        }
+        else if (cfgidx != pdev->dev_config)
+        {
+          /* Clear old configuration */
+          USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config);
+
+          /* set new configuration */
+          pdev->dev_config = cfgidx;
+          if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL)
+          {
+            USBD_CtlError(pdev, req);
+            return;
+          }
+          USBD_CtlSendStatus(pdev);
+        }
+        else
+        {
+          USBD_CtlSendStatus(pdev);
+        }
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        USBD_ClrClassConfig(pdev, cfgidx);
+        break;
     }
   }
 }
@@ -565,35 +709,29 @@ static void USBD_SetConfig(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_GetConfig(USBD_HandleTypeDef *pdev , 
-                           USBD_SetupReqTypedef *req)
+static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
 {
-
-  if (req->wLength != 1) 
-  {                   
-     USBD_CtlError(pdev , req);
+  if (req->wLength != 1U)
+  {
+    USBD_CtlError(pdev, req);
   }
-  else 
+  else
   {
-    switch (pdev->dev_state )  
+    switch (pdev->dev_state)
     {
-    case USBD_STATE_ADDRESSED:                     
-      pdev->dev_default_config = 0;
-      USBD_CtlSendData (pdev, 
-                        (uint8_t *)&pdev->dev_default_config,
-                        1);
-      break;
-      
-    case USBD_STATE_CONFIGURED:   
-      
-      USBD_CtlSendData (pdev, 
-                        (uint8_t *)&pdev->dev_config,
-                        1);
-      break;
-      
-    default:
-       USBD_CtlError(pdev , req);
-      break;
+      case USBD_STATE_DEFAULT:
+      case USBD_STATE_ADDRESSED:
+        pdev->dev_default_config = 0U;
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U);
+        break;
+
+      case USBD_STATE_CONFIGURED:
+        USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U);
+        break;
+
+      default:
+        USBD_CtlError(pdev, req);
+        break;
     }
   }
 }
@@ -605,35 +743,36 @@ static void USBD_GetConfig(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_GetStatus(USBD_HandleTypeDef *pdev , 
-                           USBD_SetupReqTypedef *req)
+static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)
 {
-  
-    
-  switch (pdev->dev_state) 
+  switch (pdev->dev_state)
   {
-  case USBD_STATE_ADDRESSED:
-  case USBD_STATE_CONFIGURED:
-    
-#if ( USBD_SELF_POWERED == 1)
-    pdev->dev_config_status = USB_CONFIG_SELF_POWERED;                                  
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wLength != 0x2U)
+      {
+        USBD_CtlError(pdev, req);
+        break;
+      }
+
+#if (USBD_SELF_POWERED == 1U)
+      pdev->dev_config_status = USB_CONFIG_SELF_POWERED;
 #else
-    pdev->dev_config_status = 0;                                   
+      pdev->dev_config_status = 0U;
 #endif
-                      
-    if (pdev->dev_remote_wakeup) 
-    {
-       pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;                                
-    }
-    
-    USBD_CtlSendData (pdev, 
-                      (uint8_t *)& pdev->dev_config_status,
-                      2);
-    break;
-    
-  default :
-    USBD_CtlError(pdev , req);                        
-    break;
+
+      if (pdev->dev_remote_wakeup)
+      {
+        pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;
+      }
+
+      USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U);
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
   }
 }
 
@@ -645,17 +784,14 @@ static void USBD_GetStatus(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_SetFeature(USBD_HandleTypeDef *pdev , 
+static void USBD_SetFeature(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req)
 {
-
   if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
   {
-    pdev->dev_remote_wakeup = 1;  
-    pdev->pClass->Setup (pdev, req);   
+    pdev->dev_remote_wakeup = 1U;
     USBD_CtlSendStatus(pdev);
   }
-
 }
 
 
@@ -666,29 +802,29 @@ static void USBD_SetFeature(USBD_HandleTypeDef *pdev ,
 * @param  req: usb request
 * @retval status
 */
-static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , 
+static void USBD_ClrFeature(USBD_HandleTypeDef *pdev,
                             USBD_SetupReqTypedef *req)
 {
   switch (pdev->dev_state)
   {
-  case USBD_STATE_ADDRESSED:
-  case USBD_STATE_CONFIGURED:
-    if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) 
-    {
-      pdev->dev_remote_wakeup = 0; 
-      pdev->pClass->Setup (pdev, req);   
-      USBD_CtlSendStatus(pdev);
-    }
-    break;
-    
-  default :
-     USBD_CtlError(pdev , req);
-    break;
+    case USBD_STATE_DEFAULT:
+    case USBD_STATE_ADDRESSED:
+    case USBD_STATE_CONFIGURED:
+      if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
+      {
+        pdev->dev_remote_wakeup = 0U;
+        USBD_CtlSendStatus(pdev);
+      }
+      break;
+
+    default:
+      USBD_CtlError(pdev, req);
+      break;
   }
 }
 
 /**
-* @brief  USBD_ParseSetupRequest 
+* @brief  USBD_ParseSetupRequest
 *         Copy buffer into setup structure
 * @param  pdev: device instance
 * @param  req: usb request
@@ -697,27 +833,27 @@ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev ,
 
 void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)
 {
-  req->bmRequest     = *(uint8_t *)  (pdata);
-  req->bRequest      = *(uint8_t *)  (pdata +  1);
-  req->wValue        = SWAPBYTE      (pdata +  2);
-  req->wIndex        = SWAPBYTE      (pdata +  4);
-  req->wLength       = SWAPBYTE      (pdata +  6);
+  req->bmRequest = *(uint8_t *)(pdata);
+  req->bRequest = *(uint8_t *)(pdata + 1U);
+  req->wValue = SWAPBYTE(pdata + 2U);
+  req->wIndex = SWAPBYTE(pdata + 4U);
+  req->wLength = SWAPBYTE(pdata + 6U);
 
 }
 
 /**
-* @brief  USBD_CtlError 
+* @brief  USBD_CtlError
 *         Handle USB low level Error
 * @param  pdev: device instance
 * @param  req: usb request
 * @retval None
 */
 
-void USBD_CtlError( USBD_HandleTypeDef *pdev ,
-                            USBD_SetupReqTypedef *req)
+void USBD_CtlError(USBD_HandleTypeDef *pdev,
+                   USBD_SetupReqTypedef *req)
 {
-  USBD_LL_StallEP(pdev , 0x80);
-  USBD_LL_StallEP(pdev , 0);
+  USBD_LL_StallEP(pdev, 0x80U);
+  USBD_LL_StallEP(pdev, 0U);
 }
 
 
@@ -731,20 +867,20 @@ void USBD_CtlError( USBD_HandleTypeDef *pdev ,
   */
 void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
 {
-  uint8_t idx = 0;
-  
-  if (desc != NULL) 
+  uint8_t idx = 0U;
+
+  if (desc != NULL)
   {
-    *len =  USBD_GetLen(desc) * 2 + 2;    
-    unicode[idx++] = *len;
-    unicode[idx++] =  USB_DESC_TYPE_STRING;
-    
-    while (*desc != '\0') 
+    *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U;
+    unicode[idx++] = *(uint8_t *)(void *)len;
+    unicode[idx++] = USB_DESC_TYPE_STRING;
+
+    while (*desc != '\0')
     {
       unicode[idx++] = *desc++;
-      unicode[idx++] =  0x00;
+      unicode[idx++] =  0U;
     }
-  } 
+  }
 }
 
 /**
@@ -755,28 +891,28 @@ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
   */
 static uint8_t USBD_GetLen(uint8_t *buf)
 {
-    uint8_t  len = 0;
+  uint8_t  len = 0U;
 
-    while (*buf != '\0') 
-    {
-        len++;
-        buf++;
-    }
+  while (*buf != '\0')
+  {
+    len++;
+    buf++;
+  }
 
-    return len;
+  return len;
 }
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
index 254613d9..7e969de6 100644
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
+++ b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
@@ -2,28 +2,20 @@
   ******************************************************************************
   * @file    usbd_ioreq.c
   * @author  MCD Application Team
-  * @version V2.4.1
-  * @date    19-June-2015
   * @brief   This file provides the IO requests APIs for control endpoints.
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT 2015 STMicroelectronics

+  * 
© Copyright (c) 2015 STMicroelectronics.
+  * All rights reserved.

   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                      www.st.com/SLA0044
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_ioreq.h"
@@ -33,56 +25,56 @@
   */
 
 
-/** @defgroup USBD_IOREQ 
+/** @defgroup USBD_IOREQ
   * @brief control I/O requests module
   * @{
-  */ 
+  */
 
 /** @defgroup USBD_IOREQ_Private_TypesDefinitions
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Private_Defines
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Private_Macros
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Private_Variables
   * @{
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Private_FunctionPrototypes
   * @{
-  */ 
+  */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup USBD_IOREQ_Private_Functions
   * @{
-  */ 
+  */
 
 /**
 * @brief  USBD_CtlSendData
@@ -92,17 +84,17 @@
 * @param  len: length of data to be sent
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, 
-                               uint8_t *pbuf,
-                               uint16_t len)
+USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
+                                    uint8_t *pbuf, uint16_t len)
 {
   /* Set EP0 State */
-  pdev->ep0_state          = USBD_EP0_DATA_IN;                                      
+  pdev->ep0_state = USBD_EP0_DATA_IN;
   pdev->ep_in[0].total_length = len;
   pdev->ep_in[0].rem_length   = len;
- /* Start the transfer */
-  USBD_LL_Transmit (pdev, 0x00, pbuf, len);  
-  
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
   return USBD_OK;
 }
 
@@ -114,13 +106,12 @@ USBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev,
 * @param  len: length of data to be sent
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, 
-                                       uint8_t *pbuf,
-                                       uint16_t len)
+USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
+                                            uint8_t *pbuf, uint16_t len)
 {
- /* Start the next transfer */
-  USBD_LL_Transmit (pdev, 0x00, pbuf, len);   
-  
+  /* Start the next transfer */
+  USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
+
   return USBD_OK;
 }
 
@@ -132,20 +123,17 @@ USBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev,
 * @param  len: length of data to be received
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,
-                                  uint8_t *pbuf,                                  
-                                  uint16_t len)
+USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
+                                     uint8_t *pbuf, uint16_t len)
 {
   /* Set EP0 State */
-  pdev->ep0_state = USBD_EP0_DATA_OUT; 
+  pdev->ep0_state = USBD_EP0_DATA_OUT;
   pdev->ep_out[0].total_length = len;
   pdev->ep_out[0].rem_length   = len;
+
   /* Start the transfer */
-  USBD_LL_PrepareReceive (pdev,
-                          0,
-                          pbuf,
-                         len);
-  
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
+
   return USBD_OK;
 }
 
@@ -157,32 +145,28 @@ USBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,
 * @param  len: length of data to be received
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, 
-                                          uint8_t *pbuf,                                          
-                                          uint16_t len)
+USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
+                                      uint8_t *pbuf, uint16_t len)
 {
+  USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
 
-  USBD_LL_PrepareReceive (pdev,
-                          0,                     
-                          pbuf,                         
-                          len);
   return USBD_OK;
 }
+
 /**
 * @brief  USBD_CtlSendStatus
 *         send zero lzngth packet on the ctl pipe
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
 {
-
   /* Set EP0 State */
   pdev->ep0_state = USBD_EP0_STATUS_IN;
-  
- /* Start the transfer */
-  USBD_LL_Transmit (pdev, 0x00, NULL, 0);   
-  
+
+  /* Start the transfer */
+  USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
+
   return USBD_OK;
 }
 
@@ -192,21 +176,17 @@ USBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)
 * @param  pdev: device instance
 * @retval status
 */
-USBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)
+USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
 {
   /* Set EP0 State */
-  pdev->ep0_state = USBD_EP0_STATUS_OUT; 
-  
- /* Start the transfer */  
-  USBD_LL_PrepareReceive ( pdev,
-                    0,
-                    NULL,
-                    0);  
+  pdev->ep0_state = USBD_EP0_STATUS_OUT;
+
+  /* Start the transfer */
+  USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
 
   return USBD_OK;
 }
 
-
 /**
 * @brief  USBD_GetRxCount
 *         returns the received data length
@@ -214,23 +194,23 @@ USBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)
 * @param  ep_addr: endpoint address
 * @retval Rx Data blength
 */
-uint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , uint8_t ep_addr)
+uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
   return USBD_LL_GetRxDataSize(pdev, ep_addr);
 }
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h
deleted file mode 100644
index de79dacb..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file contains all the prototypes for the usbh_msc.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_MSC_H
-#define __USBH_MSC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-#include "usbh_msc_bot.h"
-#include "usbh_msc_scsi.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_CLASS
-  * @{
-  */
-
-/** @addtogroup USBH_MSC_CLASS
-  * @{
-  */
-  
-/** @defgroup USBH_MSC_CORE
-  * @brief This file is the Header file for usbh_msc.c
-  * @{
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Types
-  * @{
-  */ 
-
-typedef enum
-{
-  MSC_INIT = 0,     
-  MSC_IDLE,    
-  MSC_TEST_UNIT_READY,          
-  MSC_READ_CAPACITY10,
-  MSC_READ_INQUIRY,
-  MSC_REQUEST_SENSE,
-  MSC_READ,
-  MSC_WRITE,
-  MSC_UNRECOVERED_ERROR,  
-  MSC_PERIODIC_CHECK,    
-}
-MSC_StateTypeDef;
-
-typedef enum
-{
-  MSC_OK,
-  MSC_NOT_READY,
-  MSC_ERROR,  
-
-}
-MSC_ErrorTypeDef;
-
-typedef enum
-{
-  MSC_REQ_IDLE = 0,
-  MSC_REQ_RESET,                
-  MSC_REQ_GET_MAX_LUN,  
-  MSC_REQ_ERROR,  
-}
-MSC_ReqStateTypeDef;
-
-#ifndef MAX_SUPPORTED_LUN       
-    #define MAX_SUPPORTED_LUN       2
-#endif
-
-
-/* Structure for LUN */
-typedef struct
-{
-  MSC_StateTypeDef            state; 
-  MSC_ErrorTypeDef            error;   
-  USBH_StatusTypeDef          prev_ready_state;
-  SCSI_CapacityTypeDef        capacity;
-  SCSI_SenseTypeDef           sense;  
-  SCSI_StdInquiryDataTypeDef  inquiry;
-  uint8_t                     state_changed; 
-  
-}
-MSC_LUNTypeDef; 
-
-/* Structure for MSC process */
-typedef struct _MSC_Process
-{
-  uint32_t             max_lun;   
-  uint8_t              InPipe; 
-  uint8_t              OutPipe; 
-  uint8_t              OutEp;
-  uint8_t              InEp;
-  uint16_t             OutEpSize;
-  uint16_t             InEpSize;
-  MSC_StateTypeDef     state;
-  MSC_ErrorTypeDef     error;
-  MSC_ReqStateTypeDef  req_state;
-  MSC_ReqStateTypeDef  prev_req_state;  
-  BOT_HandleTypeDef    hbot;
-  MSC_LUNTypeDef       unit[MAX_SUPPORTED_LUN];
-  uint16_t             current_lun; 
-  uint16_t             rw_lun;   
-  uint32_t             timer;
-}
-MSC_HandleTypeDef; 
-
-
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Defines
-  * @{
-  */
-
-#define USB_REQ_BOT_RESET                0xFF
-#define USB_REQ_GET_MAX_LUN              0xFE
-   
-
-/* MSC Class Codes */
-#define USB_MSC_CLASS                                   0x08
-
-/* Interface Descriptor field values for HID Boot Protocol */
-#define MSC_BOT                                        0x50 
-#define MSC_TRANSPARENT                                0x06     
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_CORE_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_CORE_Exported_Variables
-  * @{
-  */ 
-extern USBH_ClassTypeDef  USBH_msc;
-#define USBH_MSC_CLASS    &USBH_msc
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_CORE_Exported_FunctionsPrototype
-  * @{
-  */ 
-
-/* Common APIs */     
-uint8_t            USBH_MSC_IsReady (USBH_HandleTypeDef *phost);
-
-/* APIs for LUN */
-int8_t             USBH_MSC_GetMaxLUN (USBH_HandleTypeDef *phost);
-
-uint8_t            USBH_MSC_UnitIsReady (USBH_HandleTypeDef *phost, uint8_t lun);
-
-USBH_StatusTypeDef USBH_MSC_GetLUNInfo(USBH_HandleTypeDef *phost, uint8_t lun, MSC_LUNTypeDef *info);
-                                 
-USBH_StatusTypeDef USBH_MSC_Read(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length);
-
-USBH_StatusTypeDef USBH_MSC_Write(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length);
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __USBH_MSC_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_bot.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_bot.h
deleted file mode 100644
index 64e7ca74..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_bot.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc_bot.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_msc_bot.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_MSC_BOT_H
-#define __USBH_MSC_BOT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-#include "usbh_msc_bot.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_CLASS
-  * @{
-  */
-
-/** @addtogroup USBH_MSC_CLASS
-  * @{
-  */
-  
-/** @defgroup USBH_MSC_BOT
-  * @brief This file is the Header file for usbh_msc_bot.c
-  * @{
-  */ 
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Types
-  * @{
-  */ 
-    
-typedef enum {
-  BOT_OK          = 0,
-  BOT_FAIL        = 1,
-  BOT_PHASE_ERROR = 2,
-  BOT_BUSY        = 3
-}
-BOT_StatusTypeDef;
-
-typedef enum {
-  BOT_CMD_IDLE  = 0,
-  BOT_CMD_SEND,
-  BOT_CMD_WAIT,
-} 
-BOT_CMDStateTypeDef;  
-
-/* CSW Status Definitions */
-typedef enum 
-{
-
-   BOT_CSW_CMD_PASSED   =        0x00,
-   BOT_CSW_CMD_FAILED   =        0x01,
-   BOT_CSW_PHASE_ERROR  =        0x02,
-} 
-BOT_CSWStatusTypeDef;  
-
-typedef enum {
-  BOT_SEND_CBW  = 1,
-  BOT_SEND_CBW_WAIT,         
-  BOT_DATA_IN,    
-  BOT_DATA_IN_WAIT,    
-  BOT_DATA_OUT, 
-  BOT_DATA_OUT_WAIT,     
-  BOT_RECEIVE_CSW,
-  BOT_RECEIVE_CSW_WAIT,       
-  BOT_ERROR_IN,         
-  BOT_ERROR_OUT, 
-  BOT_UNRECOVERED_ERROR
-} 
-BOT_StateTypeDef;  
-  
-typedef union 
-{
-  struct __CBW
-  {
-    uint32_t Signature;
-    uint32_t Tag;
-    uint32_t DataTransferLength;
-    uint8_t  Flags;
-    uint8_t  LUN; 
-    uint8_t  CBLength;
-    uint8_t  CB[16];
-  }field;
-  uint8_t data[31];
-}
-BOT_CBWTypeDef;
-
-typedef union 
-{
-  struct __CSW
-  {
-    uint32_t Signature;
-    uint32_t Tag;
-    uint32_t DataResidue;
-    uint8_t  Status;
-  }field;
-  uint8_t data[13];
-}
-BOT_CSWTypeDef;
-
-typedef struct
-{
-  uint32_t                   data[16];    
-  BOT_StateTypeDef           state;
-  BOT_StateTypeDef           prev_state;  
-  BOT_CMDStateTypeDef        cmd_state;
-  BOT_CBWTypeDef             cbw;
-  uint8_t                    Reserved1;
-  BOT_CSWTypeDef             csw; 
-  uint8_t                    Reserved2[3];  
-  uint8_t                    *pbuf;
-} 
-BOT_HandleTypeDef;
-
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Defines
-  * @{
-  */ 
-#define BOT_CBW_SIGNATURE            0x43425355
-#define BOT_CBW_TAG                  0x20304050             
-#define BOT_CSW_SIGNATURE            0x53425355           
-#define BOT_CBW_LENGTH               31
-#define BOT_CSW_LENGTH               13     
-
-
-
-#define BOT_SEND_CSW_DISABLE         0
-#define BOT_SEND_CSW_ENABLE          1
-
-#define BOT_DIR_IN                   0
-#define BOT_DIR_OUT                  1
-#define BOT_DIR_BOTH                 2
-
-#define BOT_PAGE_LENGTH              512
-
-
-#define BOT_CBW_CB_LENGTH            16
-
-
-#define USB_REQ_BOT_RESET                0xFF
-#define USB_REQ_GET_MAX_LUN              0xFE
-
-#define MAX_BULK_STALL_COUNT_LIMIT       0x04   /* If STALL is seen on Bulk 
-                                         Endpoint continuously, this means 
-                                         that device and Host has phase error
-                                         Hence a Reset is needed */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_BOT_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_BOT_Exported_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_BOT_Exported_FunctionsPrototype
-  * @{
-  */ 
-USBH_StatusTypeDef USBH_MSC_BOT_REQ_Reset(USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef USBH_MSC_BOT_REQ_GetMaxLUN(USBH_HandleTypeDef *phost, uint8_t *Maxlun);
-
-USBH_StatusTypeDef USBH_MSC_BOT_Init(USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef USBH_MSC_BOT_Process (USBH_HandleTypeDef *phost, uint8_t lun);
-USBH_StatusTypeDef USBH_MSC_BOT_Error(USBH_HandleTypeDef *phost, uint8_t lun);
-
-
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __USBH_MSC_BOT_H__ */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_scsi.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_scsi.h
deleted file mode 100644
index a70b0276..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc_scsi.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc_scsi.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_msc_scsi.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_MSC_SCSI_H
-#define __USBH_MSC_SCSI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_CLASS
-  * @{
-  */
-
-/** @addtogroup USBH_MSC_CLASS
-  * @{
-  */
-  
-/** @defgroup USBH_MSC_SCSI
-  * @brief This file is the Header file for usbh_msc_scsi.c
-  * @{
-  */ 
-    
-    
-// Capacity data.
-typedef struct
-{
-  uint32_t block_nbr;   
-  uint16_t block_size;   
-} SCSI_CapacityTypeDef;
-
-
-// Sense data.
-typedef struct
-{
-  uint8_t key;   
-  uint8_t asc;   
-  uint8_t ascq;  
-} SCSI_SenseTypeDef;
-
-// INQUIRY data.
-typedef struct
-{
-  uint8_t PeripheralQualifier;
-  uint8_t DeviceType;
-  uint8_t RemovableMedia;
-  uint8_t vendor_id[9];
-  uint8_t product_id[17];
-  uint8_t revision_id[5];
-}SCSI_StdInquiryDataTypeDef;
-
-/** @defgroup USBH_MSC_SCSI_Exported_Defines
-  * @{
-  */ 
-#define OPCODE_TEST_UNIT_READY            0x00
-#define OPCODE_READ_CAPACITY10            0x25
-#define OPCODE_READ10                     0x28
-#define OPCODE_WRITE10                    0x2A
-#define OPCODE_REQUEST_SENSE              0x03
-#define OPCODE_INQUIRY                    0x12    
-
-#define DATA_LEN_MODE_TEST_UNIT_READY        0
-#define DATA_LEN_READ_CAPACITY10             8
-#define DATA_LEN_INQUIRY                    36  
-#define DATA_LEN_REQUEST_SENSE              14       
-
-#define CBW_CB_LENGTH                       16
-#define CBW_LENGTH                          10    
-
-/** @defgroup USBH_MSC_SCSI_Exported_Defines
-  * @{
-  */ 
-#define SCSI_SENSE_KEY_NO_SENSE                          0x00
-#define SCSI_SENSE_KEY_RECOVERED_ERROR                   0x01
-#define SCSI_SENSE_KEY_NOT_READY                         0x02
-#define SCSI_SENSE_KEY_MEDIUM_ERROR                      0x03
-#define SCSI_SENSE_KEY_HARDWARE_ERROR                    0x04
-#define SCSI_SENSE_KEY_ILLEGAL_REQUEST                   0x05
-#define SCSI_SENSE_KEY_UNIT_ATTENTION                    0x06
-#define SCSI_SENSE_KEY_DATA_PROTECT                      0x07
-#define SCSI_SENSE_KEY_BLANK_CHECK                       0x08
-#define SCSI_SENSE_KEY_VENDOR_SPECIFIC                   0x09
-#define SCSI_SENSE_KEY_COPY_ABORTED                      0x0A
-#define SCSI_SENSE_KEY_ABORTED_COMMAND                   0x0B
-#define SCSI_SENSE_KEY_VOLUME_OVERFLOW                   0x0D
-#define SCSI_SENSE_KEY_MISCOMPARE                        0x0E
-/**
-  * @}
-  */ 
-    
-    
-/** @defgroup USBH_MSC_SCSI_Exported_Defines
-  * @{
-  */     
-#define SCSI_ASC_NO_ADDITIONAL_SENSE_INFORMATION         0x00
-#define SCSI_ASC_LOGICAL_UNIT_NOT_READY                  0x04
-#define SCSI_ASC_INVALID_FIELD_IN_CDB                    0x24
-#define SCSI_ASC_WRITE_PROTECTED                         0x27
-#define SCSI_ASC_FORMAT_ERROR                            0x31
-#define SCSI_ASC_INVALID_COMMAND_OPERATION_CODE          0x20
-#define SCSI_ASC_NOT_READY_TO_READY_CHANGE               0x28
-#define SCSI_ASC_MEDIUM_NOT_PRESENT                      0x3A
-/**
-  * @}
-  */ 
-    
-    
-/** @defgroup USBH_MSC_SCSI_Exported_Defines
-  * @{
-  */     
-#define SCSI_ASCQ_FORMAT_COMMAND_FAILED                  0x01
-#define SCSI_ASCQ_INITIALIZING_COMMAND_REQUIRED          0x02
-#define SCSI_ASCQ_OPERATION_IN_PROGRESS                  0x07
-    
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_SCSI_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup _Exported_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_SCSI_Exported_FunctionsPrototype
-  * @{
-  */ 
-USBH_StatusTypeDef USBH_MSC_SCSI_TestUnitReady (USBH_HandleTypeDef *phost, 
-                                                uint8_t lun);
-
-USBH_StatusTypeDef USBH_MSC_SCSI_ReadCapacity (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun, 
-                                               SCSI_CapacityTypeDef *capacity);
-
-USBH_StatusTypeDef USBH_MSC_SCSI_Inquiry (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun, 
-                                               SCSI_StdInquiryDataTypeDef *inquiry);
-
-USBH_StatusTypeDef USBH_MSC_SCSI_RequestSense (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun, 
-                                               SCSI_SenseTypeDef *sense_data);
-
-USBH_StatusTypeDef USBH_MSC_SCSI_Write(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length);
-
-USBH_StatusTypeDef USBH_MSC_SCSI_Read(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length);
-
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __USBH_MSC_SCSI_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c
deleted file mode 100644
index 1ea03d07..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc.c
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements the MSC class driver functions
-  *          ===================================================================      
-  *                                MSC Class  Description
-  *          =================================================================== 
-  *           This module manages the MSC class V1.0 following the "Universal 
-  *           Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
-  *           Sep. 31, 1999".
-  *           This driver implements the following aspects of the specification:
-  *             - Bulk-Only Transport protocol
-  *             - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
-  *      
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_msc.h"
-#include "usbh_msc_bot.h"    
-#include "usbh_msc_scsi.h"
-
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_CLASS
-  * @{
-  */
-
-/** @addtogroup USBH_MSC_CLASS
-  * @{
-  */
-  
-/** @defgroup USBH_MSC_CORE 
-  * @brief    This file includes the mass storage related functions
-  * @{
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_CORE_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_CORE_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Private_FunctionPrototypes
-  * @{
-  */ 
-
-static USBH_StatusTypeDef USBH_MSC_InterfaceInit  (USBH_HandleTypeDef *phost);
-
-static USBH_StatusTypeDef USBH_MSC_InterfaceDeInit  (USBH_HandleTypeDef *phost);
-
-static USBH_StatusTypeDef USBH_MSC_Process(USBH_HandleTypeDef *phost);
-
-static USBH_StatusTypeDef USBH_MSC_ClassRequest(USBH_HandleTypeDef *phost);
-
-static USBH_StatusTypeDef USBH_MSC_SOFProcess(USBH_HandleTypeDef *phost);
-
-static USBH_StatusTypeDef USBH_MSC_RdWrProcess(USBH_HandleTypeDef *phost, uint8_t lun);
-
-USBH_ClassTypeDef  USBH_msc = 
-{
-  "MSC",
-  USB_MSC_CLASS,
-  USBH_MSC_InterfaceInit,
-  USBH_MSC_InterfaceDeInit,
-  USBH_MSC_ClassRequest,
-  USBH_MSC_Process,
-  USBH_MSC_SOFProcess,
-  NULL,
-};
-
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Exported_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_CORE_Private_Functions
-  * @{
-  */ 
-
-
-/**
-  * @brief  USBH_MSC_InterfaceInit 
-  *         The function init the MSC class.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_InterfaceInit (USBH_HandleTypeDef *phost)
-{	 
-  uint8_t interface = 0; 
-  USBH_StatusTypeDef status = USBH_FAIL ;
-  MSC_HandleTypeDef *MSC_Handle;
-  
-  interface = USBH_FindInterface(phost, phost->pActiveClass->ClassCode, MSC_TRANSPARENT, MSC_BOT);
-  
-  if(interface == 0xFF) /* Not Valid Interface */
-  {
-    USBH_DbgLog ("Cannot Find the interface for %s class.", phost->pActiveClass->Name);
-    status = USBH_FAIL;      
-  }
-  else
-  {
-    USBH_SelectInterface (phost, interface);
-    
-    phost->pActiveClass->pData = (MSC_HandleTypeDef *)USBH_malloc (sizeof(MSC_HandleTypeDef));
-    MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-    
-    if(phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[0].bEndpointAddress & 0x80)
-    {
-      MSC_Handle->InEp = (phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[0].bEndpointAddress);
-      MSC_Handle->InEpSize  = phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[0].wMaxPacketSize;
-    }
-    else
-    {
-      MSC_Handle->OutEp = (phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[0].bEndpointAddress);
-      MSC_Handle->OutEpSize  = phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[0].wMaxPacketSize;      
-    }
-    
-    if(phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[1].bEndpointAddress & 0x80)
-    {
-      MSC_Handle->InEp = (phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[1].bEndpointAddress);
-      MSC_Handle->InEpSize  = phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[1].wMaxPacketSize;      
-    }
-    else
-    {
-      MSC_Handle->OutEp = (phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[1].bEndpointAddress);
-      MSC_Handle->OutEpSize  = phost->device.CfgDesc.Itf_Desc[phost->device.current_interface].Ep_Desc[1].wMaxPacketSize;      
-    }
-    
-    MSC_Handle->current_lun = 0;
-    MSC_Handle->rw_lun = 0;
-    MSC_Handle->state = MSC_INIT;
-    MSC_Handle->error = MSC_OK;
-    MSC_Handle->req_state = MSC_REQ_IDLE;
-    MSC_Handle->OutPipe = USBH_AllocPipe(phost, MSC_Handle->OutEp);
-    MSC_Handle->InPipe = USBH_AllocPipe(phost, MSC_Handle->InEp);
-
-    USBH_MSC_BOT_Init(phost);
-    
-    /* De-Initialize LUNs information */
-    USBH_memset(MSC_Handle->unit, 0, sizeof(MSC_Handle->unit));
-    
-    /* Open the new channels */
-    USBH_OpenPipe  (phost,
-                    MSC_Handle->OutPipe,
-                    MSC_Handle->OutEp,
-                    phost->device.address,
-                    phost->device.speed,
-                    USB_EP_TYPE_BULK,
-                    MSC_Handle->OutEpSize);  
-    
-    USBH_OpenPipe  (phost,
-                    MSC_Handle->InPipe,
-                    MSC_Handle->InEp,
-                    phost->device.address,
-                    phost->device.speed,
-                    USB_EP_TYPE_BULK,
-                    MSC_Handle->InEpSize);     
-    
-    
-    USBH_LL_SetToggle  (phost, MSC_Handle->InPipe,0);
-    USBH_LL_SetToggle  (phost, MSC_Handle->OutPipe,0);
-    status = USBH_OK; 
-  }
-  return status;
-}
-
-/**
-  * @brief  USBH_MSC_InterfaceDeInit 
-  *         The function DeInit the Pipes used for the MSC class.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_InterfaceDeInit (USBH_HandleTypeDef *phost)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-
-  if ( MSC_Handle->OutPipe)
-  {
-    USBH_ClosePipe(phost, MSC_Handle->OutPipe);
-    USBH_FreePipe  (phost, MSC_Handle->OutPipe);
-    MSC_Handle->OutPipe = 0;     /* Reset the Channel as Free */
-  }
-  
-  if ( MSC_Handle->InPipe)
-  {
-    USBH_ClosePipe(phost, MSC_Handle->InPipe);
-    USBH_FreePipe  (phost, MSC_Handle->InPipe);
-    MSC_Handle->InPipe = 0;     /* Reset the Channel as Free */
-  } 
-
-  if(phost->pActiveClass->pData)
-  {
-    USBH_free (phost->pActiveClass->pData);
-    phost->pActiveClass->pData = 0;
-  }
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_MSC_ClassRequest 
-  *         The function is responsible for handling Standard requests
-  *         for MSC class.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_ClassRequest(USBH_HandleTypeDef *phost)
-{   
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;  
-  USBH_StatusTypeDef status = USBH_BUSY;
-  uint8_t i;
-  
-  /* Switch MSC REQ state machine */
-  switch (MSC_Handle->req_state)
-  {
-  case MSC_REQ_IDLE:
-  case MSC_REQ_GET_MAX_LUN:   
-    /* Issue GetMaxLUN request */
-    status = USBH_MSC_BOT_REQ_GetMaxLUN(phost, (uint8_t *)&MSC_Handle->max_lun);
-    
-    /* When devices do not support the GetMaxLun request, this should
-       be considred as only one logical unit is supported */
-    if(status == USBH_NOT_SUPPORTED)
-    {
-      MSC_Handle->max_lun = 0;
-      status = USBH_OK;
-    }
-    
-    if(status == USBH_OK)
-    {
-      MSC_Handle->max_lun = (uint8_t )(MSC_Handle->max_lun) + 1;
-      USBH_UsrLog ("Number of supported LUN: %lu", (int32_t)(MSC_Handle->max_lun));
-      
-      for(i = 0; i < MSC_Handle->max_lun; i++)
-      {
-        MSC_Handle->unit[i].prev_ready_state = USBH_FAIL;
-        MSC_Handle->unit[i].state_changed = 0;
-      }
-    }
-    break;
-    
-  case MSC_REQ_ERROR :
-    /* a Clear Feature should be issued here */
-    if(USBH_ClrFeature(phost, 0x00) == USBH_OK)
-    {
-      MSC_Handle->req_state = MSC_Handle->prev_req_state; 
-    }    
-    break;
-    
-  default:
-    break;
-  }
-  
-  return status; 
-}
-
-/**
-  * @brief  USBH_MSC_Process 
-  *         The function is for managing state machine for MSC data transfers 
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_Process(USBH_HandleTypeDef *phost)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  USBH_StatusTypeDef error = USBH_BUSY ;
-  USBH_StatusTypeDef scsi_status = USBH_BUSY ;  
-  USBH_StatusTypeDef ready_status = USBH_BUSY ;
-  
-  switch (MSC_Handle->state)
-  {
-  case MSC_INIT:
-    
-    if(MSC_Handle->current_lun < MSC_Handle->max_lun)
-    {
-
-      MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_NOT_READY;
-      /* Switch MSC REQ state machine */
-      switch (MSC_Handle->unit[MSC_Handle->current_lun].state)
-      {
-      case MSC_INIT:
-        USBH_UsrLog ("LUN #%d: ", MSC_Handle->current_lun);
-        MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_READ_INQUIRY;
-        MSC_Handle->timer = phost->Timer;
-        
-      case MSC_READ_INQUIRY:
-        scsi_status = USBH_MSC_SCSI_Inquiry(phost, MSC_Handle->current_lun, &MSC_Handle->unit[MSC_Handle->current_lun].inquiry);
-        
-        if( scsi_status == USBH_OK)
-        {
-          USBH_UsrLog ("Inquiry Vendor  : %s", MSC_Handle->unit[MSC_Handle->current_lun].inquiry.vendor_id);
-          USBH_UsrLog ("Inquiry Product : %s", MSC_Handle->unit[MSC_Handle->current_lun].inquiry.product_id);
-          USBH_UsrLog ("Inquiry Version : %s", MSC_Handle->unit[MSC_Handle->current_lun].inquiry.revision_id);
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_TEST_UNIT_READY;        
-        }
-        if( scsi_status == USBH_FAIL)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_REQUEST_SENSE;         
-        }
-        else if(scsi_status == USBH_UNRECOVERED_ERROR)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_ERROR;
-        }
-        break;    
-        
-      case MSC_TEST_UNIT_READY:
-        ready_status = USBH_MSC_SCSI_TestUnitReady(phost, MSC_Handle->current_lun);
-        
-        if( ready_status == USBH_OK)
-        {
-          if( MSC_Handle->unit[MSC_Handle->current_lun].prev_ready_state != USBH_OK)
-          {
-            MSC_Handle->unit[MSC_Handle->current_lun].state_changed = 1;
-            USBH_UsrLog ("MSC Device ready");
-          }
-          else
-          {
-            MSC_Handle->unit[MSC_Handle->current_lun].state_changed = 0;
-          }
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_READ_CAPACITY10;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_OK;
-          MSC_Handle->unit[MSC_Handle->current_lun].prev_ready_state = USBH_OK;
-        }
-        if( ready_status == USBH_FAIL)
-        {
-          /* Media not ready, so try to check again during 10s */
-          if( MSC_Handle->unit[MSC_Handle->current_lun].prev_ready_state != USBH_FAIL)
-          {
-            MSC_Handle->unit[MSC_Handle->current_lun].state_changed = 1;
-            USBH_UsrLog ("MSC Device NOT ready");
-          }
-          else
-          {
-            MSC_Handle->unit[MSC_Handle->current_lun].state_changed = 0;
-          }         
-            MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_REQUEST_SENSE; 
-            MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_NOT_READY;
-            MSC_Handle->unit[MSC_Handle->current_lun].prev_ready_state = USBH_FAIL;
-        }
-        else if(ready_status == USBH_UNRECOVERED_ERROR)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_ERROR;
-        }
-        break;
-        
-      case MSC_READ_CAPACITY10:   
-        scsi_status = USBH_MSC_SCSI_ReadCapacity(phost,MSC_Handle->current_lun, &MSC_Handle->unit[MSC_Handle->current_lun].capacity) ;
-        
-        if(scsi_status == USBH_OK)
-        {
-          if(MSC_Handle->unit[MSC_Handle->current_lun].state_changed == 1)
-          {
-            USBH_UsrLog ("MSC Device capacity : %lu Bytes", \
-              (int32_t)(MSC_Handle->unit[MSC_Handle->current_lun].capacity.block_nbr * MSC_Handle->unit[MSC_Handle->current_lun].capacity.block_size));
-            USBH_UsrLog ("Block number : %lu", (int32_t)(MSC_Handle->unit[MSC_Handle->current_lun].capacity.block_nbr));
-            USBH_UsrLog ("Block Size   : %lu", (int32_t)(MSC_Handle->unit[MSC_Handle->current_lun].capacity.block_size));
-          }
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_OK;
-          MSC_Handle->current_lun++;
-        }
-        else if( scsi_status == USBH_FAIL)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_REQUEST_SENSE;
-        }
-        else if(scsi_status == USBH_UNRECOVERED_ERROR)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_ERROR;
-        }
-        break;
-        
-      case MSC_REQUEST_SENSE:
-        scsi_status = USBH_MSC_SCSI_RequestSense(phost,  MSC_Handle->current_lun, &MSC_Handle->unit[MSC_Handle->current_lun].sense);
-        
-        if( scsi_status == USBH_OK)
-        {
-          if((MSC_Handle->unit[MSC_Handle->current_lun].sense.key == SCSI_SENSE_KEY_UNIT_ATTENTION) ||
-             (MSC_Handle->unit[MSC_Handle->current_lun].sense.key == SCSI_SENSE_KEY_NOT_READY) )   
-          {
-            
-            if((phost->Timer - MSC_Handle->timer) < 10000)
-            {
-              MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_TEST_UNIT_READY;
-              break;
-            }        
-          }
-          
-          USBH_UsrLog ("Sense Key  : %x", MSC_Handle->unit[MSC_Handle->current_lun].sense.key);
-          USBH_UsrLog ("Additional Sense Code : %x", MSC_Handle->unit[MSC_Handle->current_lun].sense.asc);
-          USBH_UsrLog ("Additional Sense Code Qualifier: %x", MSC_Handle->unit[MSC_Handle->current_lun].sense.ascq);
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->current_lun++;
-        }
-        if( scsi_status == USBH_FAIL)
-        {
-          USBH_UsrLog ("MSC Device NOT ready");
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_UNRECOVERED_ERROR; 
-        }
-        else if(scsi_status == USBH_UNRECOVERED_ERROR)
-        {
-          MSC_Handle->unit[MSC_Handle->current_lun].state = MSC_IDLE;
-          MSC_Handle->unit[MSC_Handle->current_lun].error = MSC_ERROR;   
-        }
-        break;  
-    
-      case MSC_UNRECOVERED_ERROR: 
-        MSC_Handle->current_lun++;
-        break;  
-        
-      default:
-        break;
-      }
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CLASS_EVENT, 0);
-#endif       
-    }
-    else
-    {
-      MSC_Handle->current_lun = 0;
-    MSC_Handle->state = MSC_IDLE;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CLASS_EVENT, 0);
-#endif 
-    phost->pUser(phost, HOST_USER_CLASS_ACTIVE);     
-    }
-    break;
-
-  case MSC_IDLE:
-    error = USBH_OK;  
-    break;
-    
-  default:
-    break; 
-  }
-  return error;
-}
-
-
-/**
-  * @brief  USBH_MSC_SOFProcess 
-  *         The function is for SOF state
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_SOFProcess(USBH_HandleTypeDef *phost)
-{
-
-  return USBH_OK;
-}
-/**
-  * @brief  USBH_MSC_RdWrProcess 
-  *         The function is for managing state machine for MSC I/O Process
-  * @param  phost: Host handle
-  * @param  lun: logical Unit Number
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_RdWrProcess(USBH_HandleTypeDef *phost, uint8_t lun)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  USBH_StatusTypeDef error = USBH_BUSY ;
-  USBH_StatusTypeDef scsi_status = USBH_BUSY ;  
-  
-  /* Switch MSC REQ state machine */
-  switch (MSC_Handle->unit[lun].state)
-  {
- 
-  case MSC_READ: 
-    scsi_status = USBH_MSC_SCSI_Read(phost,lun, 0, NULL, 0) ;
-    
-    if(scsi_status == USBH_OK)
-    {
-      MSC_Handle->unit[lun].state = MSC_IDLE;
-      error = USBH_OK;     
-    }
-    else if( scsi_status == USBH_FAIL)
-    {
-      MSC_Handle->unit[lun].state = MSC_REQUEST_SENSE;  
-    }
-    else if(scsi_status == USBH_UNRECOVERED_ERROR)
-    {
-      MSC_Handle->unit[lun].state = MSC_UNRECOVERED_ERROR;
-          error = USBH_FAIL;
-    }
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CLASS_EVENT, 0);
-#endif   
-    break;     
-    
-  case MSC_WRITE: 
-    scsi_status = USBH_MSC_SCSI_Write(phost,lun, 0, NULL, 0) ;
-    
-    if(scsi_status == USBH_OK)
-    {
-        MSC_Handle->unit[lun].state = MSC_IDLE;
-        error = USBH_OK;             
-    }
-    else if( scsi_status == USBH_FAIL)
-    {
-      MSC_Handle->unit[lun].state = MSC_REQUEST_SENSE;  
-    }
-    else if(scsi_status == USBH_UNRECOVERED_ERROR)
-    {
-      MSC_Handle->unit[lun].state = MSC_UNRECOVERED_ERROR;
-          error = USBH_FAIL;
-    }
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CLASS_EVENT, 0);
-#endif       
-    break; 
-  
-  case MSC_REQUEST_SENSE:
-    scsi_status = USBH_MSC_SCSI_RequestSense(phost, lun, &MSC_Handle->unit[lun].sense);
-    
-    if( scsi_status == USBH_OK)
-    {
-      USBH_UsrLog ("Sense Key  : %x", MSC_Handle->unit[lun].sense.key);
-      USBH_UsrLog ("Additional Sense Code : %x", MSC_Handle->unit[lun].sense.asc);
-      USBH_UsrLog ("Additional Sense Code Qualifier: %x", MSC_Handle->unit[lun].sense.ascq);
-      MSC_Handle->unit[lun].state = MSC_IDLE;
-      MSC_Handle->unit[lun].error = MSC_ERROR;
-      
-      error = USBH_FAIL;
-    }
-    if( scsi_status == USBH_FAIL)
-    {
-      USBH_UsrLog ("MSC Device NOT ready");
-    }
-    else if(scsi_status == USBH_UNRECOVERED_ERROR)
-    {
-      MSC_Handle->unit[lun].state = MSC_UNRECOVERED_ERROR;  
-          error = USBH_FAIL;
-    }
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CLASS_EVENT, 0);
-#endif       
-    break;  
-    
-  default:
-    break;  
-    
-  }
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_IsReady 
-  *         The function check if the MSC function is ready
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-uint8_t  USBH_MSC_IsReady (USBH_HandleTypeDef *phost)
-{
-    MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;  
-    
-  if(phost->gState == HOST_CLASS)
-  {
-    return (MSC_Handle->state == MSC_IDLE);
-  }
-  else
-  {
-    return 0;
-  }
-}
-
-/**
-  * @brief  USBH_MSC_GetMaxLUN 
-  *         The function return the Max LUN supported
-  * @param  phost: Host handle
-  * @retval logical Unit Number supported
-  */
-int8_t  USBH_MSC_GetMaxLUN (USBH_HandleTypeDef *phost)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;    
-  
-  if ((phost->gState == HOST_CLASS) && (MSC_Handle->state == MSC_IDLE))
-  {
-    return  MSC_Handle->max_lun;
-  }  
-  return 0xFF;
-}
-
-/**
-  * @brief  USBH_MSC_UnitIsReady 
-  *         The function check whether a LUN is ready
-  * @param  phost: Host handle
-  * @param  lun: logical Unit Number
-  * @retval Lun status (0: not ready / 1: ready)
-  */
-uint8_t  USBH_MSC_UnitIsReady (USBH_HandleTypeDef *phost, uint8_t lun)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;  
-  
-  if(phost->gState == HOST_CLASS)
-  {
-    return (MSC_Handle->unit[lun].error == MSC_OK);
-  }
-  else
-  {
-    return 0;
-  }
-}
-      
-/**
-  * @brief  USBH_MSC_GetLUNInfo 
-  *         The function return a LUN information
-  * @param  phost: Host handle
-  * @param  lun: logical Unit Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_GetLUNInfo(USBH_HandleTypeDef *phost, uint8_t lun, MSC_LUNTypeDef *info)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;    
-  if(phost->gState == HOST_CLASS)
-  {
-    USBH_memcpy(info,&MSC_Handle->unit[lun], sizeof(MSC_LUNTypeDef));
-    return USBH_OK;
-  }
-  else
-  {
-    return USBH_FAIL;
-  }
-}
-
-/**
-  * @brief  USBH_MSC_Read 
-  *         The function performs a Read operation 
-  * @param  phost: Host handle
-  * @param  lun: logical Unit Number
-  * @param  address: sector address
-  * @param  pbuf: pointer to data
-  * @param  length: number of sector to read
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_Read(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length)
-{
-  uint32_t timeout;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;   
-  
-  if ((phost->device.is_connected == 0) || 
-      (phost->gState != HOST_CLASS) || 
-      (MSC_Handle->unit[lun].state != MSC_IDLE))
-  {
-    return  USBH_FAIL;
-  }
-  MSC_Handle->state = MSC_READ;
-  MSC_Handle->unit[lun].state = MSC_READ;
-  MSC_Handle->rw_lun = lun;
-  USBH_MSC_SCSI_Read(phost,
-                     lun,
-                     address,
-                     pbuf,
-                     length);
-  
-  timeout = phost->Timer;
-  
-  while (USBH_MSC_RdWrProcess(phost, lun) == USBH_BUSY)
-  {
-    if(((phost->Timer - timeout) > (10000 * length)) || (phost->device.is_connected == 0))
-    {
-      MSC_Handle->state = MSC_IDLE;
-      return USBH_FAIL;
-    }
-  }
-  MSC_Handle->state = MSC_IDLE;
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_MSC_Write 
-  *         The function performs a Write operation 
-  * @param  phost: Host handle
-  * @param  lun: logical Unit Number
-  * @param  address: sector address
-  * @param  pbuf: pointer to data
-  * @param  length: number of sector to write
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_Write(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length)
-{
-  uint32_t timeout;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;   
-  
-  if ((phost->device.is_connected == 0) || 
-      (phost->gState != HOST_CLASS) || 
-      (MSC_Handle->unit[lun].state != MSC_IDLE))
-  {
-    return  USBH_FAIL;
-  }
-  MSC_Handle->state = MSC_WRITE;
-  MSC_Handle->unit[lun].state = MSC_WRITE;
-  MSC_Handle->rw_lun = lun;
-  USBH_MSC_SCSI_Write(phost,
-                     lun,
-                     address,
-                     pbuf,
-                     length);
-  
-  timeout = phost->Timer;
-  while (USBH_MSC_RdWrProcess(phost, lun) == USBH_BUSY)
-  {
-    if(((phost->Timer - timeout) >  (10000 * length)) || (phost->device.is_connected == 0))
-    {
-      MSC_Handle->state = MSC_IDLE;
-      return USBH_FAIL;
-    }
-  }
-  MSC_Handle->state = MSC_IDLE;
-  return USBH_OK;
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_bot.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_bot.c
deleted file mode 100644
index 9d14dee4..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_bot.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc_bot.c 
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file includes the BOT protocol related functions
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_msc_bot.h"
-#include "usbh_msc.h"
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_CLASS
-* @{
-*/
-
-/** @addtogroup USBH_MSC_CLASS
-* @{
-*/
-
-/** @defgroup USBH_MSC_BOT 
-* @brief    This file includes the mass storage related functions
-* @{
-*/ 
-
-
-/** @defgroup USBH_MSC_BOT_Private_TypesDefinitions
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-/** @defgroup USBH_MSC_BOT_Private_Defines
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-/** @defgroup USBH_MSC_BOT_Private_Macros
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_MSC_BOT_Private_Variables
-* @{
-*/ 
-
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_MSC_BOT_Private_FunctionPrototypes
-* @{
-*/ 
-static USBH_StatusTypeDef USBH_MSC_BOT_Abort(USBH_HandleTypeDef *phost, uint8_t lun, uint8_t dir);
-static BOT_CSWStatusTypeDef USBH_MSC_DecodeCSW(USBH_HandleTypeDef *phost);
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_MSC_BOT_Exported_Variables
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_MSC_BOT_Private_Functions
-* @{
-*/ 
-
-/**
-  * @brief  USBH_MSC_BOT_REQ_Reset 
-  *         The function the MSC BOT Reset request.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_BOT_REQ_Reset(USBH_HandleTypeDef *phost)
-{
-  
-  phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \
-                              USB_REQ_RECIPIENT_INTERFACE;
-  
-  phost->Control.setup.b.bRequest = USB_REQ_BOT_RESET;
-  phost->Control.setup.b.wValue.w = 0;
-  phost->Control.setup.b.wIndex.w = 0;
-  phost->Control.setup.b.wLength.w = 0;           
-  
-  return USBH_CtlReq(phost, 0 , 0 );  
-}
-
-/**
-  * @brief  USBH_MSC_BOT_REQ_GetMaxLUN 
-  *         The function the MSC BOT GetMaxLUN request.
-  * @param  phost: Host handle
-  * @param  Maxlun: pointer to Maxlun variable
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_BOT_REQ_GetMaxLUN(USBH_HandleTypeDef *phost, uint8_t *Maxlun)
-{
-  phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
-                              USB_REQ_RECIPIENT_INTERFACE;
-  
-  phost->Control.setup.b.bRequest = USB_REQ_GET_MAX_LUN;
-  phost->Control.setup.b.wValue.w = 0;
-  phost->Control.setup.b.wIndex.w = 0;
-  phost->Control.setup.b.wLength.w = 1;           
-  
-  return USBH_CtlReq(phost, Maxlun , 1 ); 
-}
-
-
-
-/**
-  * @brief  USBH_MSC_BOT_Init 
-  *         The function Initializes the BOT protocol.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_BOT_Init(USBH_HandleTypeDef *phost)
-{
-  
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  MSC_Handle->hbot.cbw.field.Signature = BOT_CBW_SIGNATURE;
-  MSC_Handle->hbot.cbw.field.Tag = BOT_CBW_TAG;
-  MSC_Handle->hbot.state = BOT_SEND_CBW;    
-  MSC_Handle->hbot.cmd_state = BOT_CMD_SEND;   
-  
-  return USBH_OK;
-}
-
-
-
-/**
-  * @brief  USBH_MSC_BOT_Process 
-  *         The function handle the BOT protocol.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_BOT_Process (USBH_HandleTypeDef *phost, uint8_t lun)
-{
-  USBH_StatusTypeDef   status = USBH_BUSY;
-  USBH_StatusTypeDef   error  = USBH_BUSY;  
-  BOT_CSWStatusTypeDef CSW_Status = BOT_CSW_CMD_FAILED;
-  USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  uint8_t toggle = 0;
-  
-  switch (MSC_Handle->hbot.state)
-  {
-  case BOT_SEND_CBW:
-    MSC_Handle->hbot.cbw.field.LUN = lun;
-    MSC_Handle->hbot.state = BOT_SEND_CBW_WAIT;    
-    USBH_BulkSendData (phost,
-                       MSC_Handle->hbot.cbw.data, 
-                       BOT_CBW_LENGTH, 
-                       MSC_Handle->OutPipe,
-                       1);
-    
-    break;
-    
-  case BOT_SEND_CBW_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost, MSC_Handle->OutPipe); 
-    
-    if(URB_Status == USBH_URB_DONE)
-    { 
-      if ( MSC_Handle->hbot.cbw.field.DataTransferLength != 0 )
-      {
-        /* If there is Data Transfer Stage */
-        if (((MSC_Handle->hbot.cbw.field.Flags) & USB_REQ_DIR_MASK) == USB_D2H)
-        {
-          /* Data Direction is IN */
-          MSC_Handle->hbot.state = BOT_DATA_IN;
-        }
-        else
-        {
-          /* Data Direction is OUT */
-          MSC_Handle->hbot.state = BOT_DATA_OUT;
-        } 
-      }
-      
-      else
-      {/* If there is NO Data Transfer Stage */
-        MSC_Handle->hbot.state = BOT_RECEIVE_CSW;
-      }
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif   
-    
-    }   
-    else if(URB_Status == USBH_URB_NOTREADY)
-    {
-      /* Re-send CBW */
-      MSC_Handle->hbot.state = BOT_SEND_CBW;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }     
-    else if(URB_Status == USBH_URB_STALL)
-    {
-      MSC_Handle->hbot.state  = BOT_ERROR_OUT;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    break;
-    
-  case BOT_DATA_IN:   
-    /* Send first packet */        
-    USBH_BulkReceiveData (phost,
-                          MSC_Handle->hbot.pbuf, 
-                          MSC_Handle->InEpSize , 
-                          MSC_Handle->InPipe);
-    
-    MSC_Handle->hbot.state  = BOT_DATA_IN_WAIT;
-    
-    break;   
-    
-  case BOT_DATA_IN_WAIT:  
-    
-    URB_Status = USBH_LL_GetURBState(phost, MSC_Handle->InPipe); 
-    
-    if(URB_Status == USBH_URB_DONE) 
-    {
-      /* Adjust Data pointer and data length */
-      if(MSC_Handle->hbot.cbw.field.DataTransferLength > MSC_Handle->InEpSize)
-      {
-          MSC_Handle->hbot.pbuf += MSC_Handle->InEpSize;
-          MSC_Handle->hbot.cbw.field.DataTransferLength -= MSC_Handle->InEpSize;  
-      }
-      else
-      {
-        MSC_Handle->hbot.cbw.field.DataTransferLength = 0;
-      }
-        
-      /* More Data To be Received */
-      if(MSC_Handle->hbot.cbw.field.DataTransferLength > 0)
-      {
-        /* Send next packet */        
-        USBH_BulkReceiveData (phost,
-                              MSC_Handle->hbot.pbuf, 
-                              MSC_Handle->InEpSize , 
-                              MSC_Handle->InPipe);
-        
-      }
-      else
-      {
-        /* If value was 0, and successful transfer, then change the state */
-        MSC_Handle->hbot.state  = BOT_RECEIVE_CSW;
-#if (USBH_USE_OS == 1)
-        osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif 
-      }
-    }
-    else if(URB_Status == USBH_URB_STALL)
-    {
-      /* This is Data IN Stage STALL Condition */
-      MSC_Handle->hbot.state  = BOT_ERROR_IN;
-      
-      /* Refer to USB Mass-Storage Class : BOT (www.usb.org) 
-      6.7.2 Host expects to receive data from the device
-      3. On a STALL condition receiving data, then:
-      The host shall accept the data received.
-      The host shall clear the Bulk-In pipe.
-      4. The host shall attempt to receive a CSW.*/
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }     
-    break;  
-    
-  case BOT_DATA_OUT:
-    
-    USBH_BulkSendData (phost,
-                       MSC_Handle->hbot.pbuf, 
-                       MSC_Handle->OutEpSize , 
-                       MSC_Handle->OutPipe,
-                       1);
-    
-    
-    MSC_Handle->hbot.state  = BOT_DATA_OUT_WAIT;
-    break;
-    
-  case BOT_DATA_OUT_WAIT:
-    URB_Status = USBH_LL_GetURBState(phost, MSC_Handle->OutPipe);     
-    
-    if(URB_Status == USBH_URB_DONE)
-    {
-      /* Adjust Data pointer and data length */
-      if(MSC_Handle->hbot.cbw.field.DataTransferLength > MSC_Handle->OutEpSize)
-      {
-          MSC_Handle->hbot.pbuf += MSC_Handle->OutEpSize;
-          MSC_Handle->hbot.cbw.field.DataTransferLength -= MSC_Handle->OutEpSize; 
-      }
-      else
-      {
-        MSC_Handle->hbot.cbw.field.DataTransferLength = 0;
-      } 
-      
-      /* More Data To be Sent */
-      if(MSC_Handle->hbot.cbw.field.DataTransferLength > 0)
-      {
-        USBH_BulkSendData (phost,
-                           MSC_Handle->hbot.pbuf, 
-                           MSC_Handle->OutEpSize , 
-                           MSC_Handle->OutPipe,
-                           1);
-      }
-      else
-      {
-        /* If value was 0, and successful transfer, then change the state */
-        MSC_Handle->hbot.state  = BOT_RECEIVE_CSW;
-      }  
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    
-    else if(URB_Status == USBH_URB_NOTREADY)
-    {
-      /* Resend same data */      
-      MSC_Handle->hbot.state  = BOT_DATA_OUT;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    
-    else if(URB_Status == USBH_URB_STALL)
-    {
-      MSC_Handle->hbot.state  = BOT_ERROR_OUT;
-      
-      /* Refer to USB Mass-Storage Class : BOT (www.usb.org) 
-      6.7.3 Ho - Host expects to send data to the device
-      3. On a STALL condition sending data, then:
-      " The host shall clear the Bulk-Out pipe.
-      4. The host shall attempt to receive a CSW.
-      */      
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    break;
-    
-  case BOT_RECEIVE_CSW:
-    
-    USBH_BulkReceiveData (phost,
-                          MSC_Handle->hbot.csw.data, 
-                          BOT_CSW_LENGTH , 
-                          MSC_Handle->InPipe);
-    
-    MSC_Handle->hbot.state  = BOT_RECEIVE_CSW_WAIT;
-    break;
-    
-  case BOT_RECEIVE_CSW_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost, MSC_Handle->InPipe); 
-    
-    /* Decode CSW */
-    if(URB_Status == USBH_URB_DONE)
-    {
-      MSC_Handle->hbot.state = BOT_SEND_CBW;    
-      MSC_Handle->hbot.cmd_state = BOT_CMD_SEND;        
-      CSW_Status = USBH_MSC_DecodeCSW(phost);
-      
-      if(CSW_Status == BOT_CSW_CMD_PASSED)
-      {
-        status = USBH_OK;
-      }
-      else
-      {
-        status = USBH_FAIL;
-      }
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    else if(URB_Status == USBH_URB_STALL)     
-    {
-      MSC_Handle->hbot.state  = BOT_ERROR_IN;
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-#endif       
-    }
-    break;
-    
-  case BOT_ERROR_IN: 
-    error = USBH_MSC_BOT_Abort(phost, lun, BOT_DIR_IN);
-    
-    if (error == USBH_OK)
-    {
-      MSC_Handle->hbot.state = BOT_RECEIVE_CSW;
-    }
-    else if (error == USBH_UNRECOVERED_ERROR)
-    {
-      /* This means that there is a STALL Error limit, Do Reset Recovery */
-      MSC_Handle->hbot.state = BOT_UNRECOVERED_ERROR;
-    }
-    break;
-    
-  case BOT_ERROR_OUT: 
-    error = USBH_MSC_BOT_Abort(phost, lun, BOT_DIR_OUT);
-    
-    if ( error == USBH_OK)
-    { 
-      
-      toggle = USBH_LL_GetToggle(phost, MSC_Handle->OutPipe); 
-      USBH_LL_SetToggle(phost, MSC_Handle->OutPipe, 1- toggle);   
-      USBH_LL_SetToggle(phost, MSC_Handle->InPipe, 0);  
-      MSC_Handle->hbot.state = BOT_ERROR_IN;        
-    }
-    else if (error == USBH_UNRECOVERED_ERROR)
-    {
-      MSC_Handle->hbot.state = BOT_UNRECOVERED_ERROR;
-    }
-    break;
-    
-    
-  case BOT_UNRECOVERED_ERROR: 
-    status = USBH_MSC_BOT_REQ_Reset(phost);
-    if ( status == USBH_OK)
-    {
-      MSC_Handle->hbot.state = BOT_SEND_CBW; 
-    }
-    break;
-    
-  default:      
-    break;
-  }
-  return status;
-}
-
-/**
-  * @brief  USBH_MSC_BOT_Abort 
-  *         The function handle the BOT Abort process.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  dir: direction (0: out / 1 : in)
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_MSC_BOT_Abort(USBH_HandleTypeDef *phost, uint8_t lun, uint8_t dir)
-{
-  USBH_StatusTypeDef status = USBH_FAIL;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch (dir)
-  {
-  case BOT_DIR_IN :
-    /* send ClrFeture on Bulk IN endpoint */
-    status = USBH_ClrFeature(phost, MSC_Handle->InEp);
-    
-    break;
-    
-  case BOT_DIR_OUT :
-    /*send ClrFeature on Bulk OUT endpoint */
-    status = USBH_ClrFeature(phost, MSC_Handle->OutEp);
-    break;
-    
-  default:
-    break;
-  }
-  return status;
-}
-
-/**
-  * @brief  USBH_MSC_BOT_DecodeCSW
-  *         This function decodes the CSW received by the device and updates the
-  *         same to upper layer.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  * @notes
-  *     Refer to USB Mass-Storage Class : BOT (www.usb.org)
-  *    6.3.1 Valid CSW Conditions :
-  *     The host shall consider the CSW valid when:
-  *     1. dCSWSignature is equal to 53425355h
-  *     2. the CSW is 13 (Dh) bytes in length,
-  *     3. dCSWTag matches the dCBWTag from the corresponding CBW.
-  */
-
-static BOT_CSWStatusTypeDef USBH_MSC_DecodeCSW(USBH_HandleTypeDef *phost)
-{
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  BOT_CSWStatusTypeDef status = BOT_CSW_CMD_FAILED;
-  
-    /*Checking if the transfer length is different than 13*/    
-    if(USBH_LL_GetLastXferSize(phost, MSC_Handle->InPipe) != BOT_CSW_LENGTH)
-    {
-      /*(4) Hi > Dn (Host expects to receive data from the device,
-      Device intends to transfer no data)
-      (5) Hi > Di (Host expects to receive data from the device,
-      Device intends to send data to the host)
-      (9) Ho > Dn (Host expects to send data to the device,
-      Device intends to transfer no data)
-      (11) Ho > Do  (Host expects to send data to the device,
-      Device intends to receive data from the host)*/
-      
-      
-      status = BOT_CSW_PHASE_ERROR;
-    }
-    else
-    { /* CSW length is Correct */
-      
-      /* Check validity of the CSW Signature and CSWStatus */
-      if(MSC_Handle->hbot.csw.field.Signature == BOT_CSW_SIGNATURE)
-      {/* Check Condition 1. dCSWSignature is equal to 53425355h */
-        
-        if(MSC_Handle->hbot.csw.field.Tag == MSC_Handle->hbot.cbw.field.Tag)
-        {
-          /* Check Condition 3. dCSWTag matches the dCBWTag from the 
-          corresponding CBW */
-
-          if(MSC_Handle->hbot.csw.field.Status == 0) 
-          {
-            /* Refer to USB Mass-Storage Class : BOT (www.usb.org) 
-            
-            Hn Host expects no data transfers
-            Hi Host expects to receive data from the device
-            Ho Host expects to send data to the device
-            
-            Dn Device intends to transfer no data
-            Di Device intends to send data to the host
-            Do Device intends to receive data from the host
-            
-            Section 6.7 
-            (1) Hn = Dn (Host expects no data transfers,
-            Device intends to transfer no data)
-            (6) Hi = Di (Host expects to receive data from the device,
-            Device intends to send data to the host)
-            (12) Ho = Do (Host expects to send data to the device, 
-            Device intends to receive data from the host)
-            
-            */
-            
-            status = BOT_CSW_CMD_PASSED;
-          }
-          else if(MSC_Handle->hbot.csw.field.Status == 1)
-          {
-            status = BOT_CSW_CMD_FAILED;
-          }
-          
-          else if(MSC_Handle->hbot.csw.field.Status == 2)
-          { 
-            /* Refer to USB Mass-Storage Class : BOT (www.usb.org) 
-            Section 6.7 
-            (2) Hn < Di ( Host expects no data transfers, 
-            Device intends to send data to the host)
-            (3) Hn < Do ( Host expects no data transfers, 
-            Device intends to receive data from the host)
-            (7) Hi < Di ( Host expects to receive data from the device, 
-            Device intends to send data to the host)
-            (8) Hi <> Do ( Host expects to receive data from the device, 
-            Device intends to receive data from the host)
-            (10) Ho <> Di (Host expects to send data to the device,
-            Di Device intends to send data to the host)
-            (13) Ho < Do (Host expects to send data to the device, 
-            Device intends to receive data from the host)
-            */
-            
-            status = BOT_CSW_PHASE_ERROR;
-          }
-        } /* CSW Tag Matching is Checked  */
-      } /* CSW Signature Correct Checking */
-      else
-      {
-        /* If the CSW Signature is not valid, We sall return the Phase Error to
-        Upper Layers for Reset Recovery */
-        
-        status = BOT_CSW_PHASE_ERROR;
-      }
-    } /* CSW Length Check*/
-    
-  return status;
-}
-
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_scsi.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_scsi.c
deleted file mode 100644
index 40332e40..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc_scsi.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_msc_scsi.c 
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements the SCSI commands
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_msc.h"
-#include "usbh_msc_scsi.h"
-#include "usbh_msc_bot.h"
-
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_CLASS
-  * @{
-  */
-
-/** @addtogroup USBH_MSC_CLASS
-  * @{
-  */
-  
-/** @defgroup USBH_MSC_SCSI 
-  * @brief    This file includes the mass storage related functions
-  * @{
-  */ 
-
-
-/** @defgroup USBH_MSC_SCSI_Private_TypesDefinitions
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_SCSI_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_MSC_SCSI_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_SCSI_Private_FunctionPrototypes
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_SCSI_Exported_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_MSC_SCSI_Private_Functions
-  * @{
-  */ 
-
-
-/**
-  * @brief  USBH_MSC_SCSI_TestUnitReady 
-  *         Issue TestUnitReady command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_TestUnitReady (USBH_HandleTypeDef *phost, 
-                                                uint8_t lun)
-{
-  USBH_StatusTypeDef    error = USBH_FAIL ;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = DATA_LEN_MODE_TEST_UNIT_READY;     
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_OUT;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_CB_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_TEST_UNIT_READY; 
-    
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    error = USBH_MSC_BOT_Process(phost, lun);
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_SCSI_ReadCapacity 
-  *         Issue Read Capacity command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  capacity: pointer to the capacity structure
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_ReadCapacity (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun,
-                                               SCSI_CapacityTypeDef *capacity)
-{
-  USBH_StatusTypeDef    error = USBH_BUSY ;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = DATA_LEN_READ_CAPACITY10;
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_IN;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_CB_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_READ_CAPACITY10; 
-    
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-    
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    MSC_Handle->hbot.pbuf = (uint8_t *)MSC_Handle->hbot.data;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    
-    error = USBH_MSC_BOT_Process(phost, lun);
-    
-    if(error == USBH_OK)
-    {
-      /*assign the capacity*/
-      capacity->block_nbr = MSC_Handle->hbot.pbuf[3] | (MSC_Handle->hbot.pbuf[2] << 8) |\
-                           (MSC_Handle->hbot.pbuf[1] << 16) | (MSC_Handle->hbot.pbuf[0] << 24);
-
-      /*assign the page length*/
-      capacity->block_size = MSC_Handle->hbot.pbuf[7] | (MSC_Handle->hbot.pbuf[6] << 8); 
-    }
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_SCSI_Inquiry 
-  *         Issue Inquiry command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  capacity: pointer to the inquiry structure
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_Inquiry (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun, 
-                                               SCSI_StdInquiryDataTypeDef *inquiry)
-{
-  USBH_StatusTypeDef    error = USBH_FAIL ;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = DATA_LEN_INQUIRY;
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_IN;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_INQUIRY; 
-    MSC_Handle->hbot.cbw.field.CB[1]  = (lun << 5);    
-    MSC_Handle->hbot.cbw.field.CB[2]  = 0;    
-    MSC_Handle->hbot.cbw.field.CB[3]  = 0;    
-    MSC_Handle->hbot.cbw.field.CB[4]  = 0x24;    
-    MSC_Handle->hbot.cbw.field.CB[5]  = 0;    
-        
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    MSC_Handle->hbot.pbuf = (uint8_t *)MSC_Handle->hbot.data;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    
-    error = USBH_MSC_BOT_Process(phost, lun);
-    
-    if(error == USBH_OK)
-    {
-      USBH_memset(inquiry, 0, sizeof(SCSI_StdInquiryDataTypeDef));
-      /*assign Inquiry Data */
-      inquiry->DeviceType = MSC_Handle->hbot.pbuf[0] & 0x1F;
-      inquiry->PeripheralQualifier = MSC_Handle->hbot.pbuf[0] >> 5;  
-      inquiry->RemovableMedia = (MSC_Handle->hbot.pbuf[1] & 0x80)== 0x80;
-      USBH_memcpy (inquiry->vendor_id, &MSC_Handle->hbot.pbuf[8], 8);
-      USBH_memcpy (inquiry->product_id, &MSC_Handle->hbot.pbuf[16], 16);
-      USBH_memcpy (inquiry->revision_id, &MSC_Handle->hbot.pbuf[32], 4);    
-    }
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_SCSI_RequestSense 
-  *         Issue RequestSense command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  capacity: pointer to the sense data structure
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_RequestSense (USBH_HandleTypeDef *phost, 
-                                               uint8_t lun, 
-                                               SCSI_SenseTypeDef *sense_data)
-{
-  USBH_StatusTypeDef    error = USBH_FAIL ;
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = DATA_LEN_REQUEST_SENSE;
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_IN;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_CB_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_REQUEST_SENSE; 
-    MSC_Handle->hbot.cbw.field.CB[1]  = (lun << 5); 
-    MSC_Handle->hbot.cbw.field.CB[2]  = 0; 
-    MSC_Handle->hbot.cbw.field.CB[3]  = 0; 
-    MSC_Handle->hbot.cbw.field.CB[4]  = DATA_LEN_REQUEST_SENSE;
-    MSC_Handle->hbot.cbw.field.CB[5]  = 0;       
-    
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    MSC_Handle->hbot.pbuf = (uint8_t *)MSC_Handle->hbot.data;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    
-    error = USBH_MSC_BOT_Process(phost, lun);
-    
-    if(error == USBH_OK)
-    {
-      sense_data->key  = MSC_Handle->hbot.pbuf[2] & 0x0F;  
-      sense_data->asc  = MSC_Handle->hbot.pbuf[12];
-      sense_data->ascq = MSC_Handle->hbot.pbuf[13];
-    }
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_SCSI_Write 
-  *         Issue write10 command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  address: sector address
-  * @param  pbuf: pointer to data
-  * @param  length: number of sector to write
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_Write(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length)
-{
-  USBH_StatusTypeDef    error = USBH_FAIL ;
-
-  MSC_HandleTypeDef *MSC_Handle =  (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = length * 512;
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_OUT;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_CB_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_WRITE10; 
-    
-    /*logical block address*/
-    MSC_Handle->hbot.cbw.field.CB[2]  = (((uint8_t*)&address)[3]);
-    MSC_Handle->hbot.cbw.field.CB[3]  = (((uint8_t*)&address)[2]);
-    MSC_Handle->hbot.cbw.field.CB[4]  = (((uint8_t*)&address)[1]);
-    MSC_Handle->hbot.cbw.field.CB[5]  = (((uint8_t*)&address)[0]);
-    
-    
-    /*Transfer length */
-    MSC_Handle->hbot.cbw.field.CB[7]  = (((uint8_t *)&length)[1]) ; 
-    MSC_Handle->hbot.cbw.field.CB[8]  = (((uint8_t *)&length)[0]) ; 
-
-    
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    MSC_Handle->hbot.pbuf = pbuf;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    error = USBH_MSC_BOT_Process(phost, lun);
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-/**
-  * @brief  USBH_MSC_SCSI_Read 
-  *         Issue Read10 command.
-  * @param  phost: Host handle
-  * @param  lun: Logical Unit Number
-  * @param  address: sector address
-  * @param  pbuf: pointer to data
-  * @param  length: number of sector to read
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_MSC_SCSI_Read(USBH_HandleTypeDef *phost,
-                                     uint8_t lun,
-                                     uint32_t address,
-                                     uint8_t *pbuf,
-                                     uint32_t length)
-{
-  USBH_StatusTypeDef    error = USBH_FAIL ;
-  MSC_HandleTypeDef *MSC_Handle = (MSC_HandleTypeDef *) phost->pActiveClass->pData;
-  
-  switch(MSC_Handle->hbot.cmd_state)
-  {
-  case BOT_CMD_SEND:  
-    
-    /*Prepare the CBW and relevent field*/
-    MSC_Handle->hbot.cbw.field.DataTransferLength = length * 512;
-    MSC_Handle->hbot.cbw.field.Flags = USB_EP_DIR_IN;
-    MSC_Handle->hbot.cbw.field.CBLength = CBW_LENGTH;
-    
-    USBH_memset(MSC_Handle->hbot.cbw.field.CB, 0, CBW_CB_LENGTH);
-    MSC_Handle->hbot.cbw.field.CB[0]  = OPCODE_READ10; 
-    
-    /*logical block address*/
-    MSC_Handle->hbot.cbw.field.CB[2]  = (((uint8_t*)&address)[3]);
-    MSC_Handle->hbot.cbw.field.CB[3]  = (((uint8_t*)&address)[2]);
-    MSC_Handle->hbot.cbw.field.CB[4]  = (((uint8_t*)&address)[1]);
-    MSC_Handle->hbot.cbw.field.CB[5]  = (((uint8_t*)&address)[0]);
-    
-    
-    /*Transfer length */
-    MSC_Handle->hbot.cbw.field.CB[7]  = (((uint8_t *)&length)[1]) ; 
-    MSC_Handle->hbot.cbw.field.CB[8]  = (((uint8_t *)&length)[0]) ; 
-
-    
-    MSC_Handle->hbot.state = BOT_SEND_CBW;
-    MSC_Handle->hbot.cmd_state = BOT_CMD_WAIT;
-    MSC_Handle->hbot.pbuf = pbuf;
-    error = USBH_BUSY; 
-    break;
-    
-  case BOT_CMD_WAIT: 
-    error = USBH_MSC_BOT_Process(phost, lun);
-    break;
-    
-  default:
-    break;
-  }
-  
-  return error;
-}
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_conf_template.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_conf_template.h
deleted file mode 100644
index 1bc2cecd..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_conf_template.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_conf_template.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_conf_template.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBH_CONF_TEMPLATE_H
-#define __USBH_CONF_TEMPLATE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-#include 
-#include 
-#include 
-
-/** @addtogroup USBH_OTG_DRIVER
-  * @{
-  */
-  
-/** @defgroup USBH_CONF
-  * @brief usb otg low level driver configuration file
-  * @{
-  */ 
-
-/** @defgroup USBH_CONF_Exported_Defines
-  * @{
-  */ 
-
-#define USBH_MAX_NUM_ENDPOINTS                2
-#define USBH_MAX_NUM_INTERFACES               2
-#define USBH_MAX_NUM_CONFIGURATION            1
-#define USBH_KEEP_CFG_DESCRIPTOR              1
-#define USBH_MAX_NUM_SUPPORTED_CLASS          1
-#define USBH_MAX_SIZE_CONFIGURATION           0x200
-#define USBH_MAX_DATA_BUFFER                  0x200
-#define USBH_DEBUG_LEVEL                      2
-#define USBH_USE_OS                           1
-    
-/** @defgroup USBH_Exported_Macros
-  * @{
-  */ 
-
- /* Memory management macros */   
-#define USBH_malloc               malloc
-#define USBH_free                 free
-#define USBH_memset               memset
-#define USBH_memcpy               memcpy
-    
- /* DEBUG macros */  
-
-  
-#if (USBH_DEBUG_LEVEL > 0)
-#define  USBH_UsrLog(...)   printf(__VA_ARGS__);\
-                            printf("\n");
-#else
-#define USBH_UsrLog(...)   
-#endif 
-                            
-                            
-#if (USBH_DEBUG_LEVEL > 1)
-
-#define  USBH_ErrLog(...)   printf("ERROR: ") ;\
-                            printf(__VA_ARGS__);\
-                            printf("\n");
-#else
-#define USBH_ErrLog(...)   
-#endif 
-                            
-                            
-#if (USBH_DEBUG_LEVEL > 2)                         
-#define  USBH_DbgLog(...)   printf("DEBUG : ") ;\
-                            printf(__VA_ARGS__);\
-                            printf("\n");
-#else
-#define USBH_DbgLog(...)                         
-#endif
-                            
-/**
-  * @}
-  */ 
-   
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_CONF_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_CONF_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CONF_Exported_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CONF_Exported_FunctionsPrototype
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBH_CONF_TEMPLATE_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h
deleted file mode 100644
index 9a96169a..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_core.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_core.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_core.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_CORE_H
-#define __USBH_CORE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_conf.h"
-#include "usbh_def.h"
-#include "usbh_ioreq.h"
-#include "usbh_pipes.h"
-#include "usbh_ctlreq.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_CORE
-  * @brief This file is the Header file for usbh_core.c
-  * @{
-  */ 
-
-
-/** @defgroup USBH_CORE_Exported_Defines
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-#define HOST_USER_SELECT_CONFIGURATION          1
-#define HOST_USER_CLASS_ACTIVE                  2
-#define HOST_USER_CLASS_SELECTED                3
-#define HOST_USER_CONNECTION                    4
-#define HOST_USER_DISCONNECTION                 5
-#define HOST_USER_UNRECOVERED_ERROR             6
-
-
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup USBH_CORE_Exported_Macros
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CORE_Exported_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CORE_Exported_FunctionsPrototype
-  * @{
-  */ 
-
-  
-USBH_StatusTypeDef  USBH_Init(USBH_HandleTypeDef *phost, void (*pUsrFunc)(USBH_HandleTypeDef *phost, uint8_t ), uint8_t id);
-USBH_StatusTypeDef  USBH_DeInit(USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef  USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass);
-USBH_StatusTypeDef  USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface);
-uint8_t             USBH_FindInterface(USBH_HandleTypeDef *phost, 
-                                            uint8_t Class, 
-                                            uint8_t SubClass, 
-                                            uint8_t Protocol);
-uint8_t             USBH_GetActiveClass(USBH_HandleTypeDef *phost);
-
-uint8_t             USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost, 
-                                            uint8_t interface_number, 
-                                            uint8_t alt_settings);
-
-USBH_StatusTypeDef  USBH_Start            (USBH_HandleTypeDef *phost); 
-USBH_StatusTypeDef  USBH_Stop             (USBH_HandleTypeDef *phost); 
-USBH_StatusTypeDef  USBH_Process          (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef  USBH_ReEnumerate      (USBH_HandleTypeDef *phost);
-
-/* USBH Low Level Driver */
-USBH_StatusTypeDef   USBH_LL_Init         (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef   USBH_LL_DeInit       (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef   USBH_LL_Start        (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef   USBH_LL_Stop         (USBH_HandleTypeDef *phost);
-
-USBH_StatusTypeDef   USBH_LL_Connect      (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef   USBH_LL_Disconnect   (USBH_HandleTypeDef *phost);
-USBH_SpeedTypeDef    USBH_LL_GetSpeed     (USBH_HandleTypeDef *phost);
-USBH_StatusTypeDef   USBH_LL_ResetPort    (USBH_HandleTypeDef *phost);
-uint32_t             USBH_LL_GetLastXferSize   (USBH_HandleTypeDef *phost, uint8_t ); 
-USBH_StatusTypeDef   USBH_LL_DriverVBUS   (USBH_HandleTypeDef *phost, uint8_t );
-
-USBH_StatusTypeDef   USBH_LL_OpenPipe     (USBH_HandleTypeDef *phost, uint8_t, uint8_t, uint8_t, uint8_t , uint8_t, uint16_t ); 
-USBH_StatusTypeDef   USBH_LL_ClosePipe    (USBH_HandleTypeDef *phost, uint8_t );   
-USBH_StatusTypeDef   USBH_LL_SubmitURB    (USBH_HandleTypeDef *phost, uint8_t, uint8_t,uint8_t,  uint8_t, uint8_t*, uint16_t, uint8_t ); 
-USBH_URBStateTypeDef USBH_LL_GetURBState  (USBH_HandleTypeDef *phost, uint8_t ); 
-#if (USBH_USE_OS == 1)
-USBH_StatusTypeDef  USBH_LL_NotifyURBChange (USBH_HandleTypeDef *phost);
-#endif
-USBH_StatusTypeDef   USBH_LL_SetToggle    (USBH_HandleTypeDef *phost, uint8_t , uint8_t );
-uint8_t              USBH_LL_GetToggle    (USBH_HandleTypeDef *phost, uint8_t );
-
-/* USBH Time base */
-void                 USBH_Delay (uint32_t Delay);
-void                 USBH_LL_SetTimer     (USBH_HandleTypeDef *phost, uint32_t );  
-void                 USBH_LL_IncTimer     (USBH_HandleTypeDef *phost);  
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBH_CORE_H */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h
deleted file mode 100644
index 1d0e2026..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ctlreq.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_ctlreq.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_ctlreq.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_CTLREQ_H
-#define __USBH_CTLREQ_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_CTLREQ
-  * @brief This file is the 
-  * @{
-  */ 
-
-
-/** @defgroup USBH_CTLREQ_Exported_Defines
-  * @{
-  */
-/*Standard Feature Selector for clear feature command*/
-#define FEATURE_SELECTOR_ENDPOINT         0X00
-#define FEATURE_SELECTOR_DEVICE           0X01
-
-
-#define INTERFACE_DESC_TYPE               0x04
-#define ENDPOINT_DESC_TYPE                0x05
-#define INTERFACE_DESC_SIZE               0x09
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_CTLREQ_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_CTLREQ_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CTLREQ_Exported_Variables
-  * @{
-  */ 
-extern uint8_t USBH_CfgDesc[512];
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CTLREQ_Exported_FunctionsPrototype
-  * @{
-  */
-USBH_StatusTypeDef USBH_CtlReq     (USBH_HandleTypeDef *phost, 
-                             uint8_t             *buff,
-                             uint16_t            length);
-
-USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost,                                
-                               uint8_t  req_type,
-                               uint16_t value_idx, 
-                               uint8_t* buff, 
-                               uint16_t length );
-
-USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost,
-                             uint8_t length);
-
-USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost,                              
-                                uint8_t string_index, 
-                                uint8_t *buff, 
-                                uint16_t length);
-
-USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, 
-                        uint16_t configuration_value);
-
-USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost,                              
-                             uint16_t length);
-
-USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost,                          
-                            uint8_t DeviceAddress);
-
-USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, 
-                        uint8_t ep_num, uint8_t altSetting);
-
-USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, 
-                                   uint8_t ep_num);
-
-USBH_DescHeader_t      *USBH_GetNextDesc (uint8_t   *pbuf, 
-                                                  uint16_t  *ptr);
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBH_CTLREQ_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h
deleted file mode 100644
index acc19092..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_def.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Definitions used in the USB host library
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
- 
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef  USBH_DEF_H
-#define  USBH_DEF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_conf.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_DEF
-  * @brief This file is includes USB descriptors
-  * @{
-  */ 
-
-#ifndef NULL
-#define NULL  0
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef TRUE
-#define TRUE  1
-#endif
-
-
-#define ValBit(VAR,POS)                               (VAR & (1 << POS))
-#define SetBit(VAR,POS)                               (VAR |= (1 << POS))
-#define ClrBit(VAR,POS)                               (VAR &= ((1 << POS)^255))
-
-#define  LE16(addr)             (((uint16_t)(*((uint8_t *)(addr))))\
-                                + (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
-
-#define  LE16S(addr)              (uint16_t)(LE16((addr)))
-
-#define  LE32(addr)              ((((uint32_t)(*(((uint8_t *)(addr)) + 0))) + \
-                                              (((uint32_t)(*(((uint8_t *)(addr)) + 1))) << 8) + \
-                                              (((uint32_t)(*(((uint8_t *)(addr)) + 2))) << 16) + \
-                                              (((uint32_t)(*(((uint8_t *)(addr)) + 3))) << 24)))
-
-#define  LE64(addr)              ((((uint64_t)(*(((uint8_t *)(addr)) + 0))) + \
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 1))) <<  8) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 2))) << 16) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 3))) << 24) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 4))) << 32) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 5))) << 40) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 6))) << 48) +\
-                                              (((uint64_t)(*(((uint8_t *)(addr)) + 7))) << 56)))
-
-
-#define  LE24(addr)              ((((uint32_t)(*(((uint8_t *)(addr)) + 0))) + \
-                                              (((uint32_t)(*(((uint8_t *)(addr)) + 1))) << 8) + \
-                                              (((uint32_t)(*(((uint8_t *)(addr)) + 2))) << 16)))
-
-
-#define  LE32S(addr)              (int32_t)(LE32((addr)))
-
-
-
-#define  USB_LEN_DESC_HDR                               0x02
-#define  USB_LEN_DEV_DESC                               0x12
-#define  USB_LEN_CFG_DESC                               0x09
-#define  USB_LEN_IF_DESC                                0x09
-#define  USB_LEN_EP_DESC                                0x07
-#define  USB_LEN_OTG_DESC                               0x03
-#define  USB_LEN_SETUP_PKT                              0x08
-
-/* bmRequestType :D7 Data Phase Transfer Direction  */
-#define  USB_REQ_DIR_MASK                               0x80
-#define  USB_H2D                                        0x00
-#define  USB_D2H                                        0x80
-
-/* bmRequestType D6..5 Type */
-#define  USB_REQ_TYPE_STANDARD                          0x00
-#define  USB_REQ_TYPE_CLASS                             0x20
-#define  USB_REQ_TYPE_VENDOR                            0x40
-#define  USB_REQ_TYPE_RESERVED                          0x60
-
-/* bmRequestType D4..0 Recipient */
-#define  USB_REQ_RECIPIENT_DEVICE                       0x00
-#define  USB_REQ_RECIPIENT_INTERFACE                    0x01
-#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02
-#define  USB_REQ_RECIPIENT_OTHER                        0x03
-
-/* Table 9-4. Standard Request Codes  */
-/* bRequest , Value */
-#define  USB_REQ_GET_STATUS                             0x00
-#define  USB_REQ_CLEAR_FEATURE                          0x01
-#define  USB_REQ_SET_FEATURE                            0x03
-#define  USB_REQ_SET_ADDRESS                            0x05
-#define  USB_REQ_GET_DESCRIPTOR                         0x06
-#define  USB_REQ_SET_DESCRIPTOR                         0x07
-#define  USB_REQ_GET_CONFIGURATION                      0x08
-#define  USB_REQ_SET_CONFIGURATION                      0x09
-#define  USB_REQ_GET_INTERFACE                          0x0A
-#define  USB_REQ_SET_INTERFACE                          0x0B
-#define  USB_REQ_SYNCH_FRAME                            0x0C
-
-/* Table 9-5. Descriptor Types of USB Specifications */
-#define  USB_DESC_TYPE_DEVICE                              1
-#define  USB_DESC_TYPE_CONFIGURATION                       2
-#define  USB_DESC_TYPE_STRING                              3
-#define  USB_DESC_TYPE_INTERFACE                           4
-#define  USB_DESC_TYPE_ENDPOINT                            5
-#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    6
-#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           7
-#define  USB_DESC_TYPE_INTERFACE_POWER                     8
-#define  USB_DESC_TYPE_HID                                 0x21
-#define  USB_DESC_TYPE_HID_REPORT                          0x22
-
-
-#define USB_DEVICE_DESC_SIZE                               18
-#define USB_CONFIGURATION_DESC_SIZE                        9
-#define USB_HID_DESC_SIZE                                  9
-#define USB_INTERFACE_DESC_SIZE                            9
-#define USB_ENDPOINT_DESC_SIZE                             7
-
-/* Descriptor Type and Descriptor Index  */
-/* Use the following values when calling the function USBH_GetDescriptor  */
-#define  USB_DESC_DEVICE                    ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00)
-#define  USB_DESC_CONFIGURATION             ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00)
-#define  USB_DESC_STRING                    ((USB_DESC_TYPE_STRING << 8) & 0xFF00)
-#define  USB_DESC_INTERFACE                 ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
-#define  USB_DESC_ENDPOINT                  ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00)
-#define  USB_DESC_DEVICE_QUALIFIER          ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00)
-#define  USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00)
-#define  USB_DESC_INTERFACE_POWER           ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00)
-#define  USB_DESC_HID_REPORT                ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00)
-#define  USB_DESC_HID                       ((USB_DESC_TYPE_HID << 8) & 0xFF00)
-
-
-#define  USB_EP_TYPE_CTRL                               0x00
-#define  USB_EP_TYPE_ISOC                               0x01
-#define  USB_EP_TYPE_BULK                               0x02
-#define  USB_EP_TYPE_INTR                               0x03
-
-#define  USB_EP_DIR_OUT                                 0x00
-#define  USB_EP_DIR_IN                                  0x80
-#define  USB_EP_DIR_MSK                                 0x80  
-
-#ifndef USBH_MAX_PIPES_NBR
- #define USBH_MAX_PIPES_NBR                             15                                                
-#endif /* USBH_MAX_PIPES_NBR */
-
-#define USBH_DEVICE_ADDRESS_DEFAULT                     0
-#define USBH_MAX_ERROR_COUNT                            2
-#define USBH_DEVICE_ADDRESS                             1
-
-
-/**
-  * @}
-  */ 
-
-
-#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \
-                                           + USB_INTERFACE_DESC_SIZE\
-                                           + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE))
-
-
-#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\
-                                          ConfigurationDescriptor.wTotalLength)
-
-
-typedef union
-{
-  uint16_t w;
-  struct BW
-  {
-    uint8_t msb;
-    uint8_t lsb;
-  }
-  bw;
-}
-uint16_t_uint8_t;
-
-
-typedef union _USB_Setup
-{
-  uint32_t d8[2];
-  
-  struct _SetupPkt_Struc
-  {
-    uint8_t           bmRequestType;
-    uint8_t           bRequest;
-    uint16_t_uint8_t  wValue;
-    uint16_t_uint8_t  wIndex;
-    uint16_t_uint8_t  wLength;
-  } b;
-} 
-USB_Setup_TypeDef;  
-
-typedef  struct  _DescHeader 
-{
-    uint8_t  bLength;       
-    uint8_t  bDescriptorType;
-} 
-USBH_DescHeader_t;
-
-typedef struct _DeviceDescriptor
-{
-  uint8_t   bLength;
-  uint8_t   bDescriptorType;
-  uint16_t  bcdUSB;        /* USB Specification Number which device complies too */
-  uint8_t   bDeviceClass;
-  uint8_t   bDeviceSubClass; 
-  uint8_t   bDeviceProtocol;
-  /* If equal to Zero, each interface specifies its own class
-  code if equal to 0xFF, the class code is vendor specified.
-  Otherwise field is valid Class Code.*/
-  uint8_t   bMaxPacketSize;
-  uint16_t  idVendor;      /* Vendor ID (Assigned by USB Org) */
-  uint16_t  idProduct;     /* Product ID (Assigned by Manufacturer) */
-  uint16_t  bcdDevice;     /* Device Release Number */
-  uint8_t   iManufacturer;  /* Index of Manufacturer String Descriptor */
-  uint8_t   iProduct;       /* Index of Product String Descriptor */
-  uint8_t   iSerialNumber;  /* Index of Serial Number String Descriptor */
-  uint8_t   bNumConfigurations; /* Number of Possible Configurations */
-}
-USBH_DevDescTypeDef;
-
-typedef struct _EndpointDescriptor
-{
-  uint8_t   bLength;
-  uint8_t   bDescriptorType;
-  uint8_t   bEndpointAddress;   /* indicates what endpoint this descriptor is describing */
-  uint8_t   bmAttributes;       /* specifies the transfer type. */
-  uint16_t  wMaxPacketSize;    /* Maximum Packet Size this endpoint is capable of sending or receiving */  
-  uint8_t   bInterval;          /* is used to specify the polling interval of certain transfers. */
-}
-USBH_EpDescTypeDef;
-
-typedef struct _InterfaceDescriptor
-{
-  uint8_t bLength;
-  uint8_t bDescriptorType;
-  uint8_t bInterfaceNumber;
-  uint8_t bAlternateSetting;    /* Value used to select alternative setting */
-  uint8_t bNumEndpoints;        /* Number of Endpoints used for this interface */
-  uint8_t bInterfaceClass;      /* Class Code (Assigned by USB Org) */
-  uint8_t bInterfaceSubClass;   /* Subclass Code (Assigned by USB Org) */
-  uint8_t bInterfaceProtocol;   /* Protocol Code */
-  uint8_t iInterface;           /* Index of String Descriptor Describing this interface */
-  USBH_EpDescTypeDef               Ep_Desc[USBH_MAX_NUM_ENDPOINTS];   
-}
-USBH_InterfaceDescTypeDef;
-
-
-typedef struct _ConfigurationDescriptor
-{
-  uint8_t   bLength;
-  uint8_t   bDescriptorType;
-  uint16_t  wTotalLength;        /* Total Length of Data Returned */
-  uint8_t   bNumInterfaces;       /* Number of Interfaces */
-  uint8_t   bConfigurationValue;  /* Value to use as an argument to select this configuration*/
-  uint8_t   iConfiguration;       /*Index of String Descriptor Describing this configuration */
-  uint8_t   bmAttributes;         /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/
-  uint8_t   bMaxPower;            /*Maximum Power Consumption */
-  USBH_InterfaceDescTypeDef        Itf_Desc[USBH_MAX_NUM_INTERFACES];
-}
-USBH_CfgDescTypeDef;
-
-
-/* Following USB Host status */
-typedef enum 
-{
-  USBH_OK   = 0,
-  USBH_BUSY,
-  USBH_FAIL,
-  USBH_NOT_SUPPORTED,
-  USBH_UNRECOVERED_ERROR,
-  USBH_ERROR_SPEED_UNKNOWN,
-}USBH_StatusTypeDef;
-
-
-/** @defgroup USBH_CORE_Exported_Types
-  * @{
-  */
-
-typedef enum 
-{
-  USBH_SPEED_HIGH  = 0,
-  USBH_SPEED_FULL  = 1,
-  USBH_SPEED_LOW   = 2,  
-    
-}USBH_SpeedTypeDef;
-
-/* Following states are used for gState */
-typedef enum 
-{
-  HOST_IDLE =0,
-  HOST_DEV_WAIT_FOR_ATTACHMENT,  
-  HOST_DEV_ATTACHED,
-  HOST_DEV_DISCONNECTED,  
-  HOST_DETECT_DEVICE_SPEED,
-  HOST_ENUMERATION,
-  HOST_CLASS_REQUEST,  
-  HOST_INPUT,
-  HOST_SET_CONFIGURATION,
-  HOST_CHECK_CLASS,
-  HOST_CLASS,
-  HOST_SUSPENDED,
-  HOST_ABORT_STATE,  
-}HOST_StateTypeDef;  
-
-/* Following states are used for EnumerationState */
-typedef enum 
-{
-  ENUM_IDLE = 0,
-  ENUM_GET_FULL_DEV_DESC,
-  ENUM_SET_ADDR,
-  ENUM_GET_CFG_DESC,
-  ENUM_GET_FULL_CFG_DESC,
-  ENUM_GET_MFC_STRING_DESC,
-  ENUM_GET_PRODUCT_STRING_DESC,
-  ENUM_GET_SERIALNUM_STRING_DESC,
-} ENUM_StateTypeDef;  
-
-/* Following states are used for CtrlXferStateMachine */
-typedef enum 
-{
-  CTRL_IDLE =0,
-  CTRL_SETUP,
-  CTRL_SETUP_WAIT,
-  CTRL_DATA_IN,
-  CTRL_DATA_IN_WAIT,
-  CTRL_DATA_OUT,
-  CTRL_DATA_OUT_WAIT,
-  CTRL_STATUS_IN,
-  CTRL_STATUS_IN_WAIT,
-  CTRL_STATUS_OUT,
-  CTRL_STATUS_OUT_WAIT,
-  CTRL_ERROR,
-  CTRL_STALLED,
-  CTRL_COMPLETE    
-}CTRL_StateTypeDef;  
-
-
-/* Following states are used for RequestState */
-typedef enum 
-{
-  CMD_IDLE =0,
-  CMD_SEND,
-  CMD_WAIT
-} CMD_StateTypeDef;  
-
-typedef enum {
-  USBH_URB_IDLE = 0,
-  USBH_URB_DONE,
-  USBH_URB_NOTREADY,
-  USBH_URB_NYET,  
-  USBH_URB_ERROR,
-  USBH_URB_STALL
-}USBH_URBStateTypeDef;
-
-typedef enum
-{
-  USBH_PORT_EVENT = 1,  
-  USBH_URB_EVENT,
-  USBH_CONTROL_EVENT,    
-  USBH_CLASS_EVENT,     
-  USBH_STATE_CHANGED_EVENT,   
-}
-USBH_OSEventTypeDef;
-
-/* Control request structure */
-typedef struct 
-{
-  uint8_t               pipe_in; 
-  uint8_t               pipe_out; 
-  uint8_t               pipe_size;  
-  uint8_t               *buff;
-  uint16_t              length;
-  uint16_t              timer;  
-  USB_Setup_TypeDef     setup;
-  CTRL_StateTypeDef     state;  
-  uint8_t               errorcount;  
-
-} USBH_CtrlTypeDef;
-
-/* Attached device structure */
-typedef struct
-{
-#if (USBH_KEEP_CFG_DESCRIPTOR == 1)  
-  uint8_t                           CfgDesc_Raw[USBH_MAX_SIZE_CONFIGURATION];
-#endif  
-  uint8_t                           Data[USBH_MAX_DATA_BUFFER];
-  uint8_t                           address;
-  uint8_t                           speed;
-  __IO uint8_t                      is_connected;    
-  uint8_t                           current_interface;   
-  USBH_DevDescTypeDef               DevDesc;
-  USBH_CfgDescTypeDef               CfgDesc; 
-  
-}USBH_DeviceTypeDef;
-
-struct _USBH_HandleTypeDef;
-
-/* USB Host Class structure */
-typedef struct 
-{
-  const char          *Name;
-  uint8_t              ClassCode;  
-  USBH_StatusTypeDef  (*Init)        (struct _USBH_HandleTypeDef *phost);
-  USBH_StatusTypeDef  (*DeInit)      (struct _USBH_HandleTypeDef *phost);
-  USBH_StatusTypeDef  (*Requests)    (struct _USBH_HandleTypeDef *phost);  
-  USBH_StatusTypeDef  (*BgndProcess) (struct _USBH_HandleTypeDef *phost);
-  USBH_StatusTypeDef  (*SOFProcess) (struct _USBH_HandleTypeDef *phost);  
-  void*                pData;
-} USBH_ClassTypeDef;
-
-/* USB Host handle structure */
-typedef struct _USBH_HandleTypeDef
-{
-  __IO HOST_StateTypeDef     gState;       /*  Host State Machine Value */
-  ENUM_StateTypeDef     EnumState;    /* Enumeration state Machine */
-  CMD_StateTypeDef      RequestState;       
-  USBH_CtrlTypeDef      Control;
-  USBH_DeviceTypeDef    device;
-  USBH_ClassTypeDef*    pClass[USBH_MAX_NUM_SUPPORTED_CLASS];
-  USBH_ClassTypeDef*    pActiveClass;
-  uint32_t              ClassNumber;
-  uint32_t              Pipes[15];
-  __IO uint32_t         Timer;
-  uint8_t               id;  
-  void*                 pData;                  
-  void                 (* pUser )(struct _USBH_HandleTypeDef *pHandle, uint8_t id);
-  
-#if (USBH_USE_OS == 1)
-  osMessageQId          os_event;   
-  osThreadId            thread; 
-#endif  
-  
-} USBH_HandleTypeDef;
-
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* USBH_DEF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h
deleted file mode 100644
index 2cd4a193..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_ioreq.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_ioreq.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_ioreq.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_IOREQ_H
-#define __USBH_IOREQ_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_conf.h"
-#include "usbh_core.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_IOREQ
-  * @brief This file is the header file for usbh_ioreq.c
-  * @{
-  */ 
-
-
-/** @defgroup USBH_IOREQ_Exported_Defines
-  * @{
-  */
-    
-#define USBH_PID_SETUP                            0
-#define USBH_PID_DATA                             1
-
-#define USBH_EP_CONTROL                           0
-#define USBH_EP_ISO                               1
-#define USBH_EP_BULK                              2
-#define USBH_EP_INTERRUPT                         3
-
-#define USBH_SETUP_PKT_SIZE                       8
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_IOREQ_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_IOREQ_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_IOREQ_Exported_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype
-  * @{
-  */
-USBH_StatusTypeDef USBH_CtlSendSetup (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint8_t hc_num);
-
-USBH_StatusTypeDef USBH_CtlSendData (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t hc_num,
-                                uint8_t do_ping );
-
-USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t hc_num);
-
-USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t hc_num);
-
-USBH_StatusTypeDef USBH_BulkSendData (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t hc_num,
-                                uint8_t do_ping );
-
-USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost, 
-                                       uint8_t             *buff, 
-                                       uint8_t             length,
-                                       uint8_t             hc_num);
-
-USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost, 
-                                    uint8_t *buff, 
-                                    uint8_t length,
-                                    uint8_t hc_num);
-
-
-USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint32_t length,
-                                uint8_t hc_num);
-
-
-USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint32_t length,
-                                uint8_t hc_num);
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBH_IOREQ_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h
deleted file mode 100644
index 5ba4aa13..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_pipes.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_pipes.h
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   Header file for usbh_pipes.c
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive  ----------------------------------------------*/
-#ifndef __USBH_PIPES_H
-#define __USBH_PIPES_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_PIPES
-  * @brief This file is the header file for usbh_pipes.c
-  * @{
-  */ 
-
-/** @defgroup USBH_PIPES_Exported_Defines
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_PIPES_Exported_Types
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_PIPES_Exported_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_PIPES_Exported_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_PIPES_Exported_FunctionsPrototype
-  * @{
-  */
-
-USBH_StatusTypeDef USBH_OpenPipe  (USBH_HandleTypeDef *phost,
-                            uint8_t ch_num,
-                            uint8_t epnum,                            
-                            uint8_t dev_address,
-                            uint8_t speed,
-                            uint8_t ep_type,
-                            uint16_t mps);
-
-USBH_StatusTypeDef USBH_ClosePipe  (USBH_HandleTypeDef *phost,
-                            uint8_t pipe_num);
-
-uint8_t USBH_AllocPipe  (USBH_HandleTypeDef *phost, 
-                         uint8_t ep_addr);
-
-USBH_StatusTypeDef USBH_FreePipe  (USBH_HandleTypeDef *phost, 
-                                   uint8_t idx);
-
-
-
-
-/**
-  * @}
-  */ 
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USBH_PIPES_H */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_conf_template.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_conf_template.c
deleted file mode 100644
index 611b2fd1..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_conf_template.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usb_bsp.c
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements the board support package for the USB host library
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_core.h"
-
-/**
-  * @brief  USBH_LL_Init 
-  *         Initialize the Low Level portion of the Host driver.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_LL_Init (USBH_HandleTypeDef *phost)
-{
-
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_LL_DeInit 
-  *         De-Initialize the Low Level portion of the Host driver.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_LL_DeInit (USBH_HandleTypeDef *phost)
-{
-
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_Start 
-  *         Start the Low Level portion of the Host driver.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_LL_Start(USBH_HandleTypeDef *phost)
-{
-
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_Stop 
-  *         Stop the Low Level portion of the Host driver.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_LL_Stop (USBH_HandleTypeDef *phost)
-{
-
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_GetSpeed 
-  *         Return the USB Host Speed from the Low Level Driver.
-  * @param  phost: Host handle
-  * @retval USBH Speeds
-  */
-USBH_SpeedTypeDef USBH_LL_GetSpeed  (USBH_HandleTypeDef *phost)
-{
-  USBH_SpeedTypeDef speed = USBH_SPEED_FULL;
-    
-
-  return  speed;
-}
-
-/**
-  * @brief  USBH_LL_ResetPort 
-  *         Reset the Host Port of the Low Level Driver.
-  * @param  phost: Host handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_LL_ResetPort (USBH_HandleTypeDef *phost) 
-{
-
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_GetLastXferSize 
-  *         Return the last transferred packet size.
-  * @param  phost: Host handle
-  * @param  pipe: Pipe index   
-  * @retval Packet Size
-  */
-uint32_t USBH_LL_GetLastXferSize  (USBH_HandleTypeDef *phost, uint8_t pipe)  
-{
-   return 0; 
-}
-
-/**
-  * @brief  USBH_LL_OpenPipe 
-  *         Open a pipe of the Low Level Driver.
-  * @param  phost: Host handle
-  * @param  pipe_num: Pipe index
-  * @param  epnum: Endpoint Number
-  * @param  dev_address: Device USB address
-  * @param  speed: Device Speed 
-  * @param  ep_type: Endpoint Type
-  * @param  mps: Endpoint Max Packet Size                 
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef   USBH_LL_OpenPipe (USBH_HandleTypeDef *phost, 
-                                      uint8_t pipe_num,
-                                      uint8_t epnum,                                      
-                                      uint8_t dev_address,
-                                      uint8_t speed,
-                                      uint8_t ep_type,
-                                      uint16_t mps)
-{
- 
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_ClosePipe 
-  *         Close a pipe of the Low Level Driver.
-  * @param  phost: Host handle
-  * @param  pipe_num: Pipe index               
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef   USBH_LL_ClosePipe   (USBH_HandleTypeDef *phost, uint8_t pipe)   
-{
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_SubmitURB 
-  *         Submit a new URB to the low level driver.
-  * @param  phost: Host handle
-  * @param  pipe: Pipe index    
-  *         This parameter can be a value from 1 to 15
-  * @param  direction : Channel number
-  *          This parameter can be one of the these values:
-  *           0 : Output 
-  *           1 : Input
-  * @param  ep_type : Endpoint Type
-  *          This parameter can be one of the these values:
-  *            @arg EP_TYPE_CTRL: Control type
-  *            @arg EP_TYPE_ISOC: Isochronous type
-  *            @arg EP_TYPE_BULK: Bulk type
-  *            @arg EP_TYPE_INTR: Interrupt type
-  * @param  token : Endpoint Type
-  *          This parameter can be one of the these values:
-  *            @arg 0: PID_SETUP
-  *            @arg 1: PID_DATA
-  * @param  pbuff : pointer to URB data
-  * @param  length : Length of URB data
-  * @param  do_ping : activate do ping protocol (for high speed only)
-  *          This parameter can be one of the these values:
-  *           0 : do ping inactive 
-  *           1 : do ping active 
-  * @retval Status
-  */
-
-USBH_StatusTypeDef   USBH_LL_SubmitURB  (USBH_HandleTypeDef *phost, 
-                                            uint8_t pipe, 
-                                            uint8_t direction ,
-                                            uint8_t ep_type,  
-                                            uint8_t token, 
-                                            uint8_t* pbuff, 
-                                            uint16_t length,
-                                            uint8_t do_ping ) 
-{
-
-  return USBH_OK;   
-}
-
-/**
-  * @brief  USBH_LL_GetURBState 
-  *         Get a URB state from the low level driver.
-  * @param  phost: Host handle
-  * @param  pipe: Pipe index
-  *         This parameter can be a value from 1 to 15
-  * @retval URB state
-  *          This parameter can be one of the these values:
-  *            @arg URB_IDLE
-  *            @arg URB_DONE
-  *            @arg URB_NOTREADY
-  *            @arg URB_NYET 
-  *            @arg URB_ERROR  
-  *            @arg URB_STALL      
-  */
-USBH_URBStateTypeDef  USBH_LL_GetURBState (USBH_HandleTypeDef *phost, uint8_t pipe) 
-{
-  return USBH_URB_IDLE; 
-}
-
-/**
-  * @brief  USBH_LL_DriverVBUS 
-  *         Drive VBUS.
-  * @param  phost: Host handle
-  * @param  state : VBUS state
-  *          This parameter can be one of the these values:
-  *           0 : VBUS Active 
-  *           1 : VBUS Inactive
-  * @retval Status
-  */
-
-USBH_StatusTypeDef  USBH_LL_DriverVBUS (USBH_HandleTypeDef *phost, uint8_t state)
-{
-
-  return USBH_OK;  
-}
-
-/**
-  * @brief  USBH_LL_SetToggle 
-  *         Set toggle for a pipe.
-  * @param  phost: Host handle
-  * @param  pipe: Pipe index
-  * @param  pipe_num: Pipe index     
-  * @param  toggle: toggle (0/1)
-  * @retval Status
-  */
-USBH_StatusTypeDef   USBH_LL_SetToggle   (USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle)   
-{
-
-  return USBH_OK; 
-}
-
-/**
-  * @brief  USBH_LL_GetToggle 
-  *         Return the current toggle of a pipe.
-  * @param  phost: Host handle
-  * @param  pipe: Pipe index
-  * @retval toggle (0/1)
-  */
-uint8_t  USBH_LL_GetToggle   (USBH_HandleTypeDef *phost, uint8_t pipe)   
-{
-  uint8_t toggle = 0;
-  
-
-  return toggle; 
-}
-/**
-  * @brief  USBH_Delay 
-  *         Delay routine for the USB Host Library
-  * @param  Delay: Delay in ms
-  * @retval None
-  */
-void  USBH_Delay (uint32_t Delay)
-{
-
-}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c
deleted file mode 100644
index 4ba78458..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c
+++ /dev/null
@@ -1,933 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_core.c 
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements the functions for the core state machine process
-  *          the enumeration and the control transfer process
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_core.h"
-
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-  * @{
-  */
-
-/** @defgroup USBH_CORE 
-  * @brief This file handles the basic enumeration when a device is connected 
-  *          to the host.
-  * @{
-  */ 
-
-
-/** @defgroup USBH_CORE_Private_Defines
-  * @{
-  */ 
-#define USBH_ADDRESS_DEFAULT                     0
-#define USBH_ADDRESS_ASSIGNED                    1      
-#define USBH_MPS_DEFAULT                         0x40
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_CORE_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_CORE_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
- 
-
-/** @defgroup USBH_CORE_Private_Functions
-  * @{
-  */ 
-static USBH_StatusTypeDef  USBH_HandleEnum    (USBH_HandleTypeDef *phost);
-static void                USBH_HandleSof     (USBH_HandleTypeDef *phost);
-static USBH_StatusTypeDef  DeInitStateMachine(USBH_HandleTypeDef *phost);
-
-#if (USBH_USE_OS == 1)  
-static void USBH_Process_OS(void const * argument);
-#endif
-
-/**
-  * @brief  HCD_Init 
-  *         Initialize the HOST Core.
-  * @param  phost: Host Handle
-  * @param  pUsrFunc: User Callback
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_Init(USBH_HandleTypeDef *phost, void (*pUsrFunc)(USBH_HandleTypeDef *phost, uint8_t ), uint8_t id)
-{
-  /* Check whether the USB Host handle is valid */
-  if(phost == NULL)
-  {
-    USBH_ErrLog("Invalid Host handle");
-    return USBH_FAIL; 
-  }
-  
-  /* Set DRiver ID */
-  phost->id = id;
-  
-  /* Unlink class*/
-  phost->pActiveClass = NULL;
-  phost->ClassNumber = 0;
-  
-  /* Restore default states and prepare EP0 */ 
-  DeInitStateMachine(phost);
-  
-  /* Assign User process */
-  if(pUsrFunc != NULL)
-  {
-    phost->pUser = pUsrFunc;
-  }
-  
-#if (USBH_USE_OS == 1) 
-  
-  /* Create USB Host Queue */
-  osMessageQDef(USBH_Queue, 10, uint16_t);
-  phost->os_event = osMessageCreate (osMessageQ(USBH_Queue), NULL); 
-  
-  /*Create USB Host Task */
-#if defined (USBH_PROCESS_STACK_SIZE)
-  osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0, USBH_PROCESS_STACK_SIZE);
-#else
-  osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0, 8 * configMINIMAL_STACK_SIZE);
-#endif  
-  phost->thread = osThreadCreate (osThread(USBH_Thread), phost);
-#endif  
-  
-  /* Initialize low level driver */
-  USBH_LL_Init(phost);
-  return USBH_OK;
-}
-
-/**
-  * @brief  HCD_Init 
-  *         De-Initialize the Host portion of the driver.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_DeInit(USBH_HandleTypeDef *phost)
-{
-  DeInitStateMachine(phost);
-  
-  if(phost->pData != NULL)
-  {
-    phost->pActiveClass->pData = NULL;
-    USBH_LL_Stop(phost);
-  }
-
-  return USBH_OK;
-}
-
-/**
-  * @brief  DeInitStateMachine 
-  *         De-Initialize the Host state machine.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef  DeInitStateMachine(USBH_HandleTypeDef *phost)
-{
-  uint32_t i = 0;
-
-  /* Clear Pipes flags*/
-  for ( ; i < USBH_MAX_PIPES_NBR; i++)
-  {
-    phost->Pipes[i] = 0;
-  }
-  
-  for(i = 0; i< USBH_MAX_DATA_BUFFER; i++)
-  {
-    phost->device.Data[i] = 0;
-  }
-  
-  phost->gState = HOST_IDLE;
-  phost->EnumState = ENUM_IDLE;
-  phost->RequestState = CMD_SEND;
-  phost->Timer = 0;  
-  
-  phost->Control.state = CTRL_SETUP;
-  phost->Control.pipe_size = USBH_MPS_DEFAULT;  
-  phost->Control.errorcount = 0;
-  
-  phost->device.address = USBH_ADDRESS_DEFAULT;
-  phost->device.speed   = USBH_SPEED_FULL;
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_RegisterClass 
-  *         Link class driver to Host Core.
-  * @param  phost : Host Handle
-  * @param  pclass: Class handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass)
-{
-  USBH_StatusTypeDef   status = USBH_OK;
-  
-  if(pclass != 0)
-  {
-    if(phost->ClassNumber < USBH_MAX_NUM_SUPPORTED_CLASS)
-    {
-      /* link the class to the USB Host handle */
-      phost->pClass[phost->ClassNumber++] = pclass;
-      status = USBH_OK;
-    }
-    else
-    {
-      USBH_ErrLog("Max Class Number reached");
-      status = USBH_FAIL; 
-    }
-  }
-  else
-  {
-    USBH_ErrLog("Invalid Class handle");
-    status = USBH_FAIL; 
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  USBH_SelectInterface 
-  *         Select current interface.
-  * @param  phost: Host Handle
-  * @param  interface: Interface number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface)
-{
-  USBH_StatusTypeDef   status = USBH_OK;
-  
-  if(interface < phost->device.CfgDesc.bNumInterfaces)
-  {
-    phost->device.current_interface = interface;
-    USBH_UsrLog ("Switching to Interface (#%d)", interface);
-    USBH_UsrLog ("Class    : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceClass );
-    USBH_UsrLog ("SubClass : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceSubClass );
-    USBH_UsrLog ("Protocol : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceProtocol );                 
-  }
-  else
-  {
-    USBH_ErrLog ("Cannot Select This Interface.");
-    status = USBH_FAIL; 
-  }
-  return status;  
-}
-
-/**
-  * @brief  USBH_GetActiveClass 
-  *         Return Device Class.
-  * @param  phost: Host Handle
-  * @param  interface: Interface index
-  * @retval Class Code
-  */
-uint8_t USBH_GetActiveClass(USBH_HandleTypeDef *phost)
-{
-   return (phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass);            
-}
-/**
-  * @brief  USBH_FindInterface 
-  *         Find the interface index for a specific class.
-  * @param  phost: Host Handle
-  * @param  Class: Class code
-  * @param  SubClass: SubClass code
-  * @param  Protocol: Protocol code
-  * @retval interface index in the configuration structure
-  * @note : (1)interface index 0xFF means interface index not found
-  */
-uint8_t  USBH_FindInterface(USBH_HandleTypeDef *phost, uint8_t Class, uint8_t SubClass, uint8_t Protocol)
-{
-  USBH_InterfaceDescTypeDef    *pif ;
-  USBH_CfgDescTypeDef          *pcfg ;
-  int8_t                        if_ix = 0;
-  
-  pif = (USBH_InterfaceDescTypeDef *)0;
-  pcfg = &phost->device.CfgDesc;  
-  
-  while (if_ix < USBH_MAX_NUM_INTERFACES)
-  {
-    pif = &pcfg->Itf_Desc[if_ix];
-    if(((pif->bInterfaceClass == Class) || (Class == 0xFF))&&
-       ((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFF))&&
-         ((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFF)))
-    {
-      return  if_ix;
-    }
-    if_ix++;
-  }
-  return 0xFF;
-}
-
-/**
-  * @brief  USBH_FindInterfaceIndex 
-  *         Find the interface index for a specific class interface and alternate setting number.
-  * @param  phost: Host Handle
-  * @param  interface_number: interface number
-  * @param  alt_settings    : alternate setting number
-  * @retval interface index in the configuration structure
-  * @note : (1)interface index 0xFF means interface index not found
-  */
-uint8_t  USBH_FindInterfaceIndex(USBH_HandleTypeDef *phost, uint8_t interface_number, uint8_t alt_settings)
-{
-  USBH_InterfaceDescTypeDef    *pif ;
-  USBH_CfgDescTypeDef          *pcfg ;
-  int8_t                        if_ix = 0;
-  
-  pif = (USBH_InterfaceDescTypeDef *)0;
-  pcfg = &phost->device.CfgDesc;  
-  
-  while (if_ix < USBH_MAX_NUM_INTERFACES)
-  {
-    pif = &pcfg->Itf_Desc[if_ix];
-    if((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings))
-    {
-      return  if_ix;
-    }
-    if_ix++;
-  }
-  return 0xFF;
-}
-
-/**
-  * @brief  USBH_Start 
-  *         Start the USB Host Core.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_Start  (USBH_HandleTypeDef *phost)
-{
-  /* Start the low level driver  */
-  USBH_LL_Start(phost);
-  
-  /* Activate VBUS on the port */ 
-  USBH_LL_DriverVBUS (phost, TRUE);
-  
-  return USBH_OK;  
-}
-
-/**
-  * @brief  USBH_Stop 
-  *         Stop the USB Host Core.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_Stop   (USBH_HandleTypeDef *phost)
-{
-  /* Stop and cleanup the low level driver  */
-  USBH_LL_Stop(phost);  
-  
-  /* DeActivate VBUS on the port */ 
-  USBH_LL_DriverVBUS (phost, FALSE);
-  
-  /* FRee Control Pipes */
-  USBH_FreePipe  (phost, phost->Control.pipe_in);
-  USBH_FreePipe  (phost, phost->Control.pipe_out);  
-  
-  return USBH_OK;  
-}
-
-/**
-  * @brief  HCD_ReEnumerate 
-  *         Perform a new Enumeration phase.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_ReEnumerate   (USBH_HandleTypeDef *phost)
-{
-  /*Stop Host */ 
-  USBH_Stop(phost);
-
-  /*Device has disconnected, so wait for 200 ms */  
-  USBH_Delay(200);
-  
-  /* Set State machines in default state */
-  DeInitStateMachine(phost);
-   
-  /* Start again the host */
-  USBH_Start(phost);
-      
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_PORT_EVENT, 0);
-#endif  
-  return USBH_OK;  
-}
-
-/**
-  * @brief  USBH_Process 
-  *         Background process of the USB Core.
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef  USBH_Process(USBH_HandleTypeDef *phost)
-{
-  __IO USBH_StatusTypeDef status = USBH_FAIL;
-  uint8_t idx = 0;
-  
-  switch (phost->gState)
-  {
-  case HOST_IDLE :
-    
-    if (phost->device.is_connected)  
-    {
-      /* Wait for 200 ms after connection */
-      phost->gState = HOST_DEV_WAIT_FOR_ATTACHMENT; 
-      USBH_Delay(200); 
-      USBH_LL_ResetPort(phost);
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_PORT_EVENT, 0);
-#endif
-    }
-    break;
-    
-  case HOST_DEV_WAIT_FOR_ATTACHMENT:
-    break;    
-    
-  case HOST_DEV_ATTACHED :
-    
-    USBH_UsrLog("USB Device Attached");  
-      
-    /* Wait for 100 ms after Reset */
-    USBH_Delay(100); 
-          
-    phost->device.speed = USBH_LL_GetSpeed(phost);
-    
-    phost->gState = HOST_ENUMERATION;
-    
-    phost->Control.pipe_out = USBH_AllocPipe (phost, 0x00);
-    phost->Control.pipe_in  = USBH_AllocPipe (phost, 0x80);    
-    
-    
-    /* Open Control pipes */
-    USBH_OpenPipe (phost,
-                   phost->Control.pipe_in,
-                   0x80,
-                   phost->device.address,
-                   phost->device.speed,
-                   USBH_EP_CONTROL,
-                   phost->Control.pipe_size); 
-    
-    /* Open Control pipes */
-    USBH_OpenPipe (phost,
-                   phost->Control.pipe_out,
-                   0x00,
-                   phost->device.address,
-                   phost->device.speed,
-                   USBH_EP_CONTROL,
-                   phost->Control.pipe_size);
-    
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_PORT_EVENT, 0);
-#endif    
-    
-    break;
-    
-  case HOST_ENUMERATION:     
-    /* Check for enumeration status */  
-    if ( USBH_HandleEnum(phost) == USBH_OK)
-    { 
-      /* The function shall return USBH_OK when full enumeration is complete */
-      USBH_UsrLog ("Enumeration done.");
-      phost->device.current_interface = 0;
-      if(phost->device.DevDesc.bNumConfigurations == 1)
-      {
-        USBH_UsrLog ("This device has only 1 configuration.");
-        phost->gState  = HOST_SET_CONFIGURATION;        
-        
-      }
-      else
-      {
-        phost->gState  = HOST_INPUT; 
-      }
-          
-    }
-    break;
-    
-  case HOST_INPUT:
-    {
-      /* user callback for end of device basic enumeration */
-      if(phost->pUser != NULL)
-      {
-        phost->pUser(phost, HOST_USER_SELECT_CONFIGURATION);
-        phost->gState = HOST_SET_CONFIGURATION;
-        
-#if (USBH_USE_OS == 1)
-        osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif         
-      }
-    }
-    break;
-    
-  case HOST_SET_CONFIGURATION:
-    /* set configuration */
-    if (USBH_SetCfg(phost, phost->device.CfgDesc.bConfigurationValue) == USBH_OK)
-    {
-      phost->gState  = HOST_CHECK_CLASS;
-      USBH_UsrLog ("Default configuration set.");
-      
-    }      
-    
-    break;
-    
-  case HOST_CHECK_CLASS:
-    
-    if(phost->ClassNumber == 0)
-    {
-      USBH_UsrLog ("No Class has been registered.");
-    }
-    else
-    {
-      phost->pActiveClass = NULL;
-      
-      for (idx = 0; idx < USBH_MAX_NUM_SUPPORTED_CLASS ; idx ++)
-      {
-        if(phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass)
-        {
-          phost->pActiveClass = phost->pClass[idx];
-        }
-      }
-      
-      if(phost->pActiveClass != NULL)
-      {
-        if(phost->pActiveClass->Init(phost)== USBH_OK)
-        {
-          phost->gState  = HOST_CLASS_REQUEST; 
-          USBH_UsrLog ("%s class started.", phost->pActiveClass->Name);
-          
-          /* Inform user that a class has been activated */
-          phost->pUser(phost, HOST_USER_CLASS_SELECTED);   
-        }
-        else
-        {
-          phost->gState  = HOST_ABORT_STATE;
-          USBH_UsrLog ("Device not supporting %s class.", phost->pActiveClass->Name);
-        }
-      }
-      else
-      {
-        phost->gState  = HOST_ABORT_STATE;
-        USBH_UsrLog ("No registered class for this device.");
-      }
-    }
-    
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif 
-    break;    
-    
-  case HOST_CLASS_REQUEST:  
-    /* process class standard control requests state machine */
-    if(phost->pActiveClass != NULL)
-    {
-      status = phost->pActiveClass->Requests(phost);
-      
-      if(status == USBH_OK)
-      {
-        phost->gState  = HOST_CLASS;        
-      }  
-    }
-    else
-    {
-      phost->gState  = HOST_ABORT_STATE;
-      USBH_ErrLog ("Invalid Class Driver.");
-    
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif       
-    }
-    
-    break;    
-  case HOST_CLASS:   
-    /* process class state machine */
-    if(phost->pActiveClass != NULL)
-    { 
-      phost->pActiveClass->BgndProcess(phost);
-    }
-    break;       
-
-  case HOST_DEV_DISCONNECTED :
-    
-    DeInitStateMachine(phost);  
-    
-    /* Re-Initilaize Host for new Enumeration */
-    if(phost->pActiveClass != NULL)
-    {
-      phost->pActiveClass->DeInit(phost); 
-      phost->pActiveClass = NULL;
-    }     
-    break;
-    
-  case HOST_ABORT_STATE:
-  default :
-    break;
-  }
- return USBH_OK;  
-}
-
-
-/**
-  * @brief  USBH_HandleEnum 
-  *         This function includes the complete enumeration process
-  * @param  phost: Host Handle
-  * @retval USBH_Status
-  */
-static USBH_StatusTypeDef USBH_HandleEnum (USBH_HandleTypeDef *phost)
-{
-  USBH_StatusTypeDef Status = USBH_BUSY;  
-  
-  switch (phost->EnumState)
-  {
-  case ENUM_IDLE:  
-    /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */
-    if ( USBH_Get_DevDesc(phost, 8) == USBH_OK)
-    {
-      phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize;
-
-      phost->EnumState = ENUM_GET_FULL_DEV_DESC;
-      
-      /* modify control channels configuration for MaxPacket size */
-      USBH_OpenPipe (phost,
-                           phost->Control.pipe_in,
-                           0x80,
-                           phost->device.address,
-                           phost->device.speed,
-                           USBH_EP_CONTROL,
-                           phost->Control.pipe_size); 
-      
-      /* Open Control pipes */
-      USBH_OpenPipe (phost,
-                           phost->Control.pipe_out,
-                           0x00,
-                           phost->device.address,
-                           phost->device.speed,
-                           USBH_EP_CONTROL,
-                           phost->Control.pipe_size);           
-      
-    }
-    break;
-    
-  case ENUM_GET_FULL_DEV_DESC:  
-    /* Get FULL Device Desc  */
-    if ( USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE)== USBH_OK)
-    {
-      USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct );  
-      USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor );  
-      
-      phost->EnumState = ENUM_SET_ADDR;
-       
-    }
-    break;
-   
-  case ENUM_SET_ADDR: 
-    /* set address */
-    if ( USBH_SetAddress(phost, USBH_DEVICE_ADDRESS) == USBH_OK)
-    {
-      USBH_Delay(2);
-      phost->device.address = USBH_DEVICE_ADDRESS;
-      
-      /* user callback for device address assigned */
-      USBH_UsrLog("Address (#%d) assigned.", phost->device.address);
-      phost->EnumState = ENUM_GET_CFG_DESC;
-      
-      /* modify control channels to update device address */
-      USBH_OpenPipe (phost,
-                           phost->Control.pipe_in,
-                           0x80,
-                           phost->device.address,
-                           phost->device.speed,
-                           USBH_EP_CONTROL,
-                           phost->Control.pipe_size); 
-      
-      /* Open Control pipes */
-      USBH_OpenPipe (phost,
-                           phost->Control.pipe_out,
-                           0x00,
-                           phost->device.address,
-                           phost->device.speed,
-                           USBH_EP_CONTROL,
-                           phost->Control.pipe_size);        
-    }
-    break;
-    
-  case ENUM_GET_CFG_DESC:  
-    /* get standard configuration descriptor */
-    if ( USBH_Get_CfgDesc(phost, 
-                          USB_CONFIGURATION_DESC_SIZE) == USBH_OK)
-    {
-      phost->EnumState = ENUM_GET_FULL_CFG_DESC;        
-    }
-    break;
-    
-  case ENUM_GET_FULL_CFG_DESC:  
-    /* get FULL config descriptor (config, interface, endpoints) */
-    if (USBH_Get_CfgDesc(phost, 
-                         phost->device.CfgDesc.wTotalLength) == USBH_OK)
-    {
-      phost->EnumState = ENUM_GET_MFC_STRING_DESC;       
-    }
-    break;
-    
-  case ENUM_GET_MFC_STRING_DESC:  
-    if (phost->device.DevDesc.iManufacturer != 0)
-    { /* Check that Manufacturer String is available */
-      
-      if ( USBH_Get_StringDesc(phost,
-                               phost->device.DevDesc.iManufacturer, 
-                                phost->device.Data , 
-                               0xff) == USBH_OK)
-      {
-        /* User callback for Manufacturing string */
-        USBH_UsrLog("Manufacturer : %s",  (char *)phost->device.Data);
-        phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
-        
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif          
-      }
-    }
-    else
-    {
-     USBH_UsrLog("Manufacturer : N/A");      
-     phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; 
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif       
-    }
-    break;
-    
-  case ENUM_GET_PRODUCT_STRING_DESC:   
-    if (phost->device.DevDesc.iProduct != 0)
-    { /* Check that Product string is available */
-      if ( USBH_Get_StringDesc(phost,
-                               phost->device.DevDesc.iProduct, 
-                               phost->device.Data, 
-                               0xff) == USBH_OK)
-      {
-        /* User callback for Product string */
-        USBH_UsrLog("Product : %s",  (char *)phost->device.Data);
-        phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;        
-      }
-    }
-    else
-    {
-      USBH_UsrLog("Product : N/A");
-      phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; 
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif        
-    } 
-    break;
-    
-  case ENUM_GET_SERIALNUM_STRING_DESC:   
-    if (phost->device.DevDesc.iSerialNumber != 0)
-    { /* Check that Serial number string is available */    
-      if ( USBH_Get_StringDesc(phost,
-                               phost->device.DevDesc.iSerialNumber, 
-                               phost->device.Data, 
-                               0xff) == USBH_OK)
-      {
-        /* User callback for Serial number string */
-         USBH_UsrLog("Serial Number : %s",  (char *)phost->device.Data);
-        Status = USBH_OK;
-      }
-    }
-    else
-    {
-      USBH_UsrLog("Serial Number : N/A"); 
-      Status = USBH_OK;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_STATE_CHANGED_EVENT, 0);
-#endif        
-    }  
-    break;
-    
-  default:
-    break;
-  }  
-  return Status;
-}
-
-/**
-  * @brief  USBH_LL_SetTimer 
-  *         Set the initial Host Timer tick
-  * @param  phost: Host Handle
-  * @retval None
-  */
-void  USBH_LL_SetTimer  (USBH_HandleTypeDef *phost, uint32_t time)
-{
-  phost->Timer = time;
-}
-/**
-  * @brief  USBH_LL_IncTimer 
-  *         Increment Host Timer tick
-  * @param  phost: Host Handle
-  * @retval None
-  */
-void  USBH_LL_IncTimer  (USBH_HandleTypeDef *phost)
-{
-  phost->Timer ++;
-  USBH_HandleSof(phost);
-}
-
-/**
-  * @brief  USBH_HandleSof 
-  *         Call SOF process
-  * @param  phost: Host Handle
-  * @retval None
-  */
-void  USBH_HandleSof  (USBH_HandleTypeDef *phost)
-{
-  if((phost->gState == HOST_CLASS)&&(phost->pActiveClass != NULL))
-  {
-    phost->pActiveClass->SOFProcess(phost);
-  }
-}
-/**
-  * @brief  USBH_LL_Connect 
-  *         Handle USB Host connexion event
-  * @param  phost: Host Handle
-  * @retval USBH_Status
-  */
-USBH_StatusTypeDef  USBH_LL_Connect  (USBH_HandleTypeDef *phost)
-{
-  if(phost->gState == HOST_IDLE )
-  {
-    phost->device.is_connected = 1;
-    
-    if(phost->pUser != NULL)
-    {    
-      phost->pUser(phost, HOST_USER_CONNECTION);
-    }
-  } 
-  else if(phost->gState == HOST_DEV_WAIT_FOR_ATTACHMENT )
-  {
-    phost->gState = HOST_DEV_ATTACHED ;
-  }
-#if (USBH_USE_OS == 1)
-  osMessagePut ( phost->os_event, USBH_PORT_EVENT, 0);
-#endif 
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_LL_Disconnect 
-  *         Handle USB Host disconnection event
-  * @param  phost: Host Handle
-  * @retval USBH_Status
-  */
-USBH_StatusTypeDef  USBH_LL_Disconnect  (USBH_HandleTypeDef *phost)
-{
-  /*Stop Host */ 
-  USBH_LL_Stop(phost);  
-  
-  /* FRee Control Pipes */
-  USBH_FreePipe  (phost, phost->Control.pipe_in);
-  USBH_FreePipe  (phost, phost->Control.pipe_out);  
-   
-  phost->device.is_connected = 0; 
-   
-  if(phost->pUser != NULL)
-  {    
-    phost->pUser(phost, HOST_USER_DISCONNECTION);
-  }
-  USBH_UsrLog("USB Device disconnected"); 
-  
-  /* Start the low level driver  */
-  USBH_LL_Start(phost);
-  
-  phost->gState = HOST_DEV_DISCONNECTED;
-  
-#if (USBH_USE_OS == 1)
-  osMessagePut ( phost->os_event, USBH_PORT_EVENT, 0);
-#endif 
-  
-  return USBH_OK;
-}
-
-
-#if (USBH_USE_OS == 1)  
-/**
-  * @brief  USB Host Thread task
-  * @param  pvParameters not used
-  * @retval None
-  */
-static void USBH_Process_OS(void const * argument)
-{
-  osEvent event;
-  
-  for(;;)
-  {
-    event = osMessageGet(((USBH_HandleTypeDef *)argument)->os_event, osWaitForever );
-    
-    if( event.status == osEventMessage )
-    {
-      USBH_Process((USBH_HandleTypeDef *)argument);
-    }
-   }
-}
-
-/**
-* @brief  USBH_LL_NotifyURBChange 
-*         Notify URB state Change
-* @param  phost: Host handle
-* @retval USBH Status
-*/
-USBH_StatusTypeDef  USBH_LL_NotifyURBChange (USBH_HandleTypeDef *phost)
-{
-  osMessagePut ( phost->os_event, USBH_URB_EVENT, 0);
-  return USBH_OK;
-}
-#endif  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c
deleted file mode 100644
index c915caf5..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c
+++ /dev/null
@@ -1,881 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_ctlreq.c 
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements the control requests for device enumeration
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_ctlreq.h"
-
-/** @addtogroup USBH_LIB
-* @{
-*/
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-
-/** @defgroup USBH_CTLREQ 
-* @brief This file implements the standard requests for device enumeration
-* @{
-*/
-
-
-/** @defgroup USBH_CTLREQ_Private_Defines
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_CTLREQ_Private_TypesDefinitions
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-
-
-/** @defgroup USBH_CTLREQ_Private_Macros
-* @{
-*/ 
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_CTLREQ_Private_Variables
-* @{
-*/
-/**
-* @}
-*/ 
-
-/** @defgroup USBH_CTLREQ_Private_FunctionPrototypes
-* @{
-*/
-static USBH_StatusTypeDef USBH_HandleControl (USBH_HandleTypeDef *phost);
-
-static void USBH_ParseDevDesc (USBH_DevDescTypeDef* , uint8_t *buf, uint16_t length);
-
-static void USBH_ParseCfgDesc (USBH_CfgDescTypeDef* cfg_desc,
-                               uint8_t *buf, 
-                               uint16_t length);
-
-
-static void USBH_ParseEPDesc (USBH_EpDescTypeDef  *ep_descriptor, uint8_t *buf);
-static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length);
-static void USBH_ParseInterfaceDesc (USBH_InterfaceDescTypeDef  *if_descriptor, uint8_t *buf);
-
-
-/**
-* @}
-*/ 
-
-
-/** @defgroup USBH_CTLREQ_Private_Functions
-* @{
-*/ 
-
-
-/**
-  * @brief  USBH_Get_DevDesc
-  *         Issue Get Device Descriptor command to the device. Once the response 
-  *         received, it parses the device descriptor and updates the status.
-  * @param  phost: Host Handle
-  * @param  length: Length of the descriptor
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint8_t length)
-{
-  USBH_StatusTypeDef status;
-  
-  if((status = USBH_GetDescriptor(phost,
-                                  USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,                          
-                                  USB_DESC_DEVICE, 
-                                  phost->device.Data,
-                                  length)) == USBH_OK)
-  {
-    /* Commands successfully sent and Response Received */       
-    USBH_ParseDevDesc(&phost->device.DevDesc, phost->device.Data, length);
-  }
-  return status;      
-}
-
-/**
-  * @brief  USBH_Get_CfgDesc
-  *         Issues Configuration Descriptor to the device. Once the response 
-  *         received, it parses the configuration descriptor and updates the 
-  *         status.
-  * @param  phost: Host Handle
-  * @param  length: Length of the descriptor
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost,                      
-                             uint16_t length)
-
-{
-  USBH_StatusTypeDef status;
-  uint8_t *pData;
-#if (USBH_KEEP_CFG_DESCRIPTOR == 1)  
-  pData = phost->device.CfgDesc_Raw;
-#else
-  pData = phost->device.Data;
-#endif  
-  if((status = USBH_GetDescriptor(phost,
-                                  USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,                          
-                                  USB_DESC_CONFIGURATION, 
-                                  pData,
-                                  length)) == USBH_OK)
-  {
-    
-    /* Commands successfully sent and Response Received  */       
-    USBH_ParseCfgDesc (&phost->device.CfgDesc,
-                       pData,
-                       length); 
-    
-  }
-  return status;
-}
-
-
-/**
-  * @brief  USBH_Get_StringDesc
-  *         Issues string Descriptor command to the device. Once the response 
-  *         received, it parses the string descriptor and updates the status.
-  * @param  phost: Host Handle
-  * @param  string_index: String index for the descriptor
-  * @param  buff: Buffer address for the descriptor
-  * @param  length: Length of the descriptor
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost,
-                                uint8_t string_index, 
-                                uint8_t *buff, 
-                                uint16_t length)
-{
-  USBH_StatusTypeDef status;
-  if((status = USBH_GetDescriptor(phost,
-                                  USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,                                    
-                                  USB_DESC_STRING | string_index, 
-                                  phost->device.Data,
-                                  length)) == USBH_OK)
-  {
-    /* Commands successfully sent and Response Received  */       
-    USBH_ParseStringDesc(phost->device.Data,buff, length);    
-  }
-  return status;
-}
-
-/**
-  * @brief  USBH_GetDescriptor
-  *         Issues Descriptor command to the device. Once the response received,
-  *         it parses the descriptor and updates the status.
-  * @param  phost: Host Handle
-  * @param  req_type: Descriptor type
-  * @param  value_idx: Value for the GetDescriptr request
-  * @param  buff: Buffer to store the descriptor
-  * @param  length: Length of the descriptor
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost,                          
-                               uint8_t  req_type,
-                               uint16_t value_idx, 
-                               uint8_t* buff, 
-                               uint16_t length )
-{ 
-  if(phost->RequestState == CMD_SEND)
-  {
-    phost->Control.setup.b.bmRequestType = USB_D2H | req_type;
-    phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR;
-    phost->Control.setup.b.wValue.w = value_idx;
-    
-    if ((value_idx & 0xff00) == USB_DESC_STRING)
-    {
-      phost->Control.setup.b.wIndex.w = 0x0409;
-    }
-    else
-    {
-      phost->Control.setup.b.wIndex.w = 0;
-    }
-    phost->Control.setup.b.wLength.w = length; 
-  }
-  return USBH_CtlReq(phost, buff , length );     
-}
-
-/**
-  * @brief  USBH_SetAddress
-  *         This command sets the address to the connected device
-  * @param  phost: Host Handle
-  * @param  DeviceAddress: Device address to assign
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost, 
-                                   uint8_t DeviceAddress)
-{
-  if(phost->RequestState == CMD_SEND)
-  {
-    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \
-      USB_REQ_TYPE_STANDARD;
-    
-    phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS;
-    
-    phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress;
-    phost->Control.setup.b.wIndex.w = 0;
-    phost->Control.setup.b.wLength.w = 0;
-  }
-  return USBH_CtlReq(phost, 0 , 0 );
-}
-
-/**
-  * @brief  USBH_SetCfg
-  *         The command sets the configuration value to the connected device
-  * @param  phost: Host Handle
-  * @param  cfg_idx: Configuration value
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, 
-                               uint16_t cfg_idx)
-{
-  if(phost->RequestState == CMD_SEND)
-  {
-    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE |\
-      USB_REQ_TYPE_STANDARD;
-    phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION;
-    phost->Control.setup.b.wValue.w = cfg_idx;
-    phost->Control.setup.b.wIndex.w = 0;
-    phost->Control.setup.b.wLength.w = 0; 
-  }
-  
-  return USBH_CtlReq(phost, 0 , 0 );      
-}
-
-/**
-  * @brief  USBH_SetInterface
-  *         The command sets the Interface value to the connected device
-  * @param  phost: Host Handle
-  * @param  altSetting: Interface value
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_SetInterface(USBH_HandleTypeDef *phost, 
-                        uint8_t ep_num, uint8_t altSetting)
-{
-  
-  if(phost->RequestState == CMD_SEND)
-  {
-    phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | \
-      USB_REQ_TYPE_STANDARD;
-    
-    phost->Control.setup.b.bRequest = USB_REQ_SET_INTERFACE;
-    phost->Control.setup.b.wValue.w = altSetting;
-    phost->Control.setup.b.wIndex.w = ep_num;
-    phost->Control.setup.b.wLength.w = 0;           
-  }
-  return USBH_CtlReq(phost, 0 , 0 );     
-}
-
-/**
-  * @brief  USBH_ClrFeature
-  *         This request is used to clear or disable a specific feature.
-  * @param  phost: Host Handle
-  * @param  ep_num: endpoint number 
-  * @param  hc_num: Host channel number 
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost,
-                                   uint8_t ep_num) 
-{
-  if(phost->RequestState == CMD_SEND)
-  {
-    phost->Control.setup.b.bmRequestType = USB_H2D | 
-      USB_REQ_RECIPIENT_ENDPOINT |
-        USB_REQ_TYPE_STANDARD;
-    
-    phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE;
-    phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT;
-    phost->Control.setup.b.wIndex.w = ep_num;
-    phost->Control.setup.b.wLength.w = 0;           
-  }
-  return USBH_CtlReq(phost, 0 , 0 );   
-}
-
-/**
-  * @brief  USBH_ParseDevDesc 
-  *         This function Parses the device descriptor
-  * @param  dev_desc: device_descriptor destination address 
-  * @param  buf: Buffer where the source descriptor is available
-  * @param  length: Length of the descriptor
-  * @retval None
-  */
-static void  USBH_ParseDevDesc (USBH_DevDescTypeDef* dev_desc,
-                                uint8_t *buf, 
-                                uint16_t length)
-{
-  dev_desc->bLength            = *(uint8_t  *) (buf +  0);
-  dev_desc->bDescriptorType    = *(uint8_t  *) (buf +  1);
-  dev_desc->bcdUSB             = LE16 (buf +  2);
-  dev_desc->bDeviceClass       = *(uint8_t  *) (buf +  4);
-  dev_desc->bDeviceSubClass    = *(uint8_t  *) (buf +  5);
-  dev_desc->bDeviceProtocol    = *(uint8_t  *) (buf +  6);
-  dev_desc->bMaxPacketSize     = *(uint8_t  *) (buf +  7);
-  
-  if (length > 8)
-  { /* For 1st time after device connection, Host may issue only 8 bytes for 
-    Device Descriptor Length  */
-    dev_desc->idVendor           = LE16 (buf +  8);
-    dev_desc->idProduct          = LE16 (buf + 10);
-    dev_desc->bcdDevice          = LE16 (buf + 12);
-    dev_desc->iManufacturer      = *(uint8_t  *) (buf + 14);
-    dev_desc->iProduct           = *(uint8_t  *) (buf + 15);
-    dev_desc->iSerialNumber      = *(uint8_t  *) (buf + 16);
-    dev_desc->bNumConfigurations = *(uint8_t  *) (buf + 17);
-  }
-}
-
-/**
-  * @brief  USBH_ParseCfgDesc 
-  *         This function Parses the configuration descriptor
-  * @param  cfg_desc: Configuration Descriptor address
-  * @param  buf: Buffer where the source descriptor is available
-  * @param  length: Length of the descriptor
-  * @retval None
-  */
-static void USBH_ParseCfgDesc (USBH_CfgDescTypeDef* cfg_desc,
-                               uint8_t *buf, 
-                               uint16_t length)
-{  
-  USBH_InterfaceDescTypeDef    *pif ;
-  USBH_EpDescTypeDef           *pep;  
-  USBH_DescHeader_t             *pdesc = (USBH_DescHeader_t *)buf;
-  uint16_t                      ptr;
-  int8_t                        if_ix = 0;
-  int8_t                        ep_ix = 0;  
-  
-  pdesc   = (USBH_DescHeader_t *)buf;
-  
-  /* Parse configuration descriptor */
-  cfg_desc->bLength             = *(uint8_t  *) (buf + 0);
-  cfg_desc->bDescriptorType     = *(uint8_t  *) (buf + 1);
-  cfg_desc->wTotalLength        = LE16 (buf + 2);
-  cfg_desc->bNumInterfaces      = *(uint8_t  *) (buf + 4);
-  cfg_desc->bConfigurationValue = *(uint8_t  *) (buf + 5);
-  cfg_desc->iConfiguration      = *(uint8_t  *) (buf + 6);
-  cfg_desc->bmAttributes        = *(uint8_t  *) (buf + 7);
-  cfg_desc->bMaxPower           = *(uint8_t  *) (buf + 8);    
-  
-  
-  if (length > USB_CONFIGURATION_DESC_SIZE)
-  {
-    ptr = USB_LEN_CFG_DESC;
-    pif = (USBH_InterfaceDescTypeDef *)0;
-    
-    
-    while ((if_ix < USBH_MAX_NUM_INTERFACES ) && (ptr < cfg_desc->wTotalLength))
-    {
-      pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr);
-      if (pdesc->bDescriptorType   == USB_DESC_TYPE_INTERFACE) 
-      {
-        pif = &cfg_desc->Itf_Desc[if_ix];
-        USBH_ParseInterfaceDesc (pif, (uint8_t *)pdesc);            
-        
-        ep_ix = 0;
-        pep = (USBH_EpDescTypeDef *)0;        
-        while ((ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength))
-        {
-          pdesc = USBH_GetNextDesc((uint8_t*) pdesc, &ptr);
-          if (pdesc->bDescriptorType   == USB_DESC_TYPE_ENDPOINT) 
-          {  
-            pep = &cfg_desc->Itf_Desc[if_ix].Ep_Desc[ep_ix];
-            USBH_ParseEPDesc (pep, (uint8_t *)pdesc);
-            ep_ix++;
-          }
-        }
-        if_ix++;
-      }
-    }
-  }  
-}
-
-
-
-/**
-  * @brief  USBH_ParseInterfaceDesc 
-  *         This function Parses the interface descriptor
-  * @param  if_descriptor : Interface descriptor destination
-  * @param  buf: Buffer where the descriptor data is available
-  * @retval None
-  */
-static void  USBH_ParseInterfaceDesc (USBH_InterfaceDescTypeDef *if_descriptor, 
-                                      uint8_t *buf)
-{
-  if_descriptor->bLength            = *(uint8_t  *) (buf + 0);
-  if_descriptor->bDescriptorType    = *(uint8_t  *) (buf + 1);
-  if_descriptor->bInterfaceNumber   = *(uint8_t  *) (buf + 2);
-  if_descriptor->bAlternateSetting  = *(uint8_t  *) (buf + 3);
-  if_descriptor->bNumEndpoints      = *(uint8_t  *) (buf + 4);
-  if_descriptor->bInterfaceClass    = *(uint8_t  *) (buf + 5);
-  if_descriptor->bInterfaceSubClass = *(uint8_t  *) (buf + 6);
-  if_descriptor->bInterfaceProtocol = *(uint8_t  *) (buf + 7);
-  if_descriptor->iInterface         = *(uint8_t  *) (buf + 8);
-}
-
-/**
-  * @brief  USBH_ParseEPDesc 
-  *         This function Parses the endpoint descriptor
-  * @param  ep_descriptor: Endpoint descriptor destination address
-  * @param  buf: Buffer where the parsed descriptor stored
-  * @retval None
-  */
-static void  USBH_ParseEPDesc (USBH_EpDescTypeDef  *ep_descriptor, 
-                               uint8_t *buf)
-{
-  
-  ep_descriptor->bLength          = *(uint8_t  *) (buf + 0);
-  ep_descriptor->bDescriptorType  = *(uint8_t  *) (buf + 1);
-  ep_descriptor->bEndpointAddress = *(uint8_t  *) (buf + 2);
-  ep_descriptor->bmAttributes     = *(uint8_t  *) (buf + 3);
-  ep_descriptor->wMaxPacketSize   = LE16 (buf + 4);
-  ep_descriptor->bInterval        = *(uint8_t  *) (buf + 6);
-}
-
-/**
-  * @brief  USBH_ParseStringDesc 
-  *         This function Parses the string descriptor
-  * @param  psrc: Source pointer containing the descriptor data
-  * @param  pdest: Destination address pointer
-  * @param  length: Length of the descriptor
-  * @retval None
-  */
-static void USBH_ParseStringDesc (uint8_t* psrc, 
-                                  uint8_t* pdest, 
-                                  uint16_t length)
-{
-  uint16_t strlength;
-  uint16_t idx;
-  
-  /* The UNICODE string descriptor is not NULL-terminated. The string length is
-  computed by substracting two from the value of the first byte of the descriptor.
-  */
-  
-  /* Check which is lower size, the Size of string or the length of bytes read 
-  from the device */
-  
-  if ( psrc[1] == USB_DESC_TYPE_STRING)
-  { /* Make sure the Descriptor is String Type */
-    
-    /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */      
-    strlength = ( ( (psrc[0]-2) <= length) ? (psrc[0]-2) :length); 
-    psrc += 2; /* Adjust the offset ignoring the String Len and Descriptor type */
-    
-    for (idx = 0; idx < strlength; idx+=2 )
-    {/* Copy Only the string and ignore the UNICODE ID, hence add the src */
-      *pdest =  psrc[idx];
-      pdest++;
-    }  
-    *pdest = 0; /* mark end of string */  
-  }
-}
-
-/**
-  * @brief  USBH_GetNextDesc 
-  *         This function return the next descriptor header
-  * @param  buf: Buffer where the cfg descriptor is available
-  * @param  ptr: data pointer inside the cfg descriptor
-  * @retval next header
-  */
-USBH_DescHeader_t  *USBH_GetNextDesc (uint8_t   *pbuf, uint16_t  *ptr)
-{
-  USBH_DescHeader_t  *pnext;
- 
-  *ptr += ((USBH_DescHeader_t *)pbuf)->bLength;  
-  pnext = (USBH_DescHeader_t *)((uint8_t *)pbuf + \
-         ((USBH_DescHeader_t *)pbuf)->bLength);
- 
-  return(pnext);
-}
-
-
-/**
-  * @brief  USBH_CtlReq
-  *         USBH_CtlReq sends a control request and provide the status after 
-  *            completion of the request
-  * @param  phost: Host Handle
-  * @param  req: Setup Request Structure
-  * @param  buff: data buffer address to store the response
-  * @param  length: length of the response
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_CtlReq     (USBH_HandleTypeDef *phost, 
-                             uint8_t             *buff,
-                             uint16_t            length)
-{
-  USBH_StatusTypeDef status;
-  status = USBH_BUSY;
-  
-  switch (phost->RequestState)
-  {
-  case CMD_SEND:
-    /* Start a SETUP transfer */
-    phost->Control.buff = buff; 
-    phost->Control.length = length;
-    phost->Control.state = CTRL_SETUP;  
-    phost->RequestState = CMD_WAIT;
-    status = USBH_BUSY;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    break;
-    
-  case CMD_WAIT:
-    status = USBH_HandleControl(phost);
-     if (status == USBH_OK) 
-    {
-      /* Commands successfully sent and Response Received  */       
-      phost->RequestState = CMD_SEND;
-      phost->Control.state =CTRL_IDLE;  
-      status = USBH_OK;      
-    }
-    else if  (status == USBH_FAIL)
-    {
-      /* Failure Mode */
-      phost->RequestState = CMD_SEND;
-      status = USBH_FAIL;
-    }   
-    break;
-    
-  default:
-    break; 
-  }
-  return status;
-}
-
-/**
-  * @brief  USBH_HandleControl
-  *         Handles the USB control transfer state machine
-  * @param  phost: Host Handle
-  * @retval USBH Status
-  */
-static USBH_StatusTypeDef USBH_HandleControl (USBH_HandleTypeDef *phost)
-{
-  uint8_t direction;  
-  USBH_StatusTypeDef status = USBH_BUSY;
-  USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
-  
-  switch (phost->Control.state)
-  {
-  case CTRL_SETUP:
-    /* send a SETUP packet */
-    USBH_CtlSendSetup     (phost, 
-	                   (uint8_t *)phost->Control.setup.d8 , 
-	                   phost->Control.pipe_out); 
-    
-    phost->Control.state = CTRL_SETUP_WAIT; 
-    break; 
-    
-  case CTRL_SETUP_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out); 
-    /* case SETUP packet sent successfully */
-    if(URB_Status == USBH_URB_DONE)
-    { 
-      direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK);
-      
-      /* check if there is a data stage */
-      if (phost->Control.setup.b.wLength.w != 0 )
-      {        
-        if (direction == USB_D2H)
-        {
-          /* Data Direction is IN */
-          phost->Control.state = CTRL_DATA_IN;
-        }
-        else
-        {
-          /* Data Direction is OUT */
-          phost->Control.state = CTRL_DATA_OUT;
-        } 
-      }
-      /* No DATA stage */
-      else
-      {
-        /* If there is No Data Transfer Stage */
-        if (direction == USB_D2H)
-        {
-          /* Data Direction is IN */
-          phost->Control.state = CTRL_STATUS_OUT;
-        }
-        else
-        {
-          /* Data Direction is OUT */
-          phost->Control.state = CTRL_STATUS_IN;
-        } 
-      }          
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif
-    }
-    else if(URB_Status == USBH_URB_ERROR)
-    {
-      phost->Control.state = CTRL_ERROR;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }    
-    break;
-    
-  case CTRL_DATA_IN:  
-    /* Issue an IN token */ 
-     phost->Control.timer = phost->Timer;
-    USBH_CtlReceiveData(phost,
-                        phost->Control.buff, 
-                        phost->Control.length,
-                        phost->Control.pipe_in);
- 
-    phost->Control.state = CTRL_DATA_IN_WAIT;
-    break;    
-    
-  case CTRL_DATA_IN_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost , phost->Control.pipe_in); 
-    
-    /* check is DATA packet transferred successfully */
-    if  (URB_Status == USBH_URB_DONE)
-    { 
-      phost->Control.state = CTRL_STATUS_OUT;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-   
-    /* manage error cases*/
-    if  (URB_Status == USBH_URB_STALL) 
-    { 
-      /* In stall case, return to previous machine state*/
-      status = USBH_NOT_SUPPORTED;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }   
-    else if (URB_Status == USBH_URB_ERROR)
-    {
-      /* Device error */
-      phost->Control.state = CTRL_ERROR;  
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    break;
-    
-  case CTRL_DATA_OUT:
-    
-    USBH_CtlSendData (phost,
-                      phost->Control.buff, 
-                      phost->Control.length , 
-                      phost->Control.pipe_out,
-                      1);
-     phost->Control.timer = phost->Timer;
-    phost->Control.state = CTRL_DATA_OUT_WAIT;
-    break;
-    
-  case CTRL_DATA_OUT_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost , phost->Control.pipe_out);     
-    
-    if  (URB_Status == USBH_URB_DONE)
-    { /* If the Setup Pkt is sent successful, then change the state */
-      phost->Control.state = CTRL_STATUS_IN;
-#if (USBH_USE_OS == 1)
-      osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    
-    /* handle error cases */
-    else if  (URB_Status == USBH_URB_STALL) 
-    { 
-      /* In stall case, return to previous machine state*/
-      phost->Control.state = CTRL_STALLED; 
-      status = USBH_NOT_SUPPORTED;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    } 
-    else if  (URB_Status == USBH_URB_NOTREADY)
-    { 
-      /* Nack received from device */
-      phost->Control.state = CTRL_DATA_OUT;
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }    
-    else if (URB_Status == USBH_URB_ERROR)
-    {
-      /* device error */
-      phost->Control.state = CTRL_ERROR;  
-      status = USBH_FAIL;    
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    } 
-    break;
-    
-    
-  case CTRL_STATUS_IN:
-    /* Send 0 bytes out packet */
-    USBH_CtlReceiveData (phost,
-                         0,
-                         0,
-                         phost->Control.pipe_in);
-    phost->Control.timer = phost->Timer;
-    phost->Control.state = CTRL_STATUS_IN_WAIT;
-    
-    break;
-    
-  case CTRL_STATUS_IN_WAIT:
-    
-    URB_Status = USBH_LL_GetURBState(phost , phost->Control.pipe_in); 
-    
-    if  ( URB_Status == USBH_URB_DONE)
-    { /* Control transfers completed, Exit the State Machine */
-      phost->Control.state = CTRL_COMPLETE;
-      status = USBH_OK;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    
-    else if (URB_Status == USBH_URB_ERROR)
-    {
-      phost->Control.state = CTRL_ERROR;
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-     else if(URB_Status == USBH_URB_STALL)
-    {
-      /* Control transfers completed, Exit the State Machine */
-      status = USBH_NOT_SUPPORTED;
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    break;
-    
-  case CTRL_STATUS_OUT:
-    USBH_CtlSendData (phost,
-                      0,
-                      0,
-                      phost->Control.pipe_out,
-                      1);
-     phost->Control.timer = phost->Timer;
-    phost->Control.state = CTRL_STATUS_OUT_WAIT;
-    break;
-    
-  case CTRL_STATUS_OUT_WAIT: 
-    
-    URB_Status = USBH_LL_GetURBState(phost , phost->Control.pipe_out);  
-    if  (URB_Status == USBH_URB_DONE)
-    { 
-      status = USBH_OK;      
-      phost->Control.state = CTRL_COMPLETE; 
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    else if  (URB_Status == USBH_URB_NOTREADY)
-    { 
-      phost->Control.state = CTRL_STATUS_OUT;
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }      
-    else if (URB_Status == USBH_URB_ERROR)
-    {
-      phost->Control.state = CTRL_ERROR; 
-      
-#if (USBH_USE_OS == 1)
-    osMessagePut ( phost->os_event, USBH_CONTROL_EVENT, 0);
-#endif      
-    }
-    break;
-    
-  case CTRL_ERROR:
-    /* 
-    After a halt condition is encountered or an error is detected by the 
-    host, a control endpoint is allowed to recover by accepting the next Setup 
-    PID; i.e., recovery actions via some other pipe are not required for control
-    endpoints. For the Default Control Pipe, a device reset will ultimately be 
-    required to clear the halt or error condition if the next Setup PID is not 
-    accepted.
-    */
-    if (++ phost->Control.errorcount <= USBH_MAX_ERROR_COUNT)
-    {
-      /* try to recover control */
-      USBH_LL_Stop(phost);
-         
-      /* Do the transmission again, starting from SETUP Packet */
-      phost->Control.state = CTRL_SETUP; 
-      phost->RequestState = CMD_SEND;
-    }
-    else
-    {
-      phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR);
-      phost->Control.errorcount = 0;
-      USBH_ErrLog("Control error");
-      status = USBH_FAIL;
-    }
-    break;
-    
-  default:
-    break;
-  }
-  return status;
-}
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c
deleted file mode 100644
index dc61a4cb..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ioreq.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/** 
-  ******************************************************************************
-  * @file    usbh_ioreq.c 
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file handles the issuing of the USB transactions
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-/* Includes ------------------------------------------------------------------*/
-
-#include "usbh_ioreq.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_IOREQ 
-  * @brief This file handles the standard protocol processing (USB v2.0)
-  * @{
-  */
-
-
-/** @defgroup USBH_IOREQ_Private_Defines
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
- 
-
-/** @defgroup USBH_IOREQ_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-
-/** @defgroup USBH_IOREQ_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_IOREQ_Private_Variables
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-/** @defgroup USBH_IOREQ_Private_FunctionPrototypes
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_IOREQ_Private_Functions
-  * @{
-  */ 
-
-
-
-/**
-  * @brief  USBH_CtlSendSetup
-  *         Sends the Setup Packet to the Device
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer from which the Data will be send to Device
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_CtlSendSetup (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint8_t pipe_num)
-{
-
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          0,                    /* Direction : OUT  */
-                          USBH_EP_CONTROL,      /* EP type          */
-                          USBH_PID_SETUP,       /* Type setup       */
-                          buff,                 /* data buffer      */
-                          USBH_SETUP_PKT_SIZE,  /* data length      */ 
-                          0);
-  return USBH_OK;  
-}
-
-
-/**
-  * @brief  USBH_CtlSendData
-  *         Sends a data Packet to the Device
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer from which the Data will be sent to Device
-  * @param  length: Length of the data to be sent
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_CtlSendData (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t pipe_num,
-                                uint8_t do_ping )
-{
-  if(phost->device.speed != USBH_SPEED_HIGH)
-  {
-    do_ping = 0;
-  }
-  
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          0,                    /* Direction : OUT  */
-                          USBH_EP_CONTROL,      /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */ 
-                          do_ping);             /* do ping (HS Only)*/
-  
-  return USBH_OK;
-}
-
-
-/**
-  * @brief  USBH_CtlReceiveData
-  *         Receives the Device Response to the Setup Packet
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer in which the response needs to be copied
-  * @param  length: Length of the data to be received
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t* buff, 
-                                uint16_t length,
-                                uint8_t pipe_num)
-{
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          1,                    /* Direction : IN   */
-                          USBH_EP_CONTROL,      /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */ 
-                          0);
-  return USBH_OK;
-  
-}
-
-
-/**
-  * @brief  USBH_BulkSendData
-  *         Sends the Bulk Packet to the device
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer from which the Data will be sent to Device
-  * @param  length: Length of the data to be sent
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_BulkSendData (USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t pipe_num,
-                                uint8_t do_ping )
-{ 
-  if(phost->device.speed != USBH_SPEED_HIGH)
-  {
-    do_ping = 0;
-  }
-  
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          0,                    /* Direction : IN   */
-                          USBH_EP_BULK,         /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */  
-                          do_ping);             /* do ping (HS Only)*/
-  return USBH_OK;
-}
-
-
-/**
-  * @brief  USBH_BulkReceiveData
-  *         Receives IN bulk packet from device
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer in which the received data packet to be copied
-  * @param  length: Length of the data to be received
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint16_t length,
-                                uint8_t pipe_num)
-{
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          1,                    /* Direction : IN   */
-                          USBH_EP_BULK,         /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */  
-                          0);
-  return USBH_OK;
-}
-
-
-/**
-  * @brief  USBH_InterruptReceiveData
-  *         Receives the Device Response to the Interrupt IN token
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer in which the response needs to be copied
-  * @param  length: Length of the data to be received
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_InterruptReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint8_t length,
-                                uint8_t pipe_num)
-{
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          1,                    /* Direction : IN   */
-                          USBH_EP_INTERRUPT,    /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */  
-                          0); 
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_InterruptSendData
-  *         Sends the data on Interrupt OUT Endpoint
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer from where the data needs to be copied
-  * @param  length: Length of the data to be sent
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_InterruptSendData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint8_t length,
-                                uint8_t pipe_num)
-{
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          0,                    /* Direction : OUT   */
-                          USBH_EP_INTERRUPT,    /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */  
-                          0);  
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_IsocReceiveData
-  *         Receives the Device Response to the Isochronous IN token
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer in which the response needs to be copied
-  * @param  length: Length of the data to be received
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_IsocReceiveData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint32_t length,
-                                uint8_t pipe_num)
-{    
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          1,                    /* Direction : IN   */
-                          USBH_EP_ISO,          /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */
-                          0);
-
-  
-  return USBH_OK;
-}
-
-/**
-  * @brief  USBH_IsocSendData
-  *         Sends the data on Isochronous OUT Endpoint
-  * @param  phost: Host Handle
-  * @param  buff: Buffer pointer from where the data needs to be copied
-  * @param  length: Length of the data to be sent
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status. 
-  */
-USBH_StatusTypeDef USBH_IsocSendData(USBH_HandleTypeDef *phost, 
-                                uint8_t *buff, 
-                                uint32_t length,
-                                uint8_t pipe_num)
-{
-  USBH_LL_SubmitURB (phost,                     /* Driver handle    */
-                          pipe_num,             /* Pipe index       */
-                          0,                    /* Direction : OUT   */
-                          USBH_EP_ISO,          /* EP type          */                          
-                          USBH_PID_DATA,        /* Type Data        */
-                          buff,                 /* data buffer      */
-                          length,               /* data length      */ 
-                          0);
-  
-  return USBH_OK;
-}
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c b/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c
deleted file mode 100644
index f570ba0e..00000000
--- a/STM32CubeMX/2020c/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_pipes.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    usbh_pipes.c
-  * @author  MCD Application Team
-  * @version V3.2.2
-  * @date    07-July-2015
-  * @brief   This file implements functions for opening and closing Pipes
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT 2015 STMicroelectronics

-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbh_pipes.h"
-
-/** @addtogroup USBH_LIB
-  * @{
-  */
-
-/** @addtogroup USBH_LIB_CORE
-* @{
-*/
-  
-/** @defgroup USBH_PIPES
-  * @brief This file includes opening and closing Pipes
-  * @{
-  */ 
-
-/** @defgroup USBH_PIPES_Private_Defines
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-/** @defgroup USBH_PIPES_Private_TypesDefinitions
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_PIPES_Private_Macros
-  * @{
-  */ 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_PIPES_Private_Variables
-  * @{
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup USBH_PIPES_Private_Functions
-  * @{
-  */ 
-static uint16_t USBH_GetFreePipe (USBH_HandleTypeDef *phost);
-
-
-/**
-  * @brief  USBH_Open_Pipe
-  *         Open a  pipe
-  * @param  phost: Host Handle
-  * @param  pipe_num: Pipe Number
-  * @param  dev_address: USB Device address allocated to attached device
-  * @param  speed : USB device speed (Full/Low)
-  * @param  ep_type: end point type (Bulk/int/ctl)
-  * @param  mps: max pkt size
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_OpenPipe  (USBH_HandleTypeDef *phost,
-                            uint8_t pipe_num,
-                            uint8_t epnum,
-                            uint8_t dev_address,
-                            uint8_t speed,
-                            uint8_t ep_type,
-                            uint16_t mps)
-{
-
-  USBH_LL_OpenPipe(phost,
-                        pipe_num,
-                        epnum,
-                        dev_address,
-                        speed,
-                        ep_type,
-                        mps);
-  
-  return USBH_OK; 
-
-}
-
-/**
-  * @brief  USBH_ClosePipe
-  *         Close a  pipe
-  * @param  phost: Host Handle
-  * @param  pipe_num: Pipe Number
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_ClosePipe  (USBH_HandleTypeDef *phost,
-                            uint8_t pipe_num)
-{
-
-  USBH_LL_ClosePipe(phost, pipe_num);
-  
-  return USBH_OK; 
-
-}
-
-/**
-  * @brief  USBH_Alloc_Pipe
-  *         Allocate a new Pipe
-  * @param  phost: Host Handle
-  * @param  ep_addr: End point for which the Pipe to be allocated
-  * @retval Pipe number
-  */
-uint8_t USBH_AllocPipe  (USBH_HandleTypeDef *phost, uint8_t ep_addr)
-{
-  uint16_t pipe;
-  
-  pipe =  USBH_GetFreePipe(phost);
-
-  if (pipe != 0xFFFF)
-  {
-	phost->Pipes[pipe] = 0x8000 | ep_addr;
-  }
-  return pipe;
-}
-
-/**
-  * @brief  USBH_Free_Pipe
-  *         Free the USB Pipe
-  * @param  phost: Host Handle
-  * @param  idx: Pipe number to be freed 
-  * @retval USBH Status
-  */
-USBH_StatusTypeDef USBH_FreePipe  (USBH_HandleTypeDef *phost, uint8_t idx)
-{
-   if(idx < 11)
-   {
-	 phost->Pipes[idx] &= 0x7FFF;
-   }
-   return USBH_OK;
-}
-
-/**
-  * @brief  USBH_GetFreePipe
-  * @param  phost: Host Handle
-  *         Get a free Pipe number for allocation to a device endpoint
-  * @retval idx: Free Pipe number
-  */
-static uint16_t USBH_GetFreePipe (USBH_HandleTypeDef *phost)
-{
-  uint8_t idx = 0;
-  
-  for (idx = 0 ; idx < 11 ; idx++)
-  {
-	if ((phost->Pipes[idx] & 0x8000) == 0)
-	{
-	   return idx;
-	} 
-  }
-  return 0xFFFF;
-}
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/ 
-
-/**
-* @}
-*/
-
-/**
-* @}
-*/ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
diff --git a/STM32CubeMX/2020c/SCSI2SD-V6.ioc b/STM32CubeMX/2020c/SCSI2SD-V6.ioc
index 21010f5b..fe9afa9b 100644
--- a/STM32CubeMX/2020c/SCSI2SD-V6.ioc
+++ b/STM32CubeMX/2020c/SCSI2SD-V6.ioc
@@ -181,6 +181,7 @@ NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:false\:false
+NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
@@ -490,8 +491,8 @@ ProjectManager.BackupPrevious=false
 ProjectManager.CompilerOptimize=2
 ProjectManager.ComputerToolchain=false
 ProjectManager.CoupleFile=true
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
+ProjectManager.CustomerFirmwarePackage=..\\..\\..\\..\\STM32Cube\\Repository\\STM32Cube_FW_F2_V1.8.0
+ProjectManager.DefaultFWLocation=false
 ProjectManager.DeletePrevious=true
 ProjectManager.DeviceId=STM32F205VCTx
 ProjectManager.FirmwarePackage=STM32Cube FW_F2 V1.2.0
diff --git a/STM32CubeMX/2020c/Src/main.c b/STM32CubeMX/2020c/Src/main.c
index 3384c457..ff0cf4f0 100644
--- a/STM32CubeMX/2020c/Src/main.c
+++ b/STM32CubeMX/2020c/Src/main.c
@@ -51,7 +51,6 @@
 /* Private variables ---------------------------------------------------------*/
 
 /* USER CODE BEGIN PV */
-/* Private variables ---------------------------------------------------------*/
 
 /* USER CODE END PV */
 
@@ -63,7 +62,6 @@ void mainEarlyInit();
 void mainInit();
 void mainLoop();
 
-
 /* USER CODE END PFP */
 
 /* Private user code ---------------------------------------------------------*/
@@ -80,7 +78,6 @@ int main(void)
   /* USER CODE BEGIN 1 */
   mainEarlyInit();
 
-
   /* USER CODE END 1 */
   
 
@@ -109,7 +106,6 @@ int main(void)
   MX_UART4_Init();
   /* USER CODE BEGIN 2 */
   mainInit();
-
   /* USER CODE END 2 */
 
   /* Infinite loop */
@@ -117,11 +113,8 @@ int main(void)
   while (1)
   {
     /* USER CODE END WHILE */
-
     /* USER CODE BEGIN 3 */
   mainLoop();
-
-
   }
   /* USER CODE END 3 */
 }
@@ -193,7 +186,7 @@ void assert_failed(uint8_t *file, uint32_t line)
 { 
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
-    ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
   /* USER CODE END 6 */
 }
 #endif /* USE_FULL_ASSERT */
diff --git a/STM32CubeMX/2020c/Src/system_stm32f2xx.c b/STM32CubeMX/2020c/Src/system_stm32f2xx.c
index acd46803..3c2a20b0 100644
--- a/STM32CubeMX/2020c/Src/system_stm32f2xx.c
+++ b/STM32CubeMX/2020c/Src/system_stm32f2xx.c
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f2xx.c
   * @author  MCD Application Team
-  * @version V2.1.0
-  * @date    09-October-2015
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *             
   *   This file provides two functions and one global variable to be called from 
@@ -23,29 +21,13 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2015 STMicroelectronics

+  * 
© Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.

   *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -65,7 +47,7 @@
 #include "stm32f2xx.h"
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
@@ -123,9 +105,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  uint32_t SystemCoreClock = 12000000;
+  uint32_t SystemCoreClock = 16000000;
   const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
+  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 /**
   * @}
   */
@@ -211,10 +193,10 @@ void SystemInit(void)
   *             16 MHz) but the real value may vary depending on the variations
   *             in voltage and temperature.   
   *    
-  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
-  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
   *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
diff --git a/STM32CubeMX/2020c/Src/usbd_conf.c b/STM32CubeMX/2020c/Src/usbd_conf.c
index 5bc66b16..adb664f0 100644
--- a/STM32CubeMX/2020c/Src/usbd_conf.c
+++ b/STM32CubeMX/2020c/Src/usbd_conf.c
@@ -48,6 +48,7 @@ void Error_Handler(void);
 void SystemClock_Config(void);
 
 /* USER CODE BEGIN 0 */
+
 /* USER CODE END 0 */
 
 /* USER CODE BEGIN PFP */
@@ -59,6 +60,7 @@ USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
 /* Private functions ---------------------------------------------------------*/
 
 /* USER CODE BEGIN 1 */
+
 /* USER CODE END 1 */
 
 /*******************************************************************************
@@ -90,6 +92,10 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
 
     /* Peripheral clock enable */
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+    /* Peripheral interrupt init */
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
   /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
 
   /* USER CODE END USB_OTG_FS_MspInit 1 */
@@ -169,6 +175,9 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
     */
     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12);
 
+    /* Peripheral interrupt Deinit*/
+    HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
+
   /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
 
   /* USER CODE END USB_OTG_FS_MspDeInit 1 */
@@ -321,7 +330,7 @@ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
   /* USER CODE BEGIN 2 */
   if (hpcd->Init.low_power_enable)
   {
-    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */
+    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
     SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
   }
   /* USER CODE END 2 */
@@ -340,6 +349,7 @@ void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
   /* USER CODE BEGIN 3 */
+
   /* USER CODE END 3 */
   USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
 }
diff --git a/STM32CubeMX/2020c/Src/usbd_storage_if.c b/STM32CubeMX/2020c/Src/usbd_storage_if.c
index 738fe371..32537499 100644
--- a/STM32CubeMX/2020c/Src/usbd_storage_if.c
+++ b/STM32CubeMX/2020c/Src/usbd_storage_if.c
@@ -7,7 +7,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
© Copyright (c) 2020 STMicroelectronics.
+  * 
© Copyright (c) 2021 STMicroelectronics.
   * All rights reserved.

   *
   * This software component is licensed by ST under Ultimate Liberty license
diff --git a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/.settings/com.atollic.truestudio.debug.hardware_device.prefs
deleted file mode 100644
index 5a9a7669..00000000
--- a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/.settings/com.atollic.truestudio.debug.hardware_device.prefs	
+++ /dev/null
@@ -1,11 +0,0 @@
-BOARD=None
-CODE_LOCATION=FLASH
-ENDIAN=Little-endian
-MCU=STM32F205VC
-MCU_VENDOR=STMicroelectronics
-MODEL=Lite
-PROBE=ST-LINK
-PROJECT_FORMAT_VERSION=2
-TARGET=ARM\u00AE
-VERSION=4.1.0
-eclipse.preferences.version=1
diff --git a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/SCSI2SD-V6 Configuration.elf.launch b/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/SCSI2SD-V6 Configuration.elf.launch
deleted file mode 100644
index 5fadc6ab..00000000
--- a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/SCSI2SD-V6 Configuration.elf.launch	
+++ /dev/null
@@ -1,46 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/STM32F205VC_FLASH.ld b/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/STM32F205VC_FLASH.ld
deleted file mode 100644
index fa018e0b..00000000
--- a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6 Configuration/STM32F205VC_FLASH.ld	
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
-*****************************************************************************
-**
-**  File        : stm32_flash.ld
-**
-**  Abstract    : Linker script for STM32F205VC Device with
-**                256KByte FLASH, 96KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Environment : Atollic TrueSTUDIO(R)
-**
-**  Distribution: The file is distributed “as is,” without any warranty
-**                of any kind.
-**
-**  (c)Copyright Atollic AB.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. This file may only be built (assembled or compiled and linked)
-**  using the Atollic TrueSTUDIO(R) product. The use of this file together
-**  with other tools than Atollic TrueSTUDIO(R) is not permitted.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20018000;    /* end of RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 256K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(4);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(4);
-  } >RAM
-
-  
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6/.cproject b/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6/.cproject
index be0ab427..d38940d3 100644
--- a/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6/.cproject
+++ b/STM32CubeMX/2020c/TrueSTUDIO/SCSI2SD-V6/.cproject
@@ -34,7 +34,7 @@